Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version      : Vivado v.2023.1 (lin64) Build 3865809 Sun May  7 15:04:56 MDT 2023
| Date              : Fri Jan  3 17:08:15 2025
| Host              : linux-139028 running 64-bit Debian GNU/Linux 12 (bookworm)
| Command           : report_timing_summary -max_paths 10 -report_unconstrained -file d_1_wrapper_timing_summary_routed.rpt -pb d_1_wrapper_timing_summary_routed.pb -rpx d_1_wrapper_timing_summary_routed.rpx -warn_on_violation
| Design            : d_1_wrapper
| Device            : xczu28dr-ffvg1517
| Speed File        : -2  PRODUCTION 1.30 05-03-2022
| Design State      : Routed
| Temperature Grade : E
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------

Timing Summary Report

------------------------------------------------------------------------------------------------
| Timer Settings
| --------------
------------------------------------------------------------------------------------------------

  Enable Multi Corner Analysis               :  Yes
  Enable Pessimism Removal                   :  Yes
  Pessimism Removal Resolution               :  Nearest Common Node
  Enable Input Delay Default Clock           :  No
  Enable Preset / Clear Arcs                 :  No
  Disable Flight Delays                      :  No
  Ignore I/O Paths                           :  No
  Timing Early Launch at Borrowing Latches   :  No
  Borrow Time for Max Delay Exceptions       :  Yes
  Merge Timing Exceptions                    :  Yes

  Corner  Analyze    Analyze    
  Name    Max Paths  Min Paths  
  ------  ---------  ---------  
  Slow    Yes        Yes        
  Fast    Yes        Yes        


------------------------------------------------------------------------------------------------
| Report Methodology
| ------------------
------------------------------------------------------------------------------------------------

Rule       Severity  Description                                                                                            Violations  
---------  --------  -----------------------------------------------------------------------------------------------------  ----------  
LUTAR-1    Warning   LUT drives async reset alert                                                                           9           
TIMING-9   Warning   Unknown CDC Logic                                                                                      1           
TIMING-10  Warning   Missing property on synchronizer                                                                       1           
TIMING-18  Warning   Missing input or output delay                                                                          37          
TIMING-24  Warning   Overridden Max delay datapath only                                                                     12          
TIMING-47  Warning   False path, asynchronous clock group or max delay datapath only constraint between synchronous clocks  2           
CLKC-40    Advisory  Substitute PLLE4 for MMCME4 check                                                                      1           
CLKC-56    Advisory  MMCME4 with global clock driver has no LOC                                                             2           
XDCB-6     Advisory  Timing constraint pointing to hierarchical pins                                                        1           

Note: This report is based on the most recent report_methodology run and may not be up-to-date. Run report_methodology on the current design for the latest report.



check_timing report

Table of Contents
-----------------
1. checking no_clock (0)
2. checking constant_clock (0)
3. checking pulse_width_clock (0)
4. checking unconstrained_internal_endpoints (0)
5. checking no_input_delay (7)
6. checking no_output_delay (31)
7. checking multiple_clock (0)
8. checking generated_clocks (0)
9. checking loops (0)
10. checking partial_input_delay (0)
11. checking partial_output_delay (0)
12. checking latch_loops (0)

1. checking no_clock (0)
------------------------
 There are 0 register/latch pins with no clock.


2. checking constant_clock (0)
------------------------------
 There are 0 register/latch pins with constant_clock.


3. checking pulse_width_clock (0)
---------------------------------
 There are 0 register/latch pins which need pulse_width check


4. checking unconstrained_internal_endpoints (0)
------------------------------------------------
 There are 0 pins that are not constrained for maximum delay.

 There are 0 pins that are not constrained for maximum delay due to constant clock.


5. checking no_input_delay (7)
------------------------------
 There are 7 input ports with no input delay specified. (HIGH)

 There are 0 input ports with no input delay but user has a false path constraint.


6. checking no_output_delay (31)
--------------------------------
 There are 31 ports with no output delay specified. (HIGH)

 There are 0 ports with no output delay but user has a false path constraint

 There are 0 ports with no output delay but with a timing clock defined on it or propagating through it


7. checking multiple_clock (0)
------------------------------
 There are 0 register/latch pins with multiple clocks.


8. checking generated_clocks (0)
--------------------------------
 There are 0 generated clocks that are not connected to a clock source.


9. checking loops (0)
---------------------
 There are 0 combinational loops in the design.


10. checking partial_input_delay (0)
------------------------------------
 There are 0 input ports with partial input delay specified.


11. checking partial_output_delay (0)
-------------------------------------
 There are 0 ports with partial output delay specified.


12. checking latch_loops (0)
----------------------------
 There are 0 combinational latch loops in the design through latch input



------------------------------------------------------------------------------------------------
| Design Timing Summary
| ---------------------
------------------------------------------------------------------------------------------------

    WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints     WPWS(ns)     TPWS(ns)  TPWS Failing Endpoints  TPWS Total Endpoints  
    -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------     --------     --------  ----------------------  --------------------  
      0.001        0.000                      0               772842        0.008        0.000                      0               772140        0.000        0.000                       0                266743  


All user specified timing constraints are met.


------------------------------------------------------------------------------------------------
| Clock Summary
| -------------
------------------------------------------------------------------------------------------------

Clock                                                                                                Waveform(ns)           Period(ns)      Frequency(MHz)
-----                                                                                                ------------           ----------      --------------
RFADC0_CLK                                                                                           {0.000 1.953}          3.906           256.016         
  clk_out1_d_1_clk_adc0_x2_0                                                                         {0.000 0.976}          1.953           512.033         
RFADC0_CLK_dummy                                                                                     {0.000 1.953}          3.906           256.016         
RFADC1_CLK                                                                                           {0.000 5.000}          10.000          100.000         
RFADC1_CLK_dummy                                                                                     {0.000 5.000}          10.000          100.000         
RFADC1_FABCLK0                                                                                       {0.000 5.000}          10.000          100.000         
RFADC1_FABCLK1                                                                                       {0.000 5.000}          10.000          100.000         
RFADC1_FABCLK2                                                                                       {0.000 5.000}          10.000          100.000         
RFADC1_FABCLK3                                                                                       {0.000 5.000}          10.000          100.000         
RFADC2_CLK                                                                                           {0.000 1.953}          3.906           256.016         
RFADC2_CLK_dummy                                                                                     {0.000 1.953}          3.906           256.016         
RFADC3_CLK                                                                                           {0.000 5.000}          10.000          100.000         
RFADC3_CLK_dummy                                                                                     {0.000 5.000}          10.000          100.000         
RFADC3_FABCLK0                                                                                       {0.000 5.000}          10.000          100.000         
RFADC3_FABCLK1                                                                                       {0.000 5.000}          10.000          100.000         
RFADC3_FABCLK2                                                                                       {0.000 5.000}          10.000          100.000         
RFADC3_FABCLK3                                                                                       {0.000 5.000}          10.000          100.000         
RFDAC0_CLK                                                                                           {0.000 1.302}          2.604           384.025         
RFDAC1_CLK                                                                                           {0.000 1.302}          2.604           384.025         
clk_pl_0                                                                                             {0.000 5.000}          10.000          100.000         
  clk_out1_d_1_clk_core_0                                                                            {0.000 2.500}          5.000           200.000         
clk_pl_1                                                                                             {0.000 250.003}        500.005         2.000           
dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {0.000 25.000}         50.000          20.000          
sys_clk_ddr4_clk_p                                                                                   {0.000 1.667}          3.334           299.940         
  mmcm_clkout0                                                                                       {0.000 1.500}          3.001           333.267         
    pll_clk[0]                                                                                       {0.000 0.188}          0.375           2666.133        
      pll_clk[0]_DIV                                                                                 {0.000 1.500}          3.001           333.267         
    pll_clk[1]                                                                                       {0.000 0.188}          0.375           2666.133        
      pll_clk[1]_DIV                                                                                 {0.000 1.500}          3.001           333.267         
    pll_clk[2]                                                                                       {0.000 0.188}          0.375           2666.133        
      pll_clk[2]_DIV                                                                                 {0.000 1.500}          3.001           333.267         
  mmcm_clkout5                                                                                       {0.000 6.001}          12.002          83.317          
  mmcm_clkout6                                                                                       {0.000 3.001}          6.001           166.633         


------------------------------------------------------------------------------------------------
| Intra Clock Table
| -----------------
------------------------------------------------------------------------------------------------

Clock                                                                                                    WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints     WPWS(ns)     TPWS(ns)  TPWS Failing Endpoints  TPWS Total Endpoints  
-----                                                                                                    -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------     --------     --------  ----------------------  --------------------  
RFADC0_CLK                                                                                                 2.953        0.000                      0                   46        0.037        0.000                      0                   46        0.586        0.000                       0                    37  
  clk_out1_d_1_clk_adc0_x2_0                                                                               0.001        0.000                      0               257197        0.010        0.000                      0               257197        0.030        0.000                       0                 83222  
RFDAC0_CLK                                                                                                 0.033        0.000                      0               229386        0.008        0.000                      0               229386        0.502        0.000                       0                 86404  
clk_pl_0                                                                                                   1.565        0.000                      0               151229        0.010        0.000                      0               151229        1.000        0.000                       0                 48236  
  clk_out1_d_1_clk_core_0                                                                                  0.178        0.000                      0                14070        0.009        0.000                      0                14070        1.958        0.000                       0                  4538  
dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK       13.785        0.000                      0                  992        0.014        0.000                      0                  992       24.468        0.000                       0                   479  
sys_clk_ddr4_clk_p                                                                                         0.729        0.000                      0                   23        0.055        0.000                      0                   23        0.500        0.000                       0                    19  
  mmcm_clkout0                                                                                             0.019        0.000                      0               109871        0.010        0.000                      0               109871        0.000        0.000                       0                 41386  
    pll_clk[0]                                                                                                                                                                                                                                         0.000        0.000                       0                     9  
      pll_clk[0]_DIV                                                                                                                                                                                                                                   0.300        0.000                       0                    40  
    pll_clk[1]                                                                                                                                                                                                                                         0.000        0.000                       0                     9  
      pll_clk[1]_DIV                                                                                                                                                                                                                                   0.300        0.000                       0                    40  
    pll_clk[2]                                                                                                                                                                                                                                         0.000        0.000                       0                     7  
      pll_clk[2]_DIV                                                                                                                                                                                                                                   0.300        0.000                       0                    25  
  mmcm_clkout5                                                                                             9.803        0.000                      0                  827        0.031        0.000                      0                  827        5.469        0.000                       0                   570  
  mmcm_clkout6                                                                                             0.731        0.000                      0                 5636        0.027        0.000                      0                 5152        0.997        0.000                       0                  1722  


------------------------------------------------------------------------------------------------
| Inter Clock Table
| -----------------
------------------------------------------------------------------------------------------------

From Clock                                                                                           To Clock                                                                                                 WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints  
----------                                                                                           --------                                                                                                 -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------  
mmcm_clkout5                                                                                         dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK       11.583        0.000                      0                    8                                                                        
mmcm_clkout5                                                                                         mmcm_clkout0                                                                                               2.504        0.000                      0                   28                                                                        
mmcm_clkout6                                                                                         mmcm_clkout0                                                                                               1.139        0.000                      0                  129                                                                        
mmcm_clkout0                                                                                         pll_clk[0]_DIV                                                                                             0.424        0.000                      0                  352        0.579        0.000                      0                  352  
mmcm_clkout0                                                                                         pll_clk[1]_DIV                                                                                             0.695        0.000                      0                  352        0.504        0.000                      0                  352  
mmcm_clkout0                                                                                         pll_clk[2]_DIV                                                                                             0.491        0.000                      0                  216        0.557        0.000                      0                  216  
dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  mmcm_clkout5                                                                                              49.494        0.000                      0                    8                                                                        
mmcm_clkout0                                                                                         mmcm_clkout5                                                                                              11.312        0.000                      0                   10                                                                        
mmcm_clkout0                                                                                         mmcm_clkout6                                                                                               1.452        0.000                      0                   36        0.128        0.000                      0                    1  


------------------------------------------------------------------------------------------------
| Other Path Groups Table
| -----------------------
------------------------------------------------------------------------------------------------

Path Group                                                                                           From Clock                                                                                           To Clock                                                                                                 WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints  
----------                                                                                           ----------                                                                                           --------                                                                                                 -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------  
**async_default**                                                                                    clk_out1_d_1_clk_adc0_x2_0                                                                           clk_out1_d_1_clk_adc0_x2_0                                                                                 0.518        0.000                      0                    4        0.144        0.000                      0                    4  
**async_default**                                                                                    clk_out1_d_1_clk_core_0                                                                              clk_out1_d_1_clk_core_0                                                                                    1.795        0.000                      0                 2055        0.111        0.000                      0                 2055  
**async_default**                                                                                    clk_pl_0                                                                                             clk_pl_0                                                                                                   6.825        0.000                      0                  162        0.192        0.000                      0                  162  
**async_default**                                                                                    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK       46.222        0.000                      0                  100        0.120        0.000                      0                  100  
**async_default**                                                                                    mmcm_clkout5                                                                                         mmcm_clkout5                                                                                              10.521        0.000                      0                  105        0.114        0.000                      0                  105  


------------------------------------------------------------------------------------------------
| User Ignored Path Table
| -----------------------
------------------------------------------------------------------------------------------------

Path Group                                                                                           From Clock                                                                                           To Clock                                                                                           
----------                                                                                           ----------                                                                                           --------                                                                                           
(none)                                                                                               RFDAC0_CLK                                                                                                                                                                                                
(none)                                                                                                                                                                                                    RFADC0_CLK                                                                                           
(none)                                                                                                                                                                                                    RFDAC0_CLK                                                                                           
(none)                                                                                               RFDAC0_CLK                                                                                           RFDAC0_CLK                                                                                           
(none)                                                                                               clk_out1_d_1_clk_adc0_x2_0                                                                           RFDAC0_CLK                                                                                           
(none)                                                                                               clk_out1_d_1_clk_core_0                                                                              RFDAC0_CLK                                                                                           
(none)                                                                                               clk_pl_0                                                                                             RFDAC0_CLK                                                                                           
(none)                                                                                                                                                                                                    clk_out1_d_1_clk_adc0_x2_0                                                                           
(none)                                                                                               RFDAC0_CLK                                                                                           clk_out1_d_1_clk_adc0_x2_0                                                                           
(none)                                                                                               clk_pl_0                                                                                             clk_out1_d_1_clk_adc0_x2_0                                                                           
(none)                                                                                               mmcm_clkout0                                                                                         clk_out1_d_1_clk_adc0_x2_0                                                                           
(none)                                                                                                                                                                                                    clk_out1_d_1_clk_core_0                                                                              
(none)                                                                                               RFDAC0_CLK                                                                                           clk_out1_d_1_clk_core_0                                                                              
(none)                                                                                               clk_pl_0                                                                                             clk_out1_d_1_clk_core_0                                                                              
(none)                                                                                                                                                                                                    clk_pl_0                                                                                             
(none)                                                                                               RFADC0_CLK                                                                                           clk_pl_0                                                                                             
(none)                                                                                               RFADC1_CLK                                                                                           clk_pl_0                                                                                             
(none)                                                                                               RFADC2_CLK                                                                                           clk_pl_0                                                                                             
(none)                                                                                               RFADC3_CLK                                                                                           clk_pl_0                                                                                             
(none)                                                                                               RFDAC0_CLK                                                                                           clk_pl_0                                                                                             
(none)                                                                                               RFDAC1_CLK                                                                                           clk_pl_0                                                                                             
(none)                                                                                               clk_out1_d_1_clk_adc0_x2_0                                                                           clk_pl_0                                                                                             
(none)                                                                                               clk_out1_d_1_clk_core_0                                                                              clk_pl_0                                                                                             
(none)                                                                                               clk_pl_0                                                                                             clk_pl_0                                                                                             
(none)                                                                                               mmcm_clkout5                                                                                         dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  
(none)                                                                                               RFDAC0_CLK                                                                                           mmcm_clkout0                                                                                         
(none)                                                                                               clk_out1_d_1_clk_adc0_x2_0                                                                           mmcm_clkout0                                                                                         
(none)                                                                                               clk_pl_0                                                                                             mmcm_clkout0                                                                                         
(none)                                                                                               mmcm_clkout0                                                                                         mmcm_clkout0                                                                                         
(none)                                                                                               mmcm_clkout5                                                                                         mmcm_clkout0                                                                                         
(none)                                                                                               mmcm_clkout6                                                                                         mmcm_clkout0                                                                                         
(none)                                                                                               sys_clk_ddr4_clk_p                                                                                   mmcm_clkout0                                                                                         
(none)                                                                                               dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  mmcm_clkout5                                                                                         
(none)                                                                                               mmcm_clkout0                                                                                         mmcm_clkout5                                                                                         
(none)                                                                                               mmcm_clkout0                                                                                         mmcm_clkout6                                                                                         
(none)                                                                                               mmcm_clkout6                                                                                         mmcm_clkout6                                                                                         
(none)                                                                                               sys_clk_ddr4_clk_p                                                                                   mmcm_clkout6                                                                                         
(none)                                                                                               clk_pl_0                                                                                             sys_clk_ddr4_clk_p                                                                                   


------------------------------------------------------------------------------------------------
| Unconstrained Path Table
| ------------------------
------------------------------------------------------------------------------------------------

Path Group                                                                                           From Clock                                                                                           To Clock                                                                                           
----------                                                                                           ----------                                                                                           --------                                                                                           
(none)                                                                                               clk_pl_0                                                                                                                                                                                                  
(none)                                                                                               clk_pl_1                                                                                                                                                                                                  
(none)                                                                                               mmcm_clkout0                                                                                                                                                                                              
(none)                                                                                                                                                                                                    RFDAC0_CLK                                                                                           
(none)                                                                                                                                                                                                    clk_out1_d_1_clk_adc0_x2_0                                                                           
(none)                                                                                                                                                                                                    clk_out1_d_1_clk_core_0                                                                              
(none)                                                                                                                                                                                                    clk_pl_0                                                                                             
(none)                                                                                                                                                                                                    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  
(none)                                                                                                                                                                                                    sys_clk_ddr4_clk_p                                                                                   


------------------------------------------------------------------------------------------------
| Timing Details
| --------------
------------------------------------------------------------------------------------------------


---------------------------------------------------------------------------------------------------
From Clock:  RFADC0_CLK
  To Clock:  RFADC0_CLK

Setup :            0  Failing Endpoints,  Worst Slack        2.953ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.037ns,  Total Violation        0.000ns
PW    :            0  Failing Endpoints,  Worst Slack        0.586ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             2.953ns  (required time - arrival time)
  Source:                 d_1_i/rst_adc0/U0/SEQ/pr_reg/C
                            (rising edge-triggered cell FDSE clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/rst_adc0/U0/PR_OUT_DFF[0].FDRE_PER/D
                            (rising edge-triggered cell FDRE clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             RFADC0_CLK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.906ns  (RFADC0_CLK rise@3.906ns - RFADC0_CLK rise@0.000ns)
  Data Path Delay:        0.762ns  (logic 0.077ns (10.105%)  route 0.685ns (89.896%))
  Logic Levels:           0  
  Clock Path Skew:        -0.181ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.891ns = ( 6.797 - 3.906 ) 
    Source Clock Delay      (SCD):    3.439ns
    Clock Pessimism Removal (CPR):    0.367ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.912ns (routing 1.381ns, distribution 1.531ns)
  Clock Net Delay (Destination): 2.505ns (routing 1.251ns, distribution 1.254ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
    X4Y4 (CLOCK_ROOT)    net (fo=35, routed)          2.912     3.439    d_1_i/rst_adc0/U0/SEQ/slowest_sync_clk
    SLICE_X103Y62        FDSE                                         r  d_1_i/rst_adc0/U0/SEQ/pr_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X103Y62        FDSE (Prop_CFF2_SLICEM_C_Q)
                                                      0.077     3.516 r  d_1_i/rst_adc0/U0/SEQ/pr_reg/Q
                         net (fo=2, routed)           0.685     4.201    d_1_i/rst_adc0/U0/Pr_out
    SLICE_X89Y62         FDRE                                         r  d_1_i/rst_adc0/U0/PR_OUT_DFF[0].FDRE_PER/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC0_CLK rise edge)
                                                      3.906     3.906 r  
    HSADC_X0Y0           HSADC                        0.000     3.906 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     4.028 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     4.178    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     4.292 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
    X4Y4 (CLOCK_ROOT)    net (fo=35, routed)          2.505     6.797    d_1_i/rst_adc0/U0/slowest_sync_clk
    SLICE_X89Y62         FDRE                                         r  d_1_i/rst_adc0/U0/PR_OUT_DFF[0].FDRE_PER/C
                         clock pessimism              0.367     7.164    
                         clock uncertainty           -0.035     7.128    
    SLICE_X89Y62         FDRE (Setup_EFF_SLICEM_C_D)
                                                      0.025     7.153    d_1_i/rst_adc0/U0/PR_OUT_DFF[0].FDRE_PER
  -------------------------------------------------------------------
                         required time                          7.153    
                         arrival time                          -4.201    
  -------------------------------------------------------------------
                         slack                                  2.953    

Slack (MET) :             3.091ns  (required time - arrival time)
  Source:                 d_1_i/rst_adc0/U0/SEQ/from_sys_reg/C
                            (rising edge-triggered cell FDSE clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[1]/CE
                            (rising edge-triggered cell FDRE clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             RFADC0_CLK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.906ns  (RFADC0_CLK rise@3.906ns - RFADC0_CLK rise@0.000ns)
  Data Path Delay:        0.620ns  (logic 0.080ns (12.910%)  route 0.540ns (87.090%))
  Logic Levels:           0  
  Clock Path Skew:        -0.099ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.969ns = ( 6.875 - 3.906 ) 
    Source Clock Delay      (SCD):    3.439ns
    Clock Pessimism Removal (CPR):    0.370ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.912ns (routing 1.381ns, distribution 1.531ns)
  Clock Net Delay (Destination): 2.583ns (routing 1.251ns, distribution 1.332ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
    X4Y4 (CLOCK_ROOT)    net (fo=35, routed)          2.912     3.439    d_1_i/rst_adc0/U0/SEQ/slowest_sync_clk
    SLICE_X103Y62        FDSE                                         r  d_1_i/rst_adc0/U0/SEQ/from_sys_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X103Y62        FDSE (Prop_DFF2_SLICEM_C_Q)
                                                      0.080     3.519 r  d_1_i/rst_adc0/U0/SEQ/from_sys_reg/Q
                         net (fo=10, routed)          0.540     4.058    d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/seq_cnt_en
    SLICE_X104Y63        FDRE                                         r  d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[1]/CE
  -------------------------------------------------------------------    -------------------

                         (clock RFADC0_CLK rise edge)
                                                      3.906     3.906 r  
    HSADC_X0Y0           HSADC                        0.000     3.906 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     4.028 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     4.178    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     4.292 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
    X4Y4 (CLOCK_ROOT)    net (fo=35, routed)          2.583     6.875    d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/slowest_sync_clk
    SLICE_X104Y63        FDRE                                         r  d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[1]/C
                         clock pessimism              0.370     7.245    
                         clock uncertainty           -0.035     7.210    
    SLICE_X104Y63        FDRE (Setup_DFF_SLICEM_C_CE)
                                                     -0.061     7.149    d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[1]
  -------------------------------------------------------------------
                         required time                          7.149    
                         arrival time                          -4.058    
  -------------------------------------------------------------------
                         slack                                  3.091    

Slack (MET) :             3.092ns  (required time - arrival time)
  Source:                 d_1_i/rst_adc0/U0/SEQ/from_sys_reg/C
                            (rising edge-triggered cell FDSE clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[0]/CE
                            (rising edge-triggered cell FDRE clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             RFADC0_CLK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.906ns  (RFADC0_CLK rise@3.906ns - RFADC0_CLK rise@0.000ns)
  Data Path Delay:        0.620ns  (logic 0.080ns (12.910%)  route 0.540ns (87.090%))
  Logic Levels:           0  
  Clock Path Skew:        -0.099ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.969ns = ( 6.875 - 3.906 ) 
    Source Clock Delay      (SCD):    3.439ns
    Clock Pessimism Removal (CPR):    0.370ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.912ns (routing 1.381ns, distribution 1.531ns)
  Clock Net Delay (Destination): 2.583ns (routing 1.251ns, distribution 1.332ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
    X4Y4 (CLOCK_ROOT)    net (fo=35, routed)          2.912     3.439    d_1_i/rst_adc0/U0/SEQ/slowest_sync_clk
    SLICE_X103Y62        FDSE                                         r  d_1_i/rst_adc0/U0/SEQ/from_sys_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X103Y62        FDSE (Prop_DFF2_SLICEM_C_Q)
                                                      0.080     3.519 r  d_1_i/rst_adc0/U0/SEQ/from_sys_reg/Q
                         net (fo=10, routed)          0.540     4.058    d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/seq_cnt_en
    SLICE_X104Y63        FDRE                                         r  d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[0]/CE
  -------------------------------------------------------------------    -------------------

                         (clock RFADC0_CLK rise edge)
                                                      3.906     3.906 r  
    HSADC_X0Y0           HSADC                        0.000     3.906 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     4.028 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     4.178    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     4.292 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
    X4Y4 (CLOCK_ROOT)    net (fo=35, routed)          2.583     6.875    d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/slowest_sync_clk
    SLICE_X104Y63        FDRE                                         r  d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[0]/C
                         clock pessimism              0.370     7.245    
                         clock uncertainty           -0.035     7.210    
    SLICE_X104Y63        FDRE (Setup_CFF2_SLICEM_C_CE)
                                                     -0.060     7.150    d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[0]
  -------------------------------------------------------------------
                         required time                          7.150    
                         arrival time                          -4.058    
  -------------------------------------------------------------------
                         slack                                  3.092    

Slack (MET) :             3.092ns  (required time - arrival time)
  Source:                 d_1_i/rst_adc0/U0/SEQ/from_sys_reg/C
                            (rising edge-triggered cell FDSE clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[2]/CE
                            (rising edge-triggered cell FDRE clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             RFADC0_CLK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.906ns  (RFADC0_CLK rise@3.906ns - RFADC0_CLK rise@0.000ns)
  Data Path Delay:        0.620ns  (logic 0.080ns (12.910%)  route 0.540ns (87.090%))
  Logic Levels:           0  
  Clock Path Skew:        -0.099ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.969ns = ( 6.875 - 3.906 ) 
    Source Clock Delay      (SCD):    3.439ns
    Clock Pessimism Removal (CPR):    0.370ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.912ns (routing 1.381ns, distribution 1.531ns)
  Clock Net Delay (Destination): 2.583ns (routing 1.251ns, distribution 1.332ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
    X4Y4 (CLOCK_ROOT)    net (fo=35, routed)          2.912     3.439    d_1_i/rst_adc0/U0/SEQ/slowest_sync_clk
    SLICE_X103Y62        FDSE                                         r  d_1_i/rst_adc0/U0/SEQ/from_sys_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X103Y62        FDSE (Prop_DFF2_SLICEM_C_Q)
                                                      0.080     3.519 r  d_1_i/rst_adc0/U0/SEQ/from_sys_reg/Q
                         net (fo=10, routed)          0.540     4.058    d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/seq_cnt_en
    SLICE_X104Y63        FDRE                                         r  d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[2]/CE
  -------------------------------------------------------------------    -------------------

                         (clock RFADC0_CLK rise edge)
                                                      3.906     3.906 r  
    HSADC_X0Y0           HSADC                        0.000     3.906 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     4.028 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     4.178    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     4.292 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
    X4Y4 (CLOCK_ROOT)    net (fo=35, routed)          2.583     6.875    d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/slowest_sync_clk
    SLICE_X104Y63        FDRE                                         r  d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[2]/C
                         clock pessimism              0.370     7.245    
                         clock uncertainty           -0.035     7.210    
    SLICE_X104Y63        FDRE (Setup_DFF2_SLICEM_C_CE)
                                                     -0.060     7.150    d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[2]
  -------------------------------------------------------------------
                         required time                          7.150    
                         arrival time                          -4.058    
  -------------------------------------------------------------------
                         slack                                  3.092    

Slack (MET) :             3.167ns  (required time - arrival time)
  Source:                 d_1_i/rst_adc0/U0/EXT_LPF/POR_SRL_I/CLK
                            (rising edge-triggered cell SRL16E clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/rst_adc0/U0/EXT_LPF/lpf_int_reg/D
                            (rising edge-triggered cell FDRE clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             RFADC0_CLK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.906ns  (RFADC0_CLK rise@3.906ns - RFADC0_CLK rise@0.000ns)
  Data Path Delay:        0.650ns  (logic 0.460ns (70.769%)  route 0.190ns (29.231%))
  Logic Levels:           1  (LUT3=1)
  Clock Path Skew:        -0.079ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.970ns = ( 6.876 - 3.906 ) 
    Source Clock Delay      (SCD):    3.470ns
    Clock Pessimism Removal (CPR):    0.421ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.943ns (routing 1.381ns, distribution 1.562ns)
  Clock Net Delay (Destination): 2.584ns (routing 1.251ns, distribution 1.333ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
    X4Y4 (CLOCK_ROOT)    net (fo=35, routed)          2.943     3.470    d_1_i/rst_adc0/U0/EXT_LPF/slowest_sync_clk
    SLICE_X103Y62        SRL16E                                       r  d_1_i/rst_adc0/U0/EXT_LPF/POR_SRL_I/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X103Y62        SRL16E (Prop_H6LUT_SLICEM_CLK_Q)
                                                      0.392     3.862 r  d_1_i/rst_adc0/U0/EXT_LPF/POR_SRL_I/Q
                         net (fo=1, routed)           0.163     4.025    d_1_i/rst_adc0/U0/EXT_LPF/Q
    SLICE_X103Y64        LUT3 (Prop_C5LUT_SLICEM_I2_O)
                                                      0.068     4.093 r  d_1_i/rst_adc0/U0/EXT_LPF/lpf_int0/O
                         net (fo=1, routed)           0.027     4.120    d_1_i/rst_adc0/U0/EXT_LPF/lpf_int0__0
    SLICE_X103Y64        FDRE                                         r  d_1_i/rst_adc0/U0/EXT_LPF/lpf_int_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC0_CLK rise edge)
                                                      3.906     3.906 r  
    HSADC_X0Y0           HSADC                        0.000     3.906 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     4.028 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     4.178    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     4.292 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
    X4Y4 (CLOCK_ROOT)    net (fo=35, routed)          2.584     6.876    d_1_i/rst_adc0/U0/EXT_LPF/slowest_sync_clk
    SLICE_X103Y64        FDRE                                         r  d_1_i/rst_adc0/U0/EXT_LPF/lpf_int_reg/C
                         clock pessimism              0.421     7.297    
                         clock uncertainty           -0.035     7.261    
    SLICE_X103Y64        FDRE (Setup_CFF2_SLICEM_C_D)
                                                      0.025     7.286    d_1_i/rst_adc0/U0/EXT_LPF/lpf_int_reg
  -------------------------------------------------------------------
                         required time                          7.286    
                         arrival time                          -4.120    
  -------------------------------------------------------------------
                         slack                                  3.167    

Slack (MET) :             3.293ns  (required time - arrival time)
  Source:                 d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[3]/D
                            (rising edge-triggered cell FDRE clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             RFADC0_CLK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.906ns  (RFADC0_CLK rise@3.906ns - RFADC0_CLK rise@0.000ns)
  Data Path Delay:        0.523ns  (logic 0.230ns (43.988%)  route 0.293ns (56.012%))
  Logic Levels:           1  (LUT4=1)
  Clock Path Skew:        -0.080ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.969ns = ( 6.875 - 3.906 ) 
    Source Clock Delay      (SCD):    3.419ns
    Clock Pessimism Removal (CPR):    0.370ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.892ns (routing 1.381ns, distribution 1.511ns)
  Clock Net Delay (Destination): 2.583ns (routing 1.251ns, distribution 1.332ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
    X4Y4 (CLOCK_ROOT)    net (fo=35, routed)          2.892     3.419    d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/slowest_sync_clk
    SLICE_X104Y63        FDRE                                         r  d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X104Y63        FDRE (Prop_DFF_SLICEM_C_Q)
                                                      0.078     3.497 r  d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[1]/Q
                         net (fo=6, routed)           0.235     3.732    d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/Q[1]
    SLICE_X103Y63        LUT4 (Prop_H6LUT_SLICEM_I0_O)
                                                      0.152     3.884 r  d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int[3]_i_1/O
                         net (fo=1, routed)           0.058     3.942    d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int0[3]
    SLICE_X103Y63        FDRE                                         r  d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[3]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC0_CLK rise edge)
                                                      3.906     3.906 r  
    HSADC_X0Y0           HSADC                        0.000     3.906 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     4.028 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     4.178    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     4.292 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
    X4Y4 (CLOCK_ROOT)    net (fo=35, routed)          2.583     6.875    d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/slowest_sync_clk
    SLICE_X103Y63        FDRE                                         r  d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[3]/C
                         clock pessimism              0.370     7.245    
                         clock uncertainty           -0.035     7.210    
    SLICE_X103Y63        FDRE (Setup_HFF_SLICEM_C_D)
                                                      0.025     7.235    d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[3]
  -------------------------------------------------------------------
                         required time                          7.235    
                         arrival time                          -3.942    
  -------------------------------------------------------------------
                         slack                                  3.293    

Slack (MET) :             3.302ns  (required time - arrival time)
  Source:                 d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[5]/D
                            (rising edge-triggered cell FDRE clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             RFADC0_CLK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.906ns  (RFADC0_CLK rise@3.906ns - RFADC0_CLK rise@0.000ns)
  Data Path Delay:        0.514ns  (logic 0.228ns (44.369%)  route 0.286ns (55.631%))
  Logic Levels:           1  (LUT6=1)
  Clock Path Skew:        -0.080ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.969ns = ( 6.875 - 3.906 ) 
    Source Clock Delay      (SCD):    3.419ns
    Clock Pessimism Removal (CPR):    0.370ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.892ns (routing 1.381ns, distribution 1.511ns)
  Clock Net Delay (Destination): 2.583ns (routing 1.251ns, distribution 1.332ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
    X4Y4 (CLOCK_ROOT)    net (fo=35, routed)          2.892     3.419    d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/slowest_sync_clk
    SLICE_X104Y63        FDRE                                         r  d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X104Y63        FDRE (Prop_DFF_SLICEM_C_Q)
                                                      0.078     3.497 r  d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[1]/Q
                         net (fo=6, routed)           0.227     3.724    d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/Q[1]
    SLICE_X103Y63        LUT6 (Prop_G6LUT_SLICEM_I1_O)
                                                      0.150     3.874 r  d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int[5]_i_2/O
                         net (fo=1, routed)           0.059     3.933    d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int0[5]
    SLICE_X103Y63        FDRE                                         r  d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[5]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC0_CLK rise edge)
                                                      3.906     3.906 r  
    HSADC_X0Y0           HSADC                        0.000     3.906 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     4.028 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     4.178    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     4.292 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
    X4Y4 (CLOCK_ROOT)    net (fo=35, routed)          2.583     6.875    d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/slowest_sync_clk
    SLICE_X103Y63        FDRE                                         r  d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[5]/C
                         clock pessimism              0.370     7.245    
                         clock uncertainty           -0.035     7.210    
    SLICE_X103Y63        FDRE (Setup_GFF_SLICEM_C_D)
                                                      0.025     7.235    d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[5]
  -------------------------------------------------------------------
                         required time                          7.235    
                         arrival time                          -3.933    
  -------------------------------------------------------------------
                         slack                                  3.302    

Slack (MET) :             3.324ns  (required time - arrival time)
  Source:                 d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[4]/D
                            (rising edge-triggered cell FDRE clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             RFADC0_CLK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.906ns  (RFADC0_CLK rise@3.906ns - RFADC0_CLK rise@0.000ns)
  Data Path Delay:        0.492ns  (logic 0.239ns (48.590%)  route 0.253ns (51.410%))
  Logic Levels:           1  (LUT5=1)
  Clock Path Skew:        -0.080ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.969ns = ( 6.875 - 3.906 ) 
    Source Clock Delay      (SCD):    3.419ns
    Clock Pessimism Removal (CPR):    0.370ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.892ns (routing 1.381ns, distribution 1.511ns)
  Clock Net Delay (Destination): 2.583ns (routing 1.251ns, distribution 1.332ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
    X4Y4 (CLOCK_ROOT)    net (fo=35, routed)          2.892     3.419    d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/slowest_sync_clk
    SLICE_X104Y63        FDRE                                         r  d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X104Y63        FDRE (Prop_DFF_SLICEM_C_Q)
                                                      0.078     3.497 r  d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[1]/Q
                         net (fo=6, routed)           0.235     3.732    d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/Q[1]
    SLICE_X103Y63        LUT5 (Prop_H5LUT_SLICEM_I2_O)
                                                      0.161     3.893 r  d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int[4]_i_1/O
                         net (fo=1, routed)           0.018     3.911    d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int0[4]
    SLICE_X103Y63        FDRE                                         r  d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[4]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC0_CLK rise edge)
                                                      3.906     3.906 r  
    HSADC_X0Y0           HSADC                        0.000     3.906 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     4.028 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     4.178    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     4.292 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
    X4Y4 (CLOCK_ROOT)    net (fo=35, routed)          2.583     6.875    d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/slowest_sync_clk
    SLICE_X103Y63        FDRE                                         r  d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[4]/C
                         clock pessimism              0.370     7.245    
                         clock uncertainty           -0.035     7.210    
    SLICE_X103Y63        FDRE (Setup_HFF2_SLICEM_C_D)
                                                      0.025     7.235    d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[4]
  -------------------------------------------------------------------
                         required time                          7.235    
                         arrival time                          -3.911    
  -------------------------------------------------------------------
                         slack                                  3.324    

Slack (MET) :             3.327ns  (required time - arrival time)
  Source:                 d_1_i/rst_adc0/U0/SEQ/from_sys_reg/C
                            (rising edge-triggered cell FDSE clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/rst_adc0/U0/SEQ/pr_dec_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             RFADC0_CLK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.906ns  (RFADC0_CLK rise@3.906ns - RFADC0_CLK rise@0.000ns)
  Data Path Delay:        0.521ns  (logic 0.168ns (32.260%)  route 0.353ns (67.740%))
  Logic Levels:           1  (LUT4=1)
  Clock Path Skew:        -0.048ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.970ns = ( 6.876 - 3.906 ) 
    Source Clock Delay      (SCD):    3.439ns
    Clock Pessimism Removal (CPR):    0.421ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.912ns (routing 1.381ns, distribution 1.531ns)
  Clock Net Delay (Destination): 2.584ns (routing 1.251ns, distribution 1.333ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
    X4Y4 (CLOCK_ROOT)    net (fo=35, routed)          2.912     3.439    d_1_i/rst_adc0/U0/SEQ/slowest_sync_clk
    SLICE_X103Y62        FDSE                                         r  d_1_i/rst_adc0/U0/SEQ/from_sys_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X103Y62        FDSE (Prop_DFF2_SLICEM_C_Q)
                                                      0.080     3.519 r  d_1_i/rst_adc0/U0/SEQ/from_sys_reg/Q
                         net (fo=10, routed)          0.281     3.799    d_1_i/rst_adc0/U0/SEQ/seq_cnt_en
    SLICE_X103Y63        LUT4 (Prop_D6LUT_SLICEM_I0_O)
                                                      0.088     3.887 r  d_1_i/rst_adc0/U0/SEQ/pr_dec[0]_i_1/O
                         net (fo=1, routed)           0.072     3.959    d_1_i/rst_adc0/U0/SEQ/p_3_out[0]
    SLICE_X103Y63        FDRE                                         r  d_1_i/rst_adc0/U0/SEQ/pr_dec_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC0_CLK rise edge)
                                                      3.906     3.906 r  
    HSADC_X0Y0           HSADC                        0.000     3.906 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     4.028 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     4.178    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     4.292 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
    X4Y4 (CLOCK_ROOT)    net (fo=35, routed)          2.584     6.876    d_1_i/rst_adc0/U0/SEQ/slowest_sync_clk
    SLICE_X103Y63        FDRE                                         r  d_1_i/rst_adc0/U0/SEQ/pr_dec_reg[0]/C
                         clock pessimism              0.421     7.297    
                         clock uncertainty           -0.035     7.262    
    SLICE_X103Y63        FDRE (Setup_DFF_SLICEM_C_D)
                                                      0.025     7.287    d_1_i/rst_adc0/U0/SEQ/pr_dec_reg[0]
  -------------------------------------------------------------------
                         required time                          7.287    
                         arrival time                          -3.959    
  -------------------------------------------------------------------
                         slack                                  3.327    

Slack (MET) :             3.333ns  (required time - arrival time)
  Source:                 d_1_i/rst_adc0/U0/SEQ/from_sys_reg/C
                            (rising edge-triggered cell FDSE clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/rst_adc0/U0/SEQ/core_dec_reg[1]/D
                            (rising edge-triggered cell FDRE clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             RFADC0_CLK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.906ns  (RFADC0_CLK rise@3.906ns - RFADC0_CLK rise@0.000ns)
  Data Path Delay:        0.515ns  (logic 0.168ns (32.636%)  route 0.347ns (67.364%))
  Logic Levels:           1  (LUT4=1)
  Clock Path Skew:        -0.048ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.970ns = ( 6.876 - 3.906 ) 
    Source Clock Delay      (SCD):    3.439ns
    Clock Pessimism Removal (CPR):    0.421ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.912ns (routing 1.381ns, distribution 1.531ns)
  Clock Net Delay (Destination): 2.584ns (routing 1.251ns, distribution 1.333ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
    X4Y4 (CLOCK_ROOT)    net (fo=35, routed)          2.912     3.439    d_1_i/rst_adc0/U0/SEQ/slowest_sync_clk
    SLICE_X103Y62        FDSE                                         r  d_1_i/rst_adc0/U0/SEQ/from_sys_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X103Y62        FDSE (Prop_DFF2_SLICEM_C_Q)
                                                      0.080     3.519 r  d_1_i/rst_adc0/U0/SEQ/from_sys_reg/Q
                         net (fo=10, routed)          0.281     3.799    d_1_i/rst_adc0/U0/SEQ/seq_cnt_en
    SLICE_X103Y63        LUT4 (Prop_C6LUT_SLICEM_I0_O)
                                                      0.088     3.887 r  d_1_i/rst_adc0/U0/SEQ/pr_dec0/O
                         net (fo=1, routed)           0.066     3.953    d_1_i/rst_adc0/U0/SEQ/pr_dec0__0
    SLICE_X103Y63        FDRE                                         r  d_1_i/rst_adc0/U0/SEQ/core_dec_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC0_CLK rise edge)
                                                      3.906     3.906 r  
    HSADC_X0Y0           HSADC                        0.000     3.906 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     4.028 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     4.178    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     4.292 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
    X4Y4 (CLOCK_ROOT)    net (fo=35, routed)          2.584     6.876    d_1_i/rst_adc0/U0/SEQ/slowest_sync_clk
    SLICE_X103Y63        FDRE                                         r  d_1_i/rst_adc0/U0/SEQ/core_dec_reg[1]/C
                         clock pessimism              0.421     7.297    
                         clock uncertainty           -0.035     7.262    
    SLICE_X103Y63        FDRE (Setup_CFF_SLICEM_C_D)
                                                      0.025     7.287    d_1_i/rst_adc0/U0/SEQ/core_dec_reg[1]
  -------------------------------------------------------------------
                         required time                          7.287    
                         arrival time                          -3.953    
  -------------------------------------------------------------------
                         slack                                  3.333    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.037ns  (arrival time - required time)
  Source:                 d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[5]/C
                            (rising edge-triggered cell FDRE clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/rst_adc0/U0/SEQ/core_dec_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             RFADC0_CLK
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (RFADC0_CLK rise@0.000ns - RFADC0_CLK rise@0.000ns)
  Data Path Delay:        0.099ns  (logic 0.063ns (63.577%)  route 0.036ns (36.423%))
  Logic Levels:           1  (LUT4=1)
  Clock Path Skew:        0.015ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.146ns
    Source Clock Delay      (SCD):    1.851ns
    Clock Pessimism Removal (CPR):    0.281ns
  Clock Net Delay (Source):      1.588ns (routing 0.748ns, distribution 0.840ns)
  Clock Net Delay (Destination): 1.794ns (routing 0.844ns, distribution 0.950ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
    X4Y4 (CLOCK_ROOT)    net (fo=35, routed)          1.588     1.851    d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/slowest_sync_clk
    SLICE_X103Y63        FDRE                                         r  d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[5]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X103Y63        FDRE (Prop_GFF_SLICEM_C_Q)
                                                      0.039     1.890 r  d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[5]/Q
                         net (fo=3, routed)           0.027     1.917    d_1_i/rst_adc0/U0/SEQ/seq_cnt[5]
    SLICE_X103Y63        LUT4 (Prop_D5LUT_SLICEM_I3_O)
                                                      0.024     1.941 r  d_1_i/rst_adc0/U0/SEQ/core_dec[0]_i_1/O
                         net (fo=1, routed)           0.009     1.950    d_1_i/rst_adc0/U0/SEQ/core_dec[0]_i_1_n_0
    SLICE_X103Y63        FDRE                                         r  d_1_i/rst_adc0/U0/SEQ/core_dec_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
    X4Y4 (CLOCK_ROOT)    net (fo=35, routed)          1.794     2.146    d_1_i/rst_adc0/U0/SEQ/slowest_sync_clk
    SLICE_X103Y63        FDRE                                         r  d_1_i/rst_adc0/U0/SEQ/core_dec_reg[0]/C
                         clock pessimism             -0.281     1.865    
    SLICE_X103Y63        FDRE (Hold_DFF2_SLICEM_C_D)
                                                      0.047     1.912    d_1_i/rst_adc0/U0/SEQ/core_dec_reg[0]
  -------------------------------------------------------------------
                         required time                         -1.912    
                         arrival time                           1.950    
  -------------------------------------------------------------------
                         slack                                  0.037    

Slack (MET) :             0.038ns  (arrival time - required time)
  Source:                 d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[4]/D
                            (rising edge-triggered cell FDRE clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             RFADC0_CLK
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (RFADC0_CLK rise@0.000ns - RFADC0_CLK rise@0.000ns)
  Data Path Delay:        0.136ns  (logic 0.062ns (45.681%)  route 0.074ns (54.319%))
  Logic Levels:           1  (LUT5=1)
  Clock Path Skew:        0.050ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.145ns
    Source Clock Delay      (SCD):    1.851ns
    Clock Pessimism Removal (CPR):    0.244ns
  Clock Net Delay (Source):      1.588ns (routing 0.748ns, distribution 0.840ns)
  Clock Net Delay (Destination): 1.793ns (routing 0.844ns, distribution 0.949ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
    X4Y4 (CLOCK_ROOT)    net (fo=35, routed)          1.588     1.851    d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/slowest_sync_clk
    SLICE_X104Y63        FDRE                                         r  d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X104Y63        FDRE (Prop_DFF2_SLICEM_C_Q)
                                                      0.041     1.892 r  d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[2]/Q
                         net (fo=5, routed)           0.068     1.960    d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/Q[2]
    SLICE_X103Y63        LUT5 (Prop_H5LUT_SLICEM_I0_O)
                                                      0.021     1.981 r  d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int[4]_i_1/O
                         net (fo=1, routed)           0.006     1.987    d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int0[4]
    SLICE_X103Y63        FDRE                                         r  d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[4]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
    X4Y4 (CLOCK_ROOT)    net (fo=35, routed)          1.793     2.145    d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/slowest_sync_clk
    SLICE_X103Y63        FDRE                                         r  d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[4]/C
                         clock pessimism             -0.244     1.901    
    SLICE_X103Y63        FDRE (Hold_HFF2_SLICEM_C_D)
                                                      0.047     1.948    d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[4]
  -------------------------------------------------------------------
                         required time                         -1.948    
                         arrival time                           1.987    
  -------------------------------------------------------------------
                         slack                                  0.038    

Slack (MET) :             0.039ns  (arrival time - required time)
  Source:                 d_1_i/rst_adc0/U0/EXT_LPF/ACTIVE_LOW_AUX.ACT_LO_AUX/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3/C
                            (rising edge-triggered cell FDRE clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/rst_adc0/U0/EXT_LPF/ACTIVE_LOW_AUX.ACT_LO_AUX/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4/D
                            (rising edge-triggered cell FDRE clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             RFADC0_CLK
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (RFADC0_CLK rise@0.000ns - RFADC0_CLK rise@0.000ns)
  Data Path Delay:        0.091ns  (logic 0.038ns (41.758%)  route 0.053ns (58.242%))
  Logic Levels:           0  
  Clock Path Skew:        0.006ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.146ns
    Source Clock Delay      (SCD):    1.852ns
    Clock Pessimism Removal (CPR):    0.289ns
  Clock Net Delay (Source):      1.589ns (routing 0.748ns, distribution 0.841ns)
  Clock Net Delay (Destination): 1.794ns (routing 0.844ns, distribution 0.950ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
    X4Y4 (CLOCK_ROOT)    net (fo=35, routed)          1.589     1.852    d_1_i/rst_adc0/U0/EXT_LPF/ACTIVE_LOW_AUX.ACT_LO_AUX/slowest_sync_clk
    SLICE_X103Y64        FDRE                                         r  d_1_i/rst_adc0/U0/EXT_LPF/ACTIVE_LOW_AUX.ACT_LO_AUX/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3/C
  -------------------------------------------------------------------    -------------------
    SLICE_X103Y64        FDRE (Prop_BFF_SLICEM_C_Q)
                                                      0.038     1.890 r  d_1_i/rst_adc0/U0/EXT_LPF/ACTIVE_LOW_AUX.ACT_LO_AUX/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3/Q
                         net (fo=1, routed)           0.053     1.943    d_1_i/rst_adc0/U0/EXT_LPF/ACTIVE_LOW_AUX.ACT_LO_AUX/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3
    SLICE_X103Y64        FDRE                                         r  d_1_i/rst_adc0/U0/EXT_LPF/ACTIVE_LOW_AUX.ACT_LO_AUX/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
    X4Y4 (CLOCK_ROOT)    net (fo=35, routed)          1.794     2.146    d_1_i/rst_adc0/U0/EXT_LPF/ACTIVE_LOW_AUX.ACT_LO_AUX/slowest_sync_clk
    SLICE_X103Y64        FDRE                                         r  d_1_i/rst_adc0/U0/EXT_LPF/ACTIVE_LOW_AUX.ACT_LO_AUX/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4/C
                         clock pessimism             -0.289     1.858    
    SLICE_X103Y64        FDRE (Hold_CFF_SLICEM_C_D)
                                                      0.046     1.904    d_1_i/rst_adc0/U0/EXT_LPF/ACTIVE_LOW_AUX.ACT_LO_AUX/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4
  -------------------------------------------------------------------
                         required time                         -1.904    
                         arrival time                           1.943    
  -------------------------------------------------------------------
                         slack                                  0.039    

Slack (MET) :             0.046ns  (arrival time - required time)
  Source:                 d_1_i/rst_adc0/U0/SEQ/pr_dec_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/rst_adc0/U0/SEQ/pr_reg/D
                            (rising edge-triggered cell FDSE clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             RFADC0_CLK
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (RFADC0_CLK rise@0.000ns - RFADC0_CLK rise@0.000ns)
  Data Path Delay:        0.118ns  (logic 0.061ns (51.695%)  route 0.057ns (48.305%))
  Logic Levels:           1  (LUT2=1)
  Clock Path Skew:        0.025ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.150ns
    Source Clock Delay      (SCD):    1.852ns
    Clock Pessimism Removal (CPR):    0.273ns
  Clock Net Delay (Source):      1.589ns (routing 0.748ns, distribution 0.841ns)
  Clock Net Delay (Destination): 1.798ns (routing 0.844ns, distribution 0.954ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
    X4Y4 (CLOCK_ROOT)    net (fo=35, routed)          1.589     1.852    d_1_i/rst_adc0/U0/SEQ/slowest_sync_clk
    SLICE_X103Y63        FDRE                                         r  d_1_i/rst_adc0/U0/SEQ/pr_dec_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X103Y63        FDRE (Prop_BFF_SLICEM_C_Q)
                                                      0.038     1.890 f  d_1_i/rst_adc0/U0/SEQ/pr_dec_reg[2]/Q
                         net (fo=1, routed)           0.049     1.939    d_1_i/rst_adc0/U0/SEQ/pr_dec_reg_n_0_[2]
    SLICE_X103Y62        LUT2 (Prop_C5LUT_SLICEM_I1_O)
                                                      0.023     1.962 r  d_1_i/rst_adc0/U0/SEQ/pr_i_1/O
                         net (fo=1, routed)           0.008     1.970    d_1_i/rst_adc0/U0/SEQ/pr_i_1_n_0
    SLICE_X103Y62        FDSE                                         r  d_1_i/rst_adc0/U0/SEQ/pr_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
    X4Y4 (CLOCK_ROOT)    net (fo=35, routed)          1.798     2.150    d_1_i/rst_adc0/U0/SEQ/slowest_sync_clk
    SLICE_X103Y62        FDSE                                         r  d_1_i/rst_adc0/U0/SEQ/pr_reg/C
                         clock pessimism             -0.273     1.877    
    SLICE_X103Y62        FDSE (Hold_CFF2_SLICEM_C_D)
                                                      0.047     1.924    d_1_i/rst_adc0/U0/SEQ/pr_reg
  -------------------------------------------------------------------
                         required time                         -1.924    
                         arrival time                           1.970    
  -------------------------------------------------------------------
                         slack                                  0.046    

Slack (MET) :             0.050ns  (arrival time - required time)
  Source:                 d_1_i/rst_adc0/U0/EXT_LPF/AUX_LPF[1].asr_lpf_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/rst_adc0/U0/EXT_LPF/AUX_LPF[2].asr_lpf_reg[2]/D
                            (rising edge-triggered cell FDRE clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             RFADC0_CLK
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (RFADC0_CLK rise@0.000ns - RFADC0_CLK rise@0.000ns)
  Data Path Delay:        0.103ns  (logic 0.038ns (36.893%)  route 0.065ns (63.107%))
  Logic Levels:           0  
  Clock Path Skew:        0.006ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.145ns
    Source Clock Delay      (SCD):    1.851ns
    Clock Pessimism Removal (CPR):    0.289ns
  Clock Net Delay (Source):      1.588ns (routing 0.748ns, distribution 0.840ns)
  Clock Net Delay (Destination): 1.793ns (routing 0.844ns, distribution 0.949ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
    X4Y4 (CLOCK_ROOT)    net (fo=35, routed)          1.588     1.851    d_1_i/rst_adc0/U0/EXT_LPF/slowest_sync_clk
    SLICE_X103Y64        FDRE                                         r  d_1_i/rst_adc0/U0/EXT_LPF/AUX_LPF[1].asr_lpf_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X103Y64        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.038     1.889 r  d_1_i/rst_adc0/U0/EXT_LPF/AUX_LPF[1].asr_lpf_reg[1]/Q
                         net (fo=2, routed)           0.065     1.954    d_1_i/rst_adc0/U0/EXT_LPF/p_2_in
    SLICE_X103Y64        FDRE                                         r  d_1_i/rst_adc0/U0/EXT_LPF/AUX_LPF[2].asr_lpf_reg[2]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
    X4Y4 (CLOCK_ROOT)    net (fo=35, routed)          1.793     2.145    d_1_i/rst_adc0/U0/EXT_LPF/slowest_sync_clk
    SLICE_X103Y64        FDRE                                         r  d_1_i/rst_adc0/U0/EXT_LPF/AUX_LPF[2].asr_lpf_reg[2]/C
                         clock pessimism             -0.289     1.857    
    SLICE_X103Y64        FDRE (Hold_EFF2_SLICEM_C_D)
                                                      0.047     1.904    d_1_i/rst_adc0/U0/EXT_LPF/AUX_LPF[2].asr_lpf_reg[2]
  -------------------------------------------------------------------
                         required time                         -1.904    
                         arrival time                           1.954    
  -------------------------------------------------------------------
                         slack                                  0.050    

Slack (MET) :             0.051ns  (arrival time - required time)
  Source:                 d_1_i/rst_adc0/U0/EXT_LPF/EXT_LPF[1].exr_lpf_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/rst_adc0/U0/EXT_LPF/EXT_LPF[2].exr_lpf_reg[2]/D
                            (rising edge-triggered cell FDRE clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             RFADC0_CLK
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (RFADC0_CLK rise@0.000ns - RFADC0_CLK rise@0.000ns)
  Data Path Delay:        0.104ns  (logic 0.038ns (36.574%)  route 0.066ns (63.426%))
  Logic Levels:           0  
  Clock Path Skew:        0.006ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.144ns
    Source Clock Delay      (SCD):    1.851ns
    Clock Pessimism Removal (CPR):    0.288ns
  Clock Net Delay (Source):      1.588ns (routing 0.748ns, distribution 0.840ns)
  Clock Net Delay (Destination): 1.792ns (routing 0.844ns, distribution 0.948ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
    X4Y4 (CLOCK_ROOT)    net (fo=35, routed)          1.588     1.851    d_1_i/rst_adc0/U0/EXT_LPF/slowest_sync_clk
    SLICE_X103Y65        FDRE                                         r  d_1_i/rst_adc0/U0/EXT_LPF/EXT_LPF[1].exr_lpf_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X103Y65        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.038     1.889 r  d_1_i/rst_adc0/U0/EXT_LPF/EXT_LPF[1].exr_lpf_reg[1]/Q
                         net (fo=2, routed)           0.066     1.954    d_1_i/rst_adc0/U0/EXT_LPF/p_2_in3_in
    SLICE_X103Y65        FDRE                                         r  d_1_i/rst_adc0/U0/EXT_LPF/EXT_LPF[2].exr_lpf_reg[2]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
    X4Y4 (CLOCK_ROOT)    net (fo=35, routed)          1.792     2.144    d_1_i/rst_adc0/U0/EXT_LPF/slowest_sync_clk
    SLICE_X103Y65        FDRE                                         r  d_1_i/rst_adc0/U0/EXT_LPF/EXT_LPF[2].exr_lpf_reg[2]/C
                         clock pessimism             -0.288     1.857    
    SLICE_X103Y65        FDRE (Hold_EFF2_SLICEM_C_D)
                                                      0.047     1.904    d_1_i/rst_adc0/U0/EXT_LPF/EXT_LPF[2].exr_lpf_reg[2]
  -------------------------------------------------------------------
                         required time                         -1.904    
                         arrival time                           1.954    
  -------------------------------------------------------------------
                         slack                                  0.051    

Slack (MET) :             0.052ns  (arrival time - required time)
  Source:                 d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/rst_adc0/U0/SEQ/core_dec_reg[1]/D
                            (rising edge-triggered cell FDRE clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             RFADC0_CLK
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (RFADC0_CLK rise@0.000ns - RFADC0_CLK rise@0.000ns)
  Data Path Delay:        0.149ns  (logic 0.061ns (41.001%)  route 0.088ns (58.999%))
  Logic Levels:           1  (LUT4=1)
  Clock Path Skew:        0.051ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.146ns
    Source Clock Delay      (SCD):    1.851ns
    Clock Pessimism Removal (CPR):    0.244ns
  Clock Net Delay (Source):      1.588ns (routing 0.748ns, distribution 0.840ns)
  Clock Net Delay (Destination): 1.794ns (routing 0.844ns, distribution 0.950ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
    X4Y4 (CLOCK_ROOT)    net (fo=35, routed)          1.588     1.851    d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/slowest_sync_clk
    SLICE_X104Y63        FDRE                                         r  d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X104Y63        FDRE (Prop_DFF_SLICEM_C_Q)
                                                      0.039     1.890 f  d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[1]/Q
                         net (fo=6, routed)           0.064     1.954    d_1_i/rst_adc0/U0/SEQ/seq_cnt[1]
    SLICE_X103Y63        LUT4 (Prop_C6LUT_SLICEM_I3_O)
                                                      0.022     1.976 r  d_1_i/rst_adc0/U0/SEQ/pr_dec0/O
                         net (fo=1, routed)           0.024     2.000    d_1_i/rst_adc0/U0/SEQ/pr_dec0__0
    SLICE_X103Y63        FDRE                                         r  d_1_i/rst_adc0/U0/SEQ/core_dec_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
    X4Y4 (CLOCK_ROOT)    net (fo=35, routed)          1.794     2.146    d_1_i/rst_adc0/U0/SEQ/slowest_sync_clk
    SLICE_X103Y63        FDRE                                         r  d_1_i/rst_adc0/U0/SEQ/core_dec_reg[1]/C
                         clock pessimism             -0.244     1.902    
    SLICE_X103Y63        FDRE (Hold_CFF_SLICEM_C_D)
                                                      0.046     1.948    d_1_i/rst_adc0/U0/SEQ/core_dec_reg[1]
  -------------------------------------------------------------------
                         required time                         -1.948    
                         arrival time                           2.000    
  -------------------------------------------------------------------
                         slack                                  0.052    

Slack (MET) :             0.052ns  (arrival time - required time)
  Source:                 d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[5]/D
                            (rising edge-triggered cell FDRE clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             RFADC0_CLK
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (RFADC0_CLK rise@0.000ns - RFADC0_CLK rise@0.000ns)
  Data Path Delay:        0.104ns  (logic 0.053ns (50.908%)  route 0.051ns (49.092%))
  Logic Levels:           1  (LUT6=1)
  Clock Path Skew:        0.006ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.145ns
    Source Clock Delay      (SCD):    1.851ns
    Clock Pessimism Removal (CPR):    0.289ns
  Clock Net Delay (Source):      1.588ns (routing 0.748ns, distribution 0.840ns)
  Clock Net Delay (Destination): 1.793ns (routing 0.844ns, distribution 0.949ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
    X4Y4 (CLOCK_ROOT)    net (fo=35, routed)          1.588     1.851    d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/slowest_sync_clk
    SLICE_X103Y63        FDRE                                         r  d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X103Y63        FDRE (Prop_HFF_SLICEM_C_Q)
                                                      0.039     1.890 r  d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[3]/Q
                         net (fo=5, routed)           0.030     1.920    d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/Q[3]
    SLICE_X103Y63        LUT6 (Prop_G6LUT_SLICEM_I0_O)
                                                      0.014     1.934 r  d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int[5]_i_2/O
                         net (fo=1, routed)           0.021     1.955    d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int0[5]
    SLICE_X103Y63        FDRE                                         r  d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[5]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
    X4Y4 (CLOCK_ROOT)    net (fo=35, routed)          1.793     2.145    d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/slowest_sync_clk
    SLICE_X103Y63        FDRE                                         r  d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[5]/C
                         clock pessimism             -0.289     1.857    
    SLICE_X103Y63        FDRE (Hold_GFF_SLICEM_C_D)
                                                      0.046     1.903    d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[5]
  -------------------------------------------------------------------
                         required time                         -1.903    
                         arrival time                           1.955    
  -------------------------------------------------------------------
                         slack                                  0.052    

Slack (MET) :             0.053ns  (arrival time - required time)
  Source:                 d_1_i/rst_adc0/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4/C
                            (rising edge-triggered cell FDRE clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/rst_adc0/U0/EXT_LPF/EXT_LPF[1].exr_lpf_reg[1]/D
                            (rising edge-triggered cell FDRE clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             RFADC0_CLK
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (RFADC0_CLK rise@0.000ns - RFADC0_CLK rise@0.000ns)
  Data Path Delay:        0.118ns  (logic 0.038ns (32.199%)  route 0.080ns (67.801%))
  Logic Levels:           0  
  Clock Path Skew:        0.019ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.144ns
    Source Clock Delay      (SCD):    1.852ns
    Clock Pessimism Removal (CPR):    0.274ns
  Clock Net Delay (Source):      1.589ns (routing 0.748ns, distribution 0.841ns)
  Clock Net Delay (Destination): 1.792ns (routing 0.844ns, distribution 0.948ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
    X4Y4 (CLOCK_ROOT)    net (fo=35, routed)          1.589     1.852    d_1_i/rst_adc0/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/slowest_sync_clk
    SLICE_X103Y63        FDRE                                         r  d_1_i/rst_adc0/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4/C
  -------------------------------------------------------------------    -------------------
    SLICE_X103Y63        FDRE (Prop_AFF_SLICEM_C_Q)
                                                      0.038     1.890 r  d_1_i/rst_adc0/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4/Q
                         net (fo=2, routed)           0.080     1.970    d_1_i/rst_adc0/U0/EXT_LPF/p_3_in6_in
    SLICE_X103Y65        FDRE                                         r  d_1_i/rst_adc0/U0/EXT_LPF/EXT_LPF[1].exr_lpf_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
    X4Y4 (CLOCK_ROOT)    net (fo=35, routed)          1.792     2.144    d_1_i/rst_adc0/U0/EXT_LPF/slowest_sync_clk
    SLICE_X103Y65        FDRE                                         r  d_1_i/rst_adc0/U0/EXT_LPF/EXT_LPF[1].exr_lpf_reg[1]/C
                         clock pessimism             -0.274     1.871    
    SLICE_X103Y65        FDRE (Hold_EFF_SLICEM_C_D)
                                                      0.046     1.917    d_1_i/rst_adc0/U0/EXT_LPF/EXT_LPF[1].exr_lpf_reg[1]
  -------------------------------------------------------------------
                         required time                         -1.917    
                         arrival time                           1.970    
  -------------------------------------------------------------------
                         slack                                  0.053    

Slack (MET) :             0.053ns  (arrival time - required time)
  Source:                 d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[5]/C
                            (rising edge-triggered cell FDRE clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/rst_adc0/U0/SEQ/pr_dec_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             RFADC0_CLK
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (RFADC0_CLK rise@0.000ns - RFADC0_CLK rise@0.000ns)
  Data Path Delay:        0.114ns  (logic 0.061ns (53.465%)  route 0.053ns (46.535%))
  Logic Levels:           1  (LUT4=1)
  Clock Path Skew:        0.015ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.146ns
    Source Clock Delay      (SCD):    1.851ns
    Clock Pessimism Removal (CPR):    0.281ns
  Clock Net Delay (Source):      1.588ns (routing 0.748ns, distribution 0.840ns)
  Clock Net Delay (Destination): 1.794ns (routing 0.844ns, distribution 0.950ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
    X4Y4 (CLOCK_ROOT)    net (fo=35, routed)          1.588     1.851    d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/slowest_sync_clk
    SLICE_X103Y63        FDRE                                         r  d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[5]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X103Y63        FDRE (Prop_GFF_SLICEM_C_Q)
                                                      0.039     1.890 r  d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[5]/Q
                         net (fo=3, routed)           0.027     1.917    d_1_i/rst_adc0/U0/SEQ/seq_cnt[5]
    SLICE_X103Y63        LUT4 (Prop_D6LUT_SLICEM_I2_O)
                                                      0.022     1.939 r  d_1_i/rst_adc0/U0/SEQ/pr_dec[0]_i_1/O
                         net (fo=1, routed)           0.026     1.965    d_1_i/rst_adc0/U0/SEQ/p_3_out[0]
    SLICE_X103Y63        FDRE                                         r  d_1_i/rst_adc0/U0/SEQ/pr_dec_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
    X4Y4 (CLOCK_ROOT)    net (fo=35, routed)          1.794     2.146    d_1_i/rst_adc0/U0/SEQ/slowest_sync_clk
    SLICE_X103Y63        FDRE                                         r  d_1_i/rst_adc0/U0/SEQ/pr_dec_reg[0]/C
                         clock pessimism             -0.281     1.865    
    SLICE_X103Y63        FDRE (Hold_DFF_SLICEM_C_D)
                                                      0.046     1.911    d_1_i/rst_adc0/U0/SEQ/pr_dec_reg[0]
  -------------------------------------------------------------------
                         required time                         -1.911    
                         arrival time                           1.965    
  -------------------------------------------------------------------
                         slack                                  0.053    





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         RFADC0_CLK
Waveform(ns):       { 0.000 1.953 }
Period(ns):         3.906
Sources:            { d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX }

Check Type        Corner  Lib Pin            Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location       Pin
Min Period        n/a     HSADC/CLK_ADC      n/a            1.923         3.906       1.983      HSADC_X0Y0     d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
Min Period        n/a     BUFG_GT/I          n/a            1.290         3.906       2.616      BUFG_GT_X1Y1   d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/I
Min Period        n/a     MMCME4_ADV/CLKIN1  n/a            1.071         3.906       2.835      MMCM_X0Y7      d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKIN1
Min Period        n/a     SRL16E/CLK         n/a            1.064         3.906       2.842      SLICE_X103Y62  d_1_i/rst_adc0/U0/EXT_LPF/POR_SRL_I/CLK
Min Period        n/a     FDRE/C             n/a            0.550         3.906       3.356      SLICE_X89Y62   d_1_i/rst_adc0/U0/PR_OUT_DFF[0].FDRE_PER/C
Min Period        n/a     FDRE/C             n/a            0.550         3.906       3.356      SLICE_X103Y64  d_1_i/rst_adc0/U0/EXT_LPF/AUX_LPF[1].asr_lpf_reg[1]/C
Min Period        n/a     FDRE/C             n/a            0.550         3.906       3.356      SLICE_X103Y64  d_1_i/rst_adc0/U0/EXT_LPF/AUX_LPF[2].asr_lpf_reg[2]/C
Min Period        n/a     FDRE/C             n/a            0.550         3.906       3.356      SLICE_X103Y64  d_1_i/rst_adc0/U0/EXT_LPF/AUX_LPF[3].asr_lpf_reg[3]/C
Min Period        n/a     FDRE/C             n/a            0.550         3.906       3.356      SLICE_X103Y65  d_1_i/rst_adc0/U0/EXT_LPF/EXT_LPF[1].exr_lpf_reg[1]/C
Min Period        n/a     FDRE/C             n/a            0.550         3.906       3.356      SLICE_X103Y65  d_1_i/rst_adc0/U0/EXT_LPF/EXT_LPF[2].exr_lpf_reg[2]/C
Max Period        n/a     MMCME4_ADV/CLKIN1  n/a            100.000       3.906       96.094     MMCM_X0Y7      d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKIN1
Low Pulse Width   Slow    MMCME4_ADV/CLKIN1  n/a            1.367         1.953       0.586      MMCM_X0Y7      d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKIN1
Low Pulse Width   Fast    MMCME4_ADV/CLKIN1  n/a            1.367         1.953       0.586      MMCM_X0Y7      d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKIN1
Low Pulse Width   Slow    HSADC/CLK_ADC      n/a            0.800         1.953       1.153      HSADC_X0Y0     d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
Low Pulse Width   Fast    HSADC/CLK_ADC      n/a            0.800         1.953       1.153      HSADC_X0Y0     d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
Low Pulse Width   Slow    SRL16E/CLK         n/a            0.532         1.953       1.421      SLICE_X103Y62  d_1_i/rst_adc0/U0/EXT_LPF/POR_SRL_I/CLK
Low Pulse Width   Fast    SRL16E/CLK         n/a            0.532         1.953       1.421      SLICE_X103Y62  d_1_i/rst_adc0/U0/EXT_LPF/POR_SRL_I/CLK
Low Pulse Width   Slow    FDRE/C             n/a            0.275         1.953       1.678      SLICE_X89Y62   d_1_i/rst_adc0/U0/PR_OUT_DFF[0].FDRE_PER/C
Low Pulse Width   Fast    FDRE/C             n/a            0.275         1.953       1.678      SLICE_X89Y62   d_1_i/rst_adc0/U0/PR_OUT_DFF[0].FDRE_PER/C
Low Pulse Width   Slow    FDRE/C             n/a            0.275         1.953       1.678      SLICE_X103Y64  d_1_i/rst_adc0/U0/EXT_LPF/AUX_LPF[1].asr_lpf_reg[1]/C
Low Pulse Width   Fast    FDRE/C             n/a            0.275         1.953       1.678      SLICE_X103Y64  d_1_i/rst_adc0/U0/EXT_LPF/AUX_LPF[1].asr_lpf_reg[1]/C
High Pulse Width  Slow    MMCME4_ADV/CLKIN1  n/a            1.367         1.953       0.586      MMCM_X0Y7      d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKIN1
High Pulse Width  Fast    MMCME4_ADV/CLKIN1  n/a            1.367         1.953       0.586      MMCM_X0Y7      d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKIN1
High Pulse Width  Slow    HSADC/CLK_ADC      n/a            0.800         1.953       1.153      HSADC_X0Y0     d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
High Pulse Width  Fast    HSADC/CLK_ADC      n/a            0.800         1.953       1.153      HSADC_X0Y0     d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
High Pulse Width  Slow    SRL16E/CLK         n/a            0.532         1.953       1.421      SLICE_X103Y62  d_1_i/rst_adc0/U0/EXT_LPF/POR_SRL_I/CLK
High Pulse Width  Fast    SRL16E/CLK         n/a            0.532         1.953       1.421      SLICE_X103Y62  d_1_i/rst_adc0/U0/EXT_LPF/POR_SRL_I/CLK
High Pulse Width  Slow    FDRE/C             n/a            0.275         1.953       1.678      SLICE_X89Y62   d_1_i/rst_adc0/U0/PR_OUT_DFF[0].FDRE_PER/C
High Pulse Width  Fast    FDRE/C             n/a            0.275         1.953       1.678      SLICE_X89Y62   d_1_i/rst_adc0/U0/PR_OUT_DFF[0].FDRE_PER/C
High Pulse Width  Slow    FDRE/C             n/a            0.275         1.953       1.678      SLICE_X103Y64  d_1_i/rst_adc0/U0/EXT_LPF/AUX_LPF[1].asr_lpf_reg[1]/C
High Pulse Width  Fast    FDRE/C             n/a            0.275         1.953       1.678      SLICE_X103Y64  d_1_i/rst_adc0/U0/EXT_LPF/AUX_LPF[1].asr_lpf_reg[1]/C



---------------------------------------------------------------------------------------------------
From Clock:  clk_out1_d_1_clk_adc0_x2_0
  To Clock:  clk_out1_d_1_clk_adc0_x2_0

Setup :            0  Failing Endpoints,  Worst Slack        0.001ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.010ns,  Total Violation        0.000ns
PW    :            0  Failing Endpoints,  Worst Slack        0.030ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.001ns  (required time - arrival time)
  Source:                 d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_m_data_chan_no_fifo.m_axis_data_tdata_int_reg[30]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_dwidth_converter_0/inst/gen_upsizer_conversion.axisc_upsizer_0/acc_data_reg[510]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             clk_out1_d_1_clk_adc0_x2_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            1.953ns  (clk_out1_d_1_clk_adc0_x2_0 rise@1.953ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        1.882ns  (logic 0.170ns (9.033%)  route 1.712ns (90.967%))
  Logic Levels:           1  (LUT6=1)
  Clock Path Skew:        -0.044ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    6.399ns = ( 8.352 - 1.953 ) 
    Source Clock Delay      (SCD):    6.273ns
    Clock Pessimism Removal (CPR):    -0.170ns
  Clock Uncertainty:      0.051ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.074ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.943ns (routing 1.545ns, distribution 1.398ns)
  Clock Net Delay (Destination): 2.754ns (routing 1.400ns, distribution 1.354ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.657     3.184    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     3.057 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     3.302    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.330 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86296, routed)       2.943     6.273    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/aclk
    SLICE_X80Y202        FDRE                                         r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_m_data_chan_no_fifo.m_axis_data_tdata_int_reg[30]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X80Y202        FDRE (Prop_HFF2_SLICEL_C_Q)
                                                      0.080     6.353 r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_m_data_chan_no_fifo.m_axis_data_tdata_int_reg[30]/Q
                         net (fo=4, routed)           1.082     7.435    d_1_i/axis_switch_ddr/inst/s_axis_tdata[30]
    SLICE_X90Y261        LUT6 (Prop_G6LUT_SLICEM_I5_O)
                                                      0.090     7.525 r  d_1_i/axis_switch_ddr/inst/m_axis_tdata[30]_INST_0/O
                         net (fo=2, routed)           0.630     8.155    d_1_i/axis_dwidth_converter_0/inst/gen_upsizer_conversion.axisc_upsizer_0/s_axis_tdata[30]
    SLICE_X82Y249        FDRE                                         r  d_1_i/axis_dwidth_converter_0/inst/gen_upsizer_conversion.axisc_upsizer_0/acc_data_reg[510]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      1.953     1.953 r  
    HSADC_X0Y0           HSADC                        0.000     1.953 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     2.075 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     2.225    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     2.339 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.389     4.728    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.358 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.216     5.574    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     5.598 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86296, routed)       2.754     8.352    d_1_i/axis_dwidth_converter_0/inst/gen_upsizer_conversion.axisc_upsizer_0/aclk
    SLICE_X82Y249        FDRE                                         r  d_1_i/axis_dwidth_converter_0/inst/gen_upsizer_conversion.axisc_upsizer_0/acc_data_reg[510]/C
                         clock pessimism             -0.170     8.182    
                         clock uncertainty           -0.051     8.131    
    SLICE_X82Y249        FDRE (Setup_AFF_SLICEM_C_D)
                                                      0.025     8.156    d_1_i/axis_dwidth_converter_0/inst/gen_upsizer_conversion.axisc_upsizer_0/acc_data_reg[510]
  -------------------------------------------------------------------
                         required time                          8.156    
                         arrival time                          -8.155    
  -------------------------------------------------------------------
                         slack                                  0.001    

Slack (MET) :             0.011ns  (required time - arrival time)
  Source:                 d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_m_data_chan_no_fifo.m_axis_data_tdata_int_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/high_state_reg/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             clk_out1_d_1_clk_adc0_x2_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            1.953ns  (clk_out1_d_1_clk_adc0_x2_0 rise@1.953ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        1.809ns  (logic 0.450ns (24.876%)  route 1.359ns (75.124%))
  Logic Levels:           3  (CARRY8=1 LUT4=2)
  Clock Path Skew:        -0.107ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    6.317ns = ( 8.270 - 1.953 ) 
    Source Clock Delay      (SCD):    6.258ns
    Clock Pessimism Removal (CPR):    -0.166ns
  Clock Uncertainty:      0.051ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.074ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.928ns (routing 1.545ns, distribution 1.383ns)
  Clock Net Delay (Destination): 2.672ns (routing 1.400ns, distribution 1.272ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.657     3.184    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     3.057 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     3.302    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.330 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86296, routed)       2.928     6.258    d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/aclk
    SLICE_X80Y209        FDRE                                         r  d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_m_data_chan_no_fifo.m_axis_data_tdata_int_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X80Y209        FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.079     6.337 r  d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_m_data_chan_no_fifo.m_axis_data_tdata_int_reg[0]/Q
                         net (fo=9, routed)           0.791     7.128    d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/s_axis_tdata[0]
    SLICE_X81Y170        LUT4 (Prop_A6LUT_SLICEL_I1_O)
                                                      0.124     7.252 r  d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/high_state1_carry_i_16/O
                         net (fo=1, routed)           0.009     7.261    d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/high_state1_carry_i_16_n_0
    SLICE_X81Y170        CARRY8 (Prop_CARRY8_SLICEL_S[0]_CO[7])
                                                      0.197     7.458 f  d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/high_state1_carry/CO[7]
                         net (fo=1, routed)           0.511     7.969    d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/high_state1_carry_n_0
    SLICE_X80Y162        LUT4 (Prop_A6LUT_SLICEL_I2_O)
                                                      0.050     8.019 r  d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/high_state_i_1/O
                         net (fo=1, routed)           0.048     8.067    d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/high_state_i_1_n_0
    SLICE_X80Y162        FDRE                                         r  d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/high_state_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      1.953     1.953 r  
    HSADC_X0Y0           HSADC                        0.000     1.953 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     2.075 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     2.225    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     2.339 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.389     4.728    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.358 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.216     5.574    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     5.598 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86296, routed)       2.672     8.270    d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/s_axis_aclk
    SLICE_X80Y162        FDRE                                         r  d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/high_state_reg/C
                         clock pessimism             -0.166     8.104    
                         clock uncertainty           -0.051     8.053    
    SLICE_X80Y162        FDRE (Setup_AFF_SLICEL_C_D)
                                                      0.025     8.078    d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/high_state_reg
  -------------------------------------------------------------------
                         required time                          8.078    
                         arrival time                          -8.067    
  -------------------------------------------------------------------
                         slack                                  0.011    

Slack (MET) :             0.015ns  (required time - arrival time)
  Source:                 d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.i_cntrl_src/g_parallel.we_gen_reg_srl2_srlopt_replica_1/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[12].g_symmetric.g_data_array.g_data[1].g_data_buff.i_data_buf/g_buff.i_buff/gen_reg.d_reg_reg[14]/CE
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             clk_out1_d_1_clk_adc0_x2_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            1.953ns  (clk_out1_d_1_clk_adc0_x2_0 rise@1.953ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        1.641ns  (logic 0.079ns (4.814%)  route 1.562ns (95.186%))
  Logic Levels:           0  
  Clock Path Skew:        -0.186ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    6.363ns = ( 8.316 - 1.953 ) 
    Source Clock Delay      (SCD):    6.402ns
    Clock Pessimism Removal (CPR):    -0.147ns
  Clock Uncertainty:      0.051ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.074ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      3.072ns (routing 1.545ns, distribution 1.527ns)
  Clock Net Delay (Destination): 2.718ns (routing 1.400ns, distribution 1.318ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.657     3.184    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     3.057 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     3.302    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.330 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86296, routed)       3.072     6.402    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.i_cntrl_src/aclk
    SLICE_X85Y79         FDRE                                         r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.i_cntrl_src/g_parallel.we_gen_reg_srl2_srlopt_replica_1/C
  -------------------------------------------------------------------    -------------------
    SLICE_X85Y79         FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.079     6.481 r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.i_cntrl_src/g_parallel.we_gen_reg_srl2_srlopt_replica_1/Q
                         net (fo=240, routed)         1.562     8.043    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[12].g_symmetric.g_data_array.g_data[1].g_data_buff.i_data_buf/g_buff.i_buff/g_parallel.cntrl[-1]_4_repN_1_alias
    SLICE_X81Y128        FDRE                                         r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[12].g_symmetric.g_data_array.g_data[1].g_data_buff.i_data_buf/g_buff.i_buff/gen_reg.d_reg_reg[14]/CE
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      1.953     1.953 r  
    HSADC_X0Y0           HSADC                        0.000     1.953 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     2.075 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     2.225    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     2.339 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.389     4.728    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.358 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.216     5.574    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     5.598 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86296, routed)       2.718     8.316    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[12].g_symmetric.g_data_array.g_data[1].g_data_buff.i_data_buf/g_buff.i_buff/aclk
    SLICE_X81Y128        FDRE                                         r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[12].g_symmetric.g_data_array.g_data[1].g_data_buff.i_data_buf/g_buff.i_buff/gen_reg.d_reg_reg[14]/C
                         clock pessimism             -0.147     8.169    
                         clock uncertainty           -0.051     8.118    
    SLICE_X81Y128        FDRE (Setup_HFF_SLICEL_C_CE)
                                                     -0.060     8.058    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[12].g_symmetric.g_data_array.g_data[1].g_data_buff.i_data_buf/g_buff.i_buff/gen_reg.d_reg_reg[14]
  -------------------------------------------------------------------
                         required time                          8.058    
                         arrival time                          -8.043    
  -------------------------------------------------------------------
                         slack                                  0.015    

Slack (MET) :             0.016ns  (required time - arrival time)
  Source:                 d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/addr_r_reg[13]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_15/ENARDEN
                            (rising edge-triggered cell RAMB36E2 clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             clk_out1_d_1_clk_adc0_x2_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            1.953ns  (clk_out1_d_1_clk_adc0_x2_0 rise@1.953ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        1.445ns  (logic 0.225ns (15.572%)  route 1.220ns (84.428%))
  Logic Levels:           1  (LUT4=1)
  Clock Path Skew:        -0.099ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    6.284ns = ( 8.237 - 1.953 ) 
    Source Clock Delay      (SCD):    6.295ns
    Clock Pessimism Removal (CPR):    -0.088ns
  Clock Uncertainty:      0.051ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.074ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.965ns (routing 1.545ns, distribution 1.420ns)
  Clock Net Delay (Destination): 2.639ns (routing 1.400ns, distribution 1.239ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.657     3.184    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     3.057 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     3.302    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.330 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86296, routed)       2.965     6.295    d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/s_axis_aclk
    SLICE_X79Y123        FDRE                                         r  d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/addr_r_reg[13]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X79Y123        FDRE (Prop_AFF_SLICEM_C_Q)
                                                      0.077     6.372 r  d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/addr_r_reg[13]/Q
                         net (fo=33, routed)          0.757     7.129    d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/addr_r_reg[13]_1[13]
    SLICE_X65Y119        LUT4 (Prop_B6LUT_SLICEL_I0_O)
                                                      0.148     7.277 r  d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/RAM_reg_bram_15_i_1/O
                         net (fo=1, routed)           0.463     7.740    d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_15_0
    RAMB36_X6Y25         RAMB36E2                                     r  d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_15/ENARDEN
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      1.953     1.953 r  
    HSADC_X0Y0           HSADC                        0.000     1.953 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     2.075 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     2.225    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     2.339 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.389     4.728    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.358 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.216     5.574    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     5.598 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86296, routed)       2.639     8.237    d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/bram_i/s_axis_aclk
    RAMB36_X6Y25         RAMB36E2                                     r  d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_15/CLKARDCLK
                         clock pessimism             -0.088     8.149    
                         clock uncertainty           -0.051     8.098    
    RAMB36_X6Y25         RAMB36E2 (Setup_RAMB36E2_RAMB36_CLKARDCLK_ENARDEN)
                                                     -0.342     7.756    d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_15
  -------------------------------------------------------------------
                         required time                          7.756    
                         arrival time                          -7.740    
  -------------------------------------------------------------------
                         slack                                  0.016    

Slack (MET) :             0.017ns  (required time - arrival time)
  Source:                 d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.i_cntrl_src/g_parallel.we_gen_reg_srl2_srlopt_replica_6/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[9].g_symmetric.g_data_array.g_data[43].g_data_buff.i_data_buf/g_buff.i_buff/gen_reg.d_reg_reg[15]/CE
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             clk_out1_d_1_clk_adc0_x2_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            1.953ns  (clk_out1_d_1_clk_adc0_x2_0 rise@1.953ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        1.652ns  (logic 0.081ns (4.904%)  route 1.571ns (95.096%))
  Logic Levels:           0  
  Clock Path Skew:        -0.172ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    6.393ns = ( 8.346 - 1.953 ) 
    Source Clock Delay      (SCD):    6.418ns
    Clock Pessimism Removal (CPR):    -0.147ns
  Clock Uncertainty:      0.051ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.074ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      3.088ns (routing 1.545ns, distribution 1.543ns)
  Clock Net Delay (Destination): 2.748ns (routing 1.400ns, distribution 1.348ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.657     3.184    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     3.057 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     3.302    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.330 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86296, routed)       3.088     6.418    d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.i_cntrl_src/aclk
    SLICE_X91Y171        FDRE                                         r  d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.i_cntrl_src/g_parallel.we_gen_reg_srl2_srlopt_replica_6/C
  -------------------------------------------------------------------    -------------------
    SLICE_X91Y171        FDRE (Prop_DFF2_SLICEL_C_Q)
                                                      0.081     6.499 r  d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.i_cntrl_src/g_parallel.we_gen_reg_srl2_srlopt_replica_6/Q
                         net (fo=246, routed)         1.571     8.070    d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[9].g_symmetric.g_data_array.g_data[43].g_data_buff.i_data_buf/g_buff.i_buff/g_parallel.cntrl[-1]_4_repN_6_alias
    SLICE_X89Y95         FDRE                                         r  d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[9].g_symmetric.g_data_array.g_data[43].g_data_buff.i_data_buf/g_buff.i_buff/gen_reg.d_reg_reg[15]/CE
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      1.953     1.953 r  
    HSADC_X0Y0           HSADC                        0.000     1.953 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     2.075 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     2.225    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     2.339 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.389     4.728    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.358 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.216     5.574    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     5.598 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86296, routed)       2.748     8.346    d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[9].g_symmetric.g_data_array.g_data[43].g_data_buff.i_data_buf/g_buff.i_buff/aclk
    SLICE_X89Y95         FDRE                                         r  d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[9].g_symmetric.g_data_array.g_data[43].g_data_buff.i_data_buf/g_buff.i_buff/gen_reg.d_reg_reg[15]/C
                         clock pessimism             -0.147     8.199    
                         clock uncertainty           -0.051     8.147    
    SLICE_X89Y95         FDRE (Setup_DFF_SLICEM_C_CE)
                                                     -0.061     8.086    d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[9].g_symmetric.g_data_array.g_data[43].g_data_buff.i_data_buf/g_buff.i_buff/gen_reg.d_reg_reg[15]
  -------------------------------------------------------------------
                         required time                          8.086    
                         arrival time                          -8.070    
  -------------------------------------------------------------------
                         slack                                  0.017    

Slack (MET) :             0.024ns  (required time - arrival time)
  Source:                 d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/out_result_r_reg[15]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_0/DINADIN[15]
                            (rising edge-triggered cell RAMB36E2 clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             clk_out1_d_1_clk_adc0_x2_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            1.953ns  (clk_out1_d_1_clk_adc0_x2_0 rise@1.953ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        1.489ns  (logic 0.078ns (5.238%)  route 1.411ns (94.762%))
  Logic Levels:           0  
  Clock Path Skew:        -0.132ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    6.310ns = ( 8.263 - 1.953 ) 
    Source Clock Delay      (SCD):    6.295ns
    Clock Pessimism Removal (CPR):    -0.147ns
  Clock Uncertainty:      0.051ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.074ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.965ns (routing 1.545ns, distribution 1.420ns)
  Clock Net Delay (Destination): 2.665ns (routing 1.400ns, distribution 1.265ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.657     3.184    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     3.057 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     3.302    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.330 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86296, routed)       2.965     6.295    d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/s_axis_aclk
    SLICE_X79Y177        FDRE                                         r  d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/out_result_r_reg[15]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X79Y177        FDRE (Prop_HFF2_SLICEM_C_Q)
                                                      0.078     6.373 r  d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/out_result_r_reg[15]/Q
                         net (fo=17, routed)          1.411     7.784    d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/bram_i/dia[15]
    RAMB36_X7Y12         RAMB36E2                                     r  d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_0/DINADIN[15]
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      1.953     1.953 r  
    HSADC_X0Y0           HSADC                        0.000     1.953 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     2.075 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     2.225    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     2.339 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.389     4.728    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.358 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.216     5.574    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     5.598 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86296, routed)       2.665     8.263    d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/bram_i/s_axis_aclk
    RAMB36_X7Y12         RAMB36E2                                     r  d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_0/CLKARDCLK
                         clock pessimism             -0.147     8.116    
                         clock uncertainty           -0.051     8.065    
    RAMB36_X7Y12         RAMB36E2 (Setup_RAMB36E2_RAMB36_CLKARDCLK_DINADIN[15])
                                                     -0.257     7.808    d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_0
  -------------------------------------------------------------------
                         required time                          7.808    
                         arrival time                          -7.784    
  -------------------------------------------------------------------
                         slack                                  0.024    

Slack (MET) :             0.025ns  (required time - arrival time)
  Source:                 d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/len_r_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/FSM_onehot_state_reg[4]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             clk_out1_d_1_clk_adc0_x2_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            1.953ns  (clk_out1_d_1_clk_adc0_x2_0 rise@1.953ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        1.807ns  (logic 0.783ns (43.331%)  route 1.024ns (56.669%))
  Logic Levels:           6  (CARRY8=3 LUT1=1 LUT3=1 LUT6=1)
  Clock Path Skew:        -0.095ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    6.351ns = ( 8.304 - 1.953 ) 
    Source Clock Delay      (SCD):    6.365ns
    Clock Pessimism Removal (CPR):    -0.081ns
  Clock Uncertainty:      0.051ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.074ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      3.035ns (routing 1.545ns, distribution 1.490ns)
  Clock Net Delay (Destination): 2.706ns (routing 1.400ns, distribution 1.306ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.657     3.184    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     3.057 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     3.302    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.330 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86296, routed)       3.035     6.365    d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/s_axis_aclk
    SLICE_X81Y164        FDRE                                         r  d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/len_r_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y164        FDRE (Prop_EFF2_SLICEL_C_Q)
                                                      0.081     6.446 f  d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/len_r_reg[1]/Q
                         net (fo=2, routed)           0.132     6.578    d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/len_r[1]
    SLICE_X81Y164        LUT1 (Prop_A6LUT_SLICEL_I0_O)
                                                      0.098     6.676 r  d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/state3_carry_i_8/O
                         net (fo=1, routed)           0.009     6.685    d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/state3_carry_i_8_n_0
    SLICE_X81Y164        CARRY8 (Prop_CARRY8_SLICEL_S[0]_O[5])
                                                      0.238     6.923 r  d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/state3_carry/O[5]
                         net (fo=1, routed)           0.411     7.334    d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/state3[6]
    SLICE_X81Y168        LUT6 (Prop_C6LUT_SLICEL_I1_O)
                                                      0.088     7.422 r  d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/state2_carry_i_6/O
                         net (fo=1, routed)           0.010     7.432    d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/state2_carry_i_6_n_0
    SLICE_X81Y168        CARRY8 (Prop_CARRY8_SLICEL_S[2]_CO[7])
                                                      0.155     7.587 r  d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/state2_carry/CO[7]
                         net (fo=1, routed)           0.026     7.613    d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/state2_carry_n_0
    SLICE_X81Y169        CARRY8 (Prop_CARRY8_SLICEL_CI_CO[2])
                                                      0.057     7.670 r  d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/state2_carry__0/CO[2]
                         net (fo=2, routed)           0.421     8.091    d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/state2
    SLICE_X81Y142        LUT3 (Prop_D5LUT_SLICEL_I2_O)
                                                      0.066     8.157 r  d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/FSM_onehot_state[4]_i_1/O
                         net (fo=1, routed)           0.015     8.172    d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/state__0[4]
    SLICE_X81Y142        FDRE                                         r  d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/FSM_onehot_state_reg[4]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      1.953     1.953 r  
    HSADC_X0Y0           HSADC                        0.000     1.953 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     2.075 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     2.225    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     2.339 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.389     4.728    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.358 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.216     5.574    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     5.598 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86296, routed)       2.706     8.304    d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/s_axis_aclk
    SLICE_X81Y142        FDRE                                         r  d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/FSM_onehot_state_reg[4]/C
                         clock pessimism             -0.081     8.223    
                         clock uncertainty           -0.051     8.172    
    SLICE_X81Y142        FDRE (Setup_DFF2_SLICEL_C_D)
                                                      0.025     8.197    d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/FSM_onehot_state_reg[4]
  -------------------------------------------------------------------
                         required time                          8.197    
                         arrival time                          -8.172    
  -------------------------------------------------------------------
                         slack                                  0.025    

Slack (MET) :             0.025ns  (required time - arrival time)
  Source:                 d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.i_cntrl_src/g_parallel.we_gen_reg_srl2_srlopt_replica_1/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[14].g_symmetric.g_data_array.g_data[0].g_data_buff.i_data_buf/g_buff.i_buff/gen_reg.d_reg_reg[10]/CE
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             clk_out1_d_1_clk_adc0_x2_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            1.953ns  (clk_out1_d_1_clk_adc0_x2_0 rise@1.953ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        1.735ns  (logic 0.079ns (4.553%)  route 1.656ns (95.447%))
  Logic Levels:           0  
  Clock Path Skew:        -0.082ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    6.394ns = ( 8.347 - 1.953 ) 
    Source Clock Delay      (SCD):    6.402ns
    Clock Pessimism Removal (CPR):    -0.074ns
  Clock Uncertainty:      0.051ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.074ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      3.072ns (routing 1.545ns, distribution 1.527ns)
  Clock Net Delay (Destination): 2.749ns (routing 1.400ns, distribution 1.349ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.657     3.184    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     3.057 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     3.302    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.330 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86296, routed)       3.072     6.402    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.i_cntrl_src/aclk
    SLICE_X85Y79         FDRE                                         r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.i_cntrl_src/g_parallel.we_gen_reg_srl2_srlopt_replica_1/C
  -------------------------------------------------------------------    -------------------
    SLICE_X85Y79         FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.079     6.481 r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.i_cntrl_src/g_parallel.we_gen_reg_srl2_srlopt_replica_1/Q
                         net (fo=240, routed)         1.656     8.137    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[14].g_symmetric.g_data_array.g_data[0].g_data_buff.i_data_buf/g_buff.i_buff/g_parallel.cntrl[-1]_4_repN_1_alias
    SLICE_X85Y119        FDRE                                         r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[14].g_symmetric.g_data_array.g_data[0].g_data_buff.i_data_buf/g_buff.i_buff/gen_reg.d_reg_reg[10]/CE
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      1.953     1.953 r  
    HSADC_X0Y0           HSADC                        0.000     1.953 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     2.075 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     2.225    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     2.339 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.389     4.728    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.358 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.216     5.574    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     5.598 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86296, routed)       2.749     8.347    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[14].g_symmetric.g_data_array.g_data[0].g_data_buff.i_data_buf/g_buff.i_buff/aclk
    SLICE_X85Y119        FDRE                                         r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[14].g_symmetric.g_data_array.g_data[0].g_data_buff.i_data_buf/g_buff.i_buff/gen_reg.d_reg_reg[10]/C
                         clock pessimism             -0.074     8.273    
                         clock uncertainty           -0.051     8.222    
    SLICE_X85Y119        FDRE (Setup_HFF2_SLICEL_C_CE)
                                                     -0.060     8.162    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[14].g_symmetric.g_data_array.g_data[0].g_data_buff.i_data_buf/g_buff.i_buff/gen_reg.d_reg_reg[10]
  -------------------------------------------------------------------
                         required time                          8.162    
                         arrival time                          -8.137    
  -------------------------------------------------------------------
                         slack                                  0.025    

Slack (MET) :             0.025ns  (required time - arrival time)
  Source:                 d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.i_cntrl_src/g_parallel.we_gen_reg_srl2_srlopt_replica_1/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[6].g_symmetric.g_data_array.g_data[4].g_data_buff.i_data_buf/g_buff.i_buff/gen_reg.d_reg_reg[10]/CE
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             clk_out1_d_1_clk_adc0_x2_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            1.953ns  (clk_out1_d_1_clk_adc0_x2_0 rise@1.953ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        1.735ns  (logic 0.079ns (4.553%)  route 1.656ns (95.447%))
  Logic Levels:           0  
  Clock Path Skew:        -0.082ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    6.394ns = ( 8.347 - 1.953 ) 
    Source Clock Delay      (SCD):    6.402ns
    Clock Pessimism Removal (CPR):    -0.074ns
  Clock Uncertainty:      0.051ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.074ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      3.072ns (routing 1.545ns, distribution 1.527ns)
  Clock Net Delay (Destination): 2.749ns (routing 1.400ns, distribution 1.349ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.657     3.184    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     3.057 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     3.302    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.330 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86296, routed)       3.072     6.402    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.i_cntrl_src/aclk
    SLICE_X85Y79         FDRE                                         r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.i_cntrl_src/g_parallel.we_gen_reg_srl2_srlopt_replica_1/C
  -------------------------------------------------------------------    -------------------
    SLICE_X85Y79         FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.079     6.481 r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.i_cntrl_src/g_parallel.we_gen_reg_srl2_srlopt_replica_1/Q
                         net (fo=240, routed)         1.656     8.137    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[6].g_symmetric.g_data_array.g_data[4].g_data_buff.i_data_buf/g_buff.i_buff/g_parallel.cntrl[-1]_4_repN_1_alias
    SLICE_X85Y119        FDRE                                         r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[6].g_symmetric.g_data_array.g_data[4].g_data_buff.i_data_buf/g_buff.i_buff/gen_reg.d_reg_reg[10]/CE
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      1.953     1.953 r  
    HSADC_X0Y0           HSADC                        0.000     1.953 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     2.075 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     2.225    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     2.339 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.389     4.728    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.358 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.216     5.574    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     5.598 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86296, routed)       2.749     8.347    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[6].g_symmetric.g_data_array.g_data[4].g_data_buff.i_data_buf/g_buff.i_buff/aclk
    SLICE_X85Y119        FDRE                                         r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[6].g_symmetric.g_data_array.g_data[4].g_data_buff.i_data_buf/g_buff.i_buff/gen_reg.d_reg_reg[10]/C
                         clock pessimism             -0.074     8.273    
                         clock uncertainty           -0.051     8.222    
    SLICE_X85Y119        FDRE (Setup_GFF2_SLICEL_C_CE)
                                                     -0.060     8.162    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[6].g_symmetric.g_data_array.g_data[4].g_data_buff.i_data_buf/g_buff.i_buff/gen_reg.d_reg_reg[10]
  -------------------------------------------------------------------
                         required time                          8.162    
                         arrival time                          -8.137    
  -------------------------------------------------------------------
                         slack                                  0.025    

Slack (MET) :             0.025ns  (required time - arrival time)
  Source:                 d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.i_cntrl_src/g_parallel.we_gen_reg_srl2_srlopt_replica_1/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[6].g_symmetric.g_data_array.g_data[4].g_data_buff.i_data_buf/g_buff.i_buff/gen_reg.d_reg_reg[12]/CE
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             clk_out1_d_1_clk_adc0_x2_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            1.953ns  (clk_out1_d_1_clk_adc0_x2_0 rise@1.953ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        1.735ns  (logic 0.079ns (4.553%)  route 1.656ns (95.447%))
  Logic Levels:           0  
  Clock Path Skew:        -0.082ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    6.394ns = ( 8.347 - 1.953 ) 
    Source Clock Delay      (SCD):    6.402ns
    Clock Pessimism Removal (CPR):    -0.074ns
  Clock Uncertainty:      0.051ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.074ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      3.072ns (routing 1.545ns, distribution 1.527ns)
  Clock Net Delay (Destination): 2.749ns (routing 1.400ns, distribution 1.349ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.657     3.184    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     3.057 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     3.302    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.330 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86296, routed)       3.072     6.402    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.i_cntrl_src/aclk
    SLICE_X85Y79         FDRE                                         r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.i_cntrl_src/g_parallel.we_gen_reg_srl2_srlopt_replica_1/C
  -------------------------------------------------------------------    -------------------
    SLICE_X85Y79         FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.079     6.481 r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.i_cntrl_src/g_parallel.we_gen_reg_srl2_srlopt_replica_1/Q
                         net (fo=240, routed)         1.656     8.137    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[6].g_symmetric.g_data_array.g_data[4].g_data_buff.i_data_buf/g_buff.i_buff/g_parallel.cntrl[-1]_4_repN_1_alias
    SLICE_X85Y119        FDRE                                         r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[6].g_symmetric.g_data_array.g_data[4].g_data_buff.i_data_buf/g_buff.i_buff/gen_reg.d_reg_reg[12]/CE
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      1.953     1.953 r  
    HSADC_X0Y0           HSADC                        0.000     1.953 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     2.075 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     2.225    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     2.339 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.389     4.728    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.358 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.216     5.574    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     5.598 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86296, routed)       2.749     8.347    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[6].g_symmetric.g_data_array.g_data[4].g_data_buff.i_data_buf/g_buff.i_buff/aclk
    SLICE_X85Y119        FDRE                                         r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[6].g_symmetric.g_data_array.g_data[4].g_data_buff.i_data_buf/g_buff.i_buff/gen_reg.d_reg_reg[12]/C
                         clock pessimism             -0.074     8.273    
                         clock uncertainty           -0.051     8.222    
    SLICE_X85Y119        FDRE (Setup_FFF2_SLICEL_C_CE)
                                                     -0.060     8.162    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[6].g_symmetric.g_data_array.g_data[4].g_data_buff.i_data_buf/g_buff.i_buff/gen_reg.d_reg_reg[12]
  -------------------------------------------------------------------
                         required time                          8.162    
                         arrival time                          -8.137    
  -------------------------------------------------------------------
                         slack                                  0.025    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.010ns  (arrival time - required time)
  Source:                 d_1_i/axis_dyn_readout_v1_2/inst/readout_top_i/fifo_i/mem_i/dob_reg[48]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_dyn_readout_v1_2/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/fifo_dout_r_reg[48]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             clk_out1_d_1_clk_adc0_x2_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        0.229ns  (logic 0.061ns (26.638%)  route 0.168ns (73.362%))
  Logic Levels:           0  
  Clock Path Skew:        0.157ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    6.486ns
    Source Clock Delay      (SCD):    6.476ns
    Clock Pessimism Removal (CPR):    -0.147ns
  Clock Net Delay (Source):      2.831ns (routing 1.400ns, distribution 1.431ns)
  Clock Net Delay (Destination): 3.156ns (routing 1.545ns, distribution 1.611ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.389     2.775    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     3.405 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.216     3.621    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.645 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86296, routed)       2.831     6.476    d_1_i/axis_dyn_readout_v1_2/inst/readout_top_i/fifo_i/mem_i/aclk
    SLICE_X97Y119        FDRE                                         r  d_1_i/axis_dyn_readout_v1_2/inst/readout_top_i/fifo_i/mem_i/dob_reg[48]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X97Y119        FDRE (Prop_DFF2_SLICEM_C_Q)
                                                      0.061     6.537 r  d_1_i/axis_dyn_readout_v1_2/inst/readout_top_i/fifo_i/mem_i/dob_reg[48]/Q
                         net (fo=1, routed)           0.168     6.705    d_1_i/axis_dyn_readout_v1_2/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/fifo_dout_r_reg[83]_1[48]
    SLICE_X98Y121        FDRE                                         r  d_1_i/axis_dyn_readout_v1_2/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/fifo_dout_r_reg[48]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.657     3.184    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     3.057 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     3.302    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.330 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86296, routed)       3.156     6.486    d_1_i/axis_dyn_readout_v1_2/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/aclk
    SLICE_X98Y121        FDRE                                         r  d_1_i/axis_dyn_readout_v1_2/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/fifo_dout_r_reg[48]/C
                         clock pessimism              0.147     6.633    
    SLICE_X98Y121        FDRE (Hold_CFF2_SLICEL_C_D)
                                                      0.062     6.695    d_1_i/axis_dyn_readout_v1_2/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/fifo_dout_r_reg[48]
  -------------------------------------------------------------------
                         required time                         -6.695    
                         arrival time                           6.705    
  -------------------------------------------------------------------
                         slack                                  0.010    

Slack (MET) :             0.010ns  (arrival time - required time)
  Source:                 d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[14].g_symmetric.g_data_sym_array.g_data_sym[22].g_data_sym_casc_buff.i_data_sym_casc_buff/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[1][3]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[14].g_symmetric.g_data_sym_array.g_data_sym[16].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[3]_srl6/D
                            (rising edge-triggered cell SRL16E clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             clk_out1_d_1_clk_adc0_x2_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        0.137ns  (logic 0.058ns (42.336%)  route 0.079ns (57.664%))
  Logic Levels:           0  
  Clock Path Skew:        0.099ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    6.455ns
    Source Clock Delay      (SCD):    6.381ns
    Clock Pessimism Removal (CPR):    -0.024ns
  Clock Net Delay (Source):      2.736ns (routing 1.400ns, distribution 1.336ns)
  Clock Net Delay (Destination): 3.125ns (routing 1.545ns, distribution 1.580ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.389     2.775    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     3.405 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.216     3.621    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.645 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86296, routed)       2.736     6.381    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[14].g_symmetric.g_data_sym_array.g_data_sym[22].g_data_sym_casc_buff.i_data_sym_casc_buff/g_buff.i_buff/aclk
    SLICE_X83Y93         FDRE                                         r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[14].g_symmetric.g_data_sym_array.g_data_sym[22].g_data_sym_casc_buff.i_data_sym_casc_buff/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[1][3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X83Y93         FDRE (Prop_DFF_SLICEM_C_Q)
                                                      0.058     6.439 r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[14].g_symmetric.g_data_sym_array.g_data_sym[22].g_data_sym_casc_buff.i_data_sym_casc_buff/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[1][3]/Q
                         net (fo=1, routed)           0.079     6.518    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[14].g_symmetric.g_data_sym_array.g_data_sym[16].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[3]
    SLICE_X83Y94         SRL16E                                       r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[14].g_symmetric.g_data_sym_array.g_data_sym[16].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[3]_srl6/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.657     3.184    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     3.057 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     3.302    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.330 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86296, routed)       3.125     6.455    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[14].g_symmetric.g_data_sym_array.g_data_sym[16].g_data_sym_casc_dly.i_data_sym_casc_dly/aclk
    SLICE_X83Y94         SRL16E                                       r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[14].g_symmetric.g_data_sym_array.g_data_sym[16].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[3]_srl6/CLK
                         clock pessimism              0.024     6.479    
    SLICE_X83Y94         SRL16E (Hold_D6LUT_SLICEM_CLK_D)
                                                      0.028     6.507    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[14].g_symmetric.g_data_sym_array.g_data_sym[16].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[3]_srl6
  -------------------------------------------------------------------
                         required time                         -6.507    
                         arrival time                           6.518    
  -------------------------------------------------------------------
                         slack                                  0.010    

Slack (MET) :             0.011ns  (arrival time - required time)
  Source:                 d_1_i/axis_dyn_readout_v1_2/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[15].g_symmetric.g_data_sym_array.g_data_sym[23].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_dyn_readout_v1_2/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[15].g_symmetric.g_data_sym_array.g_data_sym[22].g_data_sym_casc_buff.i_data_sym_casc_buff/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][1]_srl1/D
                            (rising edge-triggered cell SRL16E clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             clk_out1_d_1_clk_adc0_x2_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        0.245ns  (logic 0.058ns (23.650%)  route 0.187ns (76.350%))
  Logic Levels:           0  
  Clock Path Skew:        0.205ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    6.359ns
    Source Clock Delay      (SCD):    6.320ns
    Clock Pessimism Removal (CPR):    -0.166ns
  Clock Net Delay (Source):      2.675ns (routing 1.400ns, distribution 1.275ns)
  Clock Net Delay (Destination): 3.029ns (routing 1.545ns, distribution 1.484ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.389     2.775    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     3.405 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.216     3.621    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.645 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86296, routed)       2.675     6.320    d_1_i/axis_dyn_readout_v1_2/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[15].g_symmetric.g_data_sym_array.g_data_sym[23].g_data_sym_casc_dly.i_data_sym_casc_dly/aclk
    SLICE_X60Y174        FDRE                                         r  d_1_i/axis_dyn_readout_v1_2/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[15].g_symmetric.g_data_sym_array.g_data_sym[23].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X60Y174        FDRE (Prop_BFF_SLICEM_C_Q)
                                                      0.058     6.378 r  d_1_i/axis_dyn_readout_v1_2/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[15].g_symmetric.g_data_sym_array.g_data_sym[23].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[1]/Q
                         net (fo=2, routed)           0.187     6.565    d_1_i/axis_dyn_readout_v1_2/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[15].g_symmetric.g_data_sym_array.g_data_sym[22].g_data_sym_casc_buff.i_data_sym_casc_buff/g_buff.i_buff/A[1]
    SLICE_X60Y191        SRL16E                                       r  d_1_i/axis_dyn_readout_v1_2/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[15].g_symmetric.g_data_sym_array.g_data_sym[22].g_data_sym_casc_buff.i_data_sym_casc_buff/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][1]_srl1/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.657     3.184    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     3.057 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     3.302    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.330 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86296, routed)       3.029     6.359    d_1_i/axis_dyn_readout_v1_2/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[15].g_symmetric.g_data_sym_array.g_data_sym[22].g_data_sym_casc_buff.i_data_sym_casc_buff/g_buff.i_buff/aclk
    SLICE_X60Y191        SRL16E                                       r  d_1_i/axis_dyn_readout_v1_2/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[15].g_symmetric.g_data_sym_array.g_data_sym[22].g_data_sym_casc_buff.i_data_sym_casc_buff/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][1]_srl1/CLK
                         clock pessimism              0.166     6.525    
    SLICE_X60Y191        SRL16E (Hold_B6LUT_SLICEM_CLK_D)
                                                      0.029     6.554    d_1_i/axis_dyn_readout_v1_2/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[15].g_symmetric.g_data_sym_array.g_data_sym[22].g_data_sym_casc_buff.i_data_sym_casc_buff/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][1]_srl1
  -------------------------------------------------------------------
                         required time                         -6.554    
                         arrival time                           6.565    
  -------------------------------------------------------------------
                         slack                                  0.011    

Slack (MET) :             0.011ns  (arrival time - required time)
  Source:                 d_1_i/axis_dyn_readout_v1_2/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[3].g_symmetric.g_data_sym_array.g_data_sym[25].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[7]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_dyn_readout_v1_2/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[3].g_symmetric.g_data_sym_array.g_data_sym[24].g_data_sym_casc_buff.i_data_sym_casc_buff/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][7]_srl1/D
                            (rising edge-triggered cell SRL16E clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             clk_out1_d_1_clk_adc0_x2_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        0.297ns  (logic 0.058ns (19.557%)  route 0.239ns (80.443%))
  Logic Levels:           0  
  Clock Path Skew:        0.254ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    6.360ns
    Source Clock Delay      (SCD):    6.272ns
    Clock Pessimism Removal (CPR):    -0.166ns
  Clock Net Delay (Source):      2.627ns (routing 1.400ns, distribution 1.227ns)
  Clock Net Delay (Destination): 3.030ns (routing 1.545ns, distribution 1.485ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.389     2.775    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     3.405 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.216     3.621    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.645 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86296, routed)       2.627     6.272    d_1_i/axis_dyn_readout_v1_2/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[3].g_symmetric.g_data_sym_array.g_data_sym[25].g_data_sym_casc_dly.i_data_sym_casc_dly/aclk
    SLICE_X61Y172        FDRE                                         r  d_1_i/axis_dyn_readout_v1_2/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[3].g_symmetric.g_data_sym_array.g_data_sym[25].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[7]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X61Y172        FDRE (Prop_HFF_SLICEM_C_Q)
                                                      0.058     6.330 r  d_1_i/axis_dyn_readout_v1_2/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[3].g_symmetric.g_data_sym_array.g_data_sym[25].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[7]/Q
                         net (fo=2, routed)           0.239     6.569    d_1_i/axis_dyn_readout_v1_2/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[3].g_symmetric.g_data_sym_array.g_data_sym[24].g_data_sym_casc_buff.i_data_sym_casc_buff/g_buff.i_buff/A[7]
    SLICE_X60Y188        SRL16E                                       r  d_1_i/axis_dyn_readout_v1_2/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[3].g_symmetric.g_data_sym_array.g_data_sym[24].g_data_sym_casc_buff.i_data_sym_casc_buff/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][7]_srl1/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.657     3.184    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     3.057 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     3.302    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.330 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86296, routed)       3.030     6.360    d_1_i/axis_dyn_readout_v1_2/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[3].g_symmetric.g_data_sym_array.g_data_sym[24].g_data_sym_casc_buff.i_data_sym_casc_buff/g_buff.i_buff/aclk
    SLICE_X60Y188        SRL16E                                       r  d_1_i/axis_dyn_readout_v1_2/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[3].g_symmetric.g_data_sym_array.g_data_sym[24].g_data_sym_casc_buff.i_data_sym_casc_buff/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][7]_srl1/CLK
                         clock pessimism              0.166     6.526    
    SLICE_X60Y188        SRL16E (Hold_H6LUT_SLICEM_CLK_D)
                                                      0.032     6.558    d_1_i/axis_dyn_readout_v1_2/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[3].g_symmetric.g_data_sym_array.g_data_sym[24].g_data_sym_casc_buff.i_data_sym_casc_buff/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][7]_srl1
  -------------------------------------------------------------------
                         required time                         -6.558    
                         arrival time                           6.569    
  -------------------------------------------------------------------
                         slack                                  0.011    

Slack (MET) :             0.012ns  (arrival time - required time)
  Source:                 d_1_i/axis_dyn_readout_v1_2/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[6].g_symmetric.g_data_sym_array.g_data_sym[18].g_data_sym_casc_buff.i_data_sym_casc_buff/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[1][7]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_dyn_readout_v1_2/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[6].g_symmetric.g_data_sym_array.g_data_sym[12].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[7]_srl6/D
                            (rising edge-triggered cell SRL16E clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             clk_out1_d_1_clk_adc0_x2_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        0.130ns  (logic 0.058ns (44.615%)  route 0.072ns (55.385%))
  Logic Levels:           0  
  Clock Path Skew:        0.086ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    6.323ns
    Source Clock Delay      (SCD):    6.280ns
    Clock Pessimism Removal (CPR):    -0.043ns
  Clock Net Delay (Source):      2.635ns (routing 1.400ns, distribution 1.235ns)
  Clock Net Delay (Destination): 2.993ns (routing 1.545ns, distribution 1.448ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.389     2.775    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     3.405 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.216     3.621    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.645 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86296, routed)       2.635     6.280    d_1_i/axis_dyn_readout_v1_2/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[6].g_symmetric.g_data_sym_array.g_data_sym[18].g_data_sym_casc_buff.i_data_sym_casc_buff/g_buff.i_buff/aclk
    SLICE_X79Y199        FDRE                                         r  d_1_i/axis_dyn_readout_v1_2/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[6].g_symmetric.g_data_sym_array.g_data_sym[18].g_data_sym_casc_buff.i_data_sym_casc_buff/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[1][7]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X79Y199        FDRE (Prop_HFF_SLICEM_C_Q)
                                                      0.058     6.338 r  d_1_i/axis_dyn_readout_v1_2/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[6].g_symmetric.g_data_sym_array.g_data_sym[18].g_data_sym_casc_buff.i_data_sym_casc_buff/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[1][7]/Q
                         net (fo=1, routed)           0.072     6.410    d_1_i/axis_dyn_readout_v1_2/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[6].g_symmetric.g_data_sym_array.g_data_sym[12].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[7]
    SLICE_X79Y200        SRL16E                                       r  d_1_i/axis_dyn_readout_v1_2/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[6].g_symmetric.g_data_sym_array.g_data_sym[12].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[7]_srl6/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.657     3.184    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     3.057 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     3.302    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.330 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86296, routed)       2.993     6.323    d_1_i/axis_dyn_readout_v1_2/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[6].g_symmetric.g_data_sym_array.g_data_sym[12].g_data_sym_casc_dly.i_data_sym_casc_dly/aclk
    SLICE_X79Y200        SRL16E                                       r  d_1_i/axis_dyn_readout_v1_2/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[6].g_symmetric.g_data_sym_array.g_data_sym[12].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[7]_srl6/CLK
                         clock pessimism              0.043     6.367    
    SLICE_X79Y200        SRL16E (Hold_H6LUT_SLICEM_CLK_D)
                                                      0.032     6.399    d_1_i/axis_dyn_readout_v1_2/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[6].g_symmetric.g_data_sym_array.g_data_sym[12].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[7]_srl6
  -------------------------------------------------------------------
                         required time                         -6.399    
                         arrival time                           6.410    
  -------------------------------------------------------------------
                         slack                                  0.012    

Slack (MET) :             0.012ns  (arrival time - required time)
  Source:                 d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[13].g_symmetric.g_data_sym_array.g_data_sym[21].g_data_sym_casc_buff.i_data_sym_casc_buff/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[1][6]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[13].g_symmetric.g_data_sym_array.g_data_sym[15].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[6]_srl6/D
                            (rising edge-triggered cell SRL16E clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             clk_out1_d_1_clk_adc0_x2_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        0.171ns  (logic 0.058ns (33.918%)  route 0.113ns (66.082%))
  Logic Levels:           0  
  Clock Path Skew:        0.139ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    6.647ns
    Source Clock Delay      (SCD):    6.569ns
    Clock Pessimism Removal (CPR):    -0.061ns
  Clock Net Delay (Source):      2.924ns (routing 1.400ns, distribution 1.524ns)
  Clock Net Delay (Destination): 3.317ns (routing 1.545ns, distribution 1.772ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.389     2.775    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     3.405 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.216     3.621    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.645 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86296, routed)       2.924     6.569    d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[13].g_symmetric.g_data_sym_array.g_data_sym[21].g_data_sym_casc_buff.i_data_sym_casc_buff/g_buff.i_buff/aclk
    SLICE_X109Y361       FDRE                                         r  d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[13].g_symmetric.g_data_sym_array.g_data_sym[21].g_data_sym_casc_buff.i_data_sym_casc_buff/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[1][6]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X109Y361       FDRE (Prop_GFF_SLICEM_C_Q)
                                                      0.058     6.627 r  d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[13].g_symmetric.g_data_sym_array.g_data_sym[21].g_data_sym_casc_buff.i_data_sym_casc_buff/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[1][6]/Q
                         net (fo=1, routed)           0.113     6.740    d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[13].g_symmetric.g_data_sym_array.g_data_sym[15].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[6]
    SLICE_X110Y361       SRL16E                                       r  d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[13].g_symmetric.g_data_sym_array.g_data_sym[15].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[6]_srl6/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.657     3.184    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     3.057 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     3.302    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.330 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86296, routed)       3.317     6.647    d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[13].g_symmetric.g_data_sym_array.g_data_sym[15].g_data_sym_casc_dly.i_data_sym_casc_dly/aclk
    SLICE_X110Y361       SRL16E                                       r  d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[13].g_symmetric.g_data_sym_array.g_data_sym[15].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[6]_srl6/CLK
                         clock pessimism              0.061     6.708    
    SLICE_X110Y361       SRL16E (Hold_G6LUT_SLICEM_CLK_D)
                                                      0.020     6.728    d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[13].g_symmetric.g_data_sym_array.g_data_sym[15].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[6]_srl6
  -------------------------------------------------------------------
                         required time                         -6.728    
                         arrival time                           6.740    
  -------------------------------------------------------------------
                         slack                                  0.012    

Slack (MET) :             0.012ns  (arrival time - required time)
  Source:                 d_1_i/axis_dyn_readout_v1_2/inst/readout_top_i/fifo_i/mem_i/dob_reg[34]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_dyn_readout_v1_2/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/fifo_dout_r_reg[34]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             clk_out1_d_1_clk_adc0_x2_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        0.218ns  (logic 0.061ns (27.982%)  route 0.157ns (72.018%))
  Logic Levels:           0  
  Clock Path Skew:        0.146ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    6.477ns
    Source Clock Delay      (SCD):    6.478ns
    Clock Pessimism Removal (CPR):    -0.147ns
  Clock Net Delay (Source):      2.833ns (routing 1.400ns, distribution 1.433ns)
  Clock Net Delay (Destination): 3.147ns (routing 1.545ns, distribution 1.602ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.389     2.775    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     3.405 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.216     3.621    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.645 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86296, routed)       2.833     6.478    d_1_i/axis_dyn_readout_v1_2/inst/readout_top_i/fifo_i/mem_i/aclk
    SLICE_X99Y119        FDRE                                         r  d_1_i/axis_dyn_readout_v1_2/inst/readout_top_i/fifo_i/mem_i/dob_reg[34]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X99Y119        FDRE (Prop_DFF2_SLICEM_C_Q)
                                                      0.061     6.539 r  d_1_i/axis_dyn_readout_v1_2/inst/readout_top_i/fifo_i/mem_i/dob_reg[34]/Q
                         net (fo=1, routed)           0.157     6.696    d_1_i/axis_dyn_readout_v1_2/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/fifo_dout_r_reg[83]_1[34]
    SLICE_X100Y120       FDRE                                         r  d_1_i/axis_dyn_readout_v1_2/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/fifo_dout_r_reg[34]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.657     3.184    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     3.057 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     3.302    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.330 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86296, routed)       3.147     6.477    d_1_i/axis_dyn_readout_v1_2/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/aclk
    SLICE_X100Y120       FDRE                                         r  d_1_i/axis_dyn_readout_v1_2/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/fifo_dout_r_reg[34]/C
                         clock pessimism              0.147     6.624    
    SLICE_X100Y120       FDRE (Hold_BFF_SLICEL_C_D)
                                                      0.060     6.684    d_1_i/axis_dyn_readout_v1_2/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/fifo_dout_r_reg[34]
  -------------------------------------------------------------------
                         required time                         -6.684    
                         arrival time                           6.696    
  -------------------------------------------------------------------
                         slack                                  0.012    

Slack (MET) :             0.012ns  (arrival time - required time)
  Source:                 d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.i_data_in/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[1][111]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[6].g_symmetric.g_data_array.g_data[4].i_data_casc_dly/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[31][15]_srl32/D
                            (rising edge-triggered cell SRLC32E clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             clk_out1_d_1_clk_adc0_x2_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        0.207ns  (logic 0.059ns (28.444%)  route 0.148ns (71.556%))
  Logic Levels:           0  
  Clock Path Skew:        0.116ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    6.550ns
    Source Clock Delay      (SCD):    6.506ns
    Clock Pessimism Removal (CPR):    -0.072ns
  Clock Net Delay (Source):      2.861ns (routing 1.400ns, distribution 1.461ns)
  Clock Net Delay (Destination): 3.220ns (routing 1.545ns, distribution 1.675ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.389     2.775    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     3.405 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.216     3.621    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.645 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86296, routed)       2.861     6.506    d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.i_data_in/aclk
    SLICE_X109Y170       FDRE                                         r  d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.i_data_in/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[1][111]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X109Y170       FDRE (Prop_HFF2_SLICEM_C_Q)
                                                      0.059     6.565 r  d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.i_data_in/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[1][111]/Q
                         net (fo=2, routed)           0.148     6.713    d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[6].g_symmetric.g_data_array.g_data[4].i_data_casc_dly/data_in[15]
    SLICE_X110Y172       SRLC32E                                      r  d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[6].g_symmetric.g_data_array.g_data[4].i_data_casc_dly/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[31][15]_srl32/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.657     3.184    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     3.057 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     3.302    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.330 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86296, routed)       3.220     6.550    d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[6].g_symmetric.g_data_array.g_data[4].i_data_casc_dly/aclk
    SLICE_X110Y172       SRLC32E                                      r  d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[6].g_symmetric.g_data_array.g_data[4].i_data_casc_dly/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[31][15]_srl32/CLK
                         clock pessimism              0.072     6.622    
    SLICE_X110Y172       SRLC32E (Hold_H6LUT_SLICEM_CLK_D)
                                                      0.079     6.701    d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[6].g_symmetric.g_data_array.g_data[4].i_data_casc_dly/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[31][15]_srl32
  -------------------------------------------------------------------
                         required time                         -6.701    
                         arrival time                           6.713    
  -------------------------------------------------------------------
                         slack                                  0.012    

Slack (MET) :             0.012ns  (arrival time - required time)
  Source:                 d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[14].g_symmetric.g_data_sym_array.g_data_sym[23].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[14].g_symmetric.g_data_sym_array.g_data_sym[22].g_data_sym_casc_buff.i_data_sym_casc_buff/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][3]_srl1/D
                            (rising edge-triggered cell SRL16E clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             clk_out1_d_1_clk_adc0_x2_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        0.279ns  (logic 0.058ns (20.759%)  route 0.221ns (79.242%))
  Logic Levels:           0  
  Clock Path Skew:        0.239ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    6.502ns
    Source Clock Delay      (SCD):    6.425ns
    Clock Pessimism Removal (CPR):    -0.162ns
  Clock Net Delay (Source):      2.780ns (routing 1.400ns, distribution 1.380ns)
  Clock Net Delay (Destination): 3.172ns (routing 1.545ns, distribution 1.627ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.389     2.775    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     3.405 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.216     3.621    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.645 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86296, routed)       2.780     6.425    d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[14].g_symmetric.g_data_sym_array.g_data_sym[23].g_data_sym_casc_dly.i_data_sym_casc_dly/aclk
    SLICE_X86Y297        FDRE                                         r  d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[14].g_symmetric.g_data_sym_array.g_data_sym[23].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X86Y297        FDRE (Prop_DFF_SLICEM_C_Q)
                                                      0.058     6.483 r  d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[14].g_symmetric.g_data_sym_array.g_data_sym[23].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[3]/Q
                         net (fo=2, routed)           0.221     6.704    d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[14].g_symmetric.g_data_sym_array.g_data_sym[22].g_data_sym_casc_buff.i_data_sym_casc_buff/g_buff.i_buff/A[3]
    SLICE_X86Y311        SRL16E                                       r  d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[14].g_symmetric.g_data_sym_array.g_data_sym[22].g_data_sym_casc_buff.i_data_sym_casc_buff/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][3]_srl1/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.657     3.184    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     3.057 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     3.302    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.330 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86296, routed)       3.172     6.502    d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[14].g_symmetric.g_data_sym_array.g_data_sym[22].g_data_sym_casc_buff.i_data_sym_casc_buff/g_buff.i_buff/aclk
    SLICE_X86Y311        SRL16E                                       r  d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[14].g_symmetric.g_data_sym_array.g_data_sym[22].g_data_sym_casc_buff.i_data_sym_casc_buff/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][3]_srl1/CLK
                         clock pessimism              0.162     6.664    
    SLICE_X86Y311        SRL16E (Hold_D6LUT_SLICEM_CLK_D)
                                                      0.028     6.692    d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[14].g_symmetric.g_data_sym_array.g_data_sym[22].g_data_sym_casc_buff.i_data_sym_casc_buff/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][3]_srl1
  -------------------------------------------------------------------
                         required time                         -6.692    
                         arrival time                           6.704    
  -------------------------------------------------------------------
                         slack                                  0.012    

Slack (MET) :             0.012ns  (arrival time - required time)
  Source:                 d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[13].g_symmetric.g_data_sym_array.g_data_sym[21].g_data_sym_casc_buff.i_data_sym_casc_buff/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[1][7]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[13].g_symmetric.g_data_sym_array.g_data_sym[15].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[7]_srl6/D
                            (rising edge-triggered cell SRL16E clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             clk_out1_d_1_clk_adc0_x2_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        0.130ns  (logic 0.058ns (44.615%)  route 0.072ns (55.385%))
  Logic Levels:           0  
  Clock Path Skew:        0.086ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    6.445ns
    Source Clock Delay      (SCD):    6.391ns
    Clock Pessimism Removal (CPR):    -0.031ns
  Clock Net Delay (Source):      2.746ns (routing 1.400ns, distribution 1.346ns)
  Clock Net Delay (Destination): 3.115ns (routing 1.545ns, distribution 1.570ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.389     2.775    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     3.405 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.216     3.621    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.645 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86296, routed)       2.746     6.391    d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[13].g_symmetric.g_data_sym_array.g_data_sym[21].g_data_sym_casc_buff.i_data_sym_casc_buff/g_buff.i_buff/aclk
    SLICE_X90Y190        FDRE                                         r  d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[13].g_symmetric.g_data_sym_array.g_data_sym[21].g_data_sym_casc_buff.i_data_sym_casc_buff/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[1][7]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X90Y190        FDRE (Prop_HFF_SLICEM_C_Q)
                                                      0.058     6.449 r  d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[13].g_symmetric.g_data_sym_array.g_data_sym[21].g_data_sym_casc_buff.i_data_sym_casc_buff/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[1][7]/Q
                         net (fo=1, routed)           0.072     6.521    d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[13].g_symmetric.g_data_sym_array.g_data_sym[15].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[7]
    SLICE_X90Y191        SRL16E                                       r  d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[13].g_symmetric.g_data_sym_array.g_data_sym[15].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[7]_srl6/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.657     3.184    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     3.057 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     3.302    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.330 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86296, routed)       3.115     6.445    d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[13].g_symmetric.g_data_sym_array.g_data_sym[15].g_data_sym_casc_dly.i_data_sym_casc_dly/aclk
    SLICE_X90Y191        SRL16E                                       r  d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[13].g_symmetric.g_data_sym_array.g_data_sym[15].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[7]_srl6/CLK
                         clock pessimism              0.031     6.476    
    SLICE_X90Y191        SRL16E (Hold_H6LUT_SLICEM_CLK_D)
                                                      0.032     6.508    d_1_i/axis_dyn_readout_v1_3/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[13].g_symmetric.g_data_sym_array.g_data_sym[15].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[7]_srl6
  -------------------------------------------------------------------
                         required time                         -6.508    
                         arrival time                           6.521    
  -------------------------------------------------------------------
                         slack                                  0.012    





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         clk_out1_d_1_clk_adc0_x2_0
Waveform(ns):       { 0.000 0.976 }
Period(ns):         1.953
Sources:            { d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0 }

Check Type        Corner  Lib Pin             Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location      Pin
Min Period        n/a     HSADC/FABRIC_CLK    n/a            1.923         1.953       0.030      HSADC_X0Y0    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/FABRIC_CLK
Min Period        n/a     HSADC/FABRIC_CLK    n/a            1.923         1.953       0.030      HSADC_X0Y2    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/FABRIC_CLK
Min Period        n/a     RAMB36E2/CLKARDCLK  n/a            1.355         1.953       0.598      RAMB36_X5Y12  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_0/CLKARDCLK
Min Period        n/a     RAMB36E2/CLKARDCLK  n/a            1.355         1.953       0.598      RAMB36_X5Y13  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_1/CLKARDCLK
Min Period        n/a     RAMB36E2/CLKARDCLK  n/a            1.355         1.953       0.598      RAMB36_X4Y5   d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_10/CLKARDCLK
Min Period        n/a     RAMB36E2/CLKARDCLK  n/a            1.355         1.953       0.598      RAMB36_X4Y6   d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_11/CLKARDCLK
Min Period        n/a     RAMB36E2/CLKARDCLK  n/a            1.355         1.953       0.598      RAMB36_X4Y7   d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_12/CLKARDCLK
Min Period        n/a     RAMB36E2/CLKARDCLK  n/a            1.355         1.953       0.598      RAMB36_X4Y8   d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_13/CLKARDCLK
Min Period        n/a     RAMB36E2/CLKARDCLK  n/a            1.355         1.953       0.598      RAMB36_X4Y9   d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_14/CLKARDCLK
Min Period        n/a     RAMB36E2/CLKARDCLK  n/a            1.355         1.953       0.598      RAMB36_X4Y10  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_15/CLKARDCLK
Low Pulse Width   Slow    HSADC/FABRIC_CLK    n/a            0.800         0.977       0.177      HSADC_X0Y0    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/FABRIC_CLK
Low Pulse Width   Fast    HSADC/FABRIC_CLK    n/a            0.800         0.976       0.176      HSADC_X0Y0    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/FABRIC_CLK
Low Pulse Width   Slow    HSADC/FABRIC_CLK    n/a            0.800         0.977       0.177      HSADC_X0Y2    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/FABRIC_CLK
Low Pulse Width   Fast    HSADC/FABRIC_CLK    n/a            0.800         0.976       0.176      HSADC_X0Y2    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/FABRIC_CLK
Low Pulse Width   Slow    RAMB36E2/CLKARDCLK  n/a            0.542         0.977       0.435      RAMB36_X5Y12  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_0/CLKARDCLK
Low Pulse Width   Fast    RAMB36E2/CLKARDCLK  n/a            0.542         0.977       0.435      RAMB36_X5Y12  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_0/CLKARDCLK
Low Pulse Width   Slow    RAMB36E2/CLKARDCLK  n/a            0.542         0.977       0.435      RAMB36_X5Y13  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_1/CLKARDCLK
Low Pulse Width   Fast    RAMB36E2/CLKARDCLK  n/a            0.542         0.977       0.435      RAMB36_X5Y13  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_1/CLKARDCLK
Low Pulse Width   Slow    RAMB36E2/CLKARDCLK  n/a            0.542         0.977       0.435      RAMB36_X4Y5   d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_10/CLKARDCLK
Low Pulse Width   Fast    RAMB36E2/CLKARDCLK  n/a            0.542         0.976       0.434      RAMB36_X4Y5   d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_10/CLKARDCLK
High Pulse Width  Slow    HSADC/FABRIC_CLK    n/a            0.800         0.976       0.176      HSADC_X0Y0    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/FABRIC_CLK
High Pulse Width  Fast    HSADC/FABRIC_CLK    n/a            0.800         0.977       0.177      HSADC_X0Y0    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/FABRIC_CLK
High Pulse Width  Slow    HSADC/FABRIC_CLK    n/a            0.800         0.976       0.176      HSADC_X0Y2    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/FABRIC_CLK
High Pulse Width  Fast    HSADC/FABRIC_CLK    n/a            0.800         0.977       0.177      HSADC_X0Y2    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/FABRIC_CLK
High Pulse Width  Slow    RAMB36E2/CLKARDCLK  n/a            0.542         0.976       0.434      RAMB36_X5Y12  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_0/CLKARDCLK
High Pulse Width  Fast    RAMB36E2/CLKARDCLK  n/a            0.542         0.976       0.434      RAMB36_X5Y12  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_0/CLKARDCLK
High Pulse Width  Slow    RAMB36E2/CLKARDCLK  n/a            0.542         0.976       0.434      RAMB36_X5Y13  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_1/CLKARDCLK
High Pulse Width  Fast    RAMB36E2/CLKARDCLK  n/a            0.542         0.976       0.434      RAMB36_X5Y13  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_1/CLKARDCLK
High Pulse Width  Slow    RAMB36E2/CLKARDCLK  n/a            0.542         0.976       0.434      RAMB36_X4Y5   d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_10/CLKARDCLK
High Pulse Width  Fast    RAMB36E2/CLKARDCLK  n/a            0.542         0.977       0.435      RAMB36_X4Y5   d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_10/CLKARDCLK



---------------------------------------------------------------------------------------------------
From Clock:  RFDAC0_CLK
  To Clock:  RFDAC0_CLK

Setup :            0  Failing Endpoints,  Worst Slack        0.033ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.008ns,  Total Violation        0.000ns
PW    :            0  Failing Endpoints,  Worst Slack        0.502ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.033ns  (required time - arrival time)
  Source:                 d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/ctrl_i/en_reg_r6_reg_r/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/mem_addr_int_r_reg[6]_replica/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             RFDAC0_CLK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            2.604ns  (RFDAC0_CLK rise@2.604ns - RFDAC0_CLK rise@0.000ns)
  Data Path Delay:        2.399ns  (logic 0.132ns (5.502%)  route 2.267ns (94.498%))
  Logic Levels:           1  (LUT2=1)
  Clock Path Skew:        -0.161ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.412ns = ( 6.016 - 2.604 ) 
    Source Clock Delay      (SCD):    3.866ns
    Clock Pessimism Removal (CPR):    0.293ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      3.193ns (routing 1.460ns, distribution 1.733ns)
  Clock Net Delay (Destination): 2.891ns (routing 1.327ns, distribution 1.564ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y100       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89456, routed)       3.193     3.866    d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/ctrl_i/aclk
    SLICE_X102Y245       FDRE                                         r  d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/ctrl_i/en_reg_r6_reg_r/C
  -------------------------------------------------------------------    -------------------
    SLICE_X102Y245       FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.079     3.945 r  d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/ctrl_i/en_reg_r6_reg_r/Q
                         net (fo=19, routed)          0.591     4.537    d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/ctrl_i/en_reg_r6_reg_r_n_0_alias_1
    SLICE_X93Y286        LUT2 (Prop_A6LUT_SLICEM_I1_O)
                                                      0.053     4.590 r  d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/ctrl_i/addr_cnt_r6_reg_gate__3/O
                         net (fo=9, routed)           1.676     6.266    d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/ctrl_i_n_8
    SLICE_X85Y438        FDRE                                         r  d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/mem_addr_int_r_reg[6]_replica/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      2.604     2.604 r  
    HSDAC_X0Y0           HSDAC                        0.000     2.604 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     2.885 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     3.011    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y100       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     3.125 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89456, routed)       2.891     6.016    d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/aclk
    SLICE_X85Y438        FDRE                                         r  d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/mem_addr_int_r_reg[6]_replica/C
                         clock pessimism              0.293     6.309    
                         clock uncertainty           -0.035     6.274    
    SLICE_X85Y438        FDRE (Setup_EFF2_SLICEL_C_D)
                                                      0.025     6.299    d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/mem_addr_int_r_reg[6]_replica
  -------------------------------------------------------------------
                         required time                          6.299    
                         arrival time                          -6.266    
  -------------------------------------------------------------------
                         slack                                  0.033    

Slack (MET) :             0.035ns  (required time - arrival time)
  Source:                 d_1_i/qick_processor_0/inst/QPROC/sync_ctrl_ps_t/data_r_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/qick_processor_0/WAVE_FIFO[6].wave_fifo_inst/fifo_mem/RAM_reg_2/ENARDEN
                            (rising edge-triggered cell RAMB36E2 clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             RFDAC0_CLK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            2.604ns  (RFDAC0_CLK rise@2.604ns - RFDAC0_CLK rise@0.000ns)
  Data Path Delay:        2.018ns  (logic 0.369ns (18.284%)  route 1.649ns (81.716%))
  Logic Levels:           3  (LUT3=1 LUT4=1 LUT5=1)
  Clock Path Skew:        -0.174ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.305ns = ( 5.909 - 2.604 ) 
    Source Clock Delay      (SCD):    3.768ns
    Clock Pessimism Removal (CPR):    0.289ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      3.095ns (routing 1.460ns, distribution 1.635ns)
  Clock Net Delay (Destination): 2.784ns (routing 1.327ns, distribution 1.457ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y100       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89456, routed)       3.095     3.768    d_1_i/qick_processor_0/inst/QPROC/sync_ctrl_ps_t/t_clk_i
    SLICE_X84Y167        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/sync_ctrl_ps_t/data_r_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X84Y167        FDRE (Prop_AFF2_SLICEL_C_Q)
                                                      0.081     3.849 r  d_1_i/qick_processor_0/inst/QPROC/sync_ctrl_ps_t/data_r_reg[2]/Q
                         net (fo=4, routed)           0.193     4.042    d_1_i/qick_processor_0/inst/QPROC/sync_ctrl_ps_t/data_r[2]
    SLICE_X84Y167        LUT3 (Prop_E6LUT_SLICEL_I2_O)
                                                      0.051     4.093 r  d_1_i/qick_processor_0/inst/QPROC/sync_ctrl_ps_t/FSM_sequential_time_st[0]_i_2/O
                         net (fo=1, routed)           0.057     4.150    d_1_i/qick_processor_0/inst/QPROC/sync_ctrl_ps_t/FSM_sequential_time_st[0]_i_2_n_0
    SLICE_X84Y167        LUT5 (Prop_F6LUT_SLICEL_I2_O)
                                                      0.148     4.298 r  d_1_i/qick_processor_0/inst/QPROC/sync_ctrl_ps_t/FSM_sequential_time_st[0]_i_1/O
                         net (fo=28, routed)          0.721     5.019    d_1_i/qick_processor_0/pwropt
    SLICE_X77Y164        LUT4 (Prop_D6LUT_SLICEL_I2_O)
                                                      0.089     5.108 r  d_1_i/qick_processor_0/WAVE_FIFO[6].wave_fifo_inst/fifo_mem/RAM_reg_2_ENARDEN_cooolgate_en_gate_846/O
                         net (fo=1, routed)           0.678     5.786    d_1_i/qick_processor_0/WAVE_FIFO[6].wave_fifo_inst/fifo_mem/RAM_reg_2_ENARDEN_cooolgate_en_sig_415
    RAMB36_X7Y39         RAMB36E2                                     r  d_1_i/qick_processor_0/WAVE_FIFO[6].wave_fifo_inst/fifo_mem/RAM_reg_2/ENARDEN
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      2.604     2.604 r  
    HSDAC_X0Y0           HSDAC                        0.000     2.604 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     2.885 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     3.011    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y100       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     3.125 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89456, routed)       2.784     5.909    d_1_i/qick_processor_0/t_clk_i
    RAMB36_X7Y39         RAMB36E2                                     r  d_1_i/qick_processor_0/WAVE_FIFO[6].wave_fifo_inst/fifo_mem/RAM_reg_2/CLKARDCLK
                         clock pessimism              0.289     6.198    
                         clock uncertainty           -0.035     6.163    
    RAMB36_X7Y39         RAMB36E2 (Setup_RAMB36E2_RAMB36_CLKARDCLK_ENARDEN)
                                                     -0.342     5.821    d_1_i/qick_processor_0/WAVE_FIFO[6].wave_fifo_inst/fifo_mem/RAM_reg_2
  -------------------------------------------------------------------
                         required time                          5.821    
                         arrival time                          -5.786    
  -------------------------------------------------------------------
                         slack                                  0.035    

Slack (MET) :             0.036ns  (required time - arrival time)
  Source:                 d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_replica_25/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[5].dds_i/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_use_DSP48.i_nontrivial.i_vx4_5.I_DSP/I_VX5_6.I_DSP/DSP_OUTPUT_INST/CEP
                            (rising edge-triggered cell DSP_OUTPUT clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             RFDAC0_CLK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            2.604ns  (RFDAC0_CLK rise@2.604ns - RFDAC0_CLK rise@0.000ns)
  Data Path Delay:        2.281ns  (logic 0.076ns (3.331%)  route 2.205ns (96.669%))
  Logic Levels:           0  
  Clock Path Skew:        -0.034ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.114ns = ( 5.718 - 2.604 ) 
    Source Clock Delay      (SCD):    3.564ns
    Clock Pessimism Removal (CPR):    0.417ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.891ns (routing 1.460ns, distribution 1.431ns)
  Clock Net Delay (Destination): 2.593ns (routing 1.327ns, distribution 1.266ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y100       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89456, routed)       2.891     3.564    d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/signal_gen_i/aclk
    SLICE_X37Y182        FDRE                                         r  d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_replica_25/C
  -------------------------------------------------------------------    -------------------
    SLICE_X37Y182        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     3.640 r  d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_replica_25/Q
                         net (fo=206, routed)         2.205     5.846    d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[5].dds_i/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_use_DSP48.i_nontrivial.i_vx4_5.I_DSP/I_VX5_6.I_DSP/CEP
    DSP48E2_X6Y79        DSP_OUTPUT                                   r  d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[5].dds_i/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_use_DSP48.i_nontrivial.i_vx4_5.I_DSP/I_VX5_6.I_DSP/DSP_OUTPUT_INST/CEP
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      2.604     2.604 r  
    HSDAC_X0Y0           HSDAC                        0.000     2.604 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     2.885 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     3.011    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y100       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     3.125 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89456, routed)       2.593     5.718    d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[5].dds_i/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_use_DSP48.i_nontrivial.i_vx4_5.I_DSP/I_VX5_6.I_DSP/CLK
    DSP48E2_X6Y79        DSP_OUTPUT                                   r  d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[5].dds_i/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_use_DSP48.i_nontrivial.i_vx4_5.I_DSP/I_VX5_6.I_DSP/DSP_OUTPUT_INST/CLK
                         clock pessimism              0.417     6.135    
                         clock uncertainty           -0.035     6.099    
    DSP48E2_X6Y79        DSP_OUTPUT (Setup_DSP_OUTPUT_DSP48E2_CLK_CEP)
                                                     -0.218     5.881    d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[5].dds_i/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_use_DSP48.i_nontrivial.i_vx4_5.I_DSP/I_VX5_6.I_DSP/DSP_OUTPUT_INST
  -------------------------------------------------------------------
                         required time                          5.881    
                         arrival time                          -5.846    
  -------------------------------------------------------------------
                         slack                                  0.036    

Slack (MET) :             0.036ns  (required time - arrival time)
  Source:                 d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/ctrl_i/phase_0_r1_reg[11]/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/ctrl_i/GEN_phase[9].phase_v1_r1_reg[9][23]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             RFDAC0_CLK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            2.604ns  (RFDAC0_CLK rise@2.604ns - RFDAC0_CLK rise@0.000ns)
  Data Path Delay:        2.343ns  (logic 0.395ns (16.856%)  route 1.948ns (83.144%))
  Logic Levels:           3  (CARRY8=2 LUT2=1)
  Clock Path Skew:        -0.214ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.277ns = ( 5.881 - 2.604 ) 
    Source Clock Delay      (SCD):    3.776ns
    Clock Pessimism Removal (CPR):    0.285ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      3.103ns (routing 1.460ns, distribution 1.643ns)
  Clock Net Delay (Destination): 2.756ns (routing 1.327ns, distribution 1.429ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y100       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89456, routed)       3.103     3.776    d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/ctrl_i/aclk
    SLICE_X88Y143        FDRE                                         r  d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/ctrl_i/phase_0_r1_reg[11]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X88Y143        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.079     3.855 r  d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/ctrl_i/phase_0_r1_reg[11]/Q
                         net (fo=16, routed)          1.871     5.726    d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/ctrl_i/phase_0_r1[11]
    SLICE_X79Y297        LUT2 (Prop_D6LUT_SLICEM_I1_O)
                                                      0.037     5.763 r  d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/ctrl_i/phase_v1[9]_carry__0_i_5/O
                         net (fo=1, routed)           0.025     5.788    d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/ctrl_i/phase_v1[9]_carry__0_i_5_n_0
    SLICE_X79Y297        CARRY8 (Prop_CARRY8_SLICEM_S[3]_CO[7])
                                                      0.163     5.951 r  d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/ctrl_i/phase_v1[9]_carry__0/CO[7]
                         net (fo=1, routed)           0.026     5.977    d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/ctrl_i/phase_v1[9]_carry__0_n_0
    SLICE_X79Y298        CARRY8 (Prop_CARRY8_SLICEM_CI_O[7])
                                                      0.116     6.093 r  d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/ctrl_i/phase_v1[9]_carry__1/O[7]
                         net (fo=1, routed)           0.026     6.119    d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/ctrl_i/phase_v1[9]_76[23]
    SLICE_X79Y298        FDRE                                         r  d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/ctrl_i/GEN_phase[9].phase_v1_r1_reg[9][23]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      2.604     2.604 r  
    HSDAC_X0Y0           HSDAC                        0.000     2.604 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     2.885 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     3.011    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y100       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     3.125 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89456, routed)       2.756     5.881    d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/ctrl_i/aclk
    SLICE_X79Y298        FDRE                                         r  d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/ctrl_i/GEN_phase[9].phase_v1_r1_reg[9][23]/C
                         clock pessimism              0.285     6.166    
                         clock uncertainty           -0.035     6.130    
    SLICE_X79Y298        FDRE (Setup_HFF_SLICEM_C_D)
                                                      0.025     6.155    d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/ctrl_i/GEN_phase[9].phase_v1_r1_reg[9][23]
  -------------------------------------------------------------------
                         required time                          6.155    
                         arrival time                          -6.119    
  -------------------------------------------------------------------
                         slack                                  0.036    

Slack (MET) :             0.037ns  (required time - arrival time)
  Source:                 d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/ctrl_i/phase_0_r1_reg[11]/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/ctrl_i/GEN_phase[9].phase_v1_r1_reg[9][21]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             RFDAC0_CLK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            2.604ns  (RFDAC0_CLK rise@2.604ns - RFDAC0_CLK rise@0.000ns)
  Data Path Delay:        2.342ns  (logic 0.395ns (16.863%)  route 1.947ns (83.137%))
  Logic Levels:           3  (CARRY8=2 LUT2=1)
  Clock Path Skew:        -0.214ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.277ns = ( 5.881 - 2.604 ) 
    Source Clock Delay      (SCD):    3.776ns
    Clock Pessimism Removal (CPR):    0.285ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      3.103ns (routing 1.460ns, distribution 1.643ns)
  Clock Net Delay (Destination): 2.756ns (routing 1.327ns, distribution 1.429ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y100       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89456, routed)       3.103     3.776    d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/ctrl_i/aclk
    SLICE_X88Y143        FDRE                                         r  d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/ctrl_i/phase_0_r1_reg[11]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X88Y143        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.079     3.855 r  d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/ctrl_i/phase_0_r1_reg[11]/Q
                         net (fo=16, routed)          1.871     5.726    d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/ctrl_i/phase_0_r1[11]
    SLICE_X79Y297        LUT2 (Prop_D6LUT_SLICEM_I1_O)
                                                      0.037     5.763 r  d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/ctrl_i/phase_v1[9]_carry__0_i_5/O
                         net (fo=1, routed)           0.025     5.788    d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/ctrl_i/phase_v1[9]_carry__0_i_5_n_0
    SLICE_X79Y297        CARRY8 (Prop_CARRY8_SLICEM_S[3]_CO[7])
                                                      0.163     5.951 r  d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/ctrl_i/phase_v1[9]_carry__0/CO[7]
                         net (fo=1, routed)           0.026     5.977    d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/ctrl_i/phase_v1[9]_carry__0_n_0
    SLICE_X79Y298        CARRY8 (Prop_CARRY8_SLICEM_CI_O[5])
                                                      0.116     6.093 r  d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/ctrl_i/phase_v1[9]_carry__1/O[5]
                         net (fo=1, routed)           0.025     6.118    d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/ctrl_i/phase_v1[9]_76[21]
    SLICE_X79Y298        FDRE                                         r  d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/ctrl_i/GEN_phase[9].phase_v1_r1_reg[9][21]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      2.604     2.604 r  
    HSDAC_X0Y0           HSDAC                        0.000     2.604 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     2.885 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     3.011    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y100       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     3.125 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89456, routed)       2.756     5.881    d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/ctrl_i/aclk
    SLICE_X79Y298        FDRE                                         r  d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/ctrl_i/GEN_phase[9].phase_v1_r1_reg[9][21]/C
                         clock pessimism              0.285     6.166    
                         clock uncertainty           -0.035     6.130    
    SLICE_X79Y298        FDRE (Setup_FFF_SLICEM_C_D)
                                                      0.025     6.155    d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/ctrl_i/GEN_phase[9].phase_v1_r1_reg[9][21]
  -------------------------------------------------------------------
                         required time                          6.155    
                         arrival time                          -6.118    
  -------------------------------------------------------------------
                         slack                                  0.037    

Slack (MET) :             0.037ns  (required time - arrival time)
  Source:                 d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/mem_addr_int_r_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/GEN_mem[15].mem_imag_i/RAM_reg_bram_0/ADDRBWRADDR[6]
                            (rising edge-triggered cell RAMB36E2 clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             RFDAC0_CLK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            2.604ns  (RFDAC0_CLK rise@2.604ns - RFDAC0_CLK rise@0.000ns)
  Data Path Delay:        2.138ns  (logic 0.081ns (3.788%)  route 2.057ns (96.212%))
  Logic Levels:           0  
  Clock Path Skew:        -0.106ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.400ns = ( 6.004 - 2.604 ) 
    Source Clock Delay      (SCD):    3.791ns
    Clock Pessimism Removal (CPR):    0.285ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      3.118ns (routing 1.460ns, distribution 1.658ns)
  Clock Net Delay (Destination): 2.879ns (routing 1.327ns, distribution 1.552ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y100       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89456, routed)       3.118     3.791    d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/aclk
    SLICE_X105Y211       FDRE                                         r  d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/mem_addr_int_r_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X105Y211       FDRE (Prop_DFF2_SLICEL_C_Q)
                                                      0.081     3.872 r  d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/mem_addr_int_r_reg[2]/Q
                         net (fo=32, routed)          2.057     5.929    d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/GEN_mem[15].mem_imag_i/ADDRBWRADDR[2]
    RAMB36_X9Y75         RAMB36E2                                     r  d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/GEN_mem[15].mem_imag_i/RAM_reg_bram_0/ADDRBWRADDR[6]
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      2.604     2.604 r  
    HSDAC_X0Y0           HSDAC                        0.000     2.604 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     2.885 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     3.011    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y100       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     3.125 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89456, routed)       2.879     6.004    d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/GEN_mem[15].mem_imag_i/aclk
    RAMB36_X9Y75         RAMB36E2                                     r  d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/GEN_mem[15].mem_imag_i/RAM_reg_bram_0/CLKBWRCLK
                         clock pessimism              0.285     6.289    
                         clock uncertainty           -0.035     6.253    
    RAMB36_X9Y75         RAMB36E2 (Setup_RAMB36E2_RAMB36_CLKBWRCLK_ADDRBWRADDR[6])
                                                     -0.287     5.966    d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/GEN_mem[15].mem_imag_i/RAM_reg_bram_0
  -------------------------------------------------------------------
                         required time                          5.966    
                         arrival time                          -5.929    
  -------------------------------------------------------------------
                         slack                                  0.037    

Slack (MET) :             0.040ns  (required time - arrival time)
  Source:                 d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/ctrl_i/phase_0_r1_reg[14]/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/ctrl_i/GEN_phase[11].phase_v1_r1_reg[11][31]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             RFDAC0_CLK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            2.604ns  (RFDAC0_CLK rise@2.604ns - RFDAC0_CLK rise@0.000ns)
  Data Path Delay:        2.373ns  (logic 0.364ns (15.341%)  route 2.009ns (84.659%))
  Logic Levels:           4  (CARRY8=3 LUT2=1)
  Clock Path Skew:        -0.181ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.356ns = ( 5.960 - 2.604 ) 
    Source Clock Delay      (SCD):    3.821ns
    Clock Pessimism Removal (CPR):    0.285ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      3.148ns (routing 1.460ns, distribution 1.688ns)
  Clock Net Delay (Destination): 2.835ns (routing 1.327ns, distribution 1.508ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y100       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89456, routed)       3.148     3.821    d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/ctrl_i/aclk
    SLICE_X105Y222       FDRE                                         r  d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/ctrl_i/phase_0_r1_reg[14]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X105Y222       FDRE (Prop_GFF_SLICEL_C_Q)
                                                      0.079     3.900 r  d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/ctrl_i/phase_0_r1_reg[14]/Q
                         net (fo=16, routed)          1.915     5.815    d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/ctrl_i/phase_0_r1[14]
    SLICE_X86Y376        LUT2 (Prop_G6LUT_SLICEM_I1_O)
                                                      0.037     5.852 r  d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/ctrl_i/phase_v1[11]_carry__0_i_2/O
                         net (fo=1, routed)           0.016     5.868    d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/ctrl_i/phase_v1[11]_carry__0_i_2_n_0
    SLICE_X86Y376        CARRY8 (Prop_CARRY8_SLICEM_S[6]_CO[7])
                                                      0.117     5.985 r  d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/ctrl_i/phase_v1[11]_carry__0/CO[7]
                         net (fo=1, routed)           0.026     6.011    d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/ctrl_i/phase_v1[11]_carry__0_n_0
    SLICE_X86Y377        CARRY8 (Prop_CARRY8_SLICEM_CI_CO[7])
                                                      0.015     6.026 r  d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/ctrl_i/phase_v1[11]_carry__1/CO[7]
                         net (fo=1, routed)           0.026     6.052    d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/ctrl_i/phase_v1[11]_carry__1_n_0
    SLICE_X86Y378        CARRY8 (Prop_CARRY8_SLICEM_CI_O[7])
                                                      0.116     6.168 r  d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/ctrl_i/phase_v1[11]_carry__2/O[7]
                         net (fo=1, routed)           0.026     6.194    d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/ctrl_i/phase_v1[11]_77[31]
    SLICE_X86Y378        FDRE                                         r  d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/ctrl_i/GEN_phase[11].phase_v1_r1_reg[11][31]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      2.604     2.604 r  
    HSDAC_X0Y0           HSDAC                        0.000     2.604 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     2.885 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     3.011    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y100       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     3.125 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89456, routed)       2.835     5.960    d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/ctrl_i/aclk
    SLICE_X86Y378        FDRE                                         r  d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/ctrl_i/GEN_phase[11].phase_v1_r1_reg[11][31]/C
                         clock pessimism              0.285     6.245    
                         clock uncertainty           -0.035     6.209    
    SLICE_X86Y378        FDRE (Setup_HFF_SLICEM_C_D)
                                                      0.025     6.234    d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/ctrl_i/GEN_phase[11].phase_v1_r1_reg[11][31]
  -------------------------------------------------------------------
                         required time                          6.234    
                         arrival time                          -6.194    
  -------------------------------------------------------------------
                         slack                                  0.040    

Slack (MET) :             0.041ns  (required time - arrival time)
  Source:                 d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/ctrl_i/en_reg_r6_reg_r/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/mem_addr_int_r_reg[9]_replica_5/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             RFDAC0_CLK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            2.604ns  (RFDAC0_CLK rise@2.604ns - RFDAC0_CLK rise@0.000ns)
  Data Path Delay:        2.402ns  (logic 0.145ns (6.036%)  route 2.257ns (93.964%))
  Logic Levels:           1  (LUT2=1)
  Clock Path Skew:        -0.151ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.423ns = ( 6.027 - 2.604 ) 
    Source Clock Delay      (SCD):    3.866ns
    Clock Pessimism Removal (CPR):    0.293ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      3.193ns (routing 1.460ns, distribution 1.733ns)
  Clock Net Delay (Destination): 2.902ns (routing 1.327ns, distribution 1.575ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y100       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89456, routed)       3.193     3.866    d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/ctrl_i/aclk
    SLICE_X102Y245       FDRE                                         r  d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/ctrl_i/en_reg_r6_reg_r/C
  -------------------------------------------------------------------    -------------------
    SLICE_X102Y245       FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.079     3.945 r  d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/ctrl_i/en_reg_r6_reg_r/Q
                         net (fo=19, routed)          0.324     4.270    d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/ctrl_i/en_reg_r6_reg_r_n_0_alias_1
    SLICE_X92Y247        LUT2 (Prop_D5LUT_SLICEL_I1_O)
                                                      0.066     4.336 r  d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/ctrl_i/addr_cnt_r6_reg_gate__0/O
                         net (fo=9, routed)           1.933     6.269    d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/ctrl_i_n_5
    SLICE_X104Y399       FDRE                                         r  d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/mem_addr_int_r_reg[9]_replica_5/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      2.604     2.604 r  
    HSDAC_X0Y0           HSDAC                        0.000     2.604 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     2.885 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     3.011    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y100       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     3.125 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89456, routed)       2.902     6.027    d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/aclk
    SLICE_X104Y399       FDRE                                         r  d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/mem_addr_int_r_reg[9]_replica_5/C
                         clock pessimism              0.293     6.320    
                         clock uncertainty           -0.035     6.284    
    SLICE_X104Y399       FDRE (Setup_FFF_SLICEM_C_D)
                                                      0.025     6.309    d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/mem_addr_int_r_reg[9]_replica_5
  -------------------------------------------------------------------
                         required time                          6.309    
                         arrival time                          -6.269    
  -------------------------------------------------------------------
                         slack                                  0.041    

Slack (MET) :             0.041ns  (required time - arrival time)
  Source:                 d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/ctrl_i/phase_0_r1_reg[6]/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/ctrl_i/GEN_phase[7].phase_v1_r1_reg[7][15]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             RFDAC0_CLK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            2.604ns  (RFDAC0_CLK rise@2.604ns - RFDAC0_CLK rise@0.000ns)
  Data Path Delay:        2.257ns  (logic 0.349ns (15.460%)  route 1.908ns (84.540%))
  Logic Levels:           3  (CARRY8=2 LUT2=1)
  Clock Path Skew:        -0.296ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.240ns = ( 5.844 - 2.604 ) 
    Source Clock Delay      (SCD):    3.820ns
    Clock Pessimism Removal (CPR):    0.285ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      3.147ns (routing 1.460ns, distribution 1.687ns)
  Clock Net Delay (Destination): 2.719ns (routing 1.327ns, distribution 1.392ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y100       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89456, routed)       3.147     3.820    d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/ctrl_i/aclk
    SLICE_X105Y221       FDRE                                         r  d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/ctrl_i/phase_0_r1_reg[6]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X105Y221       FDRE (Prop_GFF_SLICEL_C_Q)
                                                      0.079     3.899 r  d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/ctrl_i/phase_0_r1_reg[6]/Q
                         net (fo=16, routed)          1.840     5.740    d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/ctrl_i/phase_0_r1[6]
    SLICE_X78Y346        LUT2 (Prop_G6LUT_SLICEM_I1_O)
                                                      0.037     5.777 r  d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/ctrl_i/phase_v1[7]_carry_i_2/O
                         net (fo=1, routed)           0.016     5.793    d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/ctrl_i/phase_v1[7]_carry_i_2_n_0
    SLICE_X78Y346        CARRY8 (Prop_CARRY8_SLICEM_S[6]_CO[7])
                                                      0.117     5.910 r  d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/ctrl_i/phase_v1[7]_carry/CO[7]
                         net (fo=1, routed)           0.026     5.936    d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/ctrl_i/phase_v1[7]_carry_n_0
    SLICE_X78Y347        CARRY8 (Prop_CARRY8_SLICEM_CI_O[7])
                                                      0.116     6.052 r  d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/ctrl_i/phase_v1[7]_carry__0/O[7]
                         net (fo=1, routed)           0.026     6.078    d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/ctrl_i/phase_v1[7]_74[15]
    SLICE_X78Y347        FDRE                                         r  d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/ctrl_i/GEN_phase[7].phase_v1_r1_reg[7][15]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      2.604     2.604 r  
    HSDAC_X0Y0           HSDAC                        0.000     2.604 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     2.885 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     3.011    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y100       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     3.125 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89456, routed)       2.719     5.844    d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/ctrl_i/aclk
    SLICE_X78Y347        FDRE                                         r  d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/ctrl_i/GEN_phase[7].phase_v1_r1_reg[7][15]/C
                         clock pessimism              0.285     6.129    
                         clock uncertainty           -0.035     6.093    
    SLICE_X78Y347        FDRE (Setup_HFF_SLICEM_C_D)
                                                      0.025     6.118    d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/ctrl_i/GEN_phase[7].phase_v1_r1_reg[7][15]
  -------------------------------------------------------------------
                         required time                          6.118    
                         arrival time                          -6.078    
  -------------------------------------------------------------------
                         slack                                  0.041    

Slack (MET) :             0.041ns  (required time - arrival time)
  Source:                 d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/ctrl_i/phase_0_r1_reg[14]/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/ctrl_i/GEN_phase[11].phase_v1_r1_reg[11][29]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             RFDAC0_CLK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            2.604ns  (RFDAC0_CLK rise@2.604ns - RFDAC0_CLK rise@0.000ns)
  Data Path Delay:        2.372ns  (logic 0.364ns (15.347%)  route 2.008ns (84.653%))
  Logic Levels:           4  (CARRY8=3 LUT2=1)
  Clock Path Skew:        -0.181ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.356ns = ( 5.960 - 2.604 ) 
    Source Clock Delay      (SCD):    3.821ns
    Clock Pessimism Removal (CPR):    0.285ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      3.148ns (routing 1.460ns, distribution 1.688ns)
  Clock Net Delay (Destination): 2.835ns (routing 1.327ns, distribution 1.508ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y100       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89456, routed)       3.148     3.821    d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/ctrl_i/aclk
    SLICE_X105Y222       FDRE                                         r  d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/ctrl_i/phase_0_r1_reg[14]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X105Y222       FDRE (Prop_GFF_SLICEL_C_Q)
                                                      0.079     3.900 r  d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/ctrl_i/phase_0_r1_reg[14]/Q
                         net (fo=16, routed)          1.915     5.815    d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/ctrl_i/phase_0_r1[14]
    SLICE_X86Y376        LUT2 (Prop_G6LUT_SLICEM_I1_O)
                                                      0.037     5.852 r  d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/ctrl_i/phase_v1[11]_carry__0_i_2/O
                         net (fo=1, routed)           0.016     5.868    d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/ctrl_i/phase_v1[11]_carry__0_i_2_n_0
    SLICE_X86Y376        CARRY8 (Prop_CARRY8_SLICEM_S[6]_CO[7])
                                                      0.117     5.985 r  d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/ctrl_i/phase_v1[11]_carry__0/CO[7]
                         net (fo=1, routed)           0.026     6.011    d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/ctrl_i/phase_v1[11]_carry__0_n_0
    SLICE_X86Y377        CARRY8 (Prop_CARRY8_SLICEM_CI_CO[7])
                                                      0.015     6.026 r  d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/ctrl_i/phase_v1[11]_carry__1/CO[7]
                         net (fo=1, routed)           0.026     6.052    d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/ctrl_i/phase_v1[11]_carry__1_n_0
    SLICE_X86Y378        CARRY8 (Prop_CARRY8_SLICEM_CI_O[5])
                                                      0.116     6.168 r  d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/ctrl_i/phase_v1[11]_carry__2/O[5]
                         net (fo=1, routed)           0.025     6.193    d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/ctrl_i/phase_v1[11]_77[29]
    SLICE_X86Y378        FDRE                                         r  d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/ctrl_i/GEN_phase[11].phase_v1_r1_reg[11][29]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      2.604     2.604 r  
    HSDAC_X0Y0           HSDAC                        0.000     2.604 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     2.885 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     3.011    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y100       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     3.125 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89456, routed)       2.835     5.960    d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/ctrl_i/aclk
    SLICE_X86Y378        FDRE                                         r  d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/ctrl_i/GEN_phase[11].phase_v1_r1_reg[11][29]/C
                         clock pessimism              0.285     6.245    
                         clock uncertainty           -0.035     6.209    
    SLICE_X86Y378        FDRE (Setup_FFF_SLICEM_C_D)
                                                      0.025     6.234    d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/ctrl_i/GEN_phase[11].phase_v1_r1_reg[11][29]
  -------------------------------------------------------------------
                         required time                          6.234    
                         arrival time                          -6.193    
  -------------------------------------------------------------------
                         slack                                  0.041    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.008ns  (arrival time - required time)
  Source:                 d_1_i/axis_signal_gen_v6_4/inst/signal_gen_top_i/signal_gen_i/GEN_dds[7].mem_real_latency_reg_i/GEN_reg[7].shift_r_reg[7][15]/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/axis_signal_gen_v6_4/inst/signal_gen_top_i/signal_gen_i/GEN_dds[7].mem_mux_latency_reg_i/shift_r_reg[0][15]_srl3___inst_signal_gen_top_i_signal_gen_i_ctrl_i_en_reg_r3_reg_r/D
                            (rising edge-triggered cell SRL16E clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             RFDAC0_CLK
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (RFDAC0_CLK rise@0.000ns - RFDAC0_CLK rise@0.000ns)
  Data Path Delay:        0.279ns  (logic 0.061ns (21.832%)  route 0.218ns (78.168%))
  Logic Levels:           0  
  Clock Path Skew:        0.192ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.750ns
    Source Clock Delay      (SCD):    3.248ns
    Clock Pessimism Removal (CPR):    0.310ns
  Clock Net Delay (Source):      2.727ns (routing 1.327ns, distribution 1.400ns)
  Clock Net Delay (Destination): 3.077ns (routing 1.460ns, distribution 1.617ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y100       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89456, routed)       2.727     3.248    d_1_i/axis_signal_gen_v6_4/inst/signal_gen_top_i/signal_gen_i/GEN_dds[7].mem_real_latency_reg_i/aclk
    SLICE_X74Y365        FDRE                                         r  d_1_i/axis_signal_gen_v6_4/inst/signal_gen_top_i/signal_gen_i/GEN_dds[7].mem_real_latency_reg_i/GEN_reg[7].shift_r_reg[7][15]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X74Y365        FDRE (Prop_DFF2_SLICEL_C_Q)
                                                      0.061     3.309 r  d_1_i/axis_signal_gen_v6_4/inst/signal_gen_top_i/signal_gen_i/GEN_dds[7].mem_real_latency_reg_i/GEN_reg[7].shift_r_reg[7][15]/Q
                         net (fo=4, routed)           0.218     3.527    d_1_i/axis_signal_gen_v6_4/inst/signal_gen_top_i/signal_gen_i/GEN_dds[7].mem_mux_latency_reg_i/B[15]
    SLICE_X76Y357        SRL16E                                       r  d_1_i/axis_signal_gen_v6_4/inst/signal_gen_top_i/signal_gen_i/GEN_dds[7].mem_mux_latency_reg_i/shift_r_reg[0][15]_srl3___inst_signal_gen_top_i_signal_gen_i_ctrl_i_en_reg_r3_reg_r/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y100       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89456, routed)       3.077     3.750    d_1_i/axis_signal_gen_v6_4/inst/signal_gen_top_i/signal_gen_i/GEN_dds[7].mem_mux_latency_reg_i/aclk
    SLICE_X76Y357        SRL16E                                       r  d_1_i/axis_signal_gen_v6_4/inst/signal_gen_top_i/signal_gen_i/GEN_dds[7].mem_mux_latency_reg_i/shift_r_reg[0][15]_srl3___inst_signal_gen_top_i_signal_gen_i_ctrl_i_en_reg_r3_reg_r/CLK
                         clock pessimism             -0.310     3.440    
    SLICE_X76Y357        SRL16E (Hold_H5LUT_SLICEM_CLK_D)
                                                      0.079     3.519    d_1_i/axis_signal_gen_v6_4/inst/signal_gen_top_i/signal_gen_i/GEN_dds[7].mem_mux_latency_reg_i/shift_r_reg[0][15]_srl3___inst_signal_gen_top_i_signal_gen_i_ctrl_i_en_reg_r3_reg_r
  -------------------------------------------------------------------
                         required time                         -3.519    
                         arrival time                           3.527    
  -------------------------------------------------------------------
                         slack                                  0.008    

Slack (MET) :             0.009ns  (arrival time - required time)
  Source:                 d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/dds_ctrl_int_r_reg[1110]/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/GEN_dds[4].dds_i/U0/i_synth/has_s_phase.i_has_no_tready.reg_s_phase_fifo_din_reg[30]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             RFDAC0_CLK
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (RFDAC0_CLK rise@0.000ns - RFDAC0_CLK rise@0.000ns)
  Data Path Delay:        0.264ns  (logic 0.058ns (21.946%)  route 0.206ns (78.054%))
  Logic Levels:           0  
  Clock Path Skew:        0.195ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.701ns
    Source Clock Delay      (SCD):    3.221ns
    Clock Pessimism Removal (CPR):    0.285ns
  Clock Net Delay (Source):      2.700ns (routing 1.327ns, distribution 1.373ns)
  Clock Net Delay (Destination): 3.028ns (routing 1.460ns, distribution 1.568ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y100       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89456, routed)       2.700     3.221    d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/aclk
    SLICE_X80Y242        FDRE                                         r  d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/dds_ctrl_int_r_reg[1110]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X80Y242        FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.058     3.279 r  d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/dds_ctrl_int_r_reg[1110]/Q
                         net (fo=32, routed)          0.206     3.485    d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/GEN_dds[4].dds_i/U0/i_synth/s_axis_phase_tdata[30]
    SLICE_X80Y224        FDRE                                         r  d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/GEN_dds[4].dds_i/U0/i_synth/has_s_phase.i_has_no_tready.reg_s_phase_fifo_din_reg[30]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y100       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89456, routed)       3.028     3.701    d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/GEN_dds[4].dds_i/U0/i_synth/aclk
    SLICE_X80Y224        FDRE                                         r  d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/GEN_dds[4].dds_i/U0/i_synth/has_s_phase.i_has_no_tready.reg_s_phase_fifo_din_reg[30]/C
                         clock pessimism             -0.285     3.416    
    SLICE_X80Y224        FDRE (Hold_FFF_SLICEL_C_D)
                                                      0.060     3.476    d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/GEN_dds[4].dds_i/U0/i_synth/has_s_phase.i_has_no_tready.reg_s_phase_fifo_din_reg[30]
  -------------------------------------------------------------------
                         required time                         -3.476    
                         arrival time                           3.485    
  -------------------------------------------------------------------
                         slack                                  0.009    

Slack (MET) :             0.010ns  (arrival time - required time)
  Source:                 d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[15].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_piped_map.i_original_sin_ls/opt_has_pipe.first_q_reg[4]/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[15].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ls/opt_has_pipe.first_q_reg[4]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             RFDAC0_CLK
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (RFDAC0_CLK rise@0.000ns - RFDAC0_CLK rise@0.000ns)
  Data Path Delay:        0.273ns  (logic 0.059ns (21.612%)  route 0.214ns (78.388%))
  Logic Levels:           0  
  Clock Path Skew:        0.201ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.623ns
    Source Clock Delay      (SCD):    3.137ns
    Clock Pessimism Removal (CPR):    0.285ns
  Clock Net Delay (Source):      2.616ns (routing 1.327ns, distribution 1.289ns)
  Clock Net Delay (Destination): 2.950ns (routing 1.460ns, distribution 1.490ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y100       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89456, routed)       2.616     3.137    d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[15].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_piped_map.i_original_sin_ls/aclk
    SLICE_X29Y231        FDRE                                         r  d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[15].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_piped_map.i_original_sin_ls/opt_has_pipe.first_q_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X29Y231        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.059     3.196 r  d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[15].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_piped_map.i_original_sin_ls/opt_has_pipe.first_q_reg[4]/Q
                         net (fo=1, routed)           0.214     3.410    d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[15].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ls/D[4]
    SLICE_X32Y240        FDRE                                         r  d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[15].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ls/opt_has_pipe.first_q_reg[4]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y100       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89456, routed)       2.950     3.623    d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[15].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ls/aclk
    SLICE_X32Y240        FDRE                                         r  d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[15].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ls/opt_has_pipe.first_q_reg[4]/C
                         clock pessimism             -0.285     3.338    
    SLICE_X32Y240        FDRE (Hold_AFF2_SLICEL_C_D)
                                                      0.062     3.400    d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[15].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ls/opt_has_pipe.first_q_reg[4]
  -------------------------------------------------------------------
                         required time                         -3.400    
                         arrival time                           3.410    
  -------------------------------------------------------------------
                         slack                                  0.010    

Slack (MET) :             0.010ns  (arrival time - required time)
  Source:                 d_1_i/axis_signal_gen_v6_1/inst/signal_gen_top_i/signal_gen_i/GEN_dds[10].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_piped_map.i_original_cos_ls/opt_has_pipe.first_q_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/axis_signal_gen_v6_1/inst/signal_gen_top_i/signal_gen_i/GEN_dds[10].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_cos_ls/opt_has_pipe.first_q_reg[2]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             RFDAC0_CLK
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (RFDAC0_CLK rise@0.000ns - RFDAC0_CLK rise@0.000ns)
  Data Path Delay:        0.284ns  (logic 0.058ns (20.423%)  route 0.226ns (79.577%))
  Logic Levels:           0  
  Clock Path Skew:        0.212ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.641ns
    Source Clock Delay      (SCD):    3.144ns
    Clock Pessimism Removal (CPR):    0.285ns
  Clock Net Delay (Source):      2.623ns (routing 1.327ns, distribution 1.296ns)
  Clock Net Delay (Destination): 2.968ns (routing 1.460ns, distribution 1.508ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y100       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89456, routed)       2.623     3.144    d_1_i/axis_signal_gen_v6_1/inst/signal_gen_top_i/signal_gen_i/GEN_dds[10].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_piped_map.i_original_cos_ls/aclk
    SLICE_X24Y220        FDRE                                         r  d_1_i/axis_signal_gen_v6_1/inst/signal_gen_top_i/signal_gen_i/GEN_dds[10].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_piped_map.i_original_cos_ls/opt_has_pipe.first_q_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X24Y220        FDRE (Prop_CFF_SLICEM_C_Q)
                                                      0.058     3.202 r  d_1_i/axis_signal_gen_v6_1/inst/signal_gen_top_i/signal_gen_i/GEN_dds[10].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_piped_map.i_original_cos_ls/opt_has_pipe.first_q_reg[2]/Q
                         net (fo=1, routed)           0.226     3.428    d_1_i/axis_signal_gen_v6_1/inst/signal_gen_top_i/signal_gen_i/GEN_dds[10].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_cos_ls/D[2]
    SLICE_X25Y249        FDRE                                         r  d_1_i/axis_signal_gen_v6_1/inst/signal_gen_top_i/signal_gen_i/GEN_dds[10].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_cos_ls/opt_has_pipe.first_q_reg[2]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y100       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89456, routed)       2.968     3.641    d_1_i/axis_signal_gen_v6_1/inst/signal_gen_top_i/signal_gen_i/GEN_dds[10].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_cos_ls/aclk
    SLICE_X25Y249        FDRE                                         r  d_1_i/axis_signal_gen_v6_1/inst/signal_gen_top_i/signal_gen_i/GEN_dds[10].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_cos_ls/opt_has_pipe.first_q_reg[2]/C
                         clock pessimism             -0.285     3.356    
    SLICE_X25Y249        FDRE (Hold_HFF2_SLICEL_C_D)
                                                      0.062     3.418    d_1_i/axis_signal_gen_v6_1/inst/signal_gen_top_i/signal_gen_i/GEN_dds[10].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_cos_ls/opt_has_pipe.first_q_reg[2]
  -------------------------------------------------------------------
                         required time                         -3.418    
                         arrival time                           3.428    
  -------------------------------------------------------------------
                         slack                                  0.010    

Slack (MET) :             0.010ns  (arrival time - required time)
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/m_axis_tdata_r_reg[5][71]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/fifo_i/mem_i/RAM_reg_0_15_70_83/RAMA_D1/I
                            (rising edge-triggered cell RAMD32 clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             RFDAC0_CLK
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (RFDAC0_CLK rise@0.000ns - RFDAC0_CLK rise@0.000ns)
  Data Path Delay:        0.223ns  (logic 0.061ns (27.354%)  route 0.162ns (72.646%))
  Logic Levels:           0  
  Clock Path Skew:        0.155ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.820ns
    Source Clock Delay      (SCD):    3.283ns
    Clock Pessimism Removal (CPR):    0.382ns
  Clock Net Delay (Source):      2.762ns (routing 1.327ns, distribution 1.435ns)
  Clock Net Delay (Destination): 3.147ns (routing 1.460ns, distribution 1.687ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y100       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89456, routed)       2.762     3.283    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
    SLICE_X84Y124        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/m_axis_tdata_r_reg[5][71]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X84Y124        FDCE (Prop_DFF2_SLICEL_C_Q)
                                                      0.061     3.344 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/m_axis_tdata_r_reg[5][71]/Q
                         net (fo=1, routed)           0.162     3.506    d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/fifo_i/mem_i/RAM_reg_0_15_70_83/DIA1
    SLICE_X87Y125        RAMD32                                       r  d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/fifo_i/mem_i/RAM_reg_0_15_70_83/RAMA_D1/I
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y100       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89456, routed)       3.147     3.820    d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/fifo_i/mem_i/RAM_reg_0_15_70_83/WCLK
    SLICE_X87Y125        RAMD32                                       r  d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/fifo_i/mem_i/RAM_reg_0_15_70_83/RAMA_D1/CLK
                         clock pessimism             -0.382     3.438    
    SLICE_X87Y125        RAMD32 (Hold_A6LUT_SLICEM_CLK_I)
                                                      0.058     3.496    d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/fifo_i/mem_i/RAM_reg_0_15_70_83/RAMA_D1
  -------------------------------------------------------------------
                         required time                         -3.496    
                         arrival time                           3.506    
  -------------------------------------------------------------------
                         slack                                  0.010    

Slack (MET) :             0.011ns  (arrival time - required time)
  Source:                 d_1_i/axis_signal_gen_v6_4/inst/signal_gen_top_i/signal_gen_i/ctrl_i/GEN_phase[12].phase_v1_r1_reg[12][12]/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/axis_signal_gen_v6_4/inst/signal_gen_top_i/signal_gen_i/dds_ctrl_int_r_reg[908]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             RFDAC0_CLK
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (RFDAC0_CLK rise@0.000ns - RFDAC0_CLK rise@0.000ns)
  Data Path Delay:        0.176ns  (logic 0.058ns (32.955%)  route 0.118ns (67.045%))
  Logic Levels:           0  
  Clock Path Skew:        0.103ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.581ns
    Source Clock Delay      (SCD):    3.109ns
    Clock Pessimism Removal (CPR):    0.368ns
  Clock Net Delay (Source):      2.588ns (routing 1.327ns, distribution 1.261ns)
  Clock Net Delay (Destination): 2.908ns (routing 1.460ns, distribution 1.448ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y100       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89456, routed)       2.588     3.109    d_1_i/axis_signal_gen_v6_4/inst/signal_gen_top_i/signal_gen_i/ctrl_i/aclk
    SLICE_X55Y331        FDRE                                         r  d_1_i/axis_signal_gen_v6_4/inst/signal_gen_top_i/signal_gen_i/ctrl_i/GEN_phase[12].phase_v1_r1_reg[12][12]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X55Y331        FDRE (Prop_CFF_SLICEL_C_Q)
                                                      0.058     3.167 r  d_1_i/axis_signal_gen_v6_4/inst/signal_gen_top_i/signal_gen_i/ctrl_i/GEN_phase[12].phase_v1_r1_reg[12][12]/Q
                         net (fo=1, routed)           0.118     3.285    d_1_i/axis_signal_gen_v6_4/inst/signal_gen_top_i/signal_gen_i/dds_ctrl_int[908]
    SLICE_X55Y328        FDRE                                         r  d_1_i/axis_signal_gen_v6_4/inst/signal_gen_top_i/signal_gen_i/dds_ctrl_int_r_reg[908]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y100       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89456, routed)       2.908     3.581    d_1_i/axis_signal_gen_v6_4/inst/signal_gen_top_i/signal_gen_i/aclk
    SLICE_X55Y328        FDRE                                         r  d_1_i/axis_signal_gen_v6_4/inst/signal_gen_top_i/signal_gen_i/dds_ctrl_int_r_reg[908]/C
                         clock pessimism             -0.368     3.213    
    SLICE_X55Y328        FDRE (Hold_EFF2_SLICEL_C_D)
                                                      0.062     3.275    d_1_i/axis_signal_gen_v6_4/inst/signal_gen_top_i/signal_gen_i/dds_ctrl_int_r_reg[908]
  -------------------------------------------------------------------
                         required time                         -3.275    
                         arrival time                           3.285    
  -------------------------------------------------------------------
                         slack                                  0.011    

Slack (MET) :             0.011ns  (arrival time - required time)
  Source:                 d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/GEN_dds[7].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_piped_map.i_original_cos_ls/opt_has_pipe.first_q_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/GEN_dds[7].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_cos_ls/opt_has_pipe.first_q_reg[2]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             RFDAC0_CLK
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (RFDAC0_CLK rise@0.000ns - RFDAC0_CLK rise@0.000ns)
  Data Path Delay:        0.297ns  (logic 0.059ns (19.865%)  route 0.238ns (80.135%))
  Logic Levels:           0  
  Clock Path Skew:        0.226ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.870ns
    Source Clock Delay      (SCD):    3.334ns
    Clock Pessimism Removal (CPR):    0.310ns
  Clock Net Delay (Source):      2.813ns (routing 1.327ns, distribution 1.486ns)
  Clock Net Delay (Destination): 3.197ns (routing 1.460ns, distribution 1.737ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y100       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89456, routed)       2.813     3.334    d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/GEN_dds[7].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_piped_map.i_original_cos_ls/aclk
    SLICE_X91Y342        FDRE                                         r  d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/GEN_dds[7].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_piped_map.i_original_cos_ls/opt_has_pipe.first_q_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X91Y342        FDRE (Prop_GFF_SLICEL_C_Q)
                                                      0.059     3.393 r  d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/GEN_dds[7].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_piped_map.i_original_cos_ls/opt_has_pipe.first_q_reg[2]/Q
                         net (fo=1, routed)           0.238     3.631    d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/GEN_dds[7].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_cos_ls/D[2]
    SLICE_X90Y369        FDRE                                         r  d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/GEN_dds[7].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_cos_ls/opt_has_pipe.first_q_reg[2]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y100       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89456, routed)       3.197     3.870    d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/GEN_dds[7].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_cos_ls/aclk
    SLICE_X90Y369        FDRE                                         r  d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/GEN_dds[7].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_cos_ls/opt_has_pipe.first_q_reg[2]/C
                         clock pessimism             -0.310     3.560    
    SLICE_X90Y369        FDRE (Hold_GFF_SLICEM_C_D)
                                                      0.060     3.620    d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/GEN_dds[7].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_cos_ls/opt_has_pipe.first_q_reg[2]
  -------------------------------------------------------------------
                         required time                         -3.620    
                         arrival time                           3.631    
  -------------------------------------------------------------------
                         slack                                  0.011    

Slack (MET) :             0.011ns  (arrival time - required time)
  Source:                 d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/GEN_dds[10].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_cos_ls/opt_has_pipe.first_q_reg[7]/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/GEN_dds[10].dds_mux_latency_reg_i/shift_r_reg[0][7]_srl3___inst_signal_gen_top_i_signal_gen_i_ctrl_i_en_reg_r3_reg_r/D
                            (rising edge-triggered cell SRL16E clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             RFDAC0_CLK
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (RFDAC0_CLK rise@0.000ns - RFDAC0_CLK rise@0.000ns)
  Data Path Delay:        0.137ns  (logic 0.058ns (42.404%)  route 0.079ns (57.595%))
  Logic Levels:           0  
  Clock Path Skew:        0.094ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.754ns
    Source Clock Delay      (SCD):    3.234ns
    Clock Pessimism Removal (CPR):    0.426ns
  Clock Net Delay (Source):      2.713ns (routing 1.327ns, distribution 1.386ns)
  Clock Net Delay (Destination): 3.081ns (routing 1.460ns, distribution 1.621ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y100       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89456, routed)       2.713     3.234    d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/GEN_dds[10].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_cos_ls/aclk
    SLICE_X70Y308        FDRE                                         r  d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/GEN_dds[10].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_cos_ls/opt_has_pipe.first_q_reg[7]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X70Y308        FDRE (Prop_AFF_SLICEM_C_Q)
                                                      0.058     3.292 r  d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/GEN_dds[10].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_cos_ls/opt_has_pipe.first_q_reg[7]/Q
                         net (fo=2, routed)           0.079     3.371    d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/GEN_dds[10].dds_mux_latency_reg_i/m_axis_data_tdata[7]
    SLICE_X70Y306        SRL16E                                       r  d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/GEN_dds[10].dds_mux_latency_reg_i/shift_r_reg[0][7]_srl3___inst_signal_gen_top_i_signal_gen_i_ctrl_i_en_reg_r3_reg_r/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y100       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89456, routed)       3.081     3.754    d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/GEN_dds[10].dds_mux_latency_reg_i/aclk
    SLICE_X70Y306        SRL16E                                       r  d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/GEN_dds[10].dds_mux_latency_reg_i/shift_r_reg[0][7]_srl3___inst_signal_gen_top_i_signal_gen_i_ctrl_i_en_reg_r3_reg_r/CLK
                         clock pessimism             -0.426     3.328    
    SLICE_X70Y306        SRL16E (Hold_H6LUT_SLICEM_CLK_D)
                                                      0.032     3.360    d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/GEN_dds[10].dds_mux_latency_reg_i/shift_r_reg[0][7]_srl3___inst_signal_gen_top_i_signal_gen_i_ctrl_i_en_reg_r3_reg_r
  -------------------------------------------------------------------
                         required time                         -3.360    
                         arrival time                           3.371    
  -------------------------------------------------------------------
                         slack                                  0.011    

Slack (MET) :             0.011ns  (arrival time - required time)
  Source:                 d_1_i/axis_signal_gen_v6_4/inst/signal_gen_top_i/signal_gen_i/ctrl_i/GEN_phase[13].phase_v1_r1_reg[13][29]/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/axis_signal_gen_v6_4/inst/signal_gen_top_i/signal_gen_i/dds_ctrl_int_r_reg[997]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             RFDAC0_CLK
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (RFDAC0_CLK rise@0.000ns - RFDAC0_CLK rise@0.000ns)
  Data Path Delay:        0.124ns  (logic 0.058ns (46.774%)  route 0.066ns (53.226%))
  Logic Levels:           0  
  Clock Path Skew:        0.051ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.597ns
    Source Clock Delay      (SCD):    3.129ns
    Clock Pessimism Removal (CPR):    0.417ns
  Clock Net Delay (Source):      2.608ns (routing 1.327ns, distribution 1.281ns)
  Clock Net Delay (Destination): 2.924ns (routing 1.460ns, distribution 1.464ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y100       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89456, routed)       2.608     3.129    d_1_i/axis_signal_gen_v6_4/inst/signal_gen_top_i/signal_gen_i/ctrl_i/aclk
    SLICE_X55Y349        FDRE                                         r  d_1_i/axis_signal_gen_v6_4/inst/signal_gen_top_i/signal_gen_i/ctrl_i/GEN_phase[13].phase_v1_r1_reg[13][29]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X55Y349        FDRE (Prop_FFF_SLICEL_C_Q)
                                                      0.058     3.187 r  d_1_i/axis_signal_gen_v6_4/inst/signal_gen_top_i/signal_gen_i/ctrl_i/GEN_phase[13].phase_v1_r1_reg[13][29]/Q
                         net (fo=1, routed)           0.066     3.253    d_1_i/axis_signal_gen_v6_4/inst/signal_gen_top_i/signal_gen_i/dds_ctrl_int[997]
    SLICE_X55Y350        FDRE                                         r  d_1_i/axis_signal_gen_v6_4/inst/signal_gen_top_i/signal_gen_i/dds_ctrl_int_r_reg[997]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y100       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89456, routed)       2.924     3.597    d_1_i/axis_signal_gen_v6_4/inst/signal_gen_top_i/signal_gen_i/aclk
    SLICE_X55Y350        FDRE                                         r  d_1_i/axis_signal_gen_v6_4/inst/signal_gen_top_i/signal_gen_i/dds_ctrl_int_r_reg[997]/C
                         clock pessimism             -0.417     3.180    
    SLICE_X55Y350        FDRE (Hold_GFF2_SLICEL_C_D)
                                                      0.062     3.242    d_1_i/axis_signal_gen_v6_4/inst/signal_gen_top_i/signal_gen_i/dds_ctrl_int_r_reg[997]
  -------------------------------------------------------------------
                         required time                         -3.242    
                         arrival time                           3.253    
  -------------------------------------------------------------------
                         slack                                  0.011    

Slack (MET) :             0.011ns  (arrival time - required time)
  Source:                 d_1_i/axis_signal_gen_v6_1/inst/signal_gen_top_i/signal_gen_i/ctrl_i/fifo_dout_r_reg[108]/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/axis_signal_gen_v6_1/inst/signal_gen_top_i/signal_gen_i/gain_latency_reg_i/GEN_reg[13].shift_r_reg[13][12]_srl21___inst_signal_gen_top_i_signal_gen_i_en_latency_reg_i_GEN_reg_r_10/D
                            (rising edge-triggered cell SRLC32E clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             RFDAC0_CLK
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (RFDAC0_CLK rise@0.000ns - RFDAC0_CLK rise@0.000ns)
  Data Path Delay:        0.358ns  (logic 0.060ns (16.760%)  route 0.298ns (83.240%))
  Logic Levels:           0  
  Clock Path Skew:        0.292ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.727ns
    Source Clock Delay      (SCD):    3.150ns
    Clock Pessimism Removal (CPR):    0.285ns
  Clock Net Delay (Source):      2.629ns (routing 1.327ns, distribution 1.302ns)
  Clock Net Delay (Destination): 3.054ns (routing 1.460ns, distribution 1.594ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y100       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89456, routed)       2.629     3.150    d_1_i/axis_signal_gen_v6_1/inst/signal_gen_top_i/signal_gen_i/ctrl_i/aclk
    SLICE_X73Y223        FDRE                                         r  d_1_i/axis_signal_gen_v6_1/inst/signal_gen_top_i/signal_gen_i/ctrl_i/fifo_dout_r_reg[108]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X73Y223        FDRE (Prop_EFF2_SLICEL_C_Q)
                                                      0.060     3.210 r  d_1_i/axis_signal_gen_v6_1/inst/signal_gen_top_i/signal_gen_i/ctrl_i/fifo_dout_r_reg[108]/Q
                         net (fo=1, routed)           0.298     3.508    d_1_i/axis_signal_gen_v6_1/inst/signal_gen_top_i/signal_gen_i/gain_latency_reg_i/GEN_reg[14].shift_r_reg[14][15]_inst_signal_gen_top_i_signal_gen_i_en_latency_reg_i_GEN_reg_r_11_0[12]
    SLICE_X75Y253        SRLC32E                                      r  d_1_i/axis_signal_gen_v6_1/inst/signal_gen_top_i/signal_gen_i/gain_latency_reg_i/GEN_reg[13].shift_r_reg[13][12]_srl21___inst_signal_gen_top_i_signal_gen_i_en_latency_reg_i_GEN_reg_r_10/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y100       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89456, routed)       3.054     3.727    d_1_i/axis_signal_gen_v6_1/inst/signal_gen_top_i/signal_gen_i/gain_latency_reg_i/aclk
    SLICE_X75Y253        SRLC32E                                      r  d_1_i/axis_signal_gen_v6_1/inst/signal_gen_top_i/signal_gen_i/gain_latency_reg_i/GEN_reg[13].shift_r_reg[13][12]_srl21___inst_signal_gen_top_i_signal_gen_i_en_latency_reg_i_GEN_reg_r_10/CLK
                         clock pessimism             -0.285     3.442    
    SLICE_X75Y253        SRLC32E (Hold_A6LUT_SLICEM_CLK_D)
                                                      0.055     3.497    d_1_i/axis_signal_gen_v6_1/inst/signal_gen_top_i/signal_gen_i/gain_latency_reg_i/GEN_reg[13].shift_r_reg[13][12]_srl21___inst_signal_gen_top_i_signal_gen_i_en_latency_reg_i_GEN_reg_r_10
  -------------------------------------------------------------------
                         required time                         -3.497    
                         arrival time                           3.508    
  -------------------------------------------------------------------
                         slack                                  0.011    





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         RFDAC0_CLK
Waveform(ns):       { 0.000 1.302 }
Period(ns):         2.604
Sources:            { d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX }

Check Type        Corner  Lib Pin             Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location      Pin
Min Period        n/a     HSDAC/CLK_DAC       n/a            2.000         2.604       0.604      HSDAC_X0Y0    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
Min Period        n/a     HSDAC/FABRIC_CLK    n/a            2.000         2.604       0.604      HSDAC_X0Y0    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/FABRIC_CLK
Min Period        n/a     HSDAC/FABRIC_CLK    n/a            2.000         2.604       0.604      HSDAC_X0Y1    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/FABRIC_CLK
Min Period        n/a     RAMB36E2/CLKBWRCLK  n/a            1.355         2.604       1.249      RAMB36_X2Y51  d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/GEN_mem[0].mem_imag_i/RAM_reg_bram_0/CLKBWRCLK
Min Period        n/a     RAMB36E2/CLKBWRCLK  n/a            1.355         2.604       1.249      RAMB36_X2Y52  d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/GEN_mem[0].mem_imag_i/RAM_reg_bram_1/CLKBWRCLK
Min Period        n/a     RAMB36E2/CLKBWRCLK  n/a            1.355         2.604       1.249      RAMB36_X3Y50  d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/GEN_mem[0].mem_real_i/RAM_reg_bram_0/CLKBWRCLK
Min Period        n/a     RAMB36E2/CLKBWRCLK  n/a            1.355         2.604       1.249      RAMB36_X3Y46  d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/GEN_mem[0].mem_real_i/RAM_reg_bram_1/CLKBWRCLK
Min Period        n/a     RAMB36E2/CLKBWRCLK  n/a            1.355         2.604       1.249      RAMB36_X3Y61  d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/GEN_mem[10].mem_imag_i/RAM_reg_bram_0/CLKBWRCLK
Min Period        n/a     RAMB36E2/CLKBWRCLK  n/a            1.355         2.604       1.249      RAMB36_X4Y59  d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/GEN_mem[10].mem_imag_i/RAM_reg_bram_1/CLKBWRCLK
Min Period        n/a     RAMB36E2/CLKBWRCLK  n/a            1.355         2.604       1.249      RAMB36_X4Y61  d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/GEN_mem[10].mem_real_i/RAM_reg_bram_0/CLKBWRCLK
Low Pulse Width   Slow    HSDAC/CLK_DAC       n/a            0.800         1.302       0.502      HSDAC_X0Y0    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
Low Pulse Width   Fast    HSDAC/CLK_DAC       n/a            0.800         1.302       0.502      HSDAC_X0Y0    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
Low Pulse Width   Slow    HSDAC/FABRIC_CLK    n/a            0.800         1.302       0.502      HSDAC_X0Y0    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/FABRIC_CLK
Low Pulse Width   Fast    HSDAC/FABRIC_CLK    n/a            0.800         1.302       0.502      HSDAC_X0Y0    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/FABRIC_CLK
Low Pulse Width   Slow    HSDAC/FABRIC_CLK    n/a            0.800         1.302       0.502      HSDAC_X0Y1    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/FABRIC_CLK
Low Pulse Width   Fast    HSDAC/FABRIC_CLK    n/a            0.800         1.302       0.502      HSDAC_X0Y1    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/FABRIC_CLK
Low Pulse Width   Slow    RAMB36E2/CLKBWRCLK  n/a            0.542         1.302       0.760      RAMB36_X2Y51  d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/GEN_mem[0].mem_imag_i/RAM_reg_bram_0/CLKBWRCLK
Low Pulse Width   Fast    RAMB36E2/CLKBWRCLK  n/a            0.542         1.302       0.760      RAMB36_X2Y51  d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/GEN_mem[0].mem_imag_i/RAM_reg_bram_0/CLKBWRCLK
Low Pulse Width   Slow    RAMB36E2/CLKBWRCLK  n/a            0.542         1.302       0.760      RAMB36_X2Y52  d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/GEN_mem[0].mem_imag_i/RAM_reg_bram_1/CLKBWRCLK
Low Pulse Width   Fast    RAMB36E2/CLKBWRCLK  n/a            0.542         1.302       0.760      RAMB36_X2Y52  d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/GEN_mem[0].mem_imag_i/RAM_reg_bram_1/CLKBWRCLK
High Pulse Width  Slow    HSDAC/CLK_DAC       n/a            0.800         1.302       0.502      HSDAC_X0Y0    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
High Pulse Width  Fast    HSDAC/CLK_DAC       n/a            0.800         1.302       0.502      HSDAC_X0Y0    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
High Pulse Width  Slow    HSDAC/FABRIC_CLK    n/a            0.800         1.302       0.502      HSDAC_X0Y0    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/FABRIC_CLK
High Pulse Width  Fast    HSDAC/FABRIC_CLK    n/a            0.800         1.302       0.502      HSDAC_X0Y0    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/FABRIC_CLK
High Pulse Width  Slow    HSDAC/FABRIC_CLK    n/a            0.800         1.302       0.502      HSDAC_X0Y1    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/FABRIC_CLK
High Pulse Width  Fast    HSDAC/FABRIC_CLK    n/a            0.800         1.302       0.502      HSDAC_X0Y1    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/FABRIC_CLK
High Pulse Width  Slow    RAMB36E2/CLKBWRCLK  n/a            0.542         1.302       0.760      RAMB36_X2Y51  d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/GEN_mem[0].mem_imag_i/RAM_reg_bram_0/CLKBWRCLK
High Pulse Width  Fast    RAMB36E2/CLKBWRCLK  n/a            0.542         1.302       0.760      RAMB36_X2Y51  d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/GEN_mem[0].mem_imag_i/RAM_reg_bram_0/CLKBWRCLK
High Pulse Width  Slow    RAMB36E2/CLKBWRCLK  n/a            0.542         1.302       0.760      RAMB36_X2Y52  d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/GEN_mem[0].mem_imag_i/RAM_reg_bram_1/CLKBWRCLK
High Pulse Width  Fast    RAMB36E2/CLKBWRCLK  n/a            0.542         1.302       0.760      RAMB36_X2Y52  d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/GEN_mem[0].mem_imag_i/RAM_reg_bram_1/CLKBWRCLK



---------------------------------------------------------------------------------------------------
From Clock:  clk_pl_0
  To Clock:  clk_pl_0

Setup :            0  Failing Endpoints,  Worst Slack        1.565ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.010ns,  Total Violation        0.000ns
PW    :            0  Failing Endpoints,  Worst Slack        1.000ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             1.565ns  (required time - arrival time)
  Source:                 d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/goreg_dm.dout_i_reg[28]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/drp_di_reg[9]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk_pl_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk_pl_0 rise@10.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        8.422ns  (logic 0.533ns (6.328%)  route 7.889ns (93.672%))
  Logic Levels:           4  (LUT2=1 LUT5=1 LUT6=2)
  Clock Path Skew:        0.092ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.327ns = ( 12.327 - 10.000 ) 
    Source Clock Delay      (SCD):    2.364ns
    Clock Pessimism Removal (CPR):    0.129ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.138ns (routing 0.662ns, distribution 1.476ns)
  Clock Net Delay (Destination): 2.145ns (routing 0.599ns, distribution 1.546ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       2.138     2.364    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/clk
    SLICE_X29Y30         FDRE                                         r  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/goreg_dm.dout_i_reg[28]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X29Y30         FDRE (Prop_FFF2_SLICEL_C_Q)
                                                      0.081     2.445 f  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/goreg_dm.dout_i_reg[28]/Q
                         net (fo=8, routed)           0.339     2.784    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/dout[15]
    SLICE_X31Y32         LUT2 (Prop_D6LUT_SLICEM_I0_O)
                                                      0.088     2.872 r  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/m_axi_wdata[31]_INST_0_i_6/O
                         net (fo=1, routed)           0.052     2.924    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/m_axi_wdata[31]_INST_0_i_6_n_0
    SLICE_X31Y32         LUT6 (Prop_C6LUT_SLICEM_I1_O)
                                                      0.145     3.069 r  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/m_axi_wdata[31]_INST_0_i_3/O
                         net (fo=2, routed)           0.206     3.275    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/m_axi_wdata[31]_INST_0_i_3_n_0
    SLICE_X29Y31         LUT5 (Prop_F6LUT_SLICEL_I0_O)
                                                      0.123     3.398 r  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/m_axi_wdata[31]_INST_0_i_1/O
                         net (fo=36, routed)          0.381     3.779    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/m_axi_wdata[31]_INST_0_i_1_n_0
    SLICE_X22Y37         LUT6 (Prop_C6LUT_SLICEL_I4_O)
                                                      0.096     3.875 r  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/m_axi_wdata[9]_INST_0/O
                         net (fo=334, routed)         6.911    10.786    d_1_i/usp_rf_data_converter_0/inst/s_axi_wdata[9]
    SLICE_X117Y151       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/drp_di_reg[9]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                     10.000    10.000 r  
    PS8_X0Y0             PS8                          0.000    10.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157    10.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025    10.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       2.145    12.327    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X117Y151       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/drp_di_reg[9]/C
                         clock pessimism              0.129    12.456    
                         clock uncertainty           -0.130    12.326    
    SLICE_X117Y151       FDRE (Setup_EFF_SLICEL_C_D)
                                                      0.025    12.351    d_1_i/usp_rf_data_converter_0/inst/drp_di_reg[9]
  -------------------------------------------------------------------
                         required time                         12.351    
                         arrival time                         -10.786    
  -------------------------------------------------------------------
                         slack                                  1.565    

Slack (MET) :             1.650ns  (required time - arrival time)
  Source:                 d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/goreg_dm.dout_i_reg[28]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/adc0_cmn_en_reg[10]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk_pl_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk_pl_0 rise@10.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        8.372ns  (logic 0.561ns (6.701%)  route 7.811ns (93.299%))
  Logic Levels:           4  (LUT2=1 LUT5=1 LUT6=2)
  Clock Path Skew:        0.127ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.344ns = ( 12.344 - 10.000 ) 
    Source Clock Delay      (SCD):    2.364ns
    Clock Pessimism Removal (CPR):    0.147ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.138ns (routing 0.662ns, distribution 1.476ns)
  Clock Net Delay (Destination): 2.162ns (routing 0.599ns, distribution 1.563ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       2.138     2.364    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/clk
    SLICE_X29Y30         FDRE                                         r  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/goreg_dm.dout_i_reg[28]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X29Y30         FDRE (Prop_FFF2_SLICEL_C_Q)
                                                      0.081     2.445 f  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/goreg_dm.dout_i_reg[28]/Q
                         net (fo=8, routed)           0.339     2.784    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/dout[15]
    SLICE_X31Y32         LUT2 (Prop_D6LUT_SLICEM_I0_O)
                                                      0.088     2.872 r  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/m_axi_wdata[31]_INST_0_i_6/O
                         net (fo=1, routed)           0.052     2.924    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/m_axi_wdata[31]_INST_0_i_6_n_0
    SLICE_X31Y32         LUT6 (Prop_C6LUT_SLICEM_I1_O)
                                                      0.145     3.069 r  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/m_axi_wdata[31]_INST_0_i_3/O
                         net (fo=2, routed)           0.206     3.275    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/m_axi_wdata[31]_INST_0_i_3_n_0
    SLICE_X29Y31         LUT5 (Prop_F6LUT_SLICEL_I0_O)
                                                      0.123     3.398 r  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/m_axi_wdata[31]_INST_0_i_1/O
                         net (fo=36, routed)          0.520     3.918    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/m_axi_wdata[31]_INST_0_i_1_n_0
    SLICE_X22Y37         LUT6 (Prop_H6LUT_SLICEL_I3_O)
                                                      0.124     4.042 r  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/m_axi_wdata[10]_INST_0/O
                         net (fo=330, routed)         6.694    10.736    d_1_i/usp_rf_data_converter_0/inst/s_axi_wdata[10]
    SLICE_X108Y101       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/adc0_cmn_en_reg[10]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                     10.000    10.000 r  
    PS8_X0Y0             PS8                          0.000    10.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157    10.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025    10.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       2.162    12.344    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X108Y101       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/adc0_cmn_en_reg[10]/C
                         clock pessimism              0.147    12.491    
                         clock uncertainty           -0.130    12.361    
    SLICE_X108Y101       FDRE (Setup_DFF_SLICEL_C_D)
                                                      0.025    12.386    d_1_i/usp_rf_data_converter_0/inst/adc0_cmn_en_reg[10]
  -------------------------------------------------------------------
                         required time                         12.386    
                         arrival time                         -10.736    
  -------------------------------------------------------------------
                         slack                                  1.650    

Slack (MET) :             1.756ns  (required time - arrival time)
  Source:                 d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/goreg_dm.dout_i_reg[28]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/adc0_ref_clk_freq_reg[10]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk_pl_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk_pl_0 rise@10.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        8.269ns  (logic 0.561ns (6.784%)  route 7.708ns (93.216%))
  Logic Levels:           4  (LUT2=1 LUT5=1 LUT6=2)
  Clock Path Skew:        0.130ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.347ns = ( 12.347 - 10.000 ) 
    Source Clock Delay      (SCD):    2.364ns
    Clock Pessimism Removal (CPR):    0.147ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.138ns (routing 0.662ns, distribution 1.476ns)
  Clock Net Delay (Destination): 2.165ns (routing 0.599ns, distribution 1.566ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       2.138     2.364    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/clk
    SLICE_X29Y30         FDRE                                         r  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/goreg_dm.dout_i_reg[28]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X29Y30         FDRE (Prop_FFF2_SLICEL_C_Q)
                                                      0.081     2.445 f  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/goreg_dm.dout_i_reg[28]/Q
                         net (fo=8, routed)           0.339     2.784    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/dout[15]
    SLICE_X31Y32         LUT2 (Prop_D6LUT_SLICEM_I0_O)
                                                      0.088     2.872 r  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/m_axi_wdata[31]_INST_0_i_6/O
                         net (fo=1, routed)           0.052     2.924    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/m_axi_wdata[31]_INST_0_i_6_n_0
    SLICE_X31Y32         LUT6 (Prop_C6LUT_SLICEM_I1_O)
                                                      0.145     3.069 r  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/m_axi_wdata[31]_INST_0_i_3/O
                         net (fo=2, routed)           0.206     3.275    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/m_axi_wdata[31]_INST_0_i_3_n_0
    SLICE_X29Y31         LUT5 (Prop_F6LUT_SLICEL_I0_O)
                                                      0.123     3.398 r  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/m_axi_wdata[31]_INST_0_i_1/O
                         net (fo=36, routed)          0.520     3.918    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/m_axi_wdata[31]_INST_0_i_1_n_0
    SLICE_X22Y37         LUT6 (Prop_H6LUT_SLICEL_I3_O)
                                                      0.124     4.042 r  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/m_axi_wdata[10]_INST_0/O
                         net (fo=330, routed)         6.591    10.633    d_1_i/usp_rf_data_converter_0/inst/s_axi_wdata[10]
    SLICE_X108Y105       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/adc0_ref_clk_freq_reg[10]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                     10.000    10.000 r  
    PS8_X0Y0             PS8                          0.000    10.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157    10.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025    10.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       2.165    12.347    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X108Y105       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/adc0_ref_clk_freq_reg[10]/C
                         clock pessimism              0.147    12.494    
                         clock uncertainty           -0.130    12.364    
    SLICE_X108Y105       FDRE (Setup_DFF_SLICEL_C_D)
                                                      0.025    12.389    d_1_i/usp_rf_data_converter_0/inst/adc0_ref_clk_freq_reg[10]
  -------------------------------------------------------------------
                         required time                         12.389    
                         arrival time                         -10.633    
  -------------------------------------------------------------------
                         slack                                  1.756    

Slack (MET) :             1.785ns  (required time - arrival time)
  Source:                 d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/data_writer_i/mem_addr_full_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/data_writer_i/mem_addr_full_reg[11]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk_pl_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk_pl_0 rise@10.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        8.070ns  (logic 0.259ns (3.209%)  route 7.811ns (96.791%))
  Logic Levels:           3  (LUT4=1 LUT6=2)
  Clock Path Skew:        -0.040ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.155ns = ( 12.155 - 10.000 ) 
    Source Clock Delay      (SCD):    2.449ns
    Clock Pessimism Removal (CPR):    0.253ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.223ns (routing 0.662ns, distribution 1.561ns)
  Clock Net Delay (Destination): 1.973ns (routing 0.599ns, distribution 1.374ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       2.223     2.449    d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/data_writer_i/s0_axis_aclk
    SLICE_X80Y82         FDRE                                         r  d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/data_writer_i/mem_addr_full_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X80Y82         FDRE (Prop_DFF2_SLICEL_C_Q)
                                                      0.081     2.530 f  d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/data_writer_i/mem_addr_full_reg[2]/Q
                         net (fo=21, routed)          3.702     6.232    d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/data_writer_i/mem_addr_full_reg_n_0_[2]
    SLICE_X83Y383        LUT4 (Prop_H6LUT_SLICEM_I1_O)
                                                      0.053     6.285 f  d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/data_writer_i/mem_en_r[15]_i_1/O
                         net (fo=4, routed)           3.402     9.687    d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/data_writer_i/mem_en_i[15]
    SLICE_X81Y81         LUT6 (Prop_H6LUT_SLICEL_I3_O)
                                                      0.036     9.723 r  d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/data_writer_i/mem_addr_full[11]_i_2/O
                         net (fo=2, routed)           0.659    10.382    d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/data_writer_i/mem_addr_full[11]_i_2_n_0
    SLICE_X80Y80         LUT6 (Prop_G6LUT_SLICEL_I2_O)
                                                      0.089    10.471 r  d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/data_writer_i/mem_addr_full[11]_i_1/O
                         net (fo=1, routed)           0.048    10.519    d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/data_writer_i/p_0_in[11]
    SLICE_X80Y80         FDRE                                         r  d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/data_writer_i/mem_addr_full_reg[11]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                     10.000    10.000 r  
    PS8_X0Y0             PS8                          0.000    10.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157    10.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025    10.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.973    12.155    d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/data_writer_i/s0_axis_aclk
    SLICE_X80Y80         FDRE                                         r  d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/data_writer_i/mem_addr_full_reg[11]/C
                         clock pessimism              0.253    12.409    
                         clock uncertainty           -0.130    12.279    
    SLICE_X80Y80         FDRE (Setup_GFF_SLICEL_C_D)
                                                      0.025    12.304    d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/data_writer_i/mem_addr_full_reg[11]
  -------------------------------------------------------------------
                         required time                         12.304    
                         arrival time                         -10.519    
  -------------------------------------------------------------------
                         slack                                  1.785    

Slack (MET) :             1.838ns  (required time - arrival time)
  Source:                 d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/data_writer_i/mem_addr_full_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/data_writer_i/mem_addr_full_reg[10]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk_pl_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk_pl_0 rise@10.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        8.017ns  (logic 0.235ns (2.931%)  route 7.782ns (97.069%))
  Logic Levels:           3  (LUT4=1 LUT5=1 LUT6=1)
  Clock Path Skew:        -0.040ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.155ns = ( 12.155 - 10.000 ) 
    Source Clock Delay      (SCD):    2.449ns
    Clock Pessimism Removal (CPR):    0.253ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.223ns (routing 0.662ns, distribution 1.561ns)
  Clock Net Delay (Destination): 1.973ns (routing 0.599ns, distribution 1.374ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       2.223     2.449    d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/data_writer_i/s0_axis_aclk
    SLICE_X80Y82         FDRE                                         r  d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/data_writer_i/mem_addr_full_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X80Y82         FDRE (Prop_DFF2_SLICEL_C_Q)
                                                      0.081     2.530 f  d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/data_writer_i/mem_addr_full_reg[2]/Q
                         net (fo=21, routed)          3.702     6.232    d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/data_writer_i/mem_addr_full_reg_n_0_[2]
    SLICE_X83Y383        LUT4 (Prop_H6LUT_SLICEM_I1_O)
                                                      0.053     6.285 f  d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/data_writer_i/mem_en_r[15]_i_1/O
                         net (fo=4, routed)           3.402     9.687    d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/data_writer_i/mem_en_i[15]
    SLICE_X81Y81         LUT6 (Prop_H6LUT_SLICEL_I3_O)
                                                      0.036     9.723 r  d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/data_writer_i/mem_addr_full[11]_i_2/O
                         net (fo=2, routed)           0.663    10.386    d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/data_writer_i/mem_addr_full[11]_i_2_n_0
    SLICE_X80Y80         LUT5 (Prop_H5LUT_SLICEL_I1_O)
                                                      0.065    10.451 r  d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/data_writer_i/mem_addr_full[10]_i_1/O
                         net (fo=1, routed)           0.015    10.466    d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/data_writer_i/p_0_in[10]
    SLICE_X80Y80         FDRE                                         r  d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/data_writer_i/mem_addr_full_reg[10]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                     10.000    10.000 r  
    PS8_X0Y0             PS8                          0.000    10.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157    10.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025    10.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.973    12.155    d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/data_writer_i/s0_axis_aclk
    SLICE_X80Y80         FDRE                                         r  d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/data_writer_i/mem_addr_full_reg[10]/C
                         clock pessimism              0.253    12.409    
                         clock uncertainty           -0.130    12.279    
    SLICE_X80Y80         FDRE (Setup_HFF2_SLICEL_C_D)
                                                      0.025    12.304    d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/data_writer_i/mem_addr_full_reg[10]
  -------------------------------------------------------------------
                         required time                         12.304    
                         arrival time                         -10.466    
  -------------------------------------------------------------------
                         slack                                  1.838    

Slack (MET) :             1.846ns  (required time - arrival time)
  Source:                 d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_data_inst/WORD_LANE[3].S_AXI_RDATA_II_reg[115]/R
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk_pl_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk_pl_0 rise@10.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        7.643ns  (logic 0.168ns (2.198%)  route 7.475ns (97.802%))
  Logic Levels:           1  (LUT5=1)
  Clock Path Skew:        -0.307ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.188ns = ( 12.188 - 10.000 ) 
    Source Clock Delay      (SCD):    2.606ns
    Clock Pessimism Removal (CPR):    0.111ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.380ns (routing 0.662ns, distribution 1.718ns)
  Clock Net Delay (Destination): 2.006ns (routing 0.599ns, distribution 1.407ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       2.380     2.606    d_1_i/rst_100/U0/slowest_sync_clk
    SLICE_X102Y67        FDRE                                         r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/C
  -------------------------------------------------------------------    -------------------
    SLICE_X102Y67        FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.079     2.685 f  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/Q
                         net (fo=118, routed)         3.676     6.361    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/peripheral_aresetn[0]_bufg_place_replica
    SLICE_X26Y29         LUT5 (Prop_D6LUT_SLICEL_I0_O)
                                                      0.089     6.450 r  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/WORD_LANE[0].S_AXI_RDATA_II[31]_i_1/O
                         net (fo=128, routed)         3.799    10.249    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_data_inst/WORD_LANE[0].S_AXI_RDATA_II_reg[31]_0[0]
    SLICE_X10Y180        FDRE                                         r  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_data_inst/WORD_LANE[3].S_AXI_RDATA_II_reg[115]/R
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                     10.000    10.000 r  
    PS8_X0Y0             PS8                          0.000    10.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157    10.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025    10.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       2.006    12.188    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_data_inst/CLK
    SLICE_X10Y180        FDRE                                         r  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_data_inst/WORD_LANE[3].S_AXI_RDATA_II_reg[115]/C
                         clock pessimism              0.111    12.299    
                         clock uncertainty           -0.130    12.169    
    SLICE_X10Y180        FDRE (Setup_EFF_SLICEL_C_R)
                                                     -0.074    12.095    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_data_inst/WORD_LANE[3].S_AXI_RDATA_II_reg[115]
  -------------------------------------------------------------------
                         required time                         12.095    
                         arrival time                         -10.249    
  -------------------------------------------------------------------
                         slack                                  1.846    

Slack (MET) :             1.851ns  (required time - arrival time)
  Source:                 d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/goreg_dm.dout_i_reg[28]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/dac1_start_stage_reg[1]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk_pl_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk_pl_0 rise@10.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        8.148ns  (logic 0.533ns (6.542%)  route 7.615ns (93.458%))
  Logic Levels:           4  (LUT2=1 LUT5=1 LUT6=2)
  Clock Path Skew:        0.104ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.339ns = ( 12.339 - 10.000 ) 
    Source Clock Delay      (SCD):    2.364ns
    Clock Pessimism Removal (CPR):    0.129ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.138ns (routing 0.662ns, distribution 1.476ns)
  Clock Net Delay (Destination): 2.157ns (routing 0.599ns, distribution 1.558ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       2.138     2.364    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/clk
    SLICE_X29Y30         FDRE                                         r  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/goreg_dm.dout_i_reg[28]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X29Y30         FDRE (Prop_FFF2_SLICEL_C_Q)
                                                      0.081     2.445 f  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/goreg_dm.dout_i_reg[28]/Q
                         net (fo=8, routed)           0.339     2.784    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/dout[15]
    SLICE_X31Y32         LUT2 (Prop_D6LUT_SLICEM_I0_O)
                                                      0.088     2.872 r  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/m_axi_wdata[31]_INST_0_i_6/O
                         net (fo=1, routed)           0.052     2.924    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/m_axi_wdata[31]_INST_0_i_6_n_0
    SLICE_X31Y32         LUT6 (Prop_C6LUT_SLICEM_I1_O)
                                                      0.145     3.069 r  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/m_axi_wdata[31]_INST_0_i_3/O
                         net (fo=2, routed)           0.206     3.275    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/m_axi_wdata[31]_INST_0_i_3_n_0
    SLICE_X29Y31         LUT5 (Prop_F6LUT_SLICEL_I0_O)
                                                      0.123     3.398 r  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/m_axi_wdata[31]_INST_0_i_1/O
                         net (fo=36, routed)          0.381     3.779    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/m_axi_wdata[31]_INST_0_i_1_n_0
    SLICE_X22Y37         LUT6 (Prop_C6LUT_SLICEL_I4_O)
                                                      0.096     3.875 r  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/m_axi_wdata[9]_INST_0/O
                         net (fo=334, routed)         6.636    10.512    d_1_i/usp_rf_data_converter_0/inst/s_axi_wdata[9]
    SLICE_X108Y128       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/dac1_start_stage_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                     10.000    10.000 r  
    PS8_X0Y0             PS8                          0.000    10.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157    10.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025    10.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       2.157    12.339    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X108Y128       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/dac1_start_stage_reg[1]/C
                         clock pessimism              0.129    12.468    
                         clock uncertainty           -0.130    12.338    
    SLICE_X108Y128       FDRE (Setup_EFF2_SLICEL_C_D)
                                                      0.025    12.363    d_1_i/usp_rf_data_converter_0/inst/dac1_start_stage_reg[1]
  -------------------------------------------------------------------
                         required time                         12.363    
                         arrival time                         -10.512    
  -------------------------------------------------------------------
                         slack                                  1.851    

Slack (MET) :             1.855ns  (required time - arrival time)
  Source:                 d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/goreg_dm.dout_i_reg[28]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/adc0_start_stage_reg[2]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk_pl_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk_pl_0 rise@10.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        8.166ns  (logic 0.561ns (6.870%)  route 7.605ns (93.130%))
  Logic Levels:           4  (LUT2=1 LUT5=1 LUT6=2)
  Clock Path Skew:        0.126ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.343ns = ( 12.343 - 10.000 ) 
    Source Clock Delay      (SCD):    2.364ns
    Clock Pessimism Removal (CPR):    0.147ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.138ns (routing 0.662ns, distribution 1.476ns)
  Clock Net Delay (Destination): 2.161ns (routing 0.599ns, distribution 1.562ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       2.138     2.364    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/clk
    SLICE_X29Y30         FDRE                                         r  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/goreg_dm.dout_i_reg[28]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X29Y30         FDRE (Prop_FFF2_SLICEL_C_Q)
                                                      0.081     2.445 f  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/goreg_dm.dout_i_reg[28]/Q
                         net (fo=8, routed)           0.339     2.784    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/dout[15]
    SLICE_X31Y32         LUT2 (Prop_D6LUT_SLICEM_I0_O)
                                                      0.088     2.872 r  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/m_axi_wdata[31]_INST_0_i_6/O
                         net (fo=1, routed)           0.052     2.924    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/m_axi_wdata[31]_INST_0_i_6_n_0
    SLICE_X31Y32         LUT6 (Prop_C6LUT_SLICEM_I1_O)
                                                      0.145     3.069 r  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/m_axi_wdata[31]_INST_0_i_3/O
                         net (fo=2, routed)           0.206     3.275    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/m_axi_wdata[31]_INST_0_i_3_n_0
    SLICE_X29Y31         LUT5 (Prop_F6LUT_SLICEL_I0_O)
                                                      0.123     3.398 r  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/m_axi_wdata[31]_INST_0_i_1/O
                         net (fo=36, routed)          0.520     3.918    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/m_axi_wdata[31]_INST_0_i_1_n_0
    SLICE_X22Y37         LUT6 (Prop_H6LUT_SLICEL_I3_O)
                                                      0.124     4.042 r  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/m_axi_wdata[10]_INST_0/O
                         net (fo=330, routed)         6.488    10.530    d_1_i/usp_rf_data_converter_0/inst/s_axi_wdata[10]
    SLICE_X111Y102       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/adc0_start_stage_reg[2]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                     10.000    10.000 r  
    PS8_X0Y0             PS8                          0.000    10.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157    10.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025    10.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       2.161    12.343    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X111Y102       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/adc0_start_stage_reg[2]/C
                         clock pessimism              0.147    12.490    
                         clock uncertainty           -0.130    12.360    
    SLICE_X111Y102       FDRE (Setup_AFF_SLICEL_C_D)
                                                      0.025    12.385    d_1_i/usp_rf_data_converter_0/inst/adc0_start_stage_reg[2]
  -------------------------------------------------------------------
                         required time                         12.385    
                         arrival time                         -10.530    
  -------------------------------------------------------------------
                         slack                                  1.855    

Slack (MET) :             1.875ns  (required time - arrival time)
  Source:                 d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/goreg_dm.dout_i_reg[28]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/adc0_start_stage_reg[1]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk_pl_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk_pl_0 rise@10.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        8.146ns  (logic 0.533ns (6.543%)  route 7.613ns (93.457%))
  Logic Levels:           4  (LUT2=1 LUT5=1 LUT6=2)
  Clock Path Skew:        0.126ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.343ns = ( 12.343 - 10.000 ) 
    Source Clock Delay      (SCD):    2.364ns
    Clock Pessimism Removal (CPR):    0.147ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.138ns (routing 0.662ns, distribution 1.476ns)
  Clock Net Delay (Destination): 2.161ns (routing 0.599ns, distribution 1.562ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       2.138     2.364    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/clk
    SLICE_X29Y30         FDRE                                         r  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/goreg_dm.dout_i_reg[28]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X29Y30         FDRE (Prop_FFF2_SLICEL_C_Q)
                                                      0.081     2.445 f  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/goreg_dm.dout_i_reg[28]/Q
                         net (fo=8, routed)           0.339     2.784    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/dout[15]
    SLICE_X31Y32         LUT2 (Prop_D6LUT_SLICEM_I0_O)
                                                      0.088     2.872 r  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/m_axi_wdata[31]_INST_0_i_6/O
                         net (fo=1, routed)           0.052     2.924    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/m_axi_wdata[31]_INST_0_i_6_n_0
    SLICE_X31Y32         LUT6 (Prop_C6LUT_SLICEM_I1_O)
                                                      0.145     3.069 r  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/m_axi_wdata[31]_INST_0_i_3/O
                         net (fo=2, routed)           0.206     3.275    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/m_axi_wdata[31]_INST_0_i_3_n_0
    SLICE_X29Y31         LUT5 (Prop_F6LUT_SLICEL_I0_O)
                                                      0.123     3.398 r  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/m_axi_wdata[31]_INST_0_i_1/O
                         net (fo=36, routed)          0.381     3.779    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/m_axi_wdata[31]_INST_0_i_1_n_0
    SLICE_X22Y37         LUT6 (Prop_C6LUT_SLICEL_I4_O)
                                                      0.096     3.875 r  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/m_axi_wdata[9]_INST_0/O
                         net (fo=334, routed)         6.634    10.510    d_1_i/usp_rf_data_converter_0/inst/s_axi_wdata[9]
    SLICE_X108Y100       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/adc0_start_stage_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                     10.000    10.000 r  
    PS8_X0Y0             PS8                          0.000    10.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157    10.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025    10.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       2.161    12.343    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X108Y100       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/adc0_start_stage_reg[1]/C
                         clock pessimism              0.147    12.490    
                         clock uncertainty           -0.130    12.360    
    SLICE_X108Y100       FDRE (Setup_CFF2_SLICEL_C_D)
                                                      0.025    12.385    d_1_i/usp_rf_data_converter_0/inst/adc0_start_stage_reg[1]
  -------------------------------------------------------------------
                         required time                         12.385    
                         arrival time                         -10.510    
  -------------------------------------------------------------------
                         slack                                  1.875    

Slack (MET) :             1.889ns  (required time - arrival time)
  Source:                 d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/goreg_dm.dout_i_reg[28]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/adc1_cmn_en_reg[9]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk_pl_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk_pl_0 rise@10.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        8.130ns  (logic 0.533ns (6.556%)  route 7.597ns (93.444%))
  Logic Levels:           4  (LUT2=1 LUT5=1 LUT6=2)
  Clock Path Skew:        0.124ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.341ns = ( 12.341 - 10.000 ) 
    Source Clock Delay      (SCD):    2.364ns
    Clock Pessimism Removal (CPR):    0.147ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.138ns (routing 0.662ns, distribution 1.476ns)
  Clock Net Delay (Destination): 2.159ns (routing 0.599ns, distribution 1.560ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       2.138     2.364    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/clk
    SLICE_X29Y30         FDRE                                         r  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/goreg_dm.dout_i_reg[28]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X29Y30         FDRE (Prop_FFF2_SLICEL_C_Q)
                                                      0.081     2.445 f  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/goreg_dm.dout_i_reg[28]/Q
                         net (fo=8, routed)           0.339     2.784    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/dout[15]
    SLICE_X31Y32         LUT2 (Prop_D6LUT_SLICEM_I0_O)
                                                      0.088     2.872 r  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/m_axi_wdata[31]_INST_0_i_6/O
                         net (fo=1, routed)           0.052     2.924    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/m_axi_wdata[31]_INST_0_i_6_n_0
    SLICE_X31Y32         LUT6 (Prop_C6LUT_SLICEM_I1_O)
                                                      0.145     3.069 r  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/m_axi_wdata[31]_INST_0_i_3/O
                         net (fo=2, routed)           0.206     3.275    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/m_axi_wdata[31]_INST_0_i_3_n_0
    SLICE_X29Y31         LUT5 (Prop_F6LUT_SLICEL_I0_O)
                                                      0.123     3.398 r  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/m_axi_wdata[31]_INST_0_i_1/O
                         net (fo=36, routed)          0.381     3.779    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/m_axi_wdata[31]_INST_0_i_1_n_0
    SLICE_X22Y37         LUT6 (Prop_C6LUT_SLICEL_I4_O)
                                                      0.096     3.875 r  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/m_axi_wdata[9]_INST_0/O
                         net (fo=334, routed)         6.619    10.494    d_1_i/usp_rf_data_converter_0/inst/s_axi_wdata[9]
    SLICE_X108Y103       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/adc1_cmn_en_reg[9]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                     10.000    10.000 r  
    PS8_X0Y0             PS8                          0.000    10.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157    10.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025    10.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       2.159    12.341    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X108Y103       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/adc1_cmn_en_reg[9]/C
                         clock pessimism              0.147    12.488    
                         clock uncertainty           -0.130    12.358    
    SLICE_X108Y103       FDRE (Setup_BFF_SLICEL_C_D)
                                                      0.025    12.383    d_1_i/usp_rf_data_converter_0/inst/adc1_cmn_en_reg[9]
  -------------------------------------------------------------------
                         required time                         12.383    
                         arrival time                         -10.494    
  -------------------------------------------------------------------
                         slack                                  1.889    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.010ns  (arrival time - required time)
  Source:                 d_1_i/axi_smc/inst/s04_nodes/s04_w_node/inst/inst_mi_handler/gen_normal_area.gen_upsizer.inst_upsizer/gen_w_ch.accum_reg[bytes][12][userdata][2]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axi_smc/inst/s04_nodes/s04_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_126_139/RAMA_D1/I
                            (rising edge-triggered cell RAMD32 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk_pl_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_pl_0 rise@0.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        0.230ns  (logic 0.059ns (25.652%)  route 0.171ns (74.348%))
  Logic Levels:           0  
  Clock Path Skew:        0.162ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.401ns
    Source Clock Delay      (SCD):    2.043ns
    Clock Pessimism Removal (CPR):    0.196ns
  Clock Net Delay (Source):      1.861ns (routing 0.599ns, distribution 1.262ns)
  Clock Net Delay (Destination): 2.175ns (routing 0.662ns, distribution 1.513ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.861     2.043    d_1_i/axi_smc/inst/s04_nodes/s04_w_node/inst/inst_mi_handler/gen_normal_area.gen_upsizer.inst_upsizer/s_sc_aclk
    SLICE_X44Y7          FDRE                                         r  d_1_i/axi_smc/inst/s04_nodes/s04_w_node/inst/inst_mi_handler/gen_normal_area.gen_upsizer.inst_upsizer/gen_w_ch.accum_reg[bytes][12][userdata][2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X44Y7          FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.059     2.102 r  d_1_i/axi_smc/inst/s04_nodes/s04_w_node/inst/inst_mi_handler/gen_normal_area.gen_upsizer.inst_upsizer/gen_w_ch.accum_reg[bytes][12][userdata][2]/Q
                         net (fo=1, routed)           0.171     2.273    d_1_i/axi_smc/inst/s04_nodes/s04_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_126_139/DIA1
    SLICE_X46Y7          RAMD32                                       r  d_1_i/axi_smc/inst/s04_nodes/s04_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_126_139/RAMA_D1/I
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       2.175     2.401    d_1_i/axi_smc/inst/s04_nodes/s04_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_126_139/WCLK
    SLICE_X46Y7          RAMD32                                       r  d_1_i/axi_smc/inst/s04_nodes/s04_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_126_139/RAMA_D1/CLK
                         clock pessimism             -0.196     2.205    
    SLICE_X46Y7          RAMD32 (Hold_A6LUT_SLICEM_CLK_I)
                                                      0.058     2.263    d_1_i/axi_smc/inst/s04_nodes/s04_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_126_139/RAMA_D1
  -------------------------------------------------------------------
                         required time                         -2.263    
                         arrival time                           2.273    
  -------------------------------------------------------------------
                         slack                                  0.010    

Slack (MET) :             0.010ns  (arrival time - required time)
  Source:                 d_1_i/axi_dma_mr/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_xfer_len_reg_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axi_dma_mr/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][22]_srl4/D
                            (rising edge-triggered cell SRL16E clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk_pl_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_pl_0 rise@0.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        0.167ns  (logic 0.059ns (35.396%)  route 0.108ns (64.604%))
  Logic Levels:           0  
  Clock Path Skew:        0.125ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.372ns
    Source Clock Delay      (SCD):    2.051ns
    Clock Pessimism Removal (CPR):    0.196ns
  Clock Net Delay (Source):      1.869ns (routing 0.599ns, distribution 1.270ns)
  Clock Net Delay (Destination): 2.146ns (routing 0.662ns, distribution 1.484ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.869     2.051    d_1_i/axi_dma_mr/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/m_axi_s2mm_aclk
    SLICE_X58Y37         FDRE                                         r  d_1_i/axi_dma_mr/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_xfer_len_reg_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X58Y37         FDRE (Prop_HFF2_SLICEL_C_Q)
                                                      0.059     2.110 r  d_1_i/axi_dma_mr/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_xfer_len_reg_reg[0]/Q
                         net (fo=2, routed)           0.108     2.218    d_1_i/axi_dma_mr/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/in[32]
    SLICE_X60Y36         SRL16E                                       r  d_1_i/axi_dma_mr/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][22]_srl4/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       2.146     2.372    d_1_i/axi_dma_mr/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/m_axi_s2mm_aclk
    SLICE_X60Y36         SRL16E                                       r  d_1_i/axi_dma_mr/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][22]_srl4/CLK
                         clock pessimism             -0.196     2.175    
    SLICE_X60Y36         SRL16E (Hold_H6LUT_SLICEM_CLK_D)
                                                      0.032     2.207    d_1_i/axi_dma_mr/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][22]_srl4
  -------------------------------------------------------------------
                         required time                         -2.207    
                         arrival time                           2.218    
  -------------------------------------------------------------------
                         slack                                  0.010    

Slack (MET) :             0.011ns  (arrival time - required time)
  Source:                 d_1_i/axi_smc/inst/m00_nodes/m00_r_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[1].inst_xpm_memory/xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[132]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axi_smc/inst/switchboards/r_switchboard/inst/gen_mi[0].inst_opipe_payld/gen_pipe[1].pipe_reg[1][274]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk_pl_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_pl_0 rise@0.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        0.171ns  (logic 0.061ns (35.672%)  route 0.110ns (64.327%))
  Logic Levels:           0  
  Clock Path Skew:        0.098ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.445ns
    Source Clock Delay      (SCD):    2.149ns
    Clock Pessimism Removal (CPR):    0.198ns
  Clock Net Delay (Source):      1.967ns (routing 0.599ns, distribution 1.368ns)
  Clock Net Delay (Destination): 2.219ns (routing 0.662ns, distribution 1.557ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.967     2.149    d_1_i/axi_smc/inst/m00_nodes/m00_r_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[1].inst_xpm_memory/xpm_memory_base_inst/clka
    SLICE_X18Y193        FDRE                                         r  d_1_i/axi_smc/inst/m00_nodes/m00_r_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[1].inst_xpm_memory/xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[132]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X18Y193        FDRE (Prop_DFF2_SLICEM_C_Q)
                                                      0.061     2.210 r  d_1_i/axi_smc/inst/m00_nodes/m00_r_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[1].inst_xpm_memory/xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[132]/Q
                         net (fo=1, routed)           0.110     2.320    d_1_i/axi_smc/inst/switchboards/r_switchboard/inst/gen_mi[0].inst_opipe_payld/s_sc_payld[265]
    SLICE_X16Y194        FDRE                                         r  d_1_i/axi_smc/inst/switchboards/r_switchboard/inst/gen_mi[0].inst_opipe_payld/gen_pipe[1].pipe_reg[1][274]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       2.219     2.445    d_1_i/axi_smc/inst/switchboards/r_switchboard/inst/gen_mi[0].inst_opipe_payld/aclk
    SLICE_X16Y194        FDRE                                         r  d_1_i/axi_smc/inst/switchboards/r_switchboard/inst/gen_mi[0].inst_opipe_payld/gen_pipe[1].pipe_reg[1][274]/C
                         clock pessimism             -0.198     2.247    
    SLICE_X16Y194        FDRE (Hold_AFF2_SLICEL_C_D)
                                                      0.062     2.309    d_1_i/axi_smc/inst/switchboards/r_switchboard/inst/gen_mi[0].inst_opipe_payld/gen_pipe[1].pipe_reg[1][274]
  -------------------------------------------------------------------
                         required time                         -2.309    
                         arrival time                           2.320    
  -------------------------------------------------------------------
                         slack                                  0.011    

Slack (MET) :             0.011ns  (arrival time - required time)
  Source:                 d_1_i/axi_smc/inst/s03_nodes/s03_w_node/inst/inst_mi_handler/gen_normal_area.gen_upsizer.inst_upsizer/gen_w_ch.accum_reg[bytes][13][userdata][6]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axi_smc/inst/s03_nodes/s03_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_140_151/RAMA/I
                            (rising edge-triggered cell RAMD32 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk_pl_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_pl_0 rise@0.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        0.217ns  (logic 0.059ns (27.189%)  route 0.158ns (72.811%))
  Logic Levels:           0  
  Clock Path Skew:        0.131ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.384ns
    Source Clock Delay      (SCD):    2.056ns
    Clock Pessimism Removal (CPR):    0.196ns
  Clock Net Delay (Source):      1.874ns (routing 0.599ns, distribution 1.275ns)
  Clock Net Delay (Destination): 2.158ns (routing 0.662ns, distribution 1.496ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.874     2.056    d_1_i/axi_smc/inst/s03_nodes/s03_w_node/inst/inst_mi_handler/gen_normal_area.gen_upsizer.inst_upsizer/s_sc_aclk
    SLICE_X51Y14         FDRE                                         r  d_1_i/axi_smc/inst/s03_nodes/s03_w_node/inst/inst_mi_handler/gen_normal_area.gen_upsizer.inst_upsizer/gen_w_ch.accum_reg[bytes][13][userdata][6]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X51Y14         FDRE (Prop_HFF2_SLICEL_C_Q)
                                                      0.059     2.115 r  d_1_i/axi_smc/inst/s03_nodes/s03_w_node/inst/inst_mi_handler/gen_normal_area.gen_upsizer.inst_upsizer/gen_w_ch.accum_reg[bytes][13][userdata][6]/Q
                         net (fo=1, routed)           0.158     2.273    d_1_i/axi_smc/inst/s03_nodes/s03_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_140_151/DIA0
    SLICE_X53Y14         RAMD32                                       r  d_1_i/axi_smc/inst/s03_nodes/s03_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_140_151/RAMA/I
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       2.158     2.384    d_1_i/axi_smc/inst/s03_nodes/s03_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_140_151/WCLK
    SLICE_X53Y14         RAMD32                                       r  d_1_i/axi_smc/inst/s03_nodes/s03_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_140_151/RAMA/CLK
                         clock pessimism             -0.196     2.188    
    SLICE_X53Y14         RAMD32 (Hold_A5LUT_SLICEM_CLK_I)
                                                      0.075     2.263    d_1_i/axi_smc/inst/s03_nodes/s03_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_140_151/RAMA
  -------------------------------------------------------------------
                         required time                         -2.263    
                         arrival time                           2.273    
  -------------------------------------------------------------------
                         slack                                  0.011    

Slack (MET) :             0.011ns  (arrival time - required time)
  Source:                 d_1_i/axis_signal_gen_v6_7/inst/axi_slv_i/slv_reg4_reg[12]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_signal_gen_v6_7/inst/axi_slv_i/axi_rdata_reg[12]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk_pl_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_pl_0 rise@0.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        0.216ns  (logic 0.122ns (56.482%)  route 0.094ns (43.519%))
  Logic Levels:           3  (LUT6=1 MUXF7=1 MUXF8=1)
  Clock Path Skew:        0.145ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.305ns
    Source Clock Delay      (SCD):    2.031ns
    Clock Pessimism Removal (CPR):    0.129ns
  Clock Net Delay (Source):      1.849ns (routing 0.599ns, distribution 1.250ns)
  Clock Net Delay (Destination): 2.079ns (routing 0.662ns, distribution 1.417ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.849     2.031    d_1_i/axis_signal_gen_v6_7/inst/axi_slv_i/s_axi_aclk
    SLICE_X42Y119        FDRE                                         r  d_1_i/axis_signal_gen_v6_7/inst/axi_slv_i/slv_reg4_reg[12]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X42Y119        FDRE (Prop_DFF_SLICEM_C_Q)
                                                      0.058     2.089 r  d_1_i/axis_signal_gen_v6_7/inst/axi_slv_i/slv_reg4_reg[12]/Q
                         net (fo=1, routed)           0.062     2.151    d_1_i/axis_signal_gen_v6_7/inst/axi_slv_i/slv_reg4[12]
    SLICE_X42Y121        LUT6 (Prop_C6LUT_SLICEM_I5_O)
                                                      0.022     2.173 r  d_1_i/axis_signal_gen_v6_7/inst/axi_slv_i/axi_rdata[12]_i_5/O
                         net (fo=1, routed)           0.019     2.192    d_1_i/axis_signal_gen_v6_7/inst/axi_slv_i/axi_rdata[12]_i_5_n_0
    SLICE_X42Y121        MUXF7 (Prop_F7MUX_CD_SLICEM_I1_O)
                                                      0.022     2.214 r  d_1_i/axis_signal_gen_v6_7/inst/axi_slv_i/axi_rdata_reg[12]_i_2/O
                         net (fo=1, routed)           0.000     2.214    d_1_i/axis_signal_gen_v6_7/inst/axi_slv_i/axi_rdata_reg[12]_i_2_n_0
    SLICE_X42Y121        MUXF8 (Prop_F8MUX_BOT_SLICEM_I0_O)
                                                      0.020     2.234 r  d_1_i/axis_signal_gen_v6_7/inst/axi_slv_i/axi_rdata_reg[12]_i_1/O
                         net (fo=1, routed)           0.013     2.247    d_1_i/axis_signal_gen_v6_7/inst/axi_slv_i/reg_data_out[12]
    SLICE_X42Y121        FDRE                                         r  d_1_i/axis_signal_gen_v6_7/inst/axi_slv_i/axi_rdata_reg[12]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       2.079     2.305    d_1_i/axis_signal_gen_v6_7/inst/axi_slv_i/s_axi_aclk
    SLICE_X42Y121        FDRE                                         r  d_1_i/axis_signal_gen_v6_7/inst/axi_slv_i/axi_rdata_reg[12]/C
                         clock pessimism             -0.129     2.176    
    SLICE_X42Y121        FDRE (Hold_CFF_SLICEM_C_D)
                                                      0.060     2.236    d_1_i/axis_signal_gen_v6_7/inst/axi_slv_i/axi_rdata_reg[12]
  -------------------------------------------------------------------
                         required time                         -2.236    
                         arrival time                           2.247    
  -------------------------------------------------------------------
                         slack                                  0.011    

Slack (MET) :             0.012ns  (arrival time - required time)
  Source:                 d_1_i/axi_smc/inst/s03_nodes/s03_w_node/inst/inst_mi_handler/gen_normal_area.gen_upsizer.inst_upsizer/gen_w_ch.accum_reg[bytes][19][userdata][4]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axi_smc/inst/s03_nodes/s03_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[1].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41/RAMG/I
                            (rising edge-triggered cell RAMD32 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk_pl_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_pl_0 rise@0.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        0.226ns  (logic 0.061ns (26.991%)  route 0.165ns (73.009%))
  Logic Levels:           0  
  Clock Path Skew:        0.136ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.365ns
    Source Clock Delay      (SCD):    2.033ns
    Clock Pessimism Removal (CPR):    0.196ns
  Clock Net Delay (Source):      1.851ns (routing 0.599ns, distribution 1.252ns)
  Clock Net Delay (Destination): 2.139ns (routing 0.662ns, distribution 1.477ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.851     2.033    d_1_i/axi_smc/inst/s03_nodes/s03_w_node/inst/inst_mi_handler/gen_normal_area.gen_upsizer.inst_upsizer/s_sc_aclk
    SLICE_X38Y8          FDRE                                         r  d_1_i/axi_smc/inst/s03_nodes/s03_w_node/inst/inst_mi_handler/gen_normal_area.gen_upsizer.inst_upsizer/gen_w_ch.accum_reg[bytes][19][userdata][4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X38Y8          FDRE (Prop_DFF2_SLICEL_C_Q)
                                                      0.061     2.094 r  d_1_i/axi_smc/inst/s03_nodes/s03_w_node/inst/inst_mi_handler/gen_normal_area.gen_upsizer.inst_upsizer/gen_w_ch.accum_reg[bytes][19][userdata][4]/Q
                         net (fo=1, routed)           0.165     2.259    d_1_i/axi_smc/inst/s03_nodes/s03_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[1].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41/DIG0
    SLICE_X41Y7          RAMD32                                       r  d_1_i/axi_smc/inst/s03_nodes/s03_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[1].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41/RAMG/I
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       2.139     2.365    d_1_i/axi_smc/inst/s03_nodes/s03_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[1].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41/WCLK
    SLICE_X41Y7          RAMD32                                       r  d_1_i/axi_smc/inst/s03_nodes/s03_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[1].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41/RAMG/CLK
                         clock pessimism             -0.196     2.168    
    SLICE_X41Y7          RAMD32 (Hold_G5LUT_SLICEM_CLK_I)
                                                      0.078     2.246    d_1_i/axi_smc/inst/s03_nodes/s03_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[1].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41/RAMG
  -------------------------------------------------------------------
                         required time                         -2.246    
                         arrival time                           2.259    
  -------------------------------------------------------------------
                         slack                                  0.012    

Slack (MET) :             0.013ns  (arrival time - required time)
  Source:                 d_1_i/axi_dma_avg/U0/INCLUDE_S2MM_SOF_EOF_GENERATOR.I_S2MM_DMA_MNGR/GEN_S2MM_DMA_CONTROL.GEN_SIMPLE_DMA_MODE.I_S2MM_SMPL_SM/GEN_CMD_BTT_EQL_23.cmnd_data_reg[25]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axi_dma_avg/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SINGLE_REG.sig_regfifo_dout_reg_reg[25]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk_pl_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_pl_0 rise@0.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        0.128ns  (logic 0.059ns (46.094%)  route 0.069ns (53.906%))
  Logic Levels:           0  
  Clock Path Skew:        0.053ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.342ns
    Source Clock Delay      (SCD):    2.045ns
    Clock Pessimism Removal (CPR):    0.244ns
  Clock Net Delay (Source):      1.863ns (routing 0.599ns, distribution 1.264ns)
  Clock Net Delay (Destination): 2.116ns (routing 0.662ns, distribution 1.454ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.863     2.045    d_1_i/axi_dma_avg/U0/INCLUDE_S2MM_SOF_EOF_GENERATOR.I_S2MM_DMA_MNGR/GEN_S2MM_DMA_CONTROL.GEN_SIMPLE_DMA_MODE.I_S2MM_SMPL_SM/s_axi_lite_aclk
    SLICE_X58Y66         FDRE                                         r  d_1_i/axi_dma_avg/U0/INCLUDE_S2MM_SOF_EOF_GENERATOR.I_S2MM_DMA_MNGR/GEN_S2MM_DMA_CONTROL.GEN_SIMPLE_DMA_MODE.I_S2MM_SMPL_SM/GEN_CMD_BTT_EQL_23.cmnd_data_reg[25]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X58Y66         FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.059     2.104 r  d_1_i/axi_dma_avg/U0/INCLUDE_S2MM_SOF_EOF_GENERATOR.I_S2MM_DMA_MNGR/GEN_S2MM_DMA_CONTROL.GEN_SIMPLE_DMA_MODE.I_S2MM_SMPL_SM/GEN_CMD_BTT_EQL_23.cmnd_data_reg[25]/Q
                         net (fo=1, routed)           0.069     2.173    d_1_i/axi_dma_avg/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/D[25]
    SLICE_X58Y65         FDRE                                         r  d_1_i/axi_dma_avg/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SINGLE_REG.sig_regfifo_dout_reg_reg[25]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       2.116     2.342    d_1_i/axi_dma_avg/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/m_axi_s2mm_aclk
    SLICE_X58Y65         FDRE                                         r  d_1_i/axi_dma_avg/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SINGLE_REG.sig_regfifo_dout_reg_reg[25]/C
                         clock pessimism             -0.244     2.098    
    SLICE_X58Y65         FDRE (Hold_EFF2_SLICEL_C_D)
                                                      0.062     2.160    d_1_i/axi_dma_avg/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SINGLE_REG.sig_regfifo_dout_reg_reg[25]
  -------------------------------------------------------------------
                         required time                         -2.160    
                         arrival time                           2.173    
  -------------------------------------------------------------------
                         slack                                  0.013    

Slack (MET) :             0.013ns  (arrival time - required time)
  Source:                 d_1_i/axis_switch_gen/inst/gen_static_router.inst_static_router/inst_axi_ctrl_top/inst_axi_ctrl_write/data_r_reg[16]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_switch_gen/inst/gen_static_router.inst_static_router/inst_axi_ctrl_top/inst_reg_bank_1/gen_reg[4].reg_data_reg[144]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk_pl_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_pl_0 rise@0.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        0.176ns  (logic 0.059ns (33.559%)  route 0.117ns (66.441%))
  Logic Levels:           0  
  Clock Path Skew:        0.101ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.294ns
    Source Clock Delay      (SCD):    2.000ns
    Clock Pessimism Removal (CPR):    0.193ns
  Clock Net Delay (Source):      1.818ns (routing 0.599ns, distribution 1.219ns)
  Clock Net Delay (Destination): 2.068ns (routing 0.662ns, distribution 1.406ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.818     2.000    d_1_i/axis_switch_gen/inst/gen_static_router.inst_static_router/inst_axi_ctrl_top/inst_axi_ctrl_write/s_axi_ctrl_aclk
    SLICE_X38Y99         FDRE                                         r  d_1_i/axis_switch_gen/inst/gen_static_router.inst_static_router/inst_axi_ctrl_top/inst_axi_ctrl_write/data_r_reg[16]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X38Y99         FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.059     2.059 r  d_1_i/axis_switch_gen/inst/gen_static_router.inst_static_router/inst_axi_ctrl_top/inst_axi_ctrl_write/data_r_reg[16]/Q
                         net (fo=9, routed)           0.117     2.176    d_1_i/axis_switch_gen/inst/gen_static_router.inst_static_router/inst_axi_ctrl_top/inst_reg_bank_1/D[16]
    SLICE_X39Y98         FDRE                                         r  d_1_i/axis_switch_gen/inst/gen_static_router.inst_static_router/inst_axi_ctrl_top/inst_reg_bank_1/gen_reg[4].reg_data_reg[144]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       2.068     2.294    d_1_i/axis_switch_gen/inst/gen_static_router.inst_static_router/inst_axi_ctrl_top/inst_reg_bank_1/s_axi_ctrl_aclk
    SLICE_X39Y98         FDRE                                         r  d_1_i/axis_switch_gen/inst/gen_static_router.inst_static_router/inst_axi_ctrl_top/inst_reg_bank_1/gen_reg[4].reg_data_reg[144]/C
                         clock pessimism             -0.193     2.101    
    SLICE_X39Y98         FDRE (Hold_HFF2_SLICEM_C_D)
                                                      0.062     2.163    d_1_i/axis_switch_gen/inst/gen_static_router.inst_static_router/inst_axi_ctrl_top/inst_reg_bank_1/gen_reg[4].reg_data_reg[144]
  -------------------------------------------------------------------
                         required time                         -2.163    
                         arrival time                           2.176    
  -------------------------------------------------------------------
                         slack                                  0.013    

Slack (MET) :             0.013ns  (arrival time - required time)
  Source:                 d_1_i/dac_bias_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst/src_gray_ff_reg[4]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/dac_bias_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst/dest_graysync_ff_reg[0][4]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk_pl_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_pl_0 rise@0.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        0.128ns  (logic 0.059ns (46.094%)  route 0.069ns (53.906%))
  Logic Levels:           0  
  Clock Path Skew:        0.053ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.583ns
    Source Clock Delay      (SCD):    2.263ns
    Clock Pessimism Removal (CPR):    0.268ns
  Clock Net Delay (Source):      2.081ns (routing 0.599ns, distribution 1.482ns)
  Clock Net Delay (Destination): 2.357ns (routing 0.662ns, distribution 1.695ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       2.081     2.263    d_1_i/dac_bias_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst/src_clk
    SLICE_X91Y25         FDRE                                         r  d_1_i/dac_bias_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst/src_gray_ff_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X91Y25         FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.059     2.322 r  d_1_i/dac_bias_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst/src_gray_ff_reg[4]/Q
                         net (fo=1, routed)           0.069     2.391    d_1_i/dac_bias_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst/async_path[4]
    SLICE_X91Y24         FDRE                                         r  d_1_i/dac_bias_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst/dest_graysync_ff_reg[0][4]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       2.357     2.583    d_1_i/dac_bias_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst/dest_clk
    SLICE_X91Y24         FDRE                                         r  d_1_i/dac_bias_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst/dest_graysync_ff_reg[0][4]/C
                         clock pessimism             -0.268     2.315    
    SLICE_X91Y24         FDRE (Hold_HFF2_SLICEL_C_D)
                                                      0.062     2.377    d_1_i/dac_bias_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst/dest_graysync_ff_reg[0][4]
  -------------------------------------------------------------------
                         required time                         -2.377    
                         arrival time                           2.391    
  -------------------------------------------------------------------
                         slack                                  0.013    

Slack (MET) :             0.013ns  (arrival time - required time)
  Source:                 d_1_i/axi_smc/inst/s00_nodes/s00_ar_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[100]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axi_smc/inst/switchboards/ar_switchboard/inst/gen_mi[0].inst_opipe_payld/gen_pipe[1].pipe_reg[1][100]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk_pl_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_pl_0 rise@0.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        0.179ns  (logic 0.095ns (53.073%)  route 0.084ns (46.927%))
  Logic Levels:           1  (LUT3=1)
  Clock Path Skew:        0.106ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.398ns
    Source Clock Delay      (SCD):    2.095ns
    Clock Pessimism Removal (CPR):    0.198ns
  Clock Net Delay (Source):      1.913ns (routing 0.599ns, distribution 1.314ns)
  Clock Net Delay (Destination): 2.172ns (routing 0.662ns, distribution 1.510ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.913     2.095    d_1_i/axi_smc/inst/s00_nodes/s00_ar_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/clka
    SLICE_X30Y66         FDRE                                         r  d_1_i/axi_smc/inst/s00_nodes/s00_ar_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[100]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X30Y66         FDRE (Prop_BFF2_SLICEM_C_Q)
                                                      0.060     2.155 r  d_1_i/axi_smc/inst/s00_nodes/s00_ar_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[100]/Q
                         net (fo=1, routed)           0.062     2.217    d_1_i/axi_smc/inst/switchboards/ar_switchboard/inst/gen_mi[0].inst_opipe_payld/s_sc_payld[43]
    SLICE_X29Y66         LUT3 (Prop_D6LUT_SLICEL_I2_O)
                                                      0.035     2.252 r  d_1_i/axi_smc/inst/switchboards/ar_switchboard/inst/gen_mi[0].inst_opipe_payld/gen_pipe[1].pipe[1][100]_i_1/O
                         net (fo=1, routed)           0.022     2.274    d_1_i/axi_smc/inst/switchboards/ar_switchboard/inst/gen_mi[0].inst_opipe_payld/gen_pipe[1].pipe[1][100]_i_1_n_0
    SLICE_X29Y66         FDRE                                         r  d_1_i/axi_smc/inst/switchboards/ar_switchboard/inst/gen_mi[0].inst_opipe_payld/gen_pipe[1].pipe_reg[1][100]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       2.172     2.398    d_1_i/axi_smc/inst/switchboards/ar_switchboard/inst/gen_mi[0].inst_opipe_payld/aclk
    SLICE_X29Y66         FDRE                                         r  d_1_i/axi_smc/inst/switchboards/ar_switchboard/inst/gen_mi[0].inst_opipe_payld/gen_pipe[1].pipe_reg[1][100]/C
                         clock pessimism             -0.198     2.200    
    SLICE_X29Y66         FDRE (Hold_DFF_SLICEL_C_D)
                                                      0.060     2.260    d_1_i/axi_smc/inst/switchboards/ar_switchboard/inst/gen_mi[0].inst_opipe_payld/gen_pipe[1].pipe_reg[1][100]
  -------------------------------------------------------------------
                         required time                         -2.260    
                         arrival time                           2.274    
  -------------------------------------------------------------------
                         slack                                  0.013    





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         clk_pl_0
Waveform(ns):       { 0.000 5.000 }
Period(ns):         10.000
Sources:            { d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0] }

Check Type        Corner  Lib Pin            Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location           Pin
Min Period        n/a     FDRE/C             n/a            8.000         10.000      2.000      HDIOLOGIC_S_X0Y23  d_1_i/attn_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/LOGIC_FOR_MD_0_GEN.SPI_MODULE_I/RATIO_NOT_EQUAL_4_GENERATE.SCK_O_NQ_4_NO_STARTUP_USED.SCK_O_NE_4_FDRE_INST/C
Min Period        n/a     FDRE/C             n/a            8.000         10.000      2.000      HDIOLOGIC_S_X0Y11  d_1_i/dac_bias_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/IO1_I_REG/C
Min Period        n/a     FDRE/C             n/a            8.000         10.000      2.000      HDIOLOGIC_M_X0Y3   d_1_i/dac_bias_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/LOGIC_FOR_MD_0_GEN.SPI_MODULE_I/RATIO_NOT_EQUAL_4_GENERATE.SCK_O_NQ_4_NO_STARTUP_USED.SCK_O_NE_4_FDRE_INST/C
Min Period        n/a     FDRE/C             n/a            8.000         10.000      2.000      HDIOLOGIC_S_X0Y18  d_1_i/lo_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/LOGIC_FOR_MD_0_GEN.SPI_MODULE_I/RATIO_NOT_EQUAL_4_GENERATE.SCK_O_NQ_4_NO_STARTUP_USED.SCK_O_NE_4_FDRE_INST/C
Min Period        n/a     FDRE/C             n/a            8.000         10.000      2.000      HDIOLOGIC_S_X0Y19  d_1_i/psf_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/IO1_I_REG/C
Min Period        n/a     FDRE/C             n/a            8.000         10.000      2.000      HDIOLOGIC_M_X0Y21  d_1_i/psf_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/LOGIC_FOR_MD_0_GEN.SPI_MODULE_I/RATIO_NOT_EQUAL_4_GENERATE.SCK_O_NQ_4_NO_STARTUP_USED.SCK_O_NE_4_FDRE_INST/C
Min Period        n/a     HSADC/DCLK         n/a            4.000         10.000      6.000      HSADC_X0Y0         d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/DCLK
Min Period        n/a     HSADC/DCLK         n/a            4.000         10.000      6.000      HSADC_X0Y1         d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/DCLK
Min Period        n/a     HSADC/DCLK         n/a            4.000         10.000      6.000      HSADC_X0Y2         d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/DCLK
Min Period        n/a     HSADC/DCLK         n/a            4.000         10.000      6.000      HSADC_X0Y3         d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/DCLK
Max Period        n/a     MMCME4_ADV/CLKIN1  n/a            100.000       10.000      90.000     MMCM_X0Y5          d_1_i/clk_core/inst/mmcme4_adv_inst/CLKIN1
Low Pulse Width   Slow    FDRE/C             n/a            4.000         5.000       1.000      HDIOLOGIC_S_X0Y23  d_1_i/attn_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/LOGIC_FOR_MD_0_GEN.SPI_MODULE_I/RATIO_NOT_EQUAL_4_GENERATE.SCK_O_NQ_4_NO_STARTUP_USED.SCK_O_NE_4_FDRE_INST/C
Low Pulse Width   Fast    FDRE/C             n/a            4.000         5.000       1.000      HDIOLOGIC_S_X0Y23  d_1_i/attn_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/LOGIC_FOR_MD_0_GEN.SPI_MODULE_I/RATIO_NOT_EQUAL_4_GENERATE.SCK_O_NQ_4_NO_STARTUP_USED.SCK_O_NE_4_FDRE_INST/C
Low Pulse Width   Slow    FDRE/C             n/a            4.000         5.000       1.000      HDIOLOGIC_S_X0Y11  d_1_i/dac_bias_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/IO1_I_REG/C
Low Pulse Width   Fast    FDRE/C             n/a            4.000         5.000       1.000      HDIOLOGIC_S_X0Y11  d_1_i/dac_bias_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/IO1_I_REG/C
Low Pulse Width   Slow    FDRE/C             n/a            4.000         5.000       1.000      HDIOLOGIC_M_X0Y3   d_1_i/dac_bias_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/LOGIC_FOR_MD_0_GEN.SPI_MODULE_I/RATIO_NOT_EQUAL_4_GENERATE.SCK_O_NQ_4_NO_STARTUP_USED.SCK_O_NE_4_FDRE_INST/C
Low Pulse Width   Fast    FDRE/C             n/a            4.000         5.000       1.000      HDIOLOGIC_M_X0Y3   d_1_i/dac_bias_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/LOGIC_FOR_MD_0_GEN.SPI_MODULE_I/RATIO_NOT_EQUAL_4_GENERATE.SCK_O_NQ_4_NO_STARTUP_USED.SCK_O_NE_4_FDRE_INST/C
Low Pulse Width   Slow    FDRE/C             n/a            4.000         5.000       1.000      HDIOLOGIC_S_X0Y18  d_1_i/lo_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/LOGIC_FOR_MD_0_GEN.SPI_MODULE_I/RATIO_NOT_EQUAL_4_GENERATE.SCK_O_NQ_4_NO_STARTUP_USED.SCK_O_NE_4_FDRE_INST/C
Low Pulse Width   Fast    FDRE/C             n/a            4.000         5.000       1.000      HDIOLOGIC_S_X0Y18  d_1_i/lo_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/LOGIC_FOR_MD_0_GEN.SPI_MODULE_I/RATIO_NOT_EQUAL_4_GENERATE.SCK_O_NQ_4_NO_STARTUP_USED.SCK_O_NE_4_FDRE_INST/C
Low Pulse Width   Slow    FDRE/C             n/a            4.000         5.000       1.000      HDIOLOGIC_S_X0Y19  d_1_i/psf_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/IO1_I_REG/C
Low Pulse Width   Fast    FDRE/C             n/a            4.000         5.000       1.000      HDIOLOGIC_S_X0Y19  d_1_i/psf_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/IO1_I_REG/C
High Pulse Width  Slow    FDRE/C             n/a            4.000         5.000       1.000      HDIOLOGIC_S_X0Y23  d_1_i/attn_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/LOGIC_FOR_MD_0_GEN.SPI_MODULE_I/RATIO_NOT_EQUAL_4_GENERATE.SCK_O_NQ_4_NO_STARTUP_USED.SCK_O_NE_4_FDRE_INST/C
High Pulse Width  Fast    FDRE/C             n/a            4.000         5.000       1.000      HDIOLOGIC_S_X0Y23  d_1_i/attn_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/LOGIC_FOR_MD_0_GEN.SPI_MODULE_I/RATIO_NOT_EQUAL_4_GENERATE.SCK_O_NQ_4_NO_STARTUP_USED.SCK_O_NE_4_FDRE_INST/C
High Pulse Width  Slow    FDRE/C             n/a            4.000         5.000       1.000      HDIOLOGIC_S_X0Y11  d_1_i/dac_bias_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/IO1_I_REG/C
High Pulse Width  Fast    FDRE/C             n/a            4.000         5.000       1.000      HDIOLOGIC_S_X0Y11  d_1_i/dac_bias_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/IO1_I_REG/C
High Pulse Width  Slow    FDRE/C             n/a            4.000         5.000       1.000      HDIOLOGIC_M_X0Y3   d_1_i/dac_bias_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/LOGIC_FOR_MD_0_GEN.SPI_MODULE_I/RATIO_NOT_EQUAL_4_GENERATE.SCK_O_NQ_4_NO_STARTUP_USED.SCK_O_NE_4_FDRE_INST/C
High Pulse Width  Fast    FDRE/C             n/a            4.000         5.000       1.000      HDIOLOGIC_M_X0Y3   d_1_i/dac_bias_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/LOGIC_FOR_MD_0_GEN.SPI_MODULE_I/RATIO_NOT_EQUAL_4_GENERATE.SCK_O_NQ_4_NO_STARTUP_USED.SCK_O_NE_4_FDRE_INST/C
High Pulse Width  Slow    FDRE/C             n/a            4.000         5.000       1.000      HDIOLOGIC_S_X0Y18  d_1_i/lo_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/LOGIC_FOR_MD_0_GEN.SPI_MODULE_I/RATIO_NOT_EQUAL_4_GENERATE.SCK_O_NQ_4_NO_STARTUP_USED.SCK_O_NE_4_FDRE_INST/C
High Pulse Width  Fast    FDRE/C             n/a            4.000         5.000       1.000      HDIOLOGIC_S_X0Y18  d_1_i/lo_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/LOGIC_FOR_MD_0_GEN.SPI_MODULE_I/RATIO_NOT_EQUAL_4_GENERATE.SCK_O_NQ_4_NO_STARTUP_USED.SCK_O_NE_4_FDRE_INST/C
High Pulse Width  Slow    FDRE/C             n/a            4.000         5.000       1.000      HDIOLOGIC_S_X0Y19  d_1_i/psf_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/IO1_I_REG/C
High Pulse Width  Fast    FDRE/C             n/a            4.000         5.000       1.000      HDIOLOGIC_S_X0Y19  d_1_i/psf_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/IO1_I_REG/C



---------------------------------------------------------------------------------------------------
From Clock:  clk_out1_d_1_clk_core_0
  To Clock:  clk_out1_d_1_clk_core_0

Setup :            0  Failing Endpoints,  Worst Slack        0.178ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.009ns,  Total Violation        0.000ns
PW    :            0  Failing Endpoints,  Worst Slack        1.958ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.178ns  (required time - arrival time)
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/gcc_wr_ptr/count_gray_r_reg[4]/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_1/CASDOMUXEN_B
                            (rising edge-triggered cell RAMB36E2 clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             clk_out1_d_1_clk_core_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            5.000ns  (clk_out1_d_1_clk_core_0 rise@5.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        4.541ns  (logic 0.516ns (11.364%)  route 4.025ns (88.636%))
  Logic Levels:           5  (LUT4=1 LUT5=3 LUT6=1)
  Clock Path Skew:        -0.120ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.375ns = ( 10.375 - 5.000 ) 
    Source Clock Delay      (SCD):    5.163ns
    Clock Pessimism Removal (CPR):    -0.332ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.102ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.649ns (routing 1.461ns, distribution 1.188ns)
  Clock Net Delay (Destination): 2.393ns (routing 1.325ns, distribution 1.068ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=48236, routed)       2.142     2.368    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.241 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.486    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y133        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.514 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=4540, routed)        2.649     5.163    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/gcc_wr_ptr/c_clk_i
    SLICE_X91Y235        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/gcc_wr_ptr/count_gray_r_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X91Y235        FDCE (Prop_AFF2_SLICEL_C_Q)
                                                      0.081     5.244 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/gcc_wr_ptr/count_gray_r_reg[4]/Q
                         net (fo=8, routed)           0.788     6.032    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/gcc_wr_ptr/wr_gptr_p1[4]
    SLICE_X80Y235        LUT6 (Prop_A6LUT_SLICEL_I2_O)
                                                      0.149     6.181 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/gcc_wr_ptr/count_gray_r[8]_i_3__40/O
                         net (fo=3, routed)           0.787     6.968    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/gcc_wr_ptr/count_gray_r[8]_i_3__40_n_0
    SLICE_X71Y174        LUT5 (Prop_B6LUT_SLICEL_I0_O)
                                                      0.148     7.116 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/gcc_wr_ptr/reg_A[0][31]_i_13/O
                         net (fo=2, routed)           0.045     7.161    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[8].wave_fifo_inst/gcc_wr_ptr/c_fifo_wave_push_r_reg[0][2]
    SLICE_X71Y174        LUT5 (Prop_A6LUT_SLICEL_I3_O)
                                                      0.050     7.211 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[8].wave_fifo_inst/gcc_wr_ptr/reg_A[0][31]_i_3/O
                         net (fo=10, routed)          0.414     7.625    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[8].wave_fifo_inst/gcc_wr_ptr/clr_fifo_req_reg
    SLICE_X62Y156        LUT5 (Prop_B6LUT_SLICEL_I2_O)
                                                      0.036     7.661 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[8].wave_fifo_inst/gcc_wr_ptr/reg_A[0][31]_i_1_replica_2/O
                         net (fo=474, routed)         0.609     8.270    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/FSM_sequential_core_st_reg[0]_repN_2_alias
    SLICE_X66Y140        LUT4 (Prop_G6LUT_SLICEM_I2_O)
                                                      0.052     8.322 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_1_CASDOMUXEN_B_cooolgate_en_gate_1678/O
                         net (fo=11, routed)          1.382     9.704    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_1_CASDOMUXEN_B_cooolgate_en_sig_821
    RAMB36_X3Y21         RAMB36E2                                     r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_1/CASDOMUXEN_B
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      5.000     5.000 r  
    PS8_X0Y0             PS8                          0.000     5.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     5.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     5.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=48236, routed)       1.931     7.113    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     7.743 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     7.958    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y133        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     7.982 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=4540, routed)        2.393    10.375    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/c_clk_i
    RAMB36_X3Y21         RAMB36E2                                     r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_1/CLKBWRCLK
                         clock pessimism             -0.332    10.043    
                         clock uncertainty           -0.062     9.981    
    RAMB36_X3Y21         RAMB36E2 (Setup_RAMB36E2_RAMB36_CLKBWRCLK_CASDOMUXEN_B)
                                                     -0.099     9.882    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_1
  -------------------------------------------------------------------
                         required time                          9.882    
                         arrival time                          -9.704    
  -------------------------------------------------------------------
                         slack                                  0.178    

Slack (MET) :             0.214ns  (required time - arrival time)
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/c_fifo_time_in_r_reg[15]/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[7].trig_fifo_inst/fifo_mem/RAM_reg/DINADIN[15]
                            (rising edge-triggered cell RAMB36E2 clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             clk_out1_d_1_clk_core_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            5.000ns  (clk_out1_d_1_clk_core_0 rise@5.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        4.427ns  (logic 0.079ns (1.785%)  route 4.348ns (98.215%))
  Logic Levels:           0  
  Clock Path Skew:        -0.027ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.315ns = ( 10.315 - 5.000 ) 
    Source Clock Delay      (SCD):    5.018ns
    Clock Pessimism Removal (CPR):    -0.324ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.102ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.504ns (routing 1.461ns, distribution 1.043ns)
  Clock Net Delay (Destination): 2.333ns (routing 1.325ns, distribution 1.008ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=48236, routed)       2.142     2.368    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.241 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.486    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y133        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.514 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=4540, routed)        2.504     5.018    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/c_clk_i
    SLICE_X66Y143        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/c_fifo_time_in_r_reg[15]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X66Y143        FDCE (Prop_HFF_SLICEM_C_Q)
                                                      0.079     5.097 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/c_fifo_time_in_r_reg[15]/Q
                         net (fo=27, routed)          4.348     9.445    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[7].trig_fifo_inst/fifo_mem/data_i[15]
    RAMB36_X7Y47         RAMB36E2                                     r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[7].trig_fifo_inst/fifo_mem/RAM_reg/DINADIN[15]
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      5.000     5.000 r  
    PS8_X0Y0             PS8                          0.000     5.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     5.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     5.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=48236, routed)       1.931     7.113    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     7.743 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     7.958    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y133        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     7.982 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=4540, routed)        2.333    10.315    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[7].trig_fifo_inst/fifo_mem/c_clk_i
    RAMB36_X7Y47         RAMB36E2                                     r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[7].trig_fifo_inst/fifo_mem/RAM_reg/CLKBWRCLK
                         clock pessimism             -0.324     9.991    
                         clock uncertainty           -0.062     9.929    
    RAMB36_X7Y47         RAMB36E2 (Setup_RAMB36E2_RAMB36_CLKBWRCLK_DINADIN[15])
                                                     -0.270     9.659    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[7].trig_fifo_inst/fifo_mem/RAM_reg
  -------------------------------------------------------------------
                         required time                          9.659    
                         arrival time                          -9.445    
  -------------------------------------------------------------------
                         slack                                  0.214    

Slack (MET) :             0.252ns  (required time - arrival time)
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/gcc_wr_ptr/count_gray_r_reg[4]/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/WAVE_FIFO[11].wave_fifo_inst/fifo_mem/RAM_reg_0/WEBWE[6]
                            (rising edge-triggered cell RAMB36E2 clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             clk_out1_d_1_clk_core_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            5.000ns  (clk_out1_d_1_clk_core_0 rise@5.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        4.250ns  (logic 0.576ns (13.554%)  route 3.674ns (86.446%))
  Logic Levels:           5  (LUT5=4 LUT6=1)
  Clock Path Skew:        -0.043ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.383ns = ( 10.383 - 5.000 ) 
    Source Clock Delay      (SCD):    5.163ns
    Clock Pessimism Removal (CPR):    -0.263ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.102ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.649ns (routing 1.461ns, distribution 1.188ns)
  Clock Net Delay (Destination): 2.401ns (routing 1.325ns, distribution 1.076ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=48236, routed)       2.142     2.368    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.241 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.486    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y133        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.514 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=4540, routed)        2.649     5.163    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/gcc_wr_ptr/c_clk_i
    SLICE_X91Y235        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/gcc_wr_ptr/count_gray_r_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X91Y235        FDCE (Prop_AFF2_SLICEL_C_Q)
                                                      0.081     5.244 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/gcc_wr_ptr/count_gray_r_reg[4]/Q
                         net (fo=8, routed)           0.788     6.032    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/gcc_wr_ptr/wr_gptr_p1[4]
    SLICE_X80Y235        LUT6 (Prop_A6LUT_SLICEL_I2_O)
                                                      0.149     6.181 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/gcc_wr_ptr/count_gray_r[8]_i_3__40/O
                         net (fo=3, routed)           0.787     6.968    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/gcc_wr_ptr/count_gray_r[8]_i_3__40_n_0
    SLICE_X71Y174        LUT5 (Prop_B6LUT_SLICEL_I0_O)
                                                      0.148     7.116 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/gcc_wr_ptr/reg_A[0][31]_i_13/O
                         net (fo=2, routed)           0.045     7.161    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[8].wave_fifo_inst/gcc_wr_ptr/c_fifo_wave_push_r_reg[0][2]
    SLICE_X71Y174        LUT5 (Prop_A6LUT_SLICEL_I3_O)
                                                      0.050     7.211 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[8].wave_fifo_inst/gcc_wr_ptr/reg_A[0][31]_i_3/O
                         net (fo=10, routed)          0.263     7.474    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[8].wave_fifo_inst/gcc_wr_ptr/clr_fifo_req_reg
    SLICE_X71Y158        LUT5 (Prop_A6LUT_SLICEL_I2_O)
                                                      0.050     7.524 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[8].wave_fifo_inst/gcc_wr_ptr/reg_A[0][31]_i_1_replica_1/O
                         net (fo=62, routed)          1.263     8.787    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/gcc_wr_ptr/FSM_sequential_core_st_reg[0]_repN_1_alias
    SLICE_X91Y212        LUT5 (Prop_A6LUT_SLICEL_I3_O)
                                                      0.098     8.885 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/gcc_wr_ptr/RAM_reg_0_i_1__8/O
                         net (fo=24, routed)          0.528     9.413    d_1_i/qick_processor_0/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/do_push
    RAMB36_X9Y44         RAMB36E2                                     r  d_1_i/qick_processor_0/WAVE_FIFO[11].wave_fifo_inst/fifo_mem/RAM_reg_0/WEBWE[6]
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      5.000     5.000 r  
    PS8_X0Y0             PS8                          0.000     5.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     5.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     5.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=48236, routed)       1.931     7.113    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     7.743 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     7.958    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y133        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     7.982 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=4540, routed)        2.401    10.383    d_1_i/qick_processor_0/c_clk_i
    RAMB36_X9Y44         RAMB36E2                                     r  d_1_i/qick_processor_0/WAVE_FIFO[11].wave_fifo_inst/fifo_mem/RAM_reg_0/CLKBWRCLK
                         clock pessimism             -0.263    10.120    
                         clock uncertainty           -0.062    10.058    
    RAMB36_X9Y44         RAMB36E2 (Setup_RAMB36E2_RAMB36_CLKBWRCLK_WEBWE[6])
                                                     -0.394     9.664    d_1_i/qick_processor_0/WAVE_FIFO[11].wave_fifo_inst/fifo_mem/RAM_reg_0
  -------------------------------------------------------------------
                         required time                          9.664    
                         arrival time                          -9.413    
  -------------------------------------------------------------------
                         slack                                  0.252    

Slack (MET) :             0.258ns  (required time - arrival time)
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/gcc_wr_ptr/count_gray_r_reg[4]/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/WAVE_FIFO[11].wave_fifo_inst/fifo_mem/RAM_reg_0/WEBWE[7]
                            (rising edge-triggered cell RAMB36E2 clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             clk_out1_d_1_clk_core_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            5.000ns  (clk_out1_d_1_clk_core_0 rise@5.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        4.244ns  (logic 0.576ns (13.573%)  route 3.668ns (86.427%))
  Logic Levels:           5  (LUT5=4 LUT6=1)
  Clock Path Skew:        -0.043ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.383ns = ( 10.383 - 5.000 ) 
    Source Clock Delay      (SCD):    5.163ns
    Clock Pessimism Removal (CPR):    -0.263ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.102ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.649ns (routing 1.461ns, distribution 1.188ns)
  Clock Net Delay (Destination): 2.401ns (routing 1.325ns, distribution 1.076ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=48236, routed)       2.142     2.368    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.241 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.486    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y133        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.514 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=4540, routed)        2.649     5.163    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/gcc_wr_ptr/c_clk_i
    SLICE_X91Y235        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/gcc_wr_ptr/count_gray_r_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X91Y235        FDCE (Prop_AFF2_SLICEL_C_Q)
                                                      0.081     5.244 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/gcc_wr_ptr/count_gray_r_reg[4]/Q
                         net (fo=8, routed)           0.788     6.032    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/gcc_wr_ptr/wr_gptr_p1[4]
    SLICE_X80Y235        LUT6 (Prop_A6LUT_SLICEL_I2_O)
                                                      0.149     6.181 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/gcc_wr_ptr/count_gray_r[8]_i_3__40/O
                         net (fo=3, routed)           0.787     6.968    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/gcc_wr_ptr/count_gray_r[8]_i_3__40_n_0
    SLICE_X71Y174        LUT5 (Prop_B6LUT_SLICEL_I0_O)
                                                      0.148     7.116 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/gcc_wr_ptr/reg_A[0][31]_i_13/O
                         net (fo=2, routed)           0.045     7.161    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[8].wave_fifo_inst/gcc_wr_ptr/c_fifo_wave_push_r_reg[0][2]
    SLICE_X71Y174        LUT5 (Prop_A6LUT_SLICEL_I3_O)
                                                      0.050     7.211 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[8].wave_fifo_inst/gcc_wr_ptr/reg_A[0][31]_i_3/O
                         net (fo=10, routed)          0.263     7.474    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[8].wave_fifo_inst/gcc_wr_ptr/clr_fifo_req_reg
    SLICE_X71Y158        LUT5 (Prop_A6LUT_SLICEL_I2_O)
                                                      0.050     7.524 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[8].wave_fifo_inst/gcc_wr_ptr/reg_A[0][31]_i_1_replica_1/O
                         net (fo=62, routed)          1.263     8.787    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/gcc_wr_ptr/FSM_sequential_core_st_reg[0]_repN_1_alias
    SLICE_X91Y212        LUT5 (Prop_A6LUT_SLICEL_I3_O)
                                                      0.098     8.885 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/gcc_wr_ptr/RAM_reg_0_i_1__8/O
                         net (fo=24, routed)          0.522     9.407    d_1_i/qick_processor_0/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/do_push
    RAMB36_X9Y44         RAMB36E2                                     r  d_1_i/qick_processor_0/WAVE_FIFO[11].wave_fifo_inst/fifo_mem/RAM_reg_0/WEBWE[7]
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      5.000     5.000 r  
    PS8_X0Y0             PS8                          0.000     5.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     5.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     5.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=48236, routed)       1.931     7.113    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     7.743 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     7.958    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y133        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     7.982 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=4540, routed)        2.401    10.383    d_1_i/qick_processor_0/c_clk_i
    RAMB36_X9Y44         RAMB36E2                                     r  d_1_i/qick_processor_0/WAVE_FIFO[11].wave_fifo_inst/fifo_mem/RAM_reg_0/CLKBWRCLK
                         clock pessimism             -0.263    10.120    
                         clock uncertainty           -0.062    10.058    
    RAMB36_X9Y44         RAMB36E2 (Setup_RAMB36E2_RAMB36_CLKBWRCLK_WEBWE[7])
                                                     -0.394     9.664    d_1_i/qick_processor_0/WAVE_FIFO[11].wave_fifo_inst/fifo_mem/RAM_reg_0
  -------------------------------------------------------------------
                         required time                          9.664    
                         arrival time                          -9.407    
  -------------------------------------------------------------------
                         slack                                  0.258    

Slack (MET) :             0.261ns  (required time - arrival time)
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/gcc_wr_ptr/count_gray_r_reg[4]/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_13/WEBWE[0]
                            (rising edge-triggered cell RAMB36E2 clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             clk_out1_d_1_clk_core_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            5.000ns  (clk_out1_d_1_clk_core_0 rise@5.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        3.997ns  (logic 0.553ns (13.836%)  route 3.444ns (86.164%))
  Logic Levels:           5  (LUT3=1 LUT5=3 LUT6=1)
  Clock Path Skew:        -0.286ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.209ns = ( 10.209 - 5.000 ) 
    Source Clock Delay      (SCD):    5.163ns
    Clock Pessimism Removal (CPR):    -0.332ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.102ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.649ns (routing 1.461ns, distribution 1.188ns)
  Clock Net Delay (Destination): 2.227ns (routing 1.325ns, distribution 0.902ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=48236, routed)       2.142     2.368    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.241 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.486    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y133        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.514 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=4540, routed)        2.649     5.163    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/gcc_wr_ptr/c_clk_i
    SLICE_X91Y235        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/gcc_wr_ptr/count_gray_r_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X91Y235        FDCE (Prop_AFF2_SLICEL_C_Q)
                                                      0.081     5.244 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/gcc_wr_ptr/count_gray_r_reg[4]/Q
                         net (fo=8, routed)           0.788     6.032    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/gcc_wr_ptr/wr_gptr_p1[4]
    SLICE_X80Y235        LUT6 (Prop_A6LUT_SLICEL_I2_O)
                                                      0.149     6.181 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/gcc_wr_ptr/count_gray_r[8]_i_3__40/O
                         net (fo=3, routed)           0.787     6.968    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/gcc_wr_ptr/count_gray_r[8]_i_3__40_n_0
    SLICE_X71Y174        LUT5 (Prop_B6LUT_SLICEL_I0_O)
                                                      0.148     7.116 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/gcc_wr_ptr/reg_A[0][31]_i_13/O
                         net (fo=2, routed)           0.045     7.161    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[8].wave_fifo_inst/gcc_wr_ptr/c_fifo_wave_push_r_reg[0][2]
    SLICE_X71Y174        LUT5 (Prop_A6LUT_SLICEL_I3_O)
                                                      0.050     7.211 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[8].wave_fifo_inst/gcc_wr_ptr/reg_A[0][31]_i_3/O
                         net (fo=10, routed)          0.409     7.620    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[8].wave_fifo_inst/gcc_wr_ptr/clr_fifo_req_reg
    SLICE_X57Y162        LUT5 (Prop_A6LUT_SLICEL_I2_O)
                                                      0.035     7.655 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[8].wave_fifo_inst/gcc_wr_ptr/reg_A[0][31]_i_1_replica/O
                         net (fo=23, routed)          0.828     8.483    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/FSM_sequential_core_st_reg[0]_repN_alias
    SLICE_X66Y98         LUT3 (Prop_G6LUT_SLICEM_I0_O)
                                                      0.090     8.573 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/RAM_reg_bram_13_i_4/O
                         net (fo=4, routed)           0.586     9.160    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_13_4[0]
    RAMB36_X6Y13         RAMB36E2                                     r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_13/WEBWE[0]
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      5.000     5.000 r  
    PS8_X0Y0             PS8                          0.000     5.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     5.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     5.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=48236, routed)       1.931     7.113    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     7.743 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     7.958    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y133        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     7.982 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=4540, routed)        2.227    10.209    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/c_clk_i
    RAMB36_X6Y13         RAMB36E2                                     r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_13/CLKBWRCLK
                         clock pessimism             -0.332     9.877    
                         clock uncertainty           -0.062     9.815    
    RAMB36_X6Y13         RAMB36E2 (Setup_RAMB36E2_RAMB36_CLKBWRCLK_WEBWE[0])
                                                     -0.394     9.421    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_13
  -------------------------------------------------------------------
                         required time                          9.421    
                         arrival time                          -9.160    
  -------------------------------------------------------------------
                         slack                                  0.261    

Slack (MET) :             0.262ns  (required time - arrival time)
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/gcc_wr_ptr/count_gray_r_reg[4]/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/WAVE_FIFO[11].wave_fifo_inst/fifo_mem/RAM_reg_0/WEBWE[1]
                            (rising edge-triggered cell RAMB36E2 clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             clk_out1_d_1_clk_core_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            5.000ns  (clk_out1_d_1_clk_core_0 rise@5.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        4.240ns  (logic 0.576ns (13.586%)  route 3.664ns (86.414%))
  Logic Levels:           5  (LUT5=4 LUT6=1)
  Clock Path Skew:        -0.043ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.383ns = ( 10.383 - 5.000 ) 
    Source Clock Delay      (SCD):    5.163ns
    Clock Pessimism Removal (CPR):    -0.263ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.102ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.649ns (routing 1.461ns, distribution 1.188ns)
  Clock Net Delay (Destination): 2.401ns (routing 1.325ns, distribution 1.076ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=48236, routed)       2.142     2.368    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.241 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.486    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y133        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.514 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=4540, routed)        2.649     5.163    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/gcc_wr_ptr/c_clk_i
    SLICE_X91Y235        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/gcc_wr_ptr/count_gray_r_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X91Y235        FDCE (Prop_AFF2_SLICEL_C_Q)
                                                      0.081     5.244 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/gcc_wr_ptr/count_gray_r_reg[4]/Q
                         net (fo=8, routed)           0.788     6.032    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/gcc_wr_ptr/wr_gptr_p1[4]
    SLICE_X80Y235        LUT6 (Prop_A6LUT_SLICEL_I2_O)
                                                      0.149     6.181 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/gcc_wr_ptr/count_gray_r[8]_i_3__40/O
                         net (fo=3, routed)           0.787     6.968    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/gcc_wr_ptr/count_gray_r[8]_i_3__40_n_0
    SLICE_X71Y174        LUT5 (Prop_B6LUT_SLICEL_I0_O)
                                                      0.148     7.116 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/gcc_wr_ptr/reg_A[0][31]_i_13/O
                         net (fo=2, routed)           0.045     7.161    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[8].wave_fifo_inst/gcc_wr_ptr/c_fifo_wave_push_r_reg[0][2]
    SLICE_X71Y174        LUT5 (Prop_A6LUT_SLICEL_I3_O)
                                                      0.050     7.211 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[8].wave_fifo_inst/gcc_wr_ptr/reg_A[0][31]_i_3/O
                         net (fo=10, routed)          0.263     7.474    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[8].wave_fifo_inst/gcc_wr_ptr/clr_fifo_req_reg
    SLICE_X71Y158        LUT5 (Prop_A6LUT_SLICEL_I2_O)
                                                      0.050     7.524 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[8].wave_fifo_inst/gcc_wr_ptr/reg_A[0][31]_i_1_replica_1/O
                         net (fo=62, routed)          1.263     8.787    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/gcc_wr_ptr/FSM_sequential_core_st_reg[0]_repN_1_alias
    SLICE_X91Y212        LUT5 (Prop_A6LUT_SLICEL_I3_O)
                                                      0.098     8.885 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/gcc_wr_ptr/RAM_reg_0_i_1__8/O
                         net (fo=24, routed)          0.518     9.403    d_1_i/qick_processor_0/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/do_push
    RAMB36_X9Y44         RAMB36E2                                     r  d_1_i/qick_processor_0/WAVE_FIFO[11].wave_fifo_inst/fifo_mem/RAM_reg_0/WEBWE[1]
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      5.000     5.000 r  
    PS8_X0Y0             PS8                          0.000     5.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     5.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     5.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=48236, routed)       1.931     7.113    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     7.743 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     7.958    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y133        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     7.982 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=4540, routed)        2.401    10.383    d_1_i/qick_processor_0/c_clk_i
    RAMB36_X9Y44         RAMB36E2                                     r  d_1_i/qick_processor_0/WAVE_FIFO[11].wave_fifo_inst/fifo_mem/RAM_reg_0/CLKBWRCLK
                         clock pessimism             -0.263    10.120    
                         clock uncertainty           -0.062    10.058    
    RAMB36_X9Y44         RAMB36E2 (Setup_RAMB36E2_RAMB36_CLKBWRCLK_WEBWE[1])
                                                     -0.394     9.664    d_1_i/qick_processor_0/WAVE_FIFO[11].wave_fifo_inst/fifo_mem/RAM_reg_0
  -------------------------------------------------------------------
                         required time                          9.664    
                         arrival time                          -9.403    
  -------------------------------------------------------------------
                         slack                                  0.262    

Slack (MET) :             0.268ns  (required time - arrival time)
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/gcc_wr_ptr/count_gray_r_reg[4]/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/WAVE_FIFO[11].wave_fifo_inst/fifo_mem/RAM_reg_0/WEBWE[0]
                            (rising edge-triggered cell RAMB36E2 clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             clk_out1_d_1_clk_core_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            5.000ns  (clk_out1_d_1_clk_core_0 rise@5.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        4.233ns  (logic 0.576ns (13.607%)  route 3.657ns (86.393%))
  Logic Levels:           5  (LUT5=4 LUT6=1)
  Clock Path Skew:        -0.043ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.383ns = ( 10.383 - 5.000 ) 
    Source Clock Delay      (SCD):    5.163ns
    Clock Pessimism Removal (CPR):    -0.263ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.102ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.649ns (routing 1.461ns, distribution 1.188ns)
  Clock Net Delay (Destination): 2.401ns (routing 1.325ns, distribution 1.076ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=48236, routed)       2.142     2.368    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.241 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.486    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y133        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.514 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=4540, routed)        2.649     5.163    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/gcc_wr_ptr/c_clk_i
    SLICE_X91Y235        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/gcc_wr_ptr/count_gray_r_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X91Y235        FDCE (Prop_AFF2_SLICEL_C_Q)
                                                      0.081     5.244 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/gcc_wr_ptr/count_gray_r_reg[4]/Q
                         net (fo=8, routed)           0.788     6.032    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/gcc_wr_ptr/wr_gptr_p1[4]
    SLICE_X80Y235        LUT6 (Prop_A6LUT_SLICEL_I2_O)
                                                      0.149     6.181 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/gcc_wr_ptr/count_gray_r[8]_i_3__40/O
                         net (fo=3, routed)           0.787     6.968    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/gcc_wr_ptr/count_gray_r[8]_i_3__40_n_0
    SLICE_X71Y174        LUT5 (Prop_B6LUT_SLICEL_I0_O)
                                                      0.148     7.116 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/gcc_wr_ptr/reg_A[0][31]_i_13/O
                         net (fo=2, routed)           0.045     7.161    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[8].wave_fifo_inst/gcc_wr_ptr/c_fifo_wave_push_r_reg[0][2]
    SLICE_X71Y174        LUT5 (Prop_A6LUT_SLICEL_I3_O)
                                                      0.050     7.211 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[8].wave_fifo_inst/gcc_wr_ptr/reg_A[0][31]_i_3/O
                         net (fo=10, routed)          0.263     7.474    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[8].wave_fifo_inst/gcc_wr_ptr/clr_fifo_req_reg
    SLICE_X71Y158        LUT5 (Prop_A6LUT_SLICEL_I2_O)
                                                      0.050     7.524 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[8].wave_fifo_inst/gcc_wr_ptr/reg_A[0][31]_i_1_replica_1/O
                         net (fo=62, routed)          1.263     8.787    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/gcc_wr_ptr/FSM_sequential_core_st_reg[0]_repN_1_alias
    SLICE_X91Y212        LUT5 (Prop_A6LUT_SLICEL_I3_O)
                                                      0.098     8.885 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/gcc_wr_ptr/RAM_reg_0_i_1__8/O
                         net (fo=24, routed)          0.512     9.396    d_1_i/qick_processor_0/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/do_push
    RAMB36_X9Y44         RAMB36E2                                     r  d_1_i/qick_processor_0/WAVE_FIFO[11].wave_fifo_inst/fifo_mem/RAM_reg_0/WEBWE[0]
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      5.000     5.000 r  
    PS8_X0Y0             PS8                          0.000     5.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     5.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     5.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=48236, routed)       1.931     7.113    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     7.743 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     7.958    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y133        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     7.982 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=4540, routed)        2.401    10.383    d_1_i/qick_processor_0/c_clk_i
    RAMB36_X9Y44         RAMB36E2                                     r  d_1_i/qick_processor_0/WAVE_FIFO[11].wave_fifo_inst/fifo_mem/RAM_reg_0/CLKBWRCLK
                         clock pessimism             -0.263    10.120    
                         clock uncertainty           -0.062    10.058    
    RAMB36_X9Y44         RAMB36E2 (Setup_RAMB36E2_RAMB36_CLKBWRCLK_WEBWE[0])
                                                     -0.394     9.664    d_1_i/qick_processor_0/WAVE_FIFO[11].wave_fifo_inst/fifo_mem/RAM_reg_0
  -------------------------------------------------------------------
                         required time                          9.664    
                         arrival time                          -9.396    
  -------------------------------------------------------------------
                         slack                                  0.268    

Slack (MET) :             0.271ns  (required time - arrival time)
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/gcc_wr_ptr/count_gray_r_reg[4]/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/WAVE_FIFO[11].wave_fifo_inst/fifo_mem/RAM_reg_0/WEBWE[2]
                            (rising edge-triggered cell RAMB36E2 clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             clk_out1_d_1_clk_core_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            5.000ns  (clk_out1_d_1_clk_core_0 rise@5.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        4.231ns  (logic 0.576ns (13.615%)  route 3.655ns (86.385%))
  Logic Levels:           5  (LUT5=4 LUT6=1)
  Clock Path Skew:        -0.043ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.383ns = ( 10.383 - 5.000 ) 
    Source Clock Delay      (SCD):    5.163ns
    Clock Pessimism Removal (CPR):    -0.263ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.102ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.649ns (routing 1.461ns, distribution 1.188ns)
  Clock Net Delay (Destination): 2.401ns (routing 1.325ns, distribution 1.076ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=48236, routed)       2.142     2.368    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.241 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.486    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y133        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.514 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=4540, routed)        2.649     5.163    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/gcc_wr_ptr/c_clk_i
    SLICE_X91Y235        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/gcc_wr_ptr/count_gray_r_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X91Y235        FDCE (Prop_AFF2_SLICEL_C_Q)
                                                      0.081     5.244 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/gcc_wr_ptr/count_gray_r_reg[4]/Q
                         net (fo=8, routed)           0.788     6.032    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/gcc_wr_ptr/wr_gptr_p1[4]
    SLICE_X80Y235        LUT6 (Prop_A6LUT_SLICEL_I2_O)
                                                      0.149     6.181 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/gcc_wr_ptr/count_gray_r[8]_i_3__40/O
                         net (fo=3, routed)           0.787     6.968    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/gcc_wr_ptr/count_gray_r[8]_i_3__40_n_0
    SLICE_X71Y174        LUT5 (Prop_B6LUT_SLICEL_I0_O)
                                                      0.148     7.116 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/gcc_wr_ptr/reg_A[0][31]_i_13/O
                         net (fo=2, routed)           0.045     7.161    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[8].wave_fifo_inst/gcc_wr_ptr/c_fifo_wave_push_r_reg[0][2]
    SLICE_X71Y174        LUT5 (Prop_A6LUT_SLICEL_I3_O)
                                                      0.050     7.211 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[8].wave_fifo_inst/gcc_wr_ptr/reg_A[0][31]_i_3/O
                         net (fo=10, routed)          0.263     7.474    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[8].wave_fifo_inst/gcc_wr_ptr/clr_fifo_req_reg
    SLICE_X71Y158        LUT5 (Prop_A6LUT_SLICEL_I2_O)
                                                      0.050     7.524 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[8].wave_fifo_inst/gcc_wr_ptr/reg_A[0][31]_i_1_replica_1/O
                         net (fo=62, routed)          1.263     8.787    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/gcc_wr_ptr/FSM_sequential_core_st_reg[0]_repN_1_alias
    SLICE_X91Y212        LUT5 (Prop_A6LUT_SLICEL_I3_O)
                                                      0.098     8.885 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/gcc_wr_ptr/RAM_reg_0_i_1__8/O
                         net (fo=24, routed)          0.509     9.394    d_1_i/qick_processor_0/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/do_push
    RAMB36_X9Y44         RAMB36E2                                     r  d_1_i/qick_processor_0/WAVE_FIFO[11].wave_fifo_inst/fifo_mem/RAM_reg_0/WEBWE[2]
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      5.000     5.000 r  
    PS8_X0Y0             PS8                          0.000     5.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     5.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     5.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=48236, routed)       1.931     7.113    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     7.743 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     7.958    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y133        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     7.982 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=4540, routed)        2.401    10.383    d_1_i/qick_processor_0/c_clk_i
    RAMB36_X9Y44         RAMB36E2                                     r  d_1_i/qick_processor_0/WAVE_FIFO[11].wave_fifo_inst/fifo_mem/RAM_reg_0/CLKBWRCLK
                         clock pessimism             -0.263    10.120    
                         clock uncertainty           -0.062    10.058    
    RAMB36_X9Y44         RAMB36E2 (Setup_RAMB36E2_RAMB36_CLKBWRCLK_WEBWE[2])
                                                     -0.394     9.664    d_1_i/qick_processor_0/WAVE_FIFO[11].wave_fifo_inst/fifo_mem/RAM_reg_0
  -------------------------------------------------------------------
                         required time                          9.664    
                         arrival time                          -9.394    
  -------------------------------------------------------------------
                         slack                                  0.271    

Slack (MET) :             0.298ns  (required time - arrival time)
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/gcc_wr_ptr/count_gray_r_reg[4]/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/WAVE_FIFO[11].wave_fifo_inst/fifo_mem/RAM_reg_1/WEBWE[2]
                            (rising edge-triggered cell RAMB36E2 clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             clk_out1_d_1_clk_core_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            5.000ns  (clk_out1_d_1_clk_core_0 rise@5.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        4.198ns  (logic 0.576ns (13.721%)  route 3.622ns (86.279%))
  Logic Levels:           5  (LUT5=4 LUT6=1)
  Clock Path Skew:        -0.049ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.377ns = ( 10.377 - 5.000 ) 
    Source Clock Delay      (SCD):    5.163ns
    Clock Pessimism Removal (CPR):    -0.263ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.102ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.649ns (routing 1.461ns, distribution 1.188ns)
  Clock Net Delay (Destination): 2.395ns (routing 1.325ns, distribution 1.070ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=48236, routed)       2.142     2.368    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.241 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.486    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y133        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.514 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=4540, routed)        2.649     5.163    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/gcc_wr_ptr/c_clk_i
    SLICE_X91Y235        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/gcc_wr_ptr/count_gray_r_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X91Y235        FDCE (Prop_AFF2_SLICEL_C_Q)
                                                      0.081     5.244 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/gcc_wr_ptr/count_gray_r_reg[4]/Q
                         net (fo=8, routed)           0.788     6.032    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/gcc_wr_ptr/wr_gptr_p1[4]
    SLICE_X80Y235        LUT6 (Prop_A6LUT_SLICEL_I2_O)
                                                      0.149     6.181 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/gcc_wr_ptr/count_gray_r[8]_i_3__40/O
                         net (fo=3, routed)           0.787     6.968    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/gcc_wr_ptr/count_gray_r[8]_i_3__40_n_0
    SLICE_X71Y174        LUT5 (Prop_B6LUT_SLICEL_I0_O)
                                                      0.148     7.116 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/gcc_wr_ptr/reg_A[0][31]_i_13/O
                         net (fo=2, routed)           0.045     7.161    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[8].wave_fifo_inst/gcc_wr_ptr/c_fifo_wave_push_r_reg[0][2]
    SLICE_X71Y174        LUT5 (Prop_A6LUT_SLICEL_I3_O)
                                                      0.050     7.211 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[8].wave_fifo_inst/gcc_wr_ptr/reg_A[0][31]_i_3/O
                         net (fo=10, routed)          0.263     7.474    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[8].wave_fifo_inst/gcc_wr_ptr/clr_fifo_req_reg
    SLICE_X71Y158        LUT5 (Prop_A6LUT_SLICEL_I2_O)
                                                      0.050     7.524 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[8].wave_fifo_inst/gcc_wr_ptr/reg_A[0][31]_i_1_replica_1/O
                         net (fo=62, routed)          1.263     8.787    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/gcc_wr_ptr/FSM_sequential_core_st_reg[0]_repN_1_alias
    SLICE_X91Y212        LUT5 (Prop_A6LUT_SLICEL_I3_O)
                                                      0.098     8.885 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/gcc_wr_ptr/RAM_reg_0_i_1__8/O
                         net (fo=24, routed)          0.476     9.361    d_1_i/qick_processor_0/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/do_push
    RAMB36_X9Y43         RAMB36E2                                     r  d_1_i/qick_processor_0/WAVE_FIFO[11].wave_fifo_inst/fifo_mem/RAM_reg_1/WEBWE[2]
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      5.000     5.000 r  
    PS8_X0Y0             PS8                          0.000     5.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     5.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     5.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=48236, routed)       1.931     7.113    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     7.743 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     7.958    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y133        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     7.982 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=4540, routed)        2.395    10.377    d_1_i/qick_processor_0/c_clk_i
    RAMB36_X9Y43         RAMB36E2                                     r  d_1_i/qick_processor_0/WAVE_FIFO[11].wave_fifo_inst/fifo_mem/RAM_reg_1/CLKBWRCLK
                         clock pessimism             -0.263    10.114    
                         clock uncertainty           -0.062    10.052    
    RAMB36_X9Y43         RAMB36E2 (Setup_RAMB36E2_RAMB36_CLKBWRCLK_WEBWE[2])
                                                     -0.394     9.658    d_1_i/qick_processor_0/WAVE_FIFO[11].wave_fifo_inst/fifo_mem/RAM_reg_1
  -------------------------------------------------------------------
                         required time                          9.658    
                         arrival time                          -9.361    
  -------------------------------------------------------------------
                         slack                                  0.298    

Slack (MET) :             0.299ns  (required time - arrival time)
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/gcc_wr_ptr/count_gray_r_reg[4]/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_2/CASDOMUXEN_B
                            (rising edge-triggered cell RAMB36E2 clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             clk_out1_d_1_clk_core_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            5.000ns  (clk_out1_d_1_clk_core_0 rise@5.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        4.423ns  (logic 0.516ns (11.666%)  route 3.907ns (88.334%))
  Logic Levels:           5  (LUT4=1 LUT5=3 LUT6=1)
  Clock Path Skew:        -0.117ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.378ns = ( 10.378 - 5.000 ) 
    Source Clock Delay      (SCD):    5.163ns
    Clock Pessimism Removal (CPR):    -0.332ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.102ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.649ns (routing 1.461ns, distribution 1.188ns)
  Clock Net Delay (Destination): 2.396ns (routing 1.325ns, distribution 1.071ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=48236, routed)       2.142     2.368    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.241 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.486    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y133        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.514 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=4540, routed)        2.649     5.163    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/gcc_wr_ptr/c_clk_i
    SLICE_X91Y235        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/gcc_wr_ptr/count_gray_r_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X91Y235        FDCE (Prop_AFF2_SLICEL_C_Q)
                                                      0.081     5.244 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/gcc_wr_ptr/count_gray_r_reg[4]/Q
                         net (fo=8, routed)           0.788     6.032    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/gcc_wr_ptr/wr_gptr_p1[4]
    SLICE_X80Y235        LUT6 (Prop_A6LUT_SLICEL_I2_O)
                                                      0.149     6.181 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/gcc_wr_ptr/count_gray_r[8]_i_3__40/O
                         net (fo=3, routed)           0.787     6.968    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/gcc_wr_ptr/count_gray_r[8]_i_3__40_n_0
    SLICE_X71Y174        LUT5 (Prop_B6LUT_SLICEL_I0_O)
                                                      0.148     7.116 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/gcc_wr_ptr/reg_A[0][31]_i_13/O
                         net (fo=2, routed)           0.045     7.161    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[8].wave_fifo_inst/gcc_wr_ptr/c_fifo_wave_push_r_reg[0][2]
    SLICE_X71Y174        LUT5 (Prop_A6LUT_SLICEL_I3_O)
                                                      0.050     7.211 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[8].wave_fifo_inst/gcc_wr_ptr/reg_A[0][31]_i_3/O
                         net (fo=10, routed)          0.414     7.625    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[8].wave_fifo_inst/gcc_wr_ptr/clr_fifo_req_reg
    SLICE_X62Y156        LUT5 (Prop_B6LUT_SLICEL_I2_O)
                                                      0.036     7.661 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[8].wave_fifo_inst/gcc_wr_ptr/reg_A[0][31]_i_1_replica_2/O
                         net (fo=474, routed)         0.609     8.270    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/FSM_sequential_core_st_reg[0]_repN_2_alias
    SLICE_X66Y140        LUT4 (Prop_G6LUT_SLICEM_I2_O)
                                                      0.052     8.322 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_1_CASDOMUXEN_B_cooolgate_en_gate_1678/O
                         net (fo=11, routed)          1.264     9.586    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_1_CASDOMUXEN_B_cooolgate_en_sig_821
    RAMB36_X3Y22         RAMB36E2                                     r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_2/CASDOMUXEN_B
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      5.000     5.000 r  
    PS8_X0Y0             PS8                          0.000     5.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     5.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     5.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=48236, routed)       1.931     7.113    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     7.743 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     7.958    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y133        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     7.982 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=4540, routed)        2.396    10.378    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/c_clk_i
    RAMB36_X3Y22         RAMB36E2                                     r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_2/CLKBWRCLK
                         clock pessimism             -0.332    10.046    
                         clock uncertainty           -0.062     9.984    
    RAMB36_X3Y22         RAMB36E2 (Setup_RAMB36E2_RAMB36_CLKBWRCLK_CASDOMUXEN_B)
                                                     -0.099     9.885    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_2
  -------------------------------------------------------------------
                         required time                          9.885    
                         arrival time                          -9.586    
  -------------------------------------------------------------------
                         slack                                  0.299    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.009ns  (arrival time - required time)
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[8].trig_fifo_inst/gcc_wr_ptr/count_gray_r_reg[0]/C
                            (rising edge-triggered cell FDPE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[8].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[0]/D
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             clk_out1_d_1_clk_core_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_core_0 rise@0.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        0.197ns  (logic 0.090ns (45.666%)  route 0.107ns (54.334%))
  Logic Levels:           1  (LUT2=1)
  Clock Path Skew:        0.126ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    5.182ns
    Source Clock Delay      (SCD):    5.323ns
    Clock Pessimism Removal (CPR):    -0.267ns
  Clock Net Delay (Source):      2.341ns (routing 1.325ns, distribution 1.016ns)
  Clock Net Delay (Destination): 2.668ns (routing 1.461ns, distribution 1.207ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=48236, routed)       1.931     2.113    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.743 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.958    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y133        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.982 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=4540, routed)        2.341     5.323    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[8].trig_fifo_inst/gcc_wr_ptr/c_clk_i
    SLICE_X52Y190        FDPE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[8].trig_fifo_inst/gcc_wr_ptr/count_gray_r_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X52Y190        FDPE (Prop_CFF_SLICEL_C_Q)
                                                      0.058     5.381 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[8].trig_fifo_inst/gcc_wr_ptr/count_gray_r_reg[0]/Q
                         net (fo=8, routed)           0.098     5.479    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[8].trig_fifo_inst/gcc_wr_ptr/wr_gptr_p1[0]
    SLICE_X52Y192        LUT2 (Prop_D5LUT_SLICEL_I0_O)
                                                      0.032     5.511 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[8].trig_fifo_inst/gcc_wr_ptr/count_gray_2r[0]_i_1__15/O
                         net (fo=1, routed)           0.009     5.520    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[8].trig_fifo_inst/gcc_wr_ptr/count_gray_2r[0]_i_1__15_n_0
    SLICE_X52Y192        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[8].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=48236, routed)       2.142     2.368    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.241 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.486    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y133        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.514 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=4540, routed)        2.668     5.182    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[8].trig_fifo_inst/gcc_wr_ptr/c_clk_i
    SLICE_X52Y192        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[8].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[0]/C
                         clock pessimism              0.267     5.449    
    SLICE_X52Y192        FDCE (Hold_DFF2_SLICEL_C_D)
                                                      0.062     5.511    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[8].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[0]
  -------------------------------------------------------------------
                         required time                         -5.511    
                         arrival time                           5.520    
  -------------------------------------------------------------------
                         slack                                  0.009    

Slack (MET) :             0.013ns  (arrival time - required time)
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[8].trig_fifo_inst/gcc_wr_ptr/count_gray_r_reg[1]/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[8].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[1]/D
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             clk_out1_d_1_clk_core_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_core_0 rise@0.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        0.199ns  (logic 0.116ns (58.182%)  route 0.083ns (41.818%))
  Logic Levels:           1  (LUT2=1)
  Clock Path Skew:        0.126ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    5.182ns
    Source Clock Delay      (SCD):    5.323ns
    Clock Pessimism Removal (CPR):    -0.267ns
  Clock Net Delay (Source):      2.341ns (routing 1.325ns, distribution 1.016ns)
  Clock Net Delay (Destination): 2.668ns (routing 1.461ns, distribution 1.207ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=48236, routed)       1.931     2.113    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.743 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.958    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y133        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.982 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=4540, routed)        2.341     5.323    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[8].trig_fifo_inst/gcc_wr_ptr/c_clk_i
    SLICE_X52Y190        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[8].trig_fifo_inst/gcc_wr_ptr/count_gray_r_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X52Y190        FDCE (Prop_BFF_SLICEL_C_Q)
                                                      0.059     5.382 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[8].trig_fifo_inst/gcc_wr_ptr/count_gray_r_reg[1]/Q
                         net (fo=9, routed)           0.061     5.443    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[8].trig_fifo_inst/gcc_wr_ptr/wr_gptr_p1[1]
    SLICE_X52Y192        LUT2 (Prop_D6LUT_SLICEL_I0_O)
                                                      0.057     5.500 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[8].trig_fifo_inst/gcc_wr_ptr/count_gray_2r[1]_i_1__15/O
                         net (fo=1, routed)           0.022     5.522    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[8].trig_fifo_inst/gcc_wr_ptr/count_gray_2r[1]_i_1__15_n_0
    SLICE_X52Y192        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[8].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=48236, routed)       2.142     2.368    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.241 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.486    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y133        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.514 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=4540, routed)        2.668     5.182    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[8].trig_fifo_inst/gcc_wr_ptr/c_clk_i
    SLICE_X52Y192        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[8].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[1]/C
                         clock pessimism              0.267     5.449    
    SLICE_X52Y192        FDCE (Hold_DFF_SLICEL_C_D)
                                                      0.060     5.509    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[8].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[1]
  -------------------------------------------------------------------
                         required time                         -5.509    
                         arrival time                           5.522    
  -------------------------------------------------------------------
                         slack                                  0.013    

Slack (MET) :             0.017ns  (arrival time - required time)
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[8].trig_fifo_inst/gcc_wr_ptr/count_gray_r_reg[5]/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[8].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[5]/D
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             clk_out1_d_1_clk_core_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_core_0 rise@0.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        0.205ns  (logic 0.116ns (56.624%)  route 0.089ns (43.377%))
  Logic Levels:           1  (LUT2=1)
  Clock Path Skew:        0.128ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    5.182ns
    Source Clock Delay      (SCD):    5.321ns
    Clock Pessimism Removal (CPR):    -0.267ns
  Clock Net Delay (Source):      2.339ns (routing 1.325ns, distribution 1.014ns)
  Clock Net Delay (Destination): 2.668ns (routing 1.461ns, distribution 1.207ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=48236, routed)       1.931     2.113    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.743 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.958    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y133        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.982 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=4540, routed)        2.339     5.321    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[8].trig_fifo_inst/gcc_wr_ptr/c_clk_i
    SLICE_X53Y192        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[8].trig_fifo_inst/gcc_wr_ptr/count_gray_r_reg[5]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X53Y192        FDCE (Prop_CFF_SLICEM_C_Q)
                                                      0.058     5.379 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[8].trig_fifo_inst/gcc_wr_ptr/count_gray_r_reg[5]/Q
                         net (fo=6, routed)           0.067     5.445    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[8].trig_fifo_inst/gcc_wr_ptr/wr_gptr_p1[5]
    SLICE_X52Y192        LUT2 (Prop_B6LUT_SLICEL_I0_O)
                                                      0.058     5.503 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[8].trig_fifo_inst/gcc_wr_ptr/count_gray_2r[5]_i_1__15/O
                         net (fo=1, routed)           0.022     5.525    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[8].trig_fifo_inst/gcc_wr_ptr/count_gray_2r[5]_i_1__15_n_0
    SLICE_X52Y192        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[8].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[5]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=48236, routed)       2.142     2.368    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.241 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.486    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y133        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.514 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=4540, routed)        2.668     5.182    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[8].trig_fifo_inst/gcc_wr_ptr/c_clk_i
    SLICE_X52Y192        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[8].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[5]/C
                         clock pessimism              0.267     5.449    
    SLICE_X52Y192        FDCE (Hold_BFF_SLICEL_C_D)
                                                      0.060     5.509    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[8].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[5]
  -------------------------------------------------------------------
                         required time                         -5.509    
                         arrival time                           5.525    
  -------------------------------------------------------------------
                         slack                                  0.017    

Slack (MET) :             0.018ns  (arrival time - required time)
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[11].trig_fifo_inst/gcc_wr_ptr/count_gray_r_reg[6]/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[11].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[6]/D
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             clk_out1_d_1_clk_core_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_core_0 rise@0.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        0.291ns  (logic 0.153ns (52.626%)  route 0.138ns (47.374%))
  Logic Levels:           1  (LUT2=1)
  Clock Path Skew:        0.212ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    5.240ns
    Source Clock Delay      (SCD):    5.295ns
    Clock Pessimism Removal (CPR):    -0.267ns
  Clock Net Delay (Source):      2.313ns (routing 1.325ns, distribution 0.988ns)
  Clock Net Delay (Destination): 2.726ns (routing 1.461ns, distribution 1.265ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=48236, routed)       1.931     2.113    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.743 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.958    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y133        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.982 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=4540, routed)        2.313     5.295    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[11].trig_fifo_inst/gcc_wr_ptr/c_clk_i
    SLICE_X54Y205        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[11].trig_fifo_inst/gcc_wr_ptr/count_gray_r_reg[6]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X54Y205        FDCE (Prop_HFF_SLICEM_C_Q)
                                                      0.058     5.353 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[11].trig_fifo_inst/gcc_wr_ptr/count_gray_r_reg[6]/Q
                         net (fo=9, routed)           0.116     5.469    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[11].trig_fifo_inst/gcc_wr_ptr/wr_gptr_p1[6]
    SLICE_X57Y206        LUT2 (Prop_G6LUT_SLICEL_I0_O)
                                                      0.095     5.564 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[11].trig_fifo_inst/gcc_wr_ptr/count_gray_2r[6]_i_1__21/O
                         net (fo=1, routed)           0.022     5.586    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[11].trig_fifo_inst/gcc_wr_ptr/count_gray_2r[6]_i_1__21_n_0
    SLICE_X57Y206        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[11].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[6]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=48236, routed)       2.142     2.368    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.241 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.486    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y133        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.514 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=4540, routed)        2.726     5.240    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[11].trig_fifo_inst/gcc_wr_ptr/c_clk_i
    SLICE_X57Y206        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[11].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[6]/C
                         clock pessimism              0.267     5.507    
    SLICE_X57Y206        FDCE (Hold_GFF_SLICEL_C_D)
                                                      0.060     5.567    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[11].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[6]
  -------------------------------------------------------------------
                         required time                         -5.567    
                         arrival time                           5.586    
  -------------------------------------------------------------------
                         slack                                  0.018    

Slack (MET) :             0.019ns  (arrival time - required time)
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[6].wave_fifo_inst/clr_fifo_req_reg/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[6].wave_fifo_inst/gcc_wr_ptr/clear_cdc_reg/D
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             clk_out1_d_1_clk_core_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_core_0 rise@0.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        0.275ns  (logic 0.061ns (22.200%)  route 0.214ns (77.800%))
  Logic Levels:           0  
  Clock Path Skew:        0.193ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    5.157ns
    Source Clock Delay      (SCD):    5.236ns
    Clock Pessimism Removal (CPR):    -0.272ns
  Clock Net Delay (Source):      2.254ns (routing 1.325ns, distribution 0.929ns)
  Clock Net Delay (Destination): 2.643ns (routing 1.461ns, distribution 1.182ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=48236, routed)       1.931     2.113    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.743 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.958    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y133        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.982 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=4540, routed)        2.254     5.236    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[6].wave_fifo_inst/c_clk_i
    SLICE_X62Y200        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[6].wave_fifo_inst/clr_fifo_req_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X62Y200        FDCE (Prop_DFF2_SLICEL_C_Q)
                                                      0.061     5.297 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[6].wave_fifo_inst/clr_fifo_req_reg/Q
                         net (fo=5, routed)           0.214     5.510    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[6].wave_fifo_inst/gcc_wr_ptr/clr_fifo_req
    SLICE_X58Y201        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[6].wave_fifo_inst/gcc_wr_ptr/clear_cdc_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=48236, routed)       2.142     2.368    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.241 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.486    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y133        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.514 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=4540, routed)        2.643     5.157    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[6].wave_fifo_inst/gcc_wr_ptr/c_clk_i
    SLICE_X58Y201        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[6].wave_fifo_inst/gcc_wr_ptr/clear_cdc_reg/C
                         clock pessimism              0.272     5.429    
    SLICE_X58Y201        FDCE (Hold_HFF2_SLICEL_C_D)
                                                      0.062     5.491    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[6].wave_fifo_inst/gcc_wr_ptr/clear_cdc_reg
  -------------------------------------------------------------------
                         required time                         -5.491    
                         arrival time                           5.510    
  -------------------------------------------------------------------
                         slack                                  0.019    

Slack (MET) :             0.020ns  (arrival time - required time)
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[8].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[2]/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[8].trig_fifo_inst/fifo_mem/RAM_reg/ADDRBWRADDR[8]
                            (rising edge-triggered cell RAMB36E2 clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             clk_out1_d_1_clk_core_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_core_0 rise@0.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        0.323ns  (logic 0.058ns (17.952%)  route 0.265ns (82.048%))
  Logic Levels:           0  
  Clock Path Skew:        0.348ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    5.450ns
    Source Clock Delay      (SCD):    5.366ns
    Clock Pessimism Removal (CPR):    -0.264ns
  Clock Net Delay (Source):      2.384ns (routing 1.325ns, distribution 1.059ns)
  Clock Net Delay (Destination): 2.936ns (routing 1.461ns, distribution 1.475ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=48236, routed)       1.931     2.113    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.743 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.958    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y133        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.982 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=4540, routed)        2.384     5.366    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[8].trig_fifo_inst/gcc_wr_ptr/c_clk_i
    SLICE_X52Y192        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[8].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X52Y192        FDCE (Prop_CFF_SLICEL_C_Q)
                                                      0.058     5.424 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[8].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[2]/Q
                         net (fo=2, routed)           0.265     5.689    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[8].trig_fifo_inst/fifo_mem/RAM_reg_1[2]
    RAMB36_X5Y42         RAMB36E2                                     r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[8].trig_fifo_inst/fifo_mem/RAM_reg/ADDRBWRADDR[8]
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=48236, routed)       2.142     2.368    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.241 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.486    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y133        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.514 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=4540, routed)        2.936     5.450    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[8].trig_fifo_inst/fifo_mem/c_clk_i
    RAMB36_X5Y42         RAMB36E2                                     r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[8].trig_fifo_inst/fifo_mem/RAM_reg/CLKBWRCLK
                         clock pessimism              0.264     5.714    
    RAMB36_X5Y42         RAMB36E2 (Hold_RAMB36E2_RAMB36_CLKBWRCLK_ADDRBWRADDR[8])
                                                     -0.045     5.669    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[8].trig_fifo_inst/fifo_mem/RAM_reg
  -------------------------------------------------------------------
                         required time                         -5.669    
                         arrival time                           5.689    
  -------------------------------------------------------------------
                         slack                                  0.020    

Slack (MET) :             0.020ns  (arrival time - required time)
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[0].wave_fifo_inst/gcc_wr_ptr/count_gray_r_reg[6]/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[0].wave_fifo_inst/gcc_wr_ptr/count_gray_r_reg[7]/D
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             clk_out1_d_1_clk_core_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_core_0 rise@0.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        0.211ns  (logic 0.115ns (54.575%)  route 0.096ns (45.425%))
  Logic Levels:           1  (LUT5=1)
  Clock Path Skew:        0.131ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    5.098ns
    Source Clock Delay      (SCD):    5.242ns
    Clock Pessimism Removal (CPR):    -0.275ns
  Clock Net Delay (Source):      2.260ns (routing 1.325ns, distribution 0.935ns)
  Clock Net Delay (Destination): 2.584ns (routing 1.461ns, distribution 1.123ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=48236, routed)       1.931     2.113    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.743 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.958    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y133        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.982 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=4540, routed)        2.260     5.242    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[0].wave_fifo_inst/gcc_wr_ptr/c_clk_i
    SLICE_X66Y187        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[0].wave_fifo_inst/gcc_wr_ptr/count_gray_r_reg[6]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X66Y187        FDCE (Prop_GFF_SLICEM_C_Q)
                                                      0.058     5.300 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[0].wave_fifo_inst/gcc_wr_ptr/count_gray_r_reg[6]/Q
                         net (fo=9, routed)           0.074     5.374    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[0].wave_fifo_inst/gcc_wr_ptr/wr_gptr_p1[6]
    SLICE_X65Y187        LUT5 (Prop_G6LUT_SLICEL_I1_O)
                                                      0.057     5.431 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[0].wave_fifo_inst/gcc_wr_ptr/count_gray_r[7]_i_1__27/O
                         net (fo=1, routed)           0.022     5.453    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[0].wave_fifo_inst/gcc_wr_ptr/p_0_in[7]
    SLICE_X65Y187        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[0].wave_fifo_inst/gcc_wr_ptr/count_gray_r_reg[7]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=48236, routed)       2.142     2.368    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.241 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.486    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y133        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.514 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=4540, routed)        2.584     5.098    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[0].wave_fifo_inst/gcc_wr_ptr/c_clk_i
    SLICE_X65Y187        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[0].wave_fifo_inst/gcc_wr_ptr/count_gray_r_reg[7]/C
                         clock pessimism              0.275     5.373    
    SLICE_X65Y187        FDCE (Hold_GFF_SLICEL_C_D)
                                                      0.060     5.433    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[0].wave_fifo_inst/gcc_wr_ptr/count_gray_r_reg[7]
  -------------------------------------------------------------------
                         required time                         -5.433    
                         arrival time                           5.453    
  -------------------------------------------------------------------
                         slack                                  0.020    

Slack (MET) :             0.020ns  (arrival time - required time)
  Source:                 d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_doutb_pipe.gen_stage.doutb_pipe_reg[0][59]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/IN_PORT_REG/genblk1[1].port_dt_r_reg[1][59]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             clk_out1_d_1_clk_core_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_core_0 rise@0.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        0.236ns  (logic 0.059ns (25.000%)  route 0.177ns (75.000%))
  Logic Levels:           0  
  Clock Path Skew:        0.156ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    5.107ns
    Source Clock Delay      (SCD):    5.227ns
    Clock Pessimism Removal (CPR):    -0.275ns
  Clock Net Delay (Source):      2.245ns (routing 1.325ns, distribution 0.920ns)
  Clock Net Delay (Destination): 2.593ns (routing 1.461ns, distribution 1.132ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=48236, routed)       1.931     2.113    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.743 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.958    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y133        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.982 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=4540, routed)        2.245     5.227    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X62Y125        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_doutb_pipe.gen_stage.doutb_pipe_reg[0][59]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X62Y125        FDRE (Prop_CFF2_SLICEL_C_Q)
                                                      0.059     5.286 r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_doutb_pipe.gen_stage.doutb_pipe_reg[0][59]/Q
                         net (fo=1, routed)           0.177     5.463    d_1_i/qick_processor_0/inst/QPROC/IN_PORT_REG/s1_axis_tdata[59]
    SLICE_X59Y128        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/IN_PORT_REG/genblk1[1].port_dt_r_reg[1][59]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=48236, routed)       2.142     2.368    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.241 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.486    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y133        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.514 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=4540, routed)        2.593     5.107    d_1_i/qick_processor_0/inst/QPROC/IN_PORT_REG/c_clk_i
    SLICE_X59Y128        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/IN_PORT_REG/genblk1[1].port_dt_r_reg[1][59]/C
                         clock pessimism              0.275     5.382    
    SLICE_X59Y128        FDRE (Hold_BFF_SLICEL_C_D)
                                                      0.060     5.442    d_1_i/qick_processor_0/inst/QPROC/IN_PORT_REG/genblk1[1].port_dt_r_reg[1][59]
  -------------------------------------------------------------------
                         required time                         -5.442    
                         arrival time                           5.463    
  -------------------------------------------------------------------
                         slack                                  0.020    

Slack (MET) :             0.021ns  (arrival time - required time)
  Source:                 d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_doutb_pipe.gen_stage.doutb_pipe_reg[0][44]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/IN_PORT_REG/genblk1[3].port_dt_r_reg[3][44]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             clk_out1_d_1_clk_core_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_core_0 rise@0.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        0.169ns  (logic 0.059ns (34.911%)  route 0.110ns (65.089%))
  Logic Levels:           0  
  Clock Path Skew:        0.086ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    5.140ns
    Source Clock Delay      (SCD):    5.324ns
    Clock Pessimism Removal (CPR):    -0.270ns
  Clock Net Delay (Source):      2.342ns (routing 1.325ns, distribution 1.017ns)
  Clock Net Delay (Destination): 2.626ns (routing 1.461ns, distribution 1.165ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=48236, routed)       1.931     2.113    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.743 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.958    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y133        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.982 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=4540, routed)        2.342     5.324    d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X44Y164        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_doutb_pipe.gen_stage.doutb_pipe_reg[0][44]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X44Y164        FDRE (Prop_BFF_SLICEL_C_Q)
                                                      0.059     5.383 r  d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_doutb_pipe.gen_stage.doutb_pipe_reg[0][44]/Q
                         net (fo=1, routed)           0.110     5.493    d_1_i/qick_processor_0/inst/QPROC/IN_PORT_REG/s3_axis_tdata[44]
    SLICE_X45Y163        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/IN_PORT_REG/genblk1[3].port_dt_r_reg[3][44]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=48236, routed)       2.142     2.368    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.241 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.486    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y133        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.514 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=4540, routed)        2.626     5.140    d_1_i/qick_processor_0/inst/QPROC/IN_PORT_REG/c_clk_i
    SLICE_X45Y163        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/IN_PORT_REG/genblk1[3].port_dt_r_reg[3][44]/C
                         clock pessimism              0.270     5.410    
    SLICE_X45Y163        FDRE (Hold_EFF2_SLICEM_C_D)
                                                      0.062     5.472    d_1_i/qick_processor_0/inst/QPROC/IN_PORT_REG/genblk1[3].port_dt_r_reg[3][44]
  -------------------------------------------------------------------
                         required time                         -5.472    
                         arrival time                           5.493    
  -------------------------------------------------------------------
                         slack                                  0.021    

Slack (MET) :             0.021ns  (arrival time - required time)
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[0].wave_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[0]/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/WAVE_FIFO[0].wave_fifo_inst/fifo_mem/RAM_reg_0/ADDRBWRADDR[6]
                            (rising edge-triggered cell RAMB36E2 clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             clk_out1_d_1_clk_core_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_core_0 rise@0.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        0.320ns  (logic 0.061ns (19.048%)  route 0.259ns (80.952%))
  Logic Levels:           0  
  Clock Path Skew:        0.344ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    5.357ns
    Source Clock Delay      (SCD):    5.285ns
    Clock Pessimism Removal (CPR):    -0.272ns
  Clock Net Delay (Source):      2.303ns (routing 1.325ns, distribution 0.978ns)
  Clock Net Delay (Destination): 2.843ns (routing 1.461ns, distribution 1.382ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=48236, routed)       1.931     2.113    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.743 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.958    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y133        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.982 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=4540, routed)        2.303     5.285    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[0].wave_fifo_inst/gcc_wr_ptr/c_clk_i
    SLICE_X65Y188        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[0].wave_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X65Y188        FDCE (Prop_DFF2_SLICEL_C_Q)
                                                      0.061     5.346 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[0].wave_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[0]/Q
                         net (fo=4, routed)           0.259     5.605    d_1_i/qick_processor_0/inst_n_8
    RAMB36_X5Y37         RAMB36E2                                     r  d_1_i/qick_processor_0/WAVE_FIFO[0].wave_fifo_inst/fifo_mem/RAM_reg_0/ADDRBWRADDR[6]
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=48236, routed)       2.142     2.368    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.241 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.486    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y133        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.514 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=4540, routed)        2.843     5.357    d_1_i/qick_processor_0/c_clk_i
    RAMB36_X5Y37         RAMB36E2                                     r  d_1_i/qick_processor_0/WAVE_FIFO[0].wave_fifo_inst/fifo_mem/RAM_reg_0/CLKBWRCLK
                         clock pessimism              0.272     5.629    
    RAMB36_X5Y37         RAMB36E2 (Hold_RAMB36E2_RAMB36_CLKBWRCLK_ADDRBWRADDR[6])
                                                     -0.045     5.584    d_1_i/qick_processor_0/WAVE_FIFO[0].wave_fifo_inst/fifo_mem/RAM_reg_0
  -------------------------------------------------------------------
                         required time                         -5.584    
                         arrival time                           5.605    
  -------------------------------------------------------------------
                         slack                                  0.021    





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         clk_out1_d_1_clk_core_0
Waveform(ns):       { 0.000 2.500 }
Period(ns):         5.000
Sources:            { d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0 }

Check Type        Corner  Lib Pin             Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location      Pin
Min Period        n/a     RAMB36E2/CLKBWRCLK  n/a            1.569         5.000       3.431      RAMB36_X3Y20  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_0/CLKBWRCLK
Min Period        n/a     RAMB36E2/CLKBWRCLK  n/a            1.569         5.000       3.431      RAMB36_X3Y21  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_1/CLKBWRCLK
Min Period        n/a     RAMB36E2/CLKBWRCLK  n/a            1.569         5.000       3.431      RAMB36_X6Y16  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_10/CLKBWRCLK
Min Period        n/a     RAMB36E2/CLKBWRCLK  n/a            1.569         5.000       3.431      RAMB36_X6Y17  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_11/CLKBWRCLK
Min Period        n/a     RAMB36E2/CLKBWRCLK  n/a            1.569         5.000       3.431      RAMB36_X6Y12  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_12/CLKBWRCLK
Min Period        n/a     RAMB36E2/CLKBWRCLK  n/a            1.569         5.000       3.431      RAMB36_X6Y13  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_13/CLKBWRCLK
Min Period        n/a     RAMB18E2/CLKBWRCLK  n/a            1.569         5.000       3.431      RAMB18_X4Y54  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_14/CLKBWRCLK
Min Period        n/a     RAMB36E2/CLKBWRCLK  n/a            1.569         5.000       3.431      RAMB36_X3Y22  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_2/CLKBWRCLK
Min Period        n/a     RAMB36E2/CLKBWRCLK  n/a            1.569         5.000       3.431      RAMB36_X3Y23  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_3/CLKBWRCLK
Min Period        n/a     RAMB36E2/CLKBWRCLK  n/a            1.569         5.000       3.431      RAMB36_X3Y24  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_4/CLKBWRCLK
Low Pulse Width   Slow    RAMB36E2/CLKBWRCLK  n/a            0.542         2.500       1.958      RAMB36_X5Y37  d_1_i/qick_processor_0/WAVE_FIFO[0].wave_fifo_inst/fifo_mem/RAM_reg_0/CLKBWRCLK
Low Pulse Width   Fast    RAMB36E2/CLKBWRCLK  n/a            0.542         2.500       1.958      RAMB36_X5Y37  d_1_i/qick_processor_0/WAVE_FIFO[0].wave_fifo_inst/fifo_mem/RAM_reg_0/CLKBWRCLK
Low Pulse Width   Slow    RAMB36E2/CLKBWRCLK  n/a            0.542         2.500       1.958      RAMB36_X7Y41  d_1_i/qick_processor_0/WAVE_FIFO[0].wave_fifo_inst/fifo_mem/RAM_reg_1/CLKBWRCLK
Low Pulse Width   Fast    RAMB36E2/CLKBWRCLK  n/a            0.542         2.500       1.958      RAMB36_X7Y41  d_1_i/qick_processor_0/WAVE_FIFO[0].wave_fifo_inst/fifo_mem/RAM_reg_1/CLKBWRCLK
Low Pulse Width   Slow    RAMB36E2/CLKBWRCLK  n/a            0.542         2.500       1.958      RAMB36_X7Y37  d_1_i/qick_processor_0/WAVE_FIFO[0].wave_fifo_inst/fifo_mem/RAM_reg_2/CLKBWRCLK
Low Pulse Width   Fast    RAMB36E2/CLKBWRCLK  n/a            0.542         2.500       1.958      RAMB36_X7Y37  d_1_i/qick_processor_0/WAVE_FIFO[0].wave_fifo_inst/fifo_mem/RAM_reg_2/CLKBWRCLK
Low Pulse Width   Slow    RAMB36E2/CLKBWRCLK  n/a            0.542         2.500       1.958      RAMB36_X8Y36  d_1_i/qick_processor_0/WAVE_FIFO[10].wave_fifo_inst/fifo_mem/RAM_reg_0/CLKBWRCLK
Low Pulse Width   Fast    RAMB36E2/CLKBWRCLK  n/a            0.542         2.500       1.958      RAMB36_X8Y36  d_1_i/qick_processor_0/WAVE_FIFO[10].wave_fifo_inst/fifo_mem/RAM_reg_0/CLKBWRCLK
Low Pulse Width   Slow    RAMB36E2/CLKBWRCLK  n/a            0.542         2.500       1.958      RAMB36_X9Y26  d_1_i/qick_processor_0/WAVE_FIFO[10].wave_fifo_inst/fifo_mem/RAM_reg_1/CLKBWRCLK
Low Pulse Width   Fast    RAMB36E2/CLKBWRCLK  n/a            0.542         2.500       1.958      RAMB36_X9Y26  d_1_i/qick_processor_0/WAVE_FIFO[10].wave_fifo_inst/fifo_mem/RAM_reg_1/CLKBWRCLK
High Pulse Width  Slow    RAMB36E2/CLKBWRCLK  n/a            0.542         2.500       1.958      RAMB36_X5Y37  d_1_i/qick_processor_0/WAVE_FIFO[0].wave_fifo_inst/fifo_mem/RAM_reg_0/CLKBWRCLK
High Pulse Width  Fast    RAMB36E2/CLKBWRCLK  n/a            0.542         2.500       1.958      RAMB36_X5Y37  d_1_i/qick_processor_0/WAVE_FIFO[0].wave_fifo_inst/fifo_mem/RAM_reg_0/CLKBWRCLK
High Pulse Width  Slow    RAMB36E2/CLKBWRCLK  n/a            0.542         2.500       1.958      RAMB36_X7Y41  d_1_i/qick_processor_0/WAVE_FIFO[0].wave_fifo_inst/fifo_mem/RAM_reg_1/CLKBWRCLK
High Pulse Width  Fast    RAMB36E2/CLKBWRCLK  n/a            0.542         2.500       1.958      RAMB36_X7Y41  d_1_i/qick_processor_0/WAVE_FIFO[0].wave_fifo_inst/fifo_mem/RAM_reg_1/CLKBWRCLK
High Pulse Width  Slow    RAMB36E2/CLKBWRCLK  n/a            0.542         2.500       1.958      RAMB36_X7Y37  d_1_i/qick_processor_0/WAVE_FIFO[0].wave_fifo_inst/fifo_mem/RAM_reg_2/CLKBWRCLK
High Pulse Width  Fast    RAMB36E2/CLKBWRCLK  n/a            0.542         2.500       1.958      RAMB36_X7Y37  d_1_i/qick_processor_0/WAVE_FIFO[0].wave_fifo_inst/fifo_mem/RAM_reg_2/CLKBWRCLK
High Pulse Width  Slow    RAMB36E2/CLKBWRCLK  n/a            0.542         2.500       1.958      RAMB36_X8Y36  d_1_i/qick_processor_0/WAVE_FIFO[10].wave_fifo_inst/fifo_mem/RAM_reg_0/CLKBWRCLK
High Pulse Width  Fast    RAMB36E2/CLKBWRCLK  n/a            0.542         2.500       1.958      RAMB36_X8Y36  d_1_i/qick_processor_0/WAVE_FIFO[10].wave_fifo_inst/fifo_mem/RAM_reg_0/CLKBWRCLK
High Pulse Width  Slow    RAMB36E2/CLKBWRCLK  n/a            0.542         2.500       1.958      RAMB36_X9Y26  d_1_i/qick_processor_0/WAVE_FIFO[10].wave_fifo_inst/fifo_mem/RAM_reg_1/CLKBWRCLK
High Pulse Width  Fast    RAMB36E2/CLKBWRCLK  n/a            0.542         2.500       1.958      RAMB36_X9Y26  d_1_i/qick_processor_0/WAVE_FIFO[10].wave_fifo_inst/fifo_mem/RAM_reg_1/CLKBWRCLK



---------------------------------------------------------------------------------------------------
From Clock:  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  To Clock:  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK

Setup :            0  Failing Endpoints,  Worst Slack       13.785ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.014ns,  Total Violation        0.000ns
PW    :            0  Failing Endpoints,  Worst Slack       24.468ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             13.785ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/iTDO_reg/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TDO
                            (falling edge-triggered cell BSCANE2 clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            25.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK fall@25.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns)
  Data Path Delay:        3.092ns  (logic 0.207ns (6.695%)  route 2.885ns (93.305%))
  Logic Levels:           2  (LUT3=1 LUT6=1)
  Clock Path Skew:        -7.887ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    0.000ns = ( 25.000 - 25.000 ) 
    Source Clock Delay      (SCD):    7.887ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.235ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + DCD
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
    Duty Cycle Distortion   (DCD):    0.200ns
  Clock Net Delay (Source):      1.752ns (routing 0.515ns, distribution 1.237ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.807     6.107    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y81         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     6.135 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.752     7.887    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/m_bscan_tck[0]
    SLICE_X104Y336       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/iTDO_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X104Y336       FDRE (Prop_HFF2_SLICEM_C_Q)
                                                      0.078     7.965 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/iTDO_reg/Q
                         net (fo=1, routed)           2.182    10.147    dbg_hub/inst/BSCANID.u_xsdbm_id/TDO
    SLICE_X106Y70        LUT3 (Prop_H6LUT_SLICEL_I2_O)
                                                      0.090    10.237 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch_i_1/O
                         net (fo=2, routed)           0.146    10.383    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_tdo[0]
    SLICE_X107Y72        LUT6 (Prop_H6LUT_SLICEM_I5_O)
                                                      0.039    10.422 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_tdo_INST_0/O
                         net (fo=1, routed)           0.557    10.979    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/TDO
    CONFIG_SITE_X0Y0     BSCANE2                                      r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TDO
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK fall edge)
                                                     25.000    25.000 f  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    25.000 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
                         clock pessimism              0.000    25.000    
                         clock uncertainty           -0.235    24.765    
    CONFIG_SITE_X0Y0     BSCANE2 (Setup_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TDO)
                                                      0.000    24.765    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst
  -------------------------------------------------------------------
                         required time                         24.765    
                         arrival time                         -10.979    
  -------------------------------------------------------------------
                         slack                                 13.785    

Slack (MET) :             18.786ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
                            (falling edge-triggered cell BSCANE2 clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_STAT/iSTAT_CNT_reg[0]/R
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            25.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@50.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK fall@25.000ns)
  Data Path Delay:        9.179ns  (logic 5.442ns (59.285%)  route 3.737ns (40.715%))
  Logic Levels:           3  (LUT4=1 LUT5=2)
  Clock Path Skew:        3.275ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.275ns = ( 53.275 - 50.000 ) 
    Source Clock Delay      (SCD):    0.000ns = ( 25.000 - 25.000 ) 
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.235ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + DCD
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
    Duty Cycle Distortion   (DCD):    0.200ns
  Clock Net Delay (Destination): 1.567ns (routing 0.470ns, distribution 1.097ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK fall edge)
                                                     25.000    25.000 f  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    25.000 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  -------------------------------------------------------------------    -------------------
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_SHIFT)
                                                      5.100    30.100 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/SHIFT
                         net (fo=37, routed)          0.586    30.686    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_shift
    SLICE_X105Y72        LUT5 (Prop_H6LUT_SLICEL_I4_O)
                                                      0.099    30.785 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_shift[0]_INST_0/O
                         net (fo=4, routed)           2.417    33.202    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/icn_cmd_en_reg[7]
    SLICE_X105Y332       LUT4 (Prop_B6LUT_SLICEL_I1_O)
                                                      0.098    33.300 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iSTAT_CNT[5]_i_4/O
                         net (fo=1, routed)           0.196    33.496    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iSTAT_CNT[5]_i_4_n_0
    SLICE_X104Y336       LUT5 (Prop_D6LUT_SLICEM_I4_O)
                                                      0.145    33.641 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iSTAT_CNT[5]_i_1/O
                         net (fo=6, routed)           0.538    34.179    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_STAT/SR[0]
    SLICE_X101Y314       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_STAT/iSTAT_CNT_reg[0]/R
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                     50.000    50.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    50.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465    50.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.219    51.684    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y81         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    51.708 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.567    53.275    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_STAT/m_bscan_tck[0]
    SLICE_X101Y314       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_STAT/iSTAT_CNT_reg[0]/C
                         clock pessimism              0.000    53.275    
                         clock uncertainty           -0.235    53.039    
    SLICE_X101Y314       FDRE (Setup_AFF2_SLICEL_C_R)
                                                     -0.074    52.965    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_STAT/iSTAT_CNT_reg[0]
  -------------------------------------------------------------------
                         required time                         52.965    
                         arrival time                         -34.179    
  -------------------------------------------------------------------
                         slack                                 18.786    

Slack (MET) :             18.786ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
                            (falling edge-triggered cell BSCANE2 clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_STAT/iSTAT_CNT_reg[3]/R
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            25.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@50.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK fall@25.000ns)
  Data Path Delay:        9.179ns  (logic 5.442ns (59.285%)  route 3.737ns (40.715%))
  Logic Levels:           3  (LUT4=1 LUT5=2)
  Clock Path Skew:        3.275ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.275ns = ( 53.275 - 50.000 ) 
    Source Clock Delay      (SCD):    0.000ns = ( 25.000 - 25.000 ) 
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.235ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + DCD
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
    Duty Cycle Distortion   (DCD):    0.200ns
  Clock Net Delay (Destination): 1.567ns (routing 0.470ns, distribution 1.097ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK fall edge)
                                                     25.000    25.000 f  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    25.000 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  -------------------------------------------------------------------    -------------------
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_SHIFT)
                                                      5.100    30.100 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/SHIFT
                         net (fo=37, routed)          0.586    30.686    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_shift
    SLICE_X105Y72        LUT5 (Prop_H6LUT_SLICEL_I4_O)
                                                      0.099    30.785 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_shift[0]_INST_0/O
                         net (fo=4, routed)           2.417    33.202    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/icn_cmd_en_reg[7]
    SLICE_X105Y332       LUT4 (Prop_B6LUT_SLICEL_I1_O)
                                                      0.098    33.300 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iSTAT_CNT[5]_i_4/O
                         net (fo=1, routed)           0.196    33.496    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iSTAT_CNT[5]_i_4_n_0
    SLICE_X104Y336       LUT5 (Prop_D6LUT_SLICEM_I4_O)
                                                      0.145    33.641 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iSTAT_CNT[5]_i_1/O
                         net (fo=6, routed)           0.538    34.179    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_STAT/SR[0]
    SLICE_X101Y314       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_STAT/iSTAT_CNT_reg[3]/R
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                     50.000    50.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    50.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465    50.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.219    51.684    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y81         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    51.708 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.567    53.275    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_STAT/m_bscan_tck[0]
    SLICE_X101Y314       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_STAT/iSTAT_CNT_reg[3]/C
                         clock pessimism              0.000    53.275    
                         clock uncertainty           -0.235    53.039    
    SLICE_X101Y314       FDRE (Setup_BFF_SLICEL_C_R)
                                                     -0.074    52.965    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_STAT/iSTAT_CNT_reg[3]
  -------------------------------------------------------------------
                         required time                         52.965    
                         arrival time                         -34.179    
  -------------------------------------------------------------------
                         slack                                 18.786    

Slack (MET) :             18.786ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
                            (falling edge-triggered cell BSCANE2 clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_STAT/iSTAT_CNT_reg[4]/R
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            25.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@50.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK fall@25.000ns)
  Data Path Delay:        9.179ns  (logic 5.442ns (59.285%)  route 3.737ns (40.715%))
  Logic Levels:           3  (LUT4=1 LUT5=2)
  Clock Path Skew:        3.275ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.275ns = ( 53.275 - 50.000 ) 
    Source Clock Delay      (SCD):    0.000ns = ( 25.000 - 25.000 ) 
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.235ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + DCD
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
    Duty Cycle Distortion   (DCD):    0.200ns
  Clock Net Delay (Destination): 1.567ns (routing 0.470ns, distribution 1.097ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK fall edge)
                                                     25.000    25.000 f  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    25.000 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  -------------------------------------------------------------------    -------------------
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_SHIFT)
                                                      5.100    30.100 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/SHIFT
                         net (fo=37, routed)          0.586    30.686    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_shift
    SLICE_X105Y72        LUT5 (Prop_H6LUT_SLICEL_I4_O)
                                                      0.099    30.785 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_shift[0]_INST_0/O
                         net (fo=4, routed)           2.417    33.202    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/icn_cmd_en_reg[7]
    SLICE_X105Y332       LUT4 (Prop_B6LUT_SLICEL_I1_O)
                                                      0.098    33.300 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iSTAT_CNT[5]_i_4/O
                         net (fo=1, routed)           0.196    33.496    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iSTAT_CNT[5]_i_4_n_0
    SLICE_X104Y336       LUT5 (Prop_D6LUT_SLICEM_I4_O)
                                                      0.145    33.641 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iSTAT_CNT[5]_i_1/O
                         net (fo=6, routed)           0.538    34.179    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_STAT/SR[0]
    SLICE_X101Y314       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_STAT/iSTAT_CNT_reg[4]/R
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                     50.000    50.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    50.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465    50.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.219    51.684    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y81         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    51.708 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.567    53.275    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_STAT/m_bscan_tck[0]
    SLICE_X101Y314       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_STAT/iSTAT_CNT_reg[4]/C
                         clock pessimism              0.000    53.275    
                         clock uncertainty           -0.235    53.039    
    SLICE_X101Y314       FDRE (Setup_BFF2_SLICEL_C_R)
                                                     -0.074    52.965    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_STAT/iSTAT_CNT_reg[4]
  -------------------------------------------------------------------
                         required time                         52.965    
                         arrival time                         -34.179    
  -------------------------------------------------------------------
                         slack                                 18.786    

Slack (MET) :             18.789ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
                            (falling edge-triggered cell BSCANE2 clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_STAT/iSTAT_CNT_reg[1]/R
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            25.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@50.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK fall@25.000ns)
  Data Path Delay:        9.178ns  (logic 5.442ns (59.292%)  route 3.736ns (40.708%))
  Logic Levels:           3  (LUT4=1 LUT5=2)
  Clock Path Skew:        3.277ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.277ns = ( 53.277 - 50.000 ) 
    Source Clock Delay      (SCD):    0.000ns = ( 25.000 - 25.000 ) 
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.235ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + DCD
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
    Duty Cycle Distortion   (DCD):    0.200ns
  Clock Net Delay (Destination): 1.569ns (routing 0.470ns, distribution 1.099ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK fall edge)
                                                     25.000    25.000 f  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    25.000 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  -------------------------------------------------------------------    -------------------
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_SHIFT)
                                                      5.100    30.100 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/SHIFT
                         net (fo=37, routed)          0.586    30.686    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_shift
    SLICE_X105Y72        LUT5 (Prop_H6LUT_SLICEL_I4_O)
                                                      0.099    30.785 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_shift[0]_INST_0/O
                         net (fo=4, routed)           2.417    33.202    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/icn_cmd_en_reg[7]
    SLICE_X105Y332       LUT4 (Prop_B6LUT_SLICEL_I1_O)
                                                      0.098    33.300 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iSTAT_CNT[5]_i_4/O
                         net (fo=1, routed)           0.196    33.496    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iSTAT_CNT[5]_i_4_n_0
    SLICE_X104Y336       LUT5 (Prop_D6LUT_SLICEM_I4_O)
                                                      0.145    33.641 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iSTAT_CNT[5]_i_1/O
                         net (fo=6, routed)           0.537    34.178    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_STAT/SR[0]
    SLICE_X102Y314       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_STAT/iSTAT_CNT_reg[1]/R
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                     50.000    50.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    50.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465    50.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.219    51.684    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y81         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    51.708 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.569    53.277    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_STAT/m_bscan_tck[0]
    SLICE_X102Y314       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_STAT/iSTAT_CNT_reg[1]/C
                         clock pessimism              0.000    53.277    
                         clock uncertainty           -0.235    53.041    
    SLICE_X102Y314       FDRE (Setup_HFF_SLICEL_C_R)
                                                     -0.074    52.967    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_STAT/iSTAT_CNT_reg[1]
  -------------------------------------------------------------------
                         required time                         52.967    
                         arrival time                         -34.178    
  -------------------------------------------------------------------
                         slack                                 18.789    

Slack (MET) :             18.789ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
                            (falling edge-triggered cell BSCANE2 clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_STAT/iSTAT_CNT_reg[2]/R
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            25.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@50.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK fall@25.000ns)
  Data Path Delay:        9.178ns  (logic 5.442ns (59.292%)  route 3.736ns (40.708%))
  Logic Levels:           3  (LUT4=1 LUT5=2)
  Clock Path Skew:        3.277ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.277ns = ( 53.277 - 50.000 ) 
    Source Clock Delay      (SCD):    0.000ns = ( 25.000 - 25.000 ) 
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.235ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + DCD
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
    Duty Cycle Distortion   (DCD):    0.200ns
  Clock Net Delay (Destination): 1.569ns (routing 0.470ns, distribution 1.099ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK fall edge)
                                                     25.000    25.000 f  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    25.000 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  -------------------------------------------------------------------    -------------------
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_SHIFT)
                                                      5.100    30.100 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/SHIFT
                         net (fo=37, routed)          0.586    30.686    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_shift
    SLICE_X105Y72        LUT5 (Prop_H6LUT_SLICEL_I4_O)
                                                      0.099    30.785 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_shift[0]_INST_0/O
                         net (fo=4, routed)           2.417    33.202    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/icn_cmd_en_reg[7]
    SLICE_X105Y332       LUT4 (Prop_B6LUT_SLICEL_I1_O)
                                                      0.098    33.300 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iSTAT_CNT[5]_i_4/O
                         net (fo=1, routed)           0.196    33.496    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iSTAT_CNT[5]_i_4_n_0
    SLICE_X104Y336       LUT5 (Prop_D6LUT_SLICEM_I4_O)
                                                      0.145    33.641 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iSTAT_CNT[5]_i_1/O
                         net (fo=6, routed)           0.537    34.178    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_STAT/SR[0]
    SLICE_X102Y314       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_STAT/iSTAT_CNT_reg[2]/R
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                     50.000    50.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    50.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465    50.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.219    51.684    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y81         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    51.708 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.569    53.277    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_STAT/m_bscan_tck[0]
    SLICE_X102Y314       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_STAT/iSTAT_CNT_reg[2]/C
                         clock pessimism              0.000    53.277    
                         clock uncertainty           -0.235    53.041    
    SLICE_X102Y314       FDRE (Setup_HFF2_SLICEL_C_R)
                                                     -0.074    52.967    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_STAT/iSTAT_CNT_reg[2]
  -------------------------------------------------------------------
                         required time                         52.967    
                         arrival time                         -34.178    
  -------------------------------------------------------------------
                         slack                                 18.789    

Slack (MET) :             18.789ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
                            (falling edge-triggered cell BSCANE2 clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_STAT/iSTAT_CNT_reg[5]/R
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            25.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@50.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK fall@25.000ns)
  Data Path Delay:        9.178ns  (logic 5.442ns (59.292%)  route 3.736ns (40.708%))
  Logic Levels:           3  (LUT4=1 LUT5=2)
  Clock Path Skew:        3.277ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.277ns = ( 53.277 - 50.000 ) 
    Source Clock Delay      (SCD):    0.000ns = ( 25.000 - 25.000 ) 
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.235ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + DCD
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
    Duty Cycle Distortion   (DCD):    0.200ns
  Clock Net Delay (Destination): 1.569ns (routing 0.470ns, distribution 1.099ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK fall edge)
                                                     25.000    25.000 f  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    25.000 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  -------------------------------------------------------------------    -------------------
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_SHIFT)
                                                      5.100    30.100 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/SHIFT
                         net (fo=37, routed)          0.586    30.686    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_shift
    SLICE_X105Y72        LUT5 (Prop_H6LUT_SLICEL_I4_O)
                                                      0.099    30.785 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_shift[0]_INST_0/O
                         net (fo=4, routed)           2.417    33.202    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/icn_cmd_en_reg[7]
    SLICE_X105Y332       LUT4 (Prop_B6LUT_SLICEL_I1_O)
                                                      0.098    33.300 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iSTAT_CNT[5]_i_4/O
                         net (fo=1, routed)           0.196    33.496    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iSTAT_CNT[5]_i_4_n_0
    SLICE_X104Y336       LUT5 (Prop_D6LUT_SLICEM_I4_O)
                                                      0.145    33.641 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iSTAT_CNT[5]_i_1/O
                         net (fo=6, routed)           0.537    34.178    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_STAT/SR[0]
    SLICE_X102Y314       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_STAT/iSTAT_CNT_reg[5]/R
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                     50.000    50.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    50.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465    50.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.219    51.684    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y81         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    51.708 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.569    53.277    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_STAT/m_bscan_tck[0]
    SLICE_X102Y314       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_STAT/iSTAT_CNT_reg[5]/C
                         clock pessimism              0.000    53.277    
                         clock uncertainty           -0.235    53.041    
    SLICE_X102Y314       FDRE (Setup_GFF_SLICEL_C_R)
                                                     -0.074    52.967    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_STAT/iSTAT_CNT_reg[5]
  -------------------------------------------------------------------
                         required time                         52.967    
                         arrival time                         -34.178    
  -------------------------------------------------------------------
                         slack                                 18.789    

Slack (MET) :             19.257ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
                            (falling edge-triggered cell BSCANE2 clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[11]/CE
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            25.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@50.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK fall@25.000ns)
  Data Path Delay:        8.704ns  (logic 5.290ns (60.777%)  route 3.414ns (39.223%))
  Logic Levels:           2  (LUT2=1 LUT5=1)
  Clock Path Skew:        3.257ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.257ns = ( 53.257 - 50.000 ) 
    Source Clock Delay      (SCD):    0.000ns = ( 25.000 - 25.000 ) 
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.235ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + DCD
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
    Duty Cycle Distortion   (DCD):    0.200ns
  Clock Net Delay (Destination): 1.549ns (routing 0.470ns, distribution 1.079ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK fall edge)
                                                     25.000    25.000 f  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    25.000 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  -------------------------------------------------------------------    -------------------
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_SHIFT)
                                                      5.100    30.100 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/SHIFT
                         net (fo=37, routed)          0.586    30.686    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_shift
    SLICE_X105Y72        LUT5 (Prop_H6LUT_SLICEL_I4_O)
                                                      0.099    30.785 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_shift[0]_INST_0/O
                         net (fo=4, routed)           2.399    33.184    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/icn_cmd_en_reg[7]
    SLICE_X104Y332       LUT2 (Prop_E6LUT_SLICEM_I0_O)
                                                      0.091    33.275 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET[15]_i_1/O
                         net (fo=10, routed)          0.429    33.704    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_CE
    SLICE_X105Y336       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[11]/CE
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                     50.000    50.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    50.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465    50.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.219    51.684    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y81         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    51.708 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.549    53.257    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/m_bscan_tck[0]
    SLICE_X105Y336       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[11]/C
                         clock pessimism              0.000    53.257    
                         clock uncertainty           -0.235    53.021    
    SLICE_X105Y336       FDCE (Setup_EFF2_SLICEL_C_CE)
                                                     -0.060    52.961    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[11]
  -------------------------------------------------------------------
                         required time                         52.961    
                         arrival time                         -33.704    
  -------------------------------------------------------------------
                         slack                                 19.257    

Slack (MET) :             19.257ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
                            (falling edge-triggered cell BSCANE2 clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[13]/CE
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            25.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@50.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK fall@25.000ns)
  Data Path Delay:        8.704ns  (logic 5.290ns (60.777%)  route 3.414ns (39.223%))
  Logic Levels:           2  (LUT2=1 LUT5=1)
  Clock Path Skew:        3.257ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.257ns = ( 53.257 - 50.000 ) 
    Source Clock Delay      (SCD):    0.000ns = ( 25.000 - 25.000 ) 
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.235ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + DCD
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
    Duty Cycle Distortion   (DCD):    0.200ns
  Clock Net Delay (Destination): 1.549ns (routing 0.470ns, distribution 1.079ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK fall edge)
                                                     25.000    25.000 f  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    25.000 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  -------------------------------------------------------------------    -------------------
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_SHIFT)
                                                      5.100    30.100 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/SHIFT
                         net (fo=37, routed)          0.586    30.686    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_shift
    SLICE_X105Y72        LUT5 (Prop_H6LUT_SLICEL_I4_O)
                                                      0.099    30.785 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_shift[0]_INST_0/O
                         net (fo=4, routed)           2.399    33.184    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/icn_cmd_en_reg[7]
    SLICE_X104Y332       LUT2 (Prop_E6LUT_SLICEM_I0_O)
                                                      0.091    33.275 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET[15]_i_1/O
                         net (fo=10, routed)          0.429    33.704    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_CE
    SLICE_X105Y336       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[13]/CE
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                     50.000    50.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    50.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465    50.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.219    51.684    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y81         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    51.708 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.549    53.257    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/m_bscan_tck[0]
    SLICE_X105Y336       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[13]/C
                         clock pessimism              0.000    53.257    
                         clock uncertainty           -0.235    53.021    
    SLICE_X105Y336       FDCE (Setup_FFF2_SLICEL_C_CE)
                                                     -0.060    52.961    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[13]
  -------------------------------------------------------------------
                         required time                         52.961    
                         arrival time                         -33.704    
  -------------------------------------------------------------------
                         slack                                 19.257    

Slack (MET) :             19.257ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
                            (falling edge-triggered cell BSCANE2 clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[7]/CE
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            25.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@50.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK fall@25.000ns)
  Data Path Delay:        8.704ns  (logic 5.290ns (60.777%)  route 3.414ns (39.223%))
  Logic Levels:           2  (LUT2=1 LUT5=1)
  Clock Path Skew:        3.257ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.257ns = ( 53.257 - 50.000 ) 
    Source Clock Delay      (SCD):    0.000ns = ( 25.000 - 25.000 ) 
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.235ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + DCD
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
    Duty Cycle Distortion   (DCD):    0.200ns
  Clock Net Delay (Destination): 1.549ns (routing 0.470ns, distribution 1.079ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK fall edge)
                                                     25.000    25.000 f  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    25.000 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  -------------------------------------------------------------------    -------------------
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_SHIFT)
                                                      5.100    30.100 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/SHIFT
                         net (fo=37, routed)          0.586    30.686    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_shift
    SLICE_X105Y72        LUT5 (Prop_H6LUT_SLICEL_I4_O)
                                                      0.099    30.785 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_shift[0]_INST_0/O
                         net (fo=4, routed)           2.399    33.184    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/icn_cmd_en_reg[7]
    SLICE_X104Y332       LUT2 (Prop_E6LUT_SLICEM_I0_O)
                                                      0.091    33.275 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET[15]_i_1/O
                         net (fo=10, routed)          0.429    33.704    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_CE
    SLICE_X105Y336       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[7]/CE
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                     50.000    50.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    50.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465    50.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.219    51.684    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y81         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    51.708 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.549    53.257    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/m_bscan_tck[0]
    SLICE_X105Y336       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[7]/C
                         clock pessimism              0.000    53.257    
                         clock uncertainty           -0.235    53.021    
    SLICE_X105Y336       FDCE (Setup_GFF2_SLICEL_C_CE)
                                                     -0.060    52.961    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[7]
  -------------------------------------------------------------------
                         required time                         52.961    
                         arrival time                         -33.704    
  -------------------------------------------------------------------
                         slack                                 19.257    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.014ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_reg[3]/C
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[3]/D
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns)
  Data Path Delay:        0.128ns  (logic 0.061ns (47.604%)  route 0.067ns (52.396%))
  Logic Levels:           0  
  Clock Path Skew:        0.052ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    7.920ns
    Source Clock Delay      (SCD):    3.279ns
    Clock Pessimism Removal (CPR):    4.589ns
  Clock Net Delay (Source):      1.571ns (routing 0.470ns, distribution 1.101ns)
  Clock Net Delay (Destination): 1.785ns (routing 0.515ns, distribution 1.270ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.219     1.684    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y81         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.708 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.571     3.279    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/rd_clk
    SLICE_X101Y351       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X101Y351       FDCE (Prop_DFF2_SLICEL_C_Q)
                                                      0.061     3.340 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_reg[3]/Q
                         net (fo=3, routed)           0.067     3.407    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Q[3]
    SLICE_X101Y350       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[3]/D
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.807     6.107    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y81         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     6.135 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.785     7.920    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/rd_clk
    SLICE_X101Y350       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[3]/C
                         clock pessimism             -4.589     3.331    
    SLICE_X101Y350       FDCE (Hold_EFF2_SLICEL_C_D)
                                                      0.062     3.393    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[3]
  -------------------------------------------------------------------
                         required time                         -3.393    
                         arrival time                           3.407    
  -------------------------------------------------------------------
                         slack                                  0.014    

Slack (MET) :             0.029ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/bscanid_reg[5]/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/bscanid_reg[4]/D
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns)
  Data Path Delay:        0.097ns  (logic 0.052ns (53.608%)  route 0.045ns (46.392%))
  Logic Levels:           1  (LUT2=1)
  Clock Path Skew:        0.022ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    6.676ns
    Source Clock Delay      (SCD):    2.400ns
    Clock Pessimism Removal (CPR):    4.255ns
  Clock Net Delay (Source):      0.964ns (routing 0.283ns, distribution 0.681ns)
  Clock Net Delay (Destination): 1.093ns (routing 0.313ns, distribution 0.780ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.954     1.419    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y81         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.436 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         0.964     2.400    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_tck
    SLICE_X107Y62        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/bscanid_reg[5]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X107Y62        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.038     2.438 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/bscanid_reg[5]/Q
                         net (fo=1, routed)           0.027     2.465    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/bscanid__0[5]
    SLICE_X107Y63        LUT2 (Prop_A6LUT_SLICEM_I1_O)
                                                      0.014     2.479 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/bscanid[4]_i_1/O
                         net (fo=1, routed)           0.018     2.497    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/bscanid[4]_i_1_n_0
    SLICE_X107Y63        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/bscanid_reg[4]/D
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.264     5.564    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y81         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     5.583 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.093     6.676    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_tck
    SLICE_X107Y63        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/bscanid_reg[4]/C
                         clock pessimism             -4.255     2.422    
    SLICE_X107Y63        FDRE (Hold_AFF_SLICEM_C_D)
                                                      0.046     2.468    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/bscanid_reg[4]
  -------------------------------------------------------------------
                         required time                         -2.468    
                         arrival time                           2.497    
  -------------------------------------------------------------------
                         slack                                  0.029    

Slack (MET) :             0.030ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/icn_cmd_din_temp_reg/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[17]/D
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns)
  Data Path Delay:        0.178ns  (logic 0.058ns (32.584%)  route 0.120ns (67.416%))
  Logic Levels:           0  
  Clock Path Skew:        0.086ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    7.899ns
    Source Clock Delay      (SCD):    3.271ns
    Clock Pessimism Removal (CPR):    4.542ns
  Clock Net Delay (Source):      1.563ns (routing 0.470ns, distribution 1.093ns)
  Clock Net Delay (Destination): 1.764ns (routing 0.515ns, distribution 1.249ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.219     1.684    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y81         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.708 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.563     3.271    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/m_bscan_tck[0]
    SLICE_X103Y355       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/icn_cmd_din_temp_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X103Y355       FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.058     3.329 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/icn_cmd_din_temp_reg/Q
                         net (fo=1, routed)           0.120     3.449    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/icn_cmd_din_temp
    SLICE_X100Y355       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[17]/D
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.807     6.107    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y81         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     6.135 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.764     7.899    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/m_bscan_tck[0]
    SLICE_X100Y355       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[17]/C
                         clock pessimism             -4.542     3.357    
    SLICE_X100Y355       FDRE (Hold_HFF2_SLICEL_C_D)
                                                      0.062     3.419    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[17]
  -------------------------------------------------------------------
                         required time                         -3.419    
                         arrival time                           3.449    
  -------------------------------------------------------------------
                         slack                                  0.030    

Slack (MET) :             0.034ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/gpr1.dout_i_reg[5]/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/goreg_dm.dout_i_reg[5]/D
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns)
  Data Path Delay:        0.097ns  (logic 0.039ns (40.206%)  route 0.058ns (59.794%))
  Logic Levels:           0  
  Clock Path Skew:        0.016ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    6.676ns
    Source Clock Delay      (SCD):    2.403ns
    Clock Pessimism Removal (CPR):    4.258ns
  Clock Net Delay (Source):      0.967ns (routing 0.283ns, distribution 0.684ns)
  Clock Net Delay (Destination): 1.093ns (routing 0.313ns, distribution 0.780ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.954     1.419    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y81         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.436 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         0.967     2.403    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/rd_clk
    SLICE_X100Y351       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/gpr1.dout_i_reg[5]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X100Y351       FDRE (Prop_CFF_SLICEL_C_Q)
                                                      0.039     2.442 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/gpr1.dout_i_reg[5]/Q
                         net (fo=1, routed)           0.058     2.500    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i[5]
    SLICE_X100Y351       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/goreg_dm.dout_i_reg[5]/D
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.264     5.564    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y81         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     5.583 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.093     6.676    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/rd_clk
    SLICE_X100Y351       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/goreg_dm.dout_i_reg[5]/C
                         clock pessimism             -4.258     2.418    
    SLICE_X100Y351       FDRE (Hold_FFF2_SLICEL_C_D)
                                                      0.047     2.465    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/goreg_dm.dout_i_reg[5]
  -------------------------------------------------------------------
                         required time                         -2.465    
                         arrival time                           2.500    
  -------------------------------------------------------------------
                         slack                                  0.034    

Slack (MET) :             0.035ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[8]/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[7]/D
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns)
  Data Path Delay:        0.087ns  (logic 0.039ns (44.992%)  route 0.048ns (55.009%))
  Logic Levels:           0  
  Clock Path Skew:        0.006ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    6.677ns
    Source Clock Delay      (SCD):    2.407ns
    Clock Pessimism Removal (CPR):    4.265ns
  Clock Net Delay (Source):      0.971ns (routing 0.283ns, distribution 0.688ns)
  Clock Net Delay (Destination): 1.094ns (routing 0.313ns, distribution 0.781ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.954     1.419    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y81         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.436 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         0.971     2.407    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/m_bscan_tck[0]
    SLICE_X100Y355       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[8]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X100Y355       FDRE (Prop_GFF_SLICEL_C_Q)
                                                      0.039     2.446 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[8]/Q
                         net (fo=2, routed)           0.048     2.493    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in[8]
    SLICE_X100Y355       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[7]/D
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.264     5.564    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y81         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     5.583 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.094     6.677    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/m_bscan_tck[0]
    SLICE_X100Y355       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[7]/C
                         clock pessimism             -4.265     2.413    
    SLICE_X100Y355       FDRE (Hold_FFF_SLICEL_C_D)
                                                      0.046     2.459    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[7]
  -------------------------------------------------------------------
                         required time                         -2.459    
                         arrival time                           2.493    
  -------------------------------------------------------------------
                         slack                                  0.035    

Slack (MET) :             0.035ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[6]/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[5]/D
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns)
  Data Path Delay:        0.098ns  (logic 0.039ns (39.925%)  route 0.059ns (60.075%))
  Logic Levels:           0  
  Clock Path Skew:        0.016ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    6.674ns
    Source Clock Delay      (SCD):    2.400ns
    Clock Pessimism Removal (CPR):    4.259ns
  Clock Net Delay (Source):      0.964ns (routing 0.283ns, distribution 0.681ns)
  Clock Net Delay (Destination): 1.091ns (routing 0.313ns, distribution 0.778ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.954     1.419    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y81         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.436 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         0.964     2.400    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/m_bscan_tck[0]
    SLICE_X105Y347       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[6]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X105Y347       FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.039     2.439 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[6]/Q
                         net (fo=2, routed)           0.059     2.497    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in[6]
    SLICE_X105Y347       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[5]/D
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.264     5.564    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y81         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     5.583 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.091     6.674    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/m_bscan_tck[0]
    SLICE_X105Y347       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[5]/C
                         clock pessimism             -4.259     2.415    
    SLICE_X105Y347       FDRE (Hold_HFF2_SLICEL_C_D)
                                                      0.047     2.462    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[5]
  -------------------------------------------------------------------
                         required time                         -2.462    
                         arrival time                           2.497    
  -------------------------------------------------------------------
                         slack                                  0.035    

Slack (MET) :             0.038ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.id_state_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscanid_reg[18]/D
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns)
  Data Path Delay:        0.178ns  (logic 0.079ns (44.354%)  route 0.099ns (55.646%))
  Logic Levels:           1  (LUT4=1)
  Clock Path Skew:        0.080ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    7.872ns
    Source Clock Delay      (SCD):    3.251ns
    Clock Pessimism Removal (CPR):    4.541ns
  Clock Net Delay (Source):      1.543ns (routing 0.470ns, distribution 1.073ns)
  Clock Net Delay (Destination): 1.737ns (routing 0.515ns, distribution 1.222ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.219     1.684    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y81         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.708 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.543     3.251    dbg_hub/inst/BSCANID.u_xsdbm_id/itck_i
    SLICE_X107Y69        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.id_state_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X107Y69        FDRE (Prop_FFF_SLICEM_C_Q)
                                                      0.057     3.308 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.id_state_reg[0]/Q
                         net (fo=34, routed)          0.077     3.385    dbg_hub/inst/BSCANID.u_xsdbm_id/id_state[0]
    SLICE_X106Y69        LUT4 (Prop_G6LUT_SLICEL_I0_O)
                                                      0.022     3.407 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscanid[18]_i_1/O
                         net (fo=1, routed)           0.022     3.429    dbg_hub/inst/BSCANID.u_xsdbm_id/p_2_in[18]
    SLICE_X106Y69        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscanid_reg[18]/D
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.807     6.107    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y81         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     6.135 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.737     7.872    dbg_hub/inst/BSCANID.u_xsdbm_id/itck_i
    SLICE_X106Y69        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscanid_reg[18]/C
                         clock pessimism             -4.541     3.331    
    SLICE_X106Y69        FDRE (Hold_GFF_SLICEL_C_D)
                                                      0.060     3.391    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscanid_reg[18]
  -------------------------------------------------------------------
                         required time                         -3.391    
                         arrival time                           3.429    
  -------------------------------------------------------------------
                         slack                                  0.038    

Slack (MET) :             0.038ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_temp_reg[4]/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[4]/D
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns)
  Data Path Delay:        0.105ns  (logic 0.039ns (37.110%)  route 0.066ns (62.890%))
  Logic Levels:           0  
  Clock Path Skew:        0.020ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    6.672ns
    Source Clock Delay      (SCD):    2.398ns
    Clock Pessimism Removal (CPR):    4.255ns
  Clock Net Delay (Source):      0.962ns (routing 0.283ns, distribution 0.679ns)
  Clock Net Delay (Destination): 1.089ns (routing 0.313ns, distribution 0.776ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.954     1.419    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y81         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.436 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         0.962     2.398    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_tck
    SLICE_X107Y73        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_temp_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X107Y73        FDRE (Prop_HFF_SLICEM_C_Q)
                                                      0.039     2.437 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_temp_reg[4]/Q
                         net (fo=2, routed)           0.066     2.503    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_temp[4]
    SLICE_X107Y72        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[4]/D
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.264     5.564    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y81         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     5.583 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.089     6.672    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_tck
    SLICE_X107Y72        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[4]/C
                         clock pessimism             -4.255     2.417    
    SLICE_X107Y72        FDRE (Hold_EFF2_SLICEM_C_D)
                                                      0.047     2.464    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[4]
  -------------------------------------------------------------------
                         required time                         -2.464    
                         arrival time                           2.503    
  -------------------------------------------------------------------
                         slack                                  0.038    

Slack (MET) :             0.039ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[1]/D
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns)
  Data Path Delay:        0.099ns  (logic 0.039ns (39.218%)  route 0.060ns (60.782%))
  Logic Levels:           0  
  Clock Path Skew:        0.014ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    6.669ns
    Source Clock Delay      (SCD):    2.404ns
    Clock Pessimism Removal (CPR):    4.252ns
  Clock Net Delay (Source):      0.968ns (routing 0.283ns, distribution 0.685ns)
  Clock Net Delay (Destination): 1.086ns (routing 0.313ns, distribution 0.773ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.954     1.419    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y81         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.436 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         0.968     2.404    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/m_bscan_tck[0]
    SLICE_X100Y355       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X100Y355       FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.039     2.443 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[2]/Q
                         net (fo=2, routed)           0.060     2.503    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in[2]
    SLICE_X100Y356       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.264     5.564    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y81         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     5.583 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.086     6.669    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/m_bscan_tck[0]
    SLICE_X100Y356       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[1]/C
                         clock pessimism             -4.252     2.417    
    SLICE_X100Y356       FDRE (Hold_BFF2_SLICEL_C_D)
                                                      0.047     2.464    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[1]
  -------------------------------------------------------------------
                         required time                         -2.464    
                         arrival time                           2.503    
  -------------------------------------------------------------------
                         slack                                  0.039    

Slack (MET) :             0.039ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/shift_bit_count_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/shift_bit_count_reg[3]/D
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns)
  Data Path Delay:        0.092ns  (logic 0.060ns (65.325%)  route 0.032ns (34.675%))
  Logic Levels:           1  (LUT4=1)
  Clock Path Skew:        0.006ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    6.681ns
    Source Clock Delay      (SCD):    2.409ns
    Clock Pessimism Removal (CPR):    4.266ns
  Clock Net Delay (Source):      0.973ns (routing 0.283ns, distribution 0.690ns)
  Clock Net Delay (Destination): 1.098ns (routing 0.313ns, distribution 0.785ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.954     1.419    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y81         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.436 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         0.973     2.409    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/m_bscan_tck[0]
    SLICE_X102Y350       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/shift_bit_count_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X102Y350       FDRE (Prop_BFF_SLICEL_C_Q)
                                                      0.039     2.448 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/shift_bit_count_reg[2]/Q
                         net (fo=3, routed)           0.025     2.472    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/shift_bit_count_reg[2]
    SLICE_X102Y350       LUT4 (Prop_B5LUT_SLICEL_I3_O)
                                                      0.021     2.493 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/shift_bit_count[3]_i_2__0/O
                         net (fo=1, routed)           0.007     2.500    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/p_0_in__1[3]
    SLICE_X102Y350       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/shift_bit_count_reg[3]/D
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.264     5.564    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y81         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     5.583 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.098     6.681    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/m_bscan_tck[0]
    SLICE_X102Y350       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/shift_bit_count_reg[3]/C
                         clock pessimism             -4.266     2.415    
    SLICE_X102Y350       FDRE (Hold_BFF2_SLICEL_C_D)
                                                      0.047     2.462    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/shift_bit_count_reg[3]
  -------------------------------------------------------------------
                         required time                         -2.462    
                         arrival time                           2.500    
  -------------------------------------------------------------------
                         slack                                  0.039    





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
Waveform(ns):       { 0.000 25.000 }
Period(ns):         50.000
Sources:            { dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK }

Check Type        Corner  Lib Pin     Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location        Pin
Min Period        n/a     BUFGCE/I    n/a            1.290         50.000      48.710     BUFGCE_X0Y81    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/I
Min Period        n/a     RAMD32/CLK  n/a            1.064         50.000      48.936     SLICE_X103Y357  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMA/CLK
Min Period        n/a     RAMD32/CLK  n/a            1.064         50.000      48.936     SLICE_X103Y357  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMA_D1/CLK
Min Period        n/a     RAMD32/CLK  n/a            1.064         50.000      48.936     SLICE_X103Y357  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMB/CLK
Min Period        n/a     RAMD32/CLK  n/a            1.064         50.000      48.936     SLICE_X103Y357  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMB_D1/CLK
Min Period        n/a     RAMD32/CLK  n/a            1.064         50.000      48.936     SLICE_X103Y357  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMC/CLK
Min Period        n/a     RAMD32/CLK  n/a            1.064         50.000      48.936     SLICE_X103Y357  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMC_D1/CLK
Min Period        n/a     RAMD32/CLK  n/a            1.064         50.000      48.936     SLICE_X103Y357  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMD/CLK
Min Period        n/a     RAMD32/CLK  n/a            1.064         50.000      48.936     SLICE_X103Y357  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMD_D1/CLK
Min Period        n/a     RAMD32/CLK  n/a            1.064         50.000      48.936     SLICE_X103Y357  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAME/CLK
Low Pulse Width   Slow    RAMD32/CLK  n/a            0.532         25.000      24.468     SLICE_X103Y357  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMA/CLK
Low Pulse Width   Fast    RAMD32/CLK  n/a            0.532         25.000      24.468     SLICE_X103Y357  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMA/CLK
Low Pulse Width   Slow    RAMD32/CLK  n/a            0.532         25.000      24.468     SLICE_X103Y357  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMA_D1/CLK
Low Pulse Width   Fast    RAMD32/CLK  n/a            0.532         25.000      24.468     SLICE_X103Y357  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMA_D1/CLK
Low Pulse Width   Slow    RAMD32/CLK  n/a            0.532         25.000      24.468     SLICE_X103Y357  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMB/CLK
Low Pulse Width   Fast    RAMD32/CLK  n/a            0.532         25.000      24.468     SLICE_X103Y357  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMB/CLK
Low Pulse Width   Slow    RAMD32/CLK  n/a            0.532         25.000      24.468     SLICE_X103Y357  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMB_D1/CLK
Low Pulse Width   Fast    RAMD32/CLK  n/a            0.532         25.000      24.468     SLICE_X103Y357  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMB_D1/CLK
Low Pulse Width   Slow    RAMD32/CLK  n/a            0.532         25.000      24.468     SLICE_X103Y357  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMC/CLK
Low Pulse Width   Fast    RAMD32/CLK  n/a            0.532         25.000      24.468     SLICE_X103Y357  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMC/CLK
High Pulse Width  Slow    RAMD32/CLK  n/a            0.532         25.000      24.468     SLICE_X103Y357  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMA/CLK
High Pulse Width  Fast    RAMD32/CLK  n/a            0.532         25.000      24.468     SLICE_X103Y357  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMA/CLK
High Pulse Width  Slow    RAMD32/CLK  n/a            0.532         25.000      24.468     SLICE_X103Y357  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMA_D1/CLK
High Pulse Width  Fast    RAMD32/CLK  n/a            0.532         25.000      24.468     SLICE_X103Y357  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMA_D1/CLK
High Pulse Width  Slow    RAMD32/CLK  n/a            0.532         25.000      24.468     SLICE_X103Y357  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMB/CLK
High Pulse Width  Fast    RAMD32/CLK  n/a            0.532         25.000      24.468     SLICE_X103Y357  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMB/CLK
High Pulse Width  Slow    RAMD32/CLK  n/a            0.532         25.000      24.468     SLICE_X103Y357  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMB_D1/CLK
High Pulse Width  Fast    RAMD32/CLK  n/a            0.532         25.000      24.468     SLICE_X103Y357  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMB_D1/CLK
High Pulse Width  Slow    RAMD32/CLK  n/a            0.532         25.000      24.468     SLICE_X103Y357  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMC/CLK
High Pulse Width  Fast    RAMD32/CLK  n/a            0.532         25.000      24.468     SLICE_X103Y357  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMC/CLK



---------------------------------------------------------------------------------------------------
From Clock:  sys_clk_ddr4_clk_p
  To Clock:  sys_clk_ddr4_clk_p

Setup :            0  Failing Endpoints,  Worst Slack        0.729ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.055ns,  Total Violation        0.000ns
PW    :            0  Failing Endpoints,  Worst Slack        0.500ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.729ns  (required time - arrival time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_infrastructure/input_rst_design_reg/C
                            (rising edge-triggered cell FDRE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_async_mb_reg/D
                            (rising edge-triggered cell FDRE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Path Group:             sys_clk_ddr4_clk_p
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.334ns  (sys_clk_ddr4_clk_p rise@3.334ns - sys_clk_ddr4_clk_p rise@0.000ns)
  Data Path Delay:        2.476ns  (logic 0.214ns (8.644%)  route 2.262ns (91.356%))
  Logic Levels:           1  (LUT2=1)
  Clock Path Skew:        -0.119ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.458ns = ( 5.792 - 3.334 ) 
    Source Clock Delay      (SCD):    2.813ns
    Clock Pessimism Removal (CPR):    0.236ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.727ns (routing 0.700ns, distribution 1.027ns)
  Clock Net Delay (Destination): 1.543ns (routing 0.635ns, distribution 0.908ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y4 (CLOCK_ROOT)    net (fo=18, routed)          1.727     2.813    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X95Y181        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/input_rst_design_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X95Y181        FDRE (Prop_DFF2_SLICEL_C_Q)
                                                      0.081     2.894 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/input_rst_design_reg/Q
                         net (fo=2, routed)           1.347     4.241    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/input_rst_design
    SLICE_X91Y294        LUT2 (Prop_D5LUT_SLICEL_I0_O)
                                                      0.133     4.374 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_async_mb_i_1/O
                         net (fo=1, routed)           0.915     5.289    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_async_mb_reg0
    SLICE_X92Y341        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_async_mb_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      3.334     3.334 r  
    J19                                               0.000     3.334 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.413    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.888 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.928    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.928 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     4.225    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     4.249 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y4 (CLOCK_ROOT)    net (fo=18, routed)          1.543     5.792    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X92Y341        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_async_mb_reg/C
                         clock pessimism              0.236     6.028    
                         clock uncertainty           -0.035     5.992    
    SLICE_X92Y341        FDRE (Setup_AFF2_SLICEL_C_D)
                                                      0.025     6.017    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_async_mb_reg
  -------------------------------------------------------------------
                         required time                          6.017    
                         arrival time                          -5.289    
  -------------------------------------------------------------------
                         slack                                  0.729    

Slack (MET) :             0.970ns  (required time - arrival time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_infrastructure/input_rst_design_reg/C
                            (rising edge-triggered cell FDRE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_async_riu_div_reg/D
                            (rising edge-triggered cell FDRE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Path Group:             sys_clk_ddr4_clk_p
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.334ns  (sys_clk_ddr4_clk_p rise@3.334ns - sys_clk_ddr4_clk_p rise@0.000ns)
  Data Path Delay:        2.240ns  (logic 0.170ns (7.590%)  route 2.070ns (92.410%))
  Logic Levels:           1  (LUT3=1)
  Clock Path Skew:        -0.114ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.463ns = ( 5.797 - 3.334 ) 
    Source Clock Delay      (SCD):    2.813ns
    Clock Pessimism Removal (CPR):    0.236ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.727ns (routing 0.700ns, distribution 1.027ns)
  Clock Net Delay (Destination): 1.548ns (routing 0.635ns, distribution 0.913ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y4 (CLOCK_ROOT)    net (fo=18, routed)          1.727     2.813    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X95Y181        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/input_rst_design_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X95Y181        FDRE (Prop_DFF2_SLICEL_C_Q)
                                                      0.081     2.894 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/input_rst_design_reg/Q
                         net (fo=2, routed)           1.342     4.236    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/input_rst_design
    SLICE_X91Y294        LUT3 (Prop_G6LUT_SLICEL_I1_O)
                                                      0.089     4.325 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_async_riu_div_i_1/O
                         net (fo=1, routed)           0.728     5.053    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_async_riu_div_reg0
    SLICE_X91Y355        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_async_riu_div_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      3.334     3.334 r  
    J19                                               0.000     3.334 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.413    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.888 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.928    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.928 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     4.225    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     4.249 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y4 (CLOCK_ROOT)    net (fo=18, routed)          1.548     5.797    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X91Y355        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_async_riu_div_reg/C
                         clock pessimism              0.236     6.033    
                         clock uncertainty           -0.035     5.997    
    SLICE_X91Y355        FDRE (Setup_AFF2_SLICEL_C_D)
                                                      0.025     6.022    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_async_riu_div_reg
  -------------------------------------------------------------------
                         required time                          6.022    
                         arrival time                          -5.053    
  -------------------------------------------------------------------
                         slack                                  0.970    

Slack (MET) :             2.176ns  (required time - arrival time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[6]/C
                            (rising edge-triggered cell FDRE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_infrastructure/input_rst_mmcm_reg/D
                            (rising edge-triggered cell FDRE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Path Group:             sys_clk_ddr4_clk_p
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.334ns  (sys_clk_ddr4_clk_p rise@3.334ns - sys_clk_ddr4_clk_p rise@0.000ns)
  Data Path Delay:        1.050ns  (logic 0.331ns (31.511%)  route 0.719ns (68.489%))
  Logic Levels:           2  (LUT3=1 LUT5=1)
  Clock Path Skew:        -0.098ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.442ns = ( 5.776 - 3.334 ) 
    Source Clock Delay      (SCD):    2.829ns
    Clock Pessimism Removal (CPR):    0.289ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.743ns (routing 0.700ns, distribution 1.043ns)
  Clock Net Delay (Destination): 1.527ns (routing 0.635ns, distribution 0.892ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y4 (CLOCK_ROOT)    net (fo=18, routed)          1.743     2.829    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X95Y180        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[6]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X95Y180        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     2.908 f  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[6]/Q
                         net (fo=7, routed)           0.113     3.021    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[6]
    SLICE_X95Y180        LUT3 (Prop_C5LUT_SLICEL_I2_O)
                                                      0.136     3.157 f  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/input_rst_mmcm_i_2/O
                         net (fo=1, routed)           0.206     3.363    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/input_rst_mmcm_i_2_n_0
    SLICE_X95Y180        LUT5 (Prop_B5LUT_SLICEL_I3_O)
                                                      0.116     3.479 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/input_rst_mmcm_i_1/O
                         net (fo=1, routed)           0.400     3.879    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/input_rst_mmcm_i_1_n_0
    SLICE_X91Y180        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/input_rst_mmcm_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      3.334     3.334 r  
    J19                                               0.000     3.334 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.413    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.888 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.928    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.928 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     4.225    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     4.249 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y4 (CLOCK_ROOT)    net (fo=18, routed)          1.527     5.776    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X91Y180        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/input_rst_mmcm_reg/C
                         clock pessimism              0.289     6.065    
                         clock uncertainty           -0.035     6.030    
    SLICE_X91Y180        FDRE (Setup_AFF_SLICEL_C_D)
                                                      0.025     6.055    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/input_rst_mmcm_reg
  -------------------------------------------------------------------
                         required time                          6.055    
                         arrival time                          -3.879    
  -------------------------------------------------------------------
                         slack                                  2.176    

Slack (MET) :             2.384ns  (required time - arrival time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[0]/R
                            (rising edge-triggered cell FDRE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Path Group:             sys_clk_ddr4_clk_p
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.334ns  (sys_clk_ddr4_clk_p rise@3.334ns - sys_clk_ddr4_clk_p rise@0.000ns)
  Data Path Delay:        0.832ns  (logic 0.350ns (42.079%)  route 0.482ns (57.921%))
  Logic Levels:           2  (LUT4=1 LUT5=1)
  Clock Path Skew:        -0.009ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.454ns = ( 5.788 - 3.334 ) 
    Source Clock Delay      (SCD):    2.829ns
    Clock Pessimism Removal (CPR):    0.366ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.743ns (routing 0.700ns, distribution 1.043ns)
  Clock Net Delay (Destination): 1.539ns (routing 0.635ns, distribution 0.904ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y4 (CLOCK_ROOT)    net (fo=18, routed)          1.743     2.829    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X95Y180        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X95Y180        FDRE (Prop_HFF_SLICEL_C_Q)
                                                      0.079     2.908 f  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[2]/Q
                         net (fo=4, routed)           0.180     3.088    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[2]
    SLICE_X95Y180        LUT4 (Prop_B6LUT_SLICEL_I2_O)
                                                      0.148     3.236 f  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[6]_i_3/O
                         net (fo=6, routed)           0.096     3.333    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[6]_i_3_n_0
    SLICE_X95Y181        LUT5 (Prop_F6LUT_SLICEL_I1_O)
                                                      0.123     3.456 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[6]_i_1/O
                         net (fo=4, routed)           0.205     3.661    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[6]_i_1_n_0
    SLICE_X95Y180        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[0]/R
  -------------------------------------------------------------------    -------------------

                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      3.334     3.334 r  
    J19                                               0.000     3.334 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.413    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.888 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.928    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.928 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     4.225    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     4.249 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y4 (CLOCK_ROOT)    net (fo=18, routed)          1.539     5.788    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X95Y180        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[0]/C
                         clock pessimism              0.366     6.154    
                         clock uncertainty           -0.035     6.118    
    SLICE_X95Y180        FDRE (Setup_GFF2_SLICEL_C_R)
                                                     -0.074     6.044    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[0]
  -------------------------------------------------------------------
                         required time                          6.044    
                         arrival time                          -3.661    
  -------------------------------------------------------------------
                         slack                                  2.384    

Slack (MET) :             2.384ns  (required time - arrival time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[2]/R
                            (rising edge-triggered cell FDRE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Path Group:             sys_clk_ddr4_clk_p
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.334ns  (sys_clk_ddr4_clk_p rise@3.334ns - sys_clk_ddr4_clk_p rise@0.000ns)
  Data Path Delay:        0.832ns  (logic 0.350ns (42.079%)  route 0.482ns (57.921%))
  Logic Levels:           2  (LUT4=1 LUT5=1)
  Clock Path Skew:        -0.009ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.454ns = ( 5.788 - 3.334 ) 
    Source Clock Delay      (SCD):    2.829ns
    Clock Pessimism Removal (CPR):    0.366ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.743ns (routing 0.700ns, distribution 1.043ns)
  Clock Net Delay (Destination): 1.539ns (routing 0.635ns, distribution 0.904ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y4 (CLOCK_ROOT)    net (fo=18, routed)          1.743     2.829    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X95Y180        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X95Y180        FDRE (Prop_HFF_SLICEL_C_Q)
                                                      0.079     2.908 f  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[2]/Q
                         net (fo=4, routed)           0.180     3.088    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[2]
    SLICE_X95Y180        LUT4 (Prop_B6LUT_SLICEL_I2_O)
                                                      0.148     3.236 f  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[6]_i_3/O
                         net (fo=6, routed)           0.096     3.333    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[6]_i_3_n_0
    SLICE_X95Y181        LUT5 (Prop_F6LUT_SLICEL_I1_O)
                                                      0.123     3.456 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[6]_i_1/O
                         net (fo=4, routed)           0.205     3.661    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[6]_i_1_n_0
    SLICE_X95Y180        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[2]/R
  -------------------------------------------------------------------    -------------------

                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      3.334     3.334 r  
    J19                                               0.000     3.334 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.413    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.888 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.928    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.928 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     4.225    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     4.249 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y4 (CLOCK_ROOT)    net (fo=18, routed)          1.539     5.788    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X95Y180        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[2]/C
                         clock pessimism              0.366     6.154    
                         clock uncertainty           -0.035     6.118    
    SLICE_X95Y180        FDRE (Setup_HFF_SLICEL_C_R)
                                                     -0.074     6.044    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[2]
  -------------------------------------------------------------------
                         required time                          6.044    
                         arrival time                          -3.661    
  -------------------------------------------------------------------
                         slack                                  2.384    

Slack (MET) :             2.384ns  (required time - arrival time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[3]/R
                            (rising edge-triggered cell FDRE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Path Group:             sys_clk_ddr4_clk_p
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.334ns  (sys_clk_ddr4_clk_p rise@3.334ns - sys_clk_ddr4_clk_p rise@0.000ns)
  Data Path Delay:        0.832ns  (logic 0.350ns (42.079%)  route 0.482ns (57.921%))
  Logic Levels:           2  (LUT4=1 LUT5=1)
  Clock Path Skew:        -0.009ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.454ns = ( 5.788 - 3.334 ) 
    Source Clock Delay      (SCD):    2.829ns
    Clock Pessimism Removal (CPR):    0.366ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.743ns (routing 0.700ns, distribution 1.043ns)
  Clock Net Delay (Destination): 1.539ns (routing 0.635ns, distribution 0.904ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y4 (CLOCK_ROOT)    net (fo=18, routed)          1.743     2.829    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X95Y180        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X95Y180        FDRE (Prop_HFF_SLICEL_C_Q)
                                                      0.079     2.908 f  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[2]/Q
                         net (fo=4, routed)           0.180     3.088    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[2]
    SLICE_X95Y180        LUT4 (Prop_B6LUT_SLICEL_I2_O)
                                                      0.148     3.236 f  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[6]_i_3/O
                         net (fo=6, routed)           0.096     3.333    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[6]_i_3_n_0
    SLICE_X95Y181        LUT5 (Prop_F6LUT_SLICEL_I1_O)
                                                      0.123     3.456 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[6]_i_1/O
                         net (fo=4, routed)           0.205     3.661    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[6]_i_1_n_0
    SLICE_X95Y180        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[3]/R
  -------------------------------------------------------------------    -------------------

                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      3.334     3.334 r  
    J19                                               0.000     3.334 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.413    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.888 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.928    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.928 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     4.225    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     4.249 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y4 (CLOCK_ROOT)    net (fo=18, routed)          1.539     5.788    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X95Y180        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[3]/C
                         clock pessimism              0.366     6.154    
                         clock uncertainty           -0.035     6.118    
    SLICE_X95Y180        FDRE (Setup_HFF2_SLICEL_C_R)
                                                     -0.074     6.044    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[3]
  -------------------------------------------------------------------
                         required time                          6.044    
                         arrival time                          -3.661    
  -------------------------------------------------------------------
                         slack                                  2.384    

Slack (MET) :             2.384ns  (required time - arrival time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[6]/R
                            (rising edge-triggered cell FDRE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Path Group:             sys_clk_ddr4_clk_p
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.334ns  (sys_clk_ddr4_clk_p rise@3.334ns - sys_clk_ddr4_clk_p rise@0.000ns)
  Data Path Delay:        0.832ns  (logic 0.350ns (42.079%)  route 0.482ns (57.921%))
  Logic Levels:           2  (LUT4=1 LUT5=1)
  Clock Path Skew:        -0.009ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.454ns = ( 5.788 - 3.334 ) 
    Source Clock Delay      (SCD):    2.829ns
    Clock Pessimism Removal (CPR):    0.366ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.743ns (routing 0.700ns, distribution 1.043ns)
  Clock Net Delay (Destination): 1.539ns (routing 0.635ns, distribution 0.904ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y4 (CLOCK_ROOT)    net (fo=18, routed)          1.743     2.829    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X95Y180        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X95Y180        FDRE (Prop_HFF_SLICEL_C_Q)
                                                      0.079     2.908 f  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[2]/Q
                         net (fo=4, routed)           0.180     3.088    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[2]
    SLICE_X95Y180        LUT4 (Prop_B6LUT_SLICEL_I2_O)
                                                      0.148     3.236 f  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[6]_i_3/O
                         net (fo=6, routed)           0.096     3.333    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[6]_i_3_n_0
    SLICE_X95Y181        LUT5 (Prop_F6LUT_SLICEL_I1_O)
                                                      0.123     3.456 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[6]_i_1/O
                         net (fo=4, routed)           0.205     3.661    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[6]_i_1_n_0
    SLICE_X95Y180        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[6]/R
  -------------------------------------------------------------------    -------------------

                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      3.334     3.334 r  
    J19                                               0.000     3.334 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.413    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.888 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.928    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.928 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     4.225    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     4.249 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y4 (CLOCK_ROOT)    net (fo=18, routed)          1.539     5.788    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X95Y180        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[6]/C
                         clock pessimism              0.366     6.154    
                         clock uncertainty           -0.035     6.118    
    SLICE_X95Y180        FDRE (Setup_EFF_SLICEL_C_R)
                                                     -0.074     6.044    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[6]
  -------------------------------------------------------------------
                         required time                          6.044    
                         arrival time                          -3.661    
  -------------------------------------------------------------------
                         slack                                  2.384    

Slack (MET) :             2.493ns  (required time - arrival time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[6]/D
                            (rising edge-triggered cell FDRE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Path Group:             sys_clk_ddr4_clk_p
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.334ns  (sys_clk_ddr4_clk_p rise@3.334ns - sys_clk_ddr4_clk_p rise@0.000ns)
  Data Path Delay:        0.822ns  (logic 0.315ns (38.323%)  route 0.507ns (61.677%))
  Logic Levels:           2  (LUT4=2)
  Clock Path Skew:        -0.009ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.454ns = ( 5.788 - 3.334 ) 
    Source Clock Delay      (SCD):    2.829ns
    Clock Pessimism Removal (CPR):    0.366ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.743ns (routing 0.700ns, distribution 1.043ns)
  Clock Net Delay (Destination): 1.539ns (routing 0.635ns, distribution 0.904ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y4 (CLOCK_ROOT)    net (fo=18, routed)          1.743     2.829    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X95Y180        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X95Y180        FDRE (Prop_HFF_SLICEL_C_Q)
                                                      0.079     2.908 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[2]/Q
                         net (fo=4, routed)           0.180     3.088    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[2]
    SLICE_X95Y180        LUT4 (Prop_B6LUT_SLICEL_I2_O)
                                                      0.148     3.236 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[6]_i_3/O
                         net (fo=6, routed)           0.104     3.341    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[6]_i_3_n_0
    SLICE_X95Y180        LUT4 (Prop_C6LUT_SLICEL_I0_O)
                                                      0.088     3.429 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[6]_i_2/O
                         net (fo=1, routed)           0.222     3.651    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst0[6]
    SLICE_X95Y180        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[6]/D
  -------------------------------------------------------------------    -------------------

                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      3.334     3.334 r  
    J19                                               0.000     3.334 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.413    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.888 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.928    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.928 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     4.225    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     4.249 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y4 (CLOCK_ROOT)    net (fo=18, routed)          1.539     5.788    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X95Y180        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[6]/C
                         clock pessimism              0.366     6.154    
                         clock uncertainty           -0.035     6.118    
    SLICE_X95Y180        FDRE (Setup_EFF_SLICEL_C_D)
                                                      0.025     6.143    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[6]
  -------------------------------------------------------------------
                         required time                          6.143    
                         arrival time                          -3.651    
  -------------------------------------------------------------------
                         slack                                  2.493    

Slack (MET) :             2.576ns  (required time - arrival time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[4]/D
                            (rising edge-triggered cell FDSE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Path Group:             sys_clk_ddr4_clk_p
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.334ns  (sys_clk_ddr4_clk_p rise@3.334ns - sys_clk_ddr4_clk_p rise@0.000ns)
  Data Path Delay:        0.721ns  (logic 0.373ns (51.737%)  route 0.348ns (48.263%))
  Logic Levels:           2  (LUT4=2)
  Clock Path Skew:        -0.027ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.452ns = ( 5.786 - 3.334 ) 
    Source Clock Delay      (SCD):    2.829ns
    Clock Pessimism Removal (CPR):    0.350ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.743ns (routing 0.700ns, distribution 1.043ns)
  Clock Net Delay (Destination): 1.537ns (routing 0.635ns, distribution 0.902ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y4 (CLOCK_ROOT)    net (fo=18, routed)          1.743     2.829    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X95Y180        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X95Y180        FDRE (Prop_HFF_SLICEL_C_Q)
                                                      0.079     2.908 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[2]/Q
                         net (fo=4, routed)           0.180     3.088    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[2]
    SLICE_X95Y180        LUT4 (Prop_B6LUT_SLICEL_I2_O)
                                                      0.148     3.236 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[6]_i_3/O
                         net (fo=6, routed)           0.118     3.355    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[6]_i_3_n_0
    SLICE_X95Y180        LUT4 (Prop_D6LUT_SLICEL_I0_O)
                                                      0.146     3.501 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[4]_i_1/O
                         net (fo=1, routed)           0.049     3.550    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[4]_i_1_n_0
    SLICE_X95Y180        FDSE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[4]/D
  -------------------------------------------------------------------    -------------------

                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      3.334     3.334 r  
    J19                                               0.000     3.334 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.413    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.888 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.928    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.928 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     4.225    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     4.249 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y4 (CLOCK_ROOT)    net (fo=18, routed)          1.537     5.786    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X95Y180        FDSE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[4]/C
                         clock pessimism              0.350     6.136    
                         clock uncertainty           -0.035     6.101    
    SLICE_X95Y180        FDSE (Setup_DFF_SLICEL_C_D)
                                                      0.025     6.126    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[4]
  -------------------------------------------------------------------
                         required time                          6.126    
                         arrival time                          -3.550    
  -------------------------------------------------------------------
                         slack                                  2.576    

Slack (MET) :             2.579ns  (required time - arrival time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[1]/D
                            (rising edge-triggered cell FDSE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Path Group:             sys_clk_ddr4_clk_p
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.334ns  (sys_clk_ddr4_clk_p rise@3.334ns - sys_clk_ddr4_clk_p rise@0.000ns)
  Data Path Delay:        0.718ns  (logic 0.376ns (52.388%)  route 0.342ns (47.612%))
  Logic Levels:           2  (LUT4=1 LUT6=1)
  Clock Path Skew:        -0.027ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.452ns = ( 5.786 - 3.334 ) 
    Source Clock Delay      (SCD):    2.829ns
    Clock Pessimism Removal (CPR):    0.350ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.743ns (routing 0.700ns, distribution 1.043ns)
  Clock Net Delay (Destination): 1.537ns (routing 0.635ns, distribution 0.902ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y4 (CLOCK_ROOT)    net (fo=18, routed)          1.743     2.829    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X95Y180        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X95Y180        FDRE (Prop_HFF_SLICEL_C_Q)
                                                      0.079     2.908 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[2]/Q
                         net (fo=4, routed)           0.180     3.088    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[2]
    SLICE_X95Y180        LUT4 (Prop_B6LUT_SLICEL_I2_O)
                                                      0.148     3.236 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[6]_i_3/O
                         net (fo=6, routed)           0.113     3.350    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[6]_i_3_n_0
    SLICE_X95Y180        LUT6 (Prop_A6LUT_SLICEL_I2_O)
                                                      0.149     3.499 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[1]_i_1/O
                         net (fo=1, routed)           0.048     3.547    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[1]_i_1_n_0
    SLICE_X95Y180        FDSE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      3.334     3.334 r  
    J19                                               0.000     3.334 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.413    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.888 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.928    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.928 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     4.225    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     4.249 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y4 (CLOCK_ROOT)    net (fo=18, routed)          1.537     5.786    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X95Y180        FDSE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[1]/C
                         clock pessimism              0.350     6.136    
                         clock uncertainty           -0.035     6.101    
    SLICE_X95Y180        FDSE (Setup_AFF_SLICEL_C_D)
                                                      0.025     6.126    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[1]
  -------------------------------------------------------------------
                         required time                          6.126    
                         arrival time                          -3.547    
  -------------------------------------------------------------------
                         slack                                  2.579    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.055ns  (arrival time - required time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[4]/C
                            (rising edge-triggered cell FDSE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[5]/D
                            (rising edge-triggered cell FDSE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Path Group:             sys_clk_ddr4_clk_p
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (sys_clk_ddr4_clk_p rise@0.000ns - sys_clk_ddr4_clk_p rise@0.000ns)
  Data Path Delay:        0.108ns  (logic 0.072ns (66.433%)  route 0.036ns (33.566%))
  Logic Levels:           1  (LUT4=1)
  Clock Path Skew:        0.006ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.881ns
    Source Clock Delay      (SCD):    1.581ns
    Clock Pessimism Removal (CPR):    0.294ns
  Clock Net Delay (Source):      0.964ns (routing 0.387ns, distribution 0.577ns)
  Clock Net Delay (Destination): 1.094ns (routing 0.434ns, distribution 0.660ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y4 (CLOCK_ROOT)    net (fo=18, routed)          0.964     1.581    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X95Y180        FDSE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X95Y180        FDSE (Prop_DFF_SLICEL_C_Q)
                                                      0.039     1.620 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[4]/Q
                         net (fo=7, routed)           0.030     1.650    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[4]
    SLICE_X95Y180        LUT4 (Prop_D5LUT_SLICEL_I2_O)
                                                      0.033     1.683 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[5]_i_1/O
                         net (fo=1, routed)           0.006     1.689    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[5]_i_1_n_0
    SLICE_X95Y180        FDSE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[5]/D
  -------------------------------------------------------------------    -------------------

                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y4 (CLOCK_ROOT)    net (fo=18, routed)          1.094     1.881    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X95Y180        FDSE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[5]/C
                         clock pessimism             -0.294     1.587    
    SLICE_X95Y180        FDSE (Hold_DFF2_SLICEL_C_D)
                                                      0.047     1.634    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[5]
  -------------------------------------------------------------------
                         required time                         -1.634    
                         arrival time                           1.689    
  -------------------------------------------------------------------
                         slack                                  0.055    

Slack (MET) :             0.056ns  (arrival time - required time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[4]/C
                            (rising edge-triggered cell FDSE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[1]/D
                            (rising edge-triggered cell FDSE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Path Group:             sys_clk_ddr4_clk_p
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (sys_clk_ddr4_clk_p rise@0.000ns - sys_clk_ddr4_clk_p rise@0.000ns)
  Data Path Delay:        0.108ns  (logic 0.061ns (56.284%)  route 0.047ns (43.716%))
  Logic Levels:           1  (LUT6=1)
  Clock Path Skew:        0.006ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.881ns
    Source Clock Delay      (SCD):    1.581ns
    Clock Pessimism Removal (CPR):    0.294ns
  Clock Net Delay (Source):      0.964ns (routing 0.387ns, distribution 0.577ns)
  Clock Net Delay (Destination): 1.094ns (routing 0.434ns, distribution 0.660ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y4 (CLOCK_ROOT)    net (fo=18, routed)          0.964     1.581    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X95Y180        FDSE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X95Y180        FDSE (Prop_DFF_SLICEL_C_Q)
                                                      0.039     1.620 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[4]/Q
                         net (fo=7, routed)           0.031     1.651    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[4]
    SLICE_X95Y180        LUT6 (Prop_A6LUT_SLICEL_I4_O)
                                                      0.022     1.673 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[1]_i_1/O
                         net (fo=1, routed)           0.016     1.689    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[1]_i_1_n_0
    SLICE_X95Y180        FDSE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y4 (CLOCK_ROOT)    net (fo=18, routed)          1.094     1.881    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X95Y180        FDSE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[1]/C
                         clock pessimism             -0.294     1.587    
    SLICE_X95Y180        FDSE (Hold_AFF_SLICEL_C_D)
                                                      0.046     1.633    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[1]
  -------------------------------------------------------------------
                         required time                         -1.633    
                         arrival time                           1.689    
  -------------------------------------------------------------------
                         slack                                  0.056    

Slack (MET) :             0.068ns  (arrival time - required time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[4]/C
                            (rising edge-triggered cell FDSE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_infrastructure/input_rst_design_reg/D
                            (rising edge-triggered cell FDRE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Path Group:             sys_clk_ddr4_clk_p
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (sys_clk_ddr4_clk_p rise@0.000ns - sys_clk_ddr4_clk_p rise@0.000ns)
  Data Path Delay:        0.129ns  (logic 0.072ns (55.606%)  route 0.057ns (44.394%))
  Logic Levels:           1  (LUT4=1)
  Clock Path Skew:        0.015ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.877ns
    Source Clock Delay      (SCD):    1.581ns
    Clock Pessimism Removal (CPR):    0.282ns
  Clock Net Delay (Source):      0.964ns (routing 0.387ns, distribution 0.577ns)
  Clock Net Delay (Destination): 1.090ns (routing 0.434ns, distribution 0.656ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y4 (CLOCK_ROOT)    net (fo=18, routed)          0.964     1.581    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X95Y180        FDSE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X95Y180        FDSE (Prop_DFF_SLICEL_C_Q)
                                                      0.039     1.620 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[4]/Q
                         net (fo=7, routed)           0.051     1.671    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[4]
    SLICE_X95Y181        LUT4 (Prop_D5LUT_SLICEL_I1_O)
                                                      0.033     1.704 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/input_rst_design_i_1/O
                         net (fo=1, routed)           0.006     1.710    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/input_rst_design_i_1_n_0
    SLICE_X95Y181        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/input_rst_design_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y4 (CLOCK_ROOT)    net (fo=18, routed)          1.090     1.877    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X95Y181        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/input_rst_design_reg/C
                         clock pessimism             -0.282     1.595    
    SLICE_X95Y181        FDRE (Hold_DFF2_SLICEL_C_D)
                                                      0.047     1.642    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/input_rst_design_reg
  -------------------------------------------------------------------
                         required time                         -1.642    
                         arrival time                           1.710    
  -------------------------------------------------------------------
                         slack                                  0.068    

Slack (MET) :             0.068ns  (arrival time - required time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[4]/C
                            (rising edge-triggered cell FDSE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[4]/D
                            (rising edge-triggered cell FDSE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Path Group:             sys_clk_ddr4_clk_p
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (sys_clk_ddr4_clk_p rise@0.000ns - sys_clk_ddr4_clk_p rise@0.000ns)
  Data Path Delay:        0.120ns  (logic 0.074ns (61.472%)  route 0.046ns (38.527%))
  Logic Levels:           1  (LUT4=1)
  Clock Path Skew:        0.006ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.881ns
    Source Clock Delay      (SCD):    1.581ns
    Clock Pessimism Removal (CPR):    0.294ns
  Clock Net Delay (Source):      0.964ns (routing 0.387ns, distribution 0.577ns)
  Clock Net Delay (Destination): 1.094ns (routing 0.434ns, distribution 0.660ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y4 (CLOCK_ROOT)    net (fo=18, routed)          0.964     1.581    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X95Y180        FDSE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X95Y180        FDSE (Prop_DFF_SLICEL_C_Q)
                                                      0.039     1.620 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[4]/Q
                         net (fo=7, routed)           0.030     1.650    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[4]
    SLICE_X95Y180        LUT4 (Prop_D6LUT_SLICEL_I2_O)
                                                      0.035     1.685 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[4]_i_1/O
                         net (fo=1, routed)           0.016     1.701    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[4]_i_1_n_0
    SLICE_X95Y180        FDSE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[4]/D
  -------------------------------------------------------------------    -------------------

                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y4 (CLOCK_ROOT)    net (fo=18, routed)          1.094     1.881    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X95Y180        FDSE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[4]/C
                         clock pessimism             -0.294     1.587    
    SLICE_X95Y180        FDSE (Hold_DFF_SLICEL_C_D)
                                                      0.046     1.633    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[4]
  -------------------------------------------------------------------
                         required time                         -1.633    
                         arrival time                           1.701    
  -------------------------------------------------------------------
                         slack                                  0.068    

Slack (MET) :             0.079ns  (arrival time - required time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r_reg[3]/D
                            (rising edge-triggered cell FDRE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Path Group:             sys_clk_ddr4_clk_p
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (sys_clk_ddr4_clk_p rise@0.000ns - sys_clk_ddr4_clk_p rise@0.000ns)
  Data Path Delay:        0.132ns  (logic 0.039ns (29.545%)  route 0.093ns (70.455%))
  Logic Levels:           0  
  Clock Path Skew:        0.006ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.885ns
    Source Clock Delay      (SCD):    1.582ns
    Clock Pessimism Removal (CPR):    0.297ns
  Clock Net Delay (Source):      0.965ns (routing 0.387ns, distribution 0.578ns)
  Clock Net Delay (Destination): 1.098ns (routing 0.434ns, distribution 0.664ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y4 (CLOCK_ROOT)    net (fo=18, routed)          0.965     1.582    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X96Y181        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X96Y181        FDRE (Prop_CFF2_SLICEM_C_Q)
                                                      0.039     1.621 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r_reg[2]/Q
                         net (fo=1, routed)           0.093     1.714    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r[2]
    SLICE_X96Y181        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r_reg[3]/D
  -------------------------------------------------------------------    -------------------

                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y4 (CLOCK_ROOT)    net (fo=18, routed)          1.098     1.885    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X96Y181        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r_reg[3]/C
                         clock pessimism             -0.297     1.588    
    SLICE_X96Y181        FDRE (Hold_DFF2_SLICEM_C_D)
                                                      0.047     1.635    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r_reg[3]
  -------------------------------------------------------------------
                         required time                         -1.635    
                         arrival time                           1.714    
  -------------------------------------------------------------------
                         slack                                  0.079    

Slack (MET) :             0.086ns  (arrival time - required time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_input_async_reg[1]/C
                            (rising edge-triggered cell FDPE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Path Group:             sys_clk_ddr4_clk_p
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (sys_clk_ddr4_clk_p rise@0.000ns - sys_clk_ddr4_clk_p rise@0.000ns)
  Data Path Delay:        0.153ns  (logic 0.040ns (26.144%)  route 0.113ns (73.856%))
  Logic Levels:           0  
  Clock Path Skew:        0.020ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.885ns
    Source Clock Delay      (SCD):    1.582ns
    Clock Pessimism Removal (CPR):    0.282ns
  Clock Net Delay (Source):      0.965ns (routing 0.387ns, distribution 0.578ns)
  Clock Net Delay (Destination): 1.098ns (routing 0.434ns, distribution 0.664ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y4 (CLOCK_ROOT)    net (fo=18, routed)          0.965     1.582    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X96Y180        FDPE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_input_async_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X96Y180        FDPE (Prop_BFF2_SLICEM_C_Q)
                                                      0.040     1.622 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_input_async_reg[1]/Q
                         net (fo=1, routed)           0.113     1.735    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_input_async[1]
    SLICE_X96Y181        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y4 (CLOCK_ROOT)    net (fo=18, routed)          1.098     1.885    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X96Y181        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r_reg[0]/C
                         clock pessimism             -0.282     1.602    
    SLICE_X96Y181        FDRE (Hold_AFF2_SLICEM_C_D)
                                                      0.047     1.649    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r_reg[0]
  -------------------------------------------------------------------
                         required time                         -1.649    
                         arrival time                           1.735    
  -------------------------------------------------------------------
                         slack                                  0.086    

Slack (MET) :             0.093ns  (arrival time - required time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r_reg[1]/D
                            (rising edge-triggered cell FDRE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Path Group:             sys_clk_ddr4_clk_p
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (sys_clk_ddr4_clk_p rise@0.000ns - sys_clk_ddr4_clk_p rise@0.000ns)
  Data Path Delay:        0.146ns  (logic 0.039ns (26.712%)  route 0.107ns (73.288%))
  Logic Levels:           0  
  Clock Path Skew:        0.006ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.885ns
    Source Clock Delay      (SCD):    1.582ns
    Clock Pessimism Removal (CPR):    0.297ns
  Clock Net Delay (Source):      0.965ns (routing 0.387ns, distribution 0.578ns)
  Clock Net Delay (Destination): 1.098ns (routing 0.434ns, distribution 0.664ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y4 (CLOCK_ROOT)    net (fo=18, routed)          0.965     1.582    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X96Y181        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X96Y181        FDRE (Prop_AFF2_SLICEM_C_Q)
                                                      0.039     1.621 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r_reg[0]/Q
                         net (fo=1, routed)           0.107     1.728    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r[0]
    SLICE_X96Y181        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y4 (CLOCK_ROOT)    net (fo=18, routed)          1.098     1.885    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X96Y181        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r_reg[1]/C
                         clock pessimism             -0.297     1.588    
    SLICE_X96Y181        FDRE (Hold_BFF2_SLICEM_C_D)
                                                      0.047     1.635    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r_reg[1]
  -------------------------------------------------------------------
                         required time                         -1.635    
                         arrival time                           1.728    
  -------------------------------------------------------------------
                         slack                                  0.093    

Slack (MET) :             0.094ns  (arrival time - required time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[3]/D
                            (rising edge-triggered cell FDRE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Path Group:             sys_clk_ddr4_clk_p
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (sys_clk_ddr4_clk_p rise@0.000ns - sys_clk_ddr4_clk_p rise@0.000ns)
  Data Path Delay:        0.147ns  (logic 0.059ns (40.132%)  route 0.088ns (59.868%))
  Logic Levels:           1  (LUT4=1)
  Clock Path Skew:        0.006ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.885ns
    Source Clock Delay      (SCD):    1.584ns
    Clock Pessimism Removal (CPR):    0.295ns
  Clock Net Delay (Source):      0.967ns (routing 0.387ns, distribution 0.580ns)
  Clock Net Delay (Destination): 1.098ns (routing 0.434ns, distribution 0.664ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y4 (CLOCK_ROOT)    net (fo=18, routed)          0.967     1.584    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X95Y180        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X95Y180        FDRE (Prop_HFF_SLICEL_C_Q)
                                                      0.039     1.623 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[2]/Q
                         net (fo=4, routed)           0.082     1.705    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[2]
    SLICE_X95Y180        LUT4 (Prop_H5LUT_SLICEL_I1_O)
                                                      0.020     1.725 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[3]_i_1/O
                         net (fo=1, routed)           0.006     1.731    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst0[3]
    SLICE_X95Y180        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[3]/D
  -------------------------------------------------------------------    -------------------

                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y4 (CLOCK_ROOT)    net (fo=18, routed)          1.098     1.885    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X95Y180        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[3]/C
                         clock pessimism             -0.295     1.590    
    SLICE_X95Y180        FDRE (Hold_HFF2_SLICEL_C_D)
                                                      0.047     1.637    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[3]
  -------------------------------------------------------------------
                         required time                         -1.637    
                         arrival time                           1.731    
  -------------------------------------------------------------------
                         slack                                  0.094    

Slack (MET) :             0.096ns  (arrival time - required time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_input_async_reg[0]/C
                            (rising edge-triggered cell FDPE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_input_async_reg[1]/D
                            (rising edge-triggered cell FDPE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Path Group:             sys_clk_ddr4_clk_p
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (sys_clk_ddr4_clk_p rise@0.000ns - sys_clk_ddr4_clk_p rise@0.000ns)
  Data Path Delay:        0.149ns  (logic 0.039ns (26.174%)  route 0.110ns (73.825%))
  Logic Levels:           0  
  Clock Path Skew:        0.006ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.885ns
    Source Clock Delay      (SCD):    1.582ns
    Clock Pessimism Removal (CPR):    0.297ns
  Clock Net Delay (Source):      0.965ns (routing 0.387ns, distribution 0.578ns)
  Clock Net Delay (Destination): 1.098ns (routing 0.434ns, distribution 0.664ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y4 (CLOCK_ROOT)    net (fo=18, routed)          0.965     1.582    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X96Y180        FDPE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_input_async_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X96Y180        FDPE (Prop_AFF2_SLICEM_C_Q)
                                                      0.039     1.621 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_input_async_reg[0]/Q
                         net (fo=1, routed)           0.110     1.731    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_input_async[0]
    SLICE_X96Y180        FDPE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_input_async_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y4 (CLOCK_ROOT)    net (fo=18, routed)          1.098     1.885    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X96Y180        FDPE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_input_async_reg[1]/C
                         clock pessimism             -0.297     1.588    
    SLICE_X96Y180        FDPE (Hold_BFF2_SLICEM_C_D)
                                                      0.047     1.635    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_input_async_reg[1]
  -------------------------------------------------------------------
                         required time                         -1.635    
                         arrival time                           1.731    
  -------------------------------------------------------------------
                         slack                                  0.096    

Slack (MET) :             0.109ns  (arrival time - required time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[2]/D
                            (rising edge-triggered cell FDRE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Path Group:             sys_clk_ddr4_clk_p
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (sys_clk_ddr4_clk_p rise@0.000ns - sys_clk_ddr4_clk_p rise@0.000ns)
  Data Path Delay:        0.161ns  (logic 0.062ns (38.505%)  route 0.099ns (61.495%))
  Logic Levels:           1  (LUT3=1)
  Clock Path Skew:        0.006ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.885ns
    Source Clock Delay      (SCD):    1.584ns
    Clock Pessimism Removal (CPR):    0.295ns
  Clock Net Delay (Source):      0.967ns (routing 0.387ns, distribution 0.580ns)
  Clock Net Delay (Destination): 1.098ns (routing 0.434ns, distribution 0.664ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y4 (CLOCK_ROOT)    net (fo=18, routed)          0.967     1.584    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X95Y180        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X95Y180        FDRE (Prop_HFF_SLICEL_C_Q)
                                                      0.039     1.623 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[2]/Q
                         net (fo=4, routed)           0.082     1.705    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[2]
    SLICE_X95Y180        LUT3 (Prop_H6LUT_SLICEL_I2_O)
                                                      0.023     1.728 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[2]_i_1/O
                         net (fo=1, routed)           0.017     1.745    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst0[2]
    SLICE_X95Y180        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[2]/D
  -------------------------------------------------------------------    -------------------

                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y4 (CLOCK_ROOT)    net (fo=18, routed)          1.098     1.885    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X95Y180        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[2]/C
                         clock pessimism             -0.295     1.590    
    SLICE_X95Y180        FDRE (Hold_HFF_SLICEL_C_D)
                                                      0.046     1.636    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[2]
  -------------------------------------------------------------------
                         required time                         -1.636    
                         arrival time                           1.745    
  -------------------------------------------------------------------
                         slack                                  0.109    





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         sys_clk_ddr4_clk_p
Waveform(ns):       { 0.000 1.667 }
Period(ns):         3.334
Sources:            { sys_clk_ddr4_clk_p }

Check Type        Corner  Lib Pin            Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location       Pin
Min Period        n/a     BUFGCE/I           n/a            1.290         3.334       2.044      BUFGCE_X0Y123  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/I
Min Period        n/a     MMCME4_ADV/CLKIN1  n/a            1.071         3.334       2.263      MMCM_X0Y4      d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKIN1
Min Period        n/a     FDRE/C             n/a            0.550         3.334       2.784      SLICE_X95Y180  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[0]/C
Min Period        n/a     FDSE/C             n/a            0.550         3.334       2.784      SLICE_X95Y180  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[1]/C
Min Period        n/a     FDRE/C             n/a            0.550         3.334       2.784      SLICE_X95Y180  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[2]/C
Min Period        n/a     FDRE/C             n/a            0.550         3.334       2.784      SLICE_X95Y180  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[3]/C
Min Period        n/a     FDSE/C             n/a            0.550         3.334       2.784      SLICE_X95Y180  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[4]/C
Min Period        n/a     FDSE/C             n/a            0.550         3.334       2.784      SLICE_X95Y180  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[5]/C
Min Period        n/a     FDRE/C             n/a            0.550         3.334       2.784      SLICE_X95Y180  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[6]/C
Min Period        n/a     FDRE/C             n/a            0.550         3.334       2.784      SLICE_X95Y181  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/input_rst_design_reg/C
Max Period        n/a     MMCME4_ADV/CLKIN1  n/a            100.000       3.334       96.666     MMCM_X0Y4      d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKIN1
Low Pulse Width   Slow    MMCME4_ADV/CLKIN1  n/a            1.167         1.667       0.500      MMCM_X0Y4      d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKIN1
Low Pulse Width   Fast    MMCME4_ADV/CLKIN1  n/a            1.167         1.667       0.500      MMCM_X0Y4      d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKIN1
Low Pulse Width   Slow    FDRE/C             n/a            0.275         1.667       1.392      SLICE_X95Y180  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[0]/C
Low Pulse Width   Fast    FDRE/C             n/a            0.275         1.667       1.392      SLICE_X95Y180  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[0]/C
Low Pulse Width   Slow    FDSE/C             n/a            0.275         1.667       1.392      SLICE_X95Y180  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[1]/C
Low Pulse Width   Fast    FDSE/C             n/a            0.275         1.667       1.392      SLICE_X95Y180  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[1]/C
Low Pulse Width   Slow    FDRE/C             n/a            0.275         1.667       1.392      SLICE_X95Y180  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[2]/C
Low Pulse Width   Fast    FDRE/C             n/a            0.275         1.667       1.392      SLICE_X95Y180  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[2]/C
Low Pulse Width   Slow    FDRE/C             n/a            0.275         1.667       1.392      SLICE_X95Y180  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[3]/C
Low Pulse Width   Fast    FDRE/C             n/a            0.275         1.667       1.392      SLICE_X95Y180  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[3]/C
High Pulse Width  Slow    MMCME4_ADV/CLKIN1  n/a            1.167         1.667       0.500      MMCM_X0Y4      d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKIN1
High Pulse Width  Fast    MMCME4_ADV/CLKIN1  n/a            1.167         1.667       0.500      MMCM_X0Y4      d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKIN1
High Pulse Width  Slow    FDRE/C             n/a            0.275         1.667       1.392      SLICE_X95Y180  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[0]/C
High Pulse Width  Fast    FDRE/C             n/a            0.275         1.667       1.392      SLICE_X95Y180  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[0]/C
High Pulse Width  Slow    FDSE/C             n/a            0.275         1.667       1.392      SLICE_X95Y180  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[1]/C
High Pulse Width  Fast    FDSE/C             n/a            0.275         1.667       1.392      SLICE_X95Y180  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[1]/C
High Pulse Width  Slow    FDRE/C             n/a            0.275         1.667       1.392      SLICE_X95Y180  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[2]/C
High Pulse Width  Fast    FDRE/C             n/a            0.275         1.667       1.392      SLICE_X95Y180  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[2]/C
High Pulse Width  Slow    FDRE/C             n/a            0.275         1.667       1.392      SLICE_X95Y180  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[3]/C
High Pulse Width  Fast    FDRE/C             n/a            0.275         1.667       1.392      SLICE_X95Y180  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[3]/C



---------------------------------------------------------------------------------------------------
From Clock:  mmcm_clkout0
  To Clock:  mmcm_clkout0

Setup :            0  Failing Endpoints,  Worst Slack        0.019ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.010ns,  Total Violation        0.000ns
PW    :            0  Failing Endpoints,  Worst Slack        0.000ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.019ns  (required time - arrival time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[2].u_ddr_mc_group/txn_fifo_output_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[2].u_ddr_mc_group/txn_fifo_output_reg[31]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (mmcm_clkout0 rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        2.850ns  (logic 0.871ns (30.556%)  route 1.979ns (69.444%))
  Logic Levels:           8  (CARRY8=1 LUT5=1 LUT6=6)
  Clock Path Skew:        -0.094ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.854ns = ( 7.855 - 3.001 ) 
    Source Clock Delay      (SCD):    4.695ns
    Clock Pessimism Removal (CPR):    -0.253ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.940ns (routing 0.696ns, distribution 1.244ns)
  Clock Net Delay (Destination): 1.707ns (routing 0.630ns, distribution 1.077ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.524     2.610    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.483 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.244     2.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.755 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.940     4.695    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[2].u_ddr_mc_group/rst_r1_reg_0
    SLICE_X85Y346        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[2].u_ddr_mc_group/txn_fifo_output_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X85Y346        FDRE (Prop_GFF_SLICEL_C_Q)
                                                      0.079     4.774 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[2].u_ddr_mc_group/txn_fifo_output_reg[1]/Q
                         net (fo=48, routed)          0.481     5.255    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[2].u_ddr_mc_group/Q[1]
    SLICE_X87Y351        LUT6 (Prop_E6LUT_SLICEM_I3_O)
                                                      0.148     5.403 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[2].u_ddr_mc_group/i__carry_i_19__1/O
                         net (fo=1, routed)           0.137     5.540    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[2].u_ddr_mc_group/i__carry_i_19__1_n_0
    SLICE_X88Y350        LUT6 (Prop_B6LUT_SLICEL_I5_O)
                                                      0.098     5.638 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[2].u_ddr_mc_group/i__carry_i_5__1/O
                         net (fo=1, routed)           0.009     5.647    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[2].u_ddr_mc_group/i__carry_i_5__1_n_0
    SLICE_X88Y350        CARRY8 (Prop_CARRY8_SLICEL_S[1]_CO[5])
                                                      0.195     5.842 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[2].u_ddr_mc_group/issue_cas3_inferred__0/i__carry/CO[5]
                         net (fo=5, routed)           0.483     6.325    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[2].u_ddr_mc_group/issue_cas3_inferred__0/i__carry_n_2
    SLICE_X86Y337        LUT5 (Prop_A6LUT_SLICEM_I2_O)
                                                      0.038     6.363 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[2].u_ddr_mc_group/FSM_sequential_grSt[1]_i_6__0/O
                         net (fo=1, routed)           0.043     6.406    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[2].u_ddr_mc_group/FSM_sequential_grSt[1]_i_6__0_n_0
    SLICE_X86Y337        LUT6 (Prop_C6LUT_SLICEM_I3_O)
                                                      0.037     6.443 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[2].u_ddr_mc_group/FSM_sequential_grSt[1]_i_2__1/O
                         net (fo=4, routed)           0.039     6.482    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[2].u_ddr_mc_group/FSM_sequential_grSt[1]_i_2__1_n_0
    SLICE_X86Y337        LUT6 (Prop_B6LUT_SLICEM_I0_O)
                                                      0.089     6.571 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[2].u_ddr_mc_group/cas_fifo_wptr[1]_i_2__1/O
                         net (fo=75, routed)          0.469     7.040    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[2].u_ddr_mc_group/cas_fifo_wptr[1]_i_2__1_n_0
    SLICE_X84Y328        LUT6 (Prop_H6LUT_SLICEL_I4_O)
                                                      0.090     7.130 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[2].u_ddr_mc_group/txn_fifo_output[31]_i_2__1/O
                         net (fo=1, routed)           0.267     7.397    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[2].u_ddr_mc_group/txn_fifo_output[31]_i_2__1_n_0
    SLICE_X84Y329        LUT6 (Prop_F6LUT_SLICEL_I2_O)
                                                      0.097     7.494 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[2].u_ddr_mc_group/txn_fifo_output[31]_i_1__1/O
                         net (fo=1, routed)           0.051     7.545    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[2].u_ddr_mc_group/txn_fifo_output[31]_i_1__1_n_0
    SLICE_X84Y329        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[2].u_ddr_mc_group/txn_fifo_output_reg[31]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      3.001     3.001 r  
    J19                                               0.000     3.001 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.555 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.595    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.595 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     3.892    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.916 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.364     5.280    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.910 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.214     6.124    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     6.148 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.707     7.855    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[2].u_ddr_mc_group/rst_r1_reg_0
    SLICE_X84Y329        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[2].u_ddr_mc_group/txn_fifo_output_reg[31]/C
                         clock pessimism             -0.253     7.602    
                         clock uncertainty           -0.062     7.539    
    SLICE_X84Y329        FDRE (Setup_FFF_SLICEL_C_D)
                                                      0.025     7.564    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[2].u_ddr_mc_group/txn_fifo_output_reg[31]
  -------------------------------------------------------------------
                         required time                          7.564    
                         arrival time                          -7.545    
  -------------------------------------------------------------------
                         slack                                  0.019    

Slack (MET) :             0.040ns  (required time - arrival time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_ui/u_ddr_ui_wr_data/data_buf_addr_cnt_r_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[1].u_ddr_mc_group/cas_dbuf_fifo_reg[2][0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (mmcm_clkout0 rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        2.790ns  (logic 0.646ns (23.155%)  route 2.144ns (76.845%))
  Logic Levels:           5  (LUT3=1 LUT4=1 LUT5=1 LUT6=1 RAMD32=1)
  Clock Path Skew:        -0.133ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.858ns = ( 7.858 - 3.001 ) 
    Source Clock Delay      (SCD):    4.673ns
    Clock Pessimism Removal (CPR):    -0.318ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.918ns (routing 0.696ns, distribution 1.222ns)
  Clock Net Delay (Destination): 1.711ns (routing 0.630ns, distribution 1.081ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.524     2.610    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.483 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.244     2.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.755 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.918     4.673    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_ui/u_ddr_ui_wr_data/rd_data_indx_r_reg[3]_0
    SLICE_X84Y278        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_ui/u_ddr_ui_wr_data/data_buf_addr_cnt_r_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X84Y278        FDRE (Prop_HFF_SLICEL_C_Q)
                                                      0.079     4.752 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_ui/u_ddr_ui_wr_data/data_buf_addr_cnt_r_reg[0]/Q
                         net (fo=8, routed)           0.351     5.103    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_ui/u_ddr_ui_wr_data/rams[0].RAM32M0/ADDRB0
    SLICE_X86Y277        RAMD32 (Prop_F5LUT_SLICEM_RADR0_O)
                                                      0.166     5.269 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_ui/u_ddr_ui_wr_data/rams[0].RAM32M0/RAMB/O
                         net (fo=1, routed)           0.368     5.637    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_ui/u_ddr_ui_wr_data/wr_data_buf_addr[0]
    SLICE_X85Y287        LUT3 (Prop_F5LUT_SLICEL_I0_O)
                                                      0.118     5.755 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_ui/u_ddr_ui_wr_data/buf_fifo[0][0]_i_4/O
                         net (fo=4, routed)           0.460     6.215    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_ui/u_ddr_ui_wr_data/rams[0].RAM32M0_0
    SLICE_X87Y315        LUT5 (Prop_G6LUT_SLICEM_I0_O)
                                                      0.037     6.252 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_ui/u_ddr_ui_wr_data/buf_fifo[0][0]_i_2__1/O
                         net (fo=4, routed)           0.228     6.480    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[1].u_ddr_mc_group/buf_fifo_reg[1][0]_1
    SLICE_X88Y316        LUT4 (Prop_C5LUT_SLICEL_I3_O)
                                                      0.158     6.638 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[1].u_ddr_mc_group/buf_fifo[3][0]_i_1__1/O
                         net (fo=2, routed)           0.223     6.861    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[1].u_ddr_mc_group/buf_fifo[3][0]_i_1__1_n_0
    SLICE_X89Y316        LUT6 (Prop_F6LUT_SLICEM_I5_O)
                                                      0.088     6.949 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[1].u_ddr_mc_group/cas_dbuf_fifo[0][0]_i_1__1/O
                         net (fo=4, routed)           0.514     7.463    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[1].u_ddr_mc_group/cas_dbuf_fifo[0][0]_i_1__1_n_0
    SLICE_X89Y329        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[1].u_ddr_mc_group/cas_dbuf_fifo_reg[2][0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      3.001     3.001 r  
    J19                                               0.000     3.001 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.555 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.595    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.595 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     3.892    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.916 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.364     5.280    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.910 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.214     6.124    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     6.148 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.711     7.858    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[1].u_ddr_mc_group/cmdGroupP_reg[0]_0
    SLICE_X89Y329        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[1].u_ddr_mc_group/cas_dbuf_fifo_reg[2][0]/C
                         clock pessimism             -0.318     7.540    
                         clock uncertainty           -0.062     7.478    
    SLICE_X89Y329        FDRE (Setup_DFF2_SLICEM_C_D)
                                                      0.025     7.503    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[1].u_ddr_mc_group/cas_dbuf_fifo_reg[2][0]
  -------------------------------------------------------------------
                         required time                          7.503    
                         arrival time                          -7.463    
  -------------------------------------------------------------------
                         slack                                  0.040    

Slack (MET) :             0.058ns  (required time - arrival time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[2].u_ddr_mc_group/txn_fifo_output_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[2].u_ddr_mc_group/txn_fifo_output_reg[32]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (mmcm_clkout0 rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        2.823ns  (logic 0.880ns (31.171%)  route 1.943ns (68.829%))
  Logic Levels:           8  (CARRY8=1 LUT5=1 LUT6=6)
  Clock Path Skew:        -0.082ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.865ns = ( 7.866 - 3.001 ) 
    Source Clock Delay      (SCD):    4.695ns
    Clock Pessimism Removal (CPR):    -0.253ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.940ns (routing 0.696ns, distribution 1.244ns)
  Clock Net Delay (Destination): 1.718ns (routing 0.630ns, distribution 1.088ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.524     2.610    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.483 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.244     2.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.755 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.940     4.695    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[2].u_ddr_mc_group/rst_r1_reg_0
    SLICE_X85Y346        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[2].u_ddr_mc_group/txn_fifo_output_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X85Y346        FDRE (Prop_GFF_SLICEL_C_Q)
                                                      0.079     4.774 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[2].u_ddr_mc_group/txn_fifo_output_reg[1]/Q
                         net (fo=48, routed)          0.481     5.255    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[2].u_ddr_mc_group/Q[1]
    SLICE_X87Y351        LUT6 (Prop_E6LUT_SLICEM_I3_O)
                                                      0.148     5.403 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[2].u_ddr_mc_group/i__carry_i_19__1/O
                         net (fo=1, routed)           0.137     5.540    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[2].u_ddr_mc_group/i__carry_i_19__1_n_0
    SLICE_X88Y350        LUT6 (Prop_B6LUT_SLICEL_I5_O)
                                                      0.098     5.638 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[2].u_ddr_mc_group/i__carry_i_5__1/O
                         net (fo=1, routed)           0.009     5.647    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[2].u_ddr_mc_group/i__carry_i_5__1_n_0
    SLICE_X88Y350        CARRY8 (Prop_CARRY8_SLICEL_S[1]_CO[5])
                                                      0.195     5.842 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[2].u_ddr_mc_group/issue_cas3_inferred__0/i__carry/CO[5]
                         net (fo=5, routed)           0.483     6.325    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[2].u_ddr_mc_group/issue_cas3_inferred__0/i__carry_n_2
    SLICE_X86Y337        LUT5 (Prop_A6LUT_SLICEM_I2_O)
                                                      0.038     6.363 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[2].u_ddr_mc_group/FSM_sequential_grSt[1]_i_6__0/O
                         net (fo=1, routed)           0.043     6.406    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[2].u_ddr_mc_group/FSM_sequential_grSt[1]_i_6__0_n_0
    SLICE_X86Y337        LUT6 (Prop_C6LUT_SLICEM_I3_O)
                                                      0.037     6.443 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[2].u_ddr_mc_group/FSM_sequential_grSt[1]_i_2__1/O
                         net (fo=4, routed)           0.039     6.482    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[2].u_ddr_mc_group/FSM_sequential_grSt[1]_i_2__1_n_0
    SLICE_X86Y337        LUT6 (Prop_B6LUT_SLICEM_I0_O)
                                                      0.089     6.571 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[2].u_ddr_mc_group/cas_fifo_wptr[1]_i_2__1/O
                         net (fo=75, routed)          0.496     7.067    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[2].u_ddr_mc_group/cas_fifo_wptr[1]_i_2__1_n_0
    SLICE_X88Y323        LUT6 (Prop_G6LUT_SLICEL_I4_O)
                                                      0.050     7.117 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[2].u_ddr_mc_group/txn_fifo_output[32]_i_2__1/O
                         net (fo=1, routed)           0.206     7.323    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[2].u_ddr_mc_group/txn_fifo_output[32]_i_2__1_n_0
    SLICE_X88Y323        LUT6 (Prop_D6LUT_SLICEL_I2_O)
                                                      0.146     7.469 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[2].u_ddr_mc_group/txn_fifo_output[32]_i_1__1/O
                         net (fo=1, routed)           0.049     7.518    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[2].u_ddr_mc_group/txn_fifo_output[32]_i_1__1_n_0
    SLICE_X88Y323        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[2].u_ddr_mc_group/txn_fifo_output_reg[32]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      3.001     3.001 r  
    J19                                               0.000     3.001 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.555 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.595    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.595 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     3.892    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.916 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.364     5.280    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.910 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.214     6.124    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     6.148 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.718     7.866    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[2].u_ddr_mc_group/rst_r1_reg_0
    SLICE_X88Y323        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[2].u_ddr_mc_group/txn_fifo_output_reg[32]/C
                         clock pessimism             -0.253     7.613    
                         clock uncertainty           -0.062     7.551    
    SLICE_X88Y323        FDRE (Setup_DFF_SLICEL_C_D)
                                                      0.025     7.576    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[2].u_ddr_mc_group/txn_fifo_output_reg[32]
  -------------------------------------------------------------------
                         required time                          7.576    
                         arrival time                          -7.518    
  -------------------------------------------------------------------
                         slack                                  0.058    

Slack (MET) :             0.066ns  (required time - arrival time)
  Source:                 d_1_i/axi_smc_1/inst/s01_entry_pipeline/s01_si_converter/inst/converter.wrap_narrow_inst/w_pack_pointer_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/axi_smc_1/inst/s01_entry_pipeline/s01_si_converter/inst/converter.wrap_narrow_inst/w_fill_mask_reg[48]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (mmcm_clkout0 rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        2.631ns  (logic 0.352ns (13.379%)  route 2.279ns (86.621%))
  Logic Levels:           3  (LUT4=3)
  Clock Path Skew:        -0.266ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.103ns = ( 8.104 - 3.001 ) 
    Source Clock Delay      (SCD):    5.043ns
    Clock Pessimism Removal (CPR):    -0.326ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.288ns (routing 0.696ns, distribution 1.592ns)
  Clock Net Delay (Destination): 1.956ns (routing 0.630ns, distribution 1.326ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.524     2.610    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.483 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.244     2.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.755 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       2.288     5.043    d_1_i/axi_smc_1/inst/s01_entry_pipeline/s01_si_converter/inst/converter.wrap_narrow_inst/aclk
    SLICE_X32Y243        FDRE                                         r  d_1_i/axi_smc_1/inst/s01_entry_pipeline/s01_si_converter/inst/converter.wrap_narrow_inst/w_pack_pointer_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X32Y243        FDRE (Prop_GFF2_SLICEL_C_Q)
                                                      0.081     5.124 f  d_1_i/axi_smc_1/inst/s01_entry_pipeline/s01_si_converter/inst/converter.wrap_narrow_inst/w_pack_pointer_reg[1]/Q
                         net (fo=92, routed)          0.901     6.025    d_1_i/axi_smc_1/inst/s01_entry_pipeline/s01_si_converter/inst/converter.wrap_narrow_inst/w_cmd_fifo/Q[1]
    SLICE_X38Y242        LUT4 (Prop_A6LUT_SLICEL_I2_O)
                                                      0.098     6.123 r  d_1_i/axi_smc_1/inst/s01_entry_pipeline/s01_si_converter/inst/converter.wrap_narrow_inst/w_cmd_fifo/w_fill_mask[63]_i_5/O
                         net (fo=9, routed)           0.635     6.758    d_1_i/axi_smc_1/inst/s01_entry_pipeline/s01_si_converter/inst/converter.wrap_narrow_inst/w_cmd_fifo/w_fill_mask[63]_i_5_n_0
    SLICE_X36Y243        LUT4 (Prop_B5LUT_SLICEL_I0_O)
                                                      0.104     6.862 r  d_1_i/axi_smc_1/inst/s01_entry_pipeline/s01_si_converter/inst/converter.wrap_narrow_inst/w_cmd_fifo/w_fill_mask[57]_i_2/O
                         net (fo=2, routed)           0.207     7.069    d_1_i/axi_smc_1/inst/s01_entry_pipeline/s01_si_converter/inst/converter.wrap_narrow_inst/w_cmd_fifo/w_fill_mask[57]_i_2_n_0
    SLICE_X36Y247        LUT4 (Prop_A5LUT_SLICEL_I0_O)
                                                      0.069     7.138 r  d_1_i/axi_smc_1/inst/s01_entry_pipeline/s01_si_converter/inst/converter.wrap_narrow_inst/w_cmd_fifo/w_fill_mask[48]_i_1/O
                         net (fo=2, routed)           0.536     7.674    d_1_i/axi_smc_1/inst/s01_entry_pipeline/s01_si_converter/inst/converter.wrap_narrow_inst/f_fill_mask0[48]
    SLICE_X35Y238        FDRE                                         r  d_1_i/axi_smc_1/inst/s01_entry_pipeline/s01_si_converter/inst/converter.wrap_narrow_inst/w_fill_mask_reg[48]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      3.001     3.001 r  
    J19                                               0.000     3.001 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.555 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.595    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.595 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     3.892    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.916 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.364     5.280    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.910 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.214     6.124    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     6.148 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.956     8.104    d_1_i/axi_smc_1/inst/s01_entry_pipeline/s01_si_converter/inst/converter.wrap_narrow_inst/aclk
    SLICE_X35Y238        FDRE                                         r  d_1_i/axi_smc_1/inst/s01_entry_pipeline/s01_si_converter/inst/converter.wrap_narrow_inst/w_fill_mask_reg[48]/C
                         clock pessimism             -0.326     7.777    
                         clock uncertainty           -0.062     7.715    
    SLICE_X35Y238        FDRE (Setup_AFF_SLICEM_C_D)
                                                      0.025     7.740    d_1_i/axi_smc_1/inst/s01_entry_pipeline/s01_si_converter/inst/converter.wrap_narrow_inst/w_fill_mask_reg[48]
  -------------------------------------------------------------------
                         required time                          7.740    
                         arrival time                          -7.674    
  -------------------------------------------------------------------
                         slack                                  0.066    

Slack (MET) :             0.074ns  (required time - arrival time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_ui/u_ddr_ui_wr_data/data_buf_addr_cnt_r_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[1].u_ddr_mc_group/cas_dbuf_fifo_reg[3][0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (mmcm_clkout0 rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        2.748ns  (logic 0.646ns (23.504%)  route 2.102ns (76.496%))
  Logic Levels:           5  (LUT3=1 LUT4=1 LUT5=1 LUT6=1 RAMD32=1)
  Clock Path Skew:        -0.141ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.850ns = ( 7.851 - 3.001 ) 
    Source Clock Delay      (SCD):    4.673ns
    Clock Pessimism Removal (CPR):    -0.318ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.918ns (routing 0.696ns, distribution 1.222ns)
  Clock Net Delay (Destination): 1.703ns (routing 0.630ns, distribution 1.073ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.524     2.610    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.483 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.244     2.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.755 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.918     4.673    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_ui/u_ddr_ui_wr_data/rd_data_indx_r_reg[3]_0
    SLICE_X84Y278        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_ui/u_ddr_ui_wr_data/data_buf_addr_cnt_r_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X84Y278        FDRE (Prop_HFF_SLICEL_C_Q)
                                                      0.079     4.752 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_ui/u_ddr_ui_wr_data/data_buf_addr_cnt_r_reg[0]/Q
                         net (fo=8, routed)           0.351     5.103    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_ui/u_ddr_ui_wr_data/rams[0].RAM32M0/ADDRB0
    SLICE_X86Y277        RAMD32 (Prop_F5LUT_SLICEM_RADR0_O)
                                                      0.166     5.269 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_ui/u_ddr_ui_wr_data/rams[0].RAM32M0/RAMB/O
                         net (fo=1, routed)           0.368     5.637    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_ui/u_ddr_ui_wr_data/wr_data_buf_addr[0]
    SLICE_X85Y287        LUT3 (Prop_F5LUT_SLICEL_I0_O)
                                                      0.118     5.755 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_ui/u_ddr_ui_wr_data/buf_fifo[0][0]_i_4/O
                         net (fo=4, routed)           0.460     6.215    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_ui/u_ddr_ui_wr_data/rams[0].RAM32M0_0
    SLICE_X87Y315        LUT5 (Prop_G6LUT_SLICEM_I0_O)
                                                      0.037     6.252 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_ui/u_ddr_ui_wr_data/buf_fifo[0][0]_i_2__1/O
                         net (fo=4, routed)           0.228     6.480    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[1].u_ddr_mc_group/buf_fifo_reg[1][0]_1
    SLICE_X88Y316        LUT4 (Prop_C5LUT_SLICEL_I3_O)
                                                      0.158     6.638 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[1].u_ddr_mc_group/buf_fifo[3][0]_i_1__1/O
                         net (fo=2, routed)           0.223     6.861    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[1].u_ddr_mc_group/buf_fifo[3][0]_i_1__1_n_0
    SLICE_X89Y316        LUT6 (Prop_F6LUT_SLICEM_I5_O)
                                                      0.088     6.949 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[1].u_ddr_mc_group/cas_dbuf_fifo[0][0]_i_1__1/O
                         net (fo=4, routed)           0.472     7.421    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[1].u_ddr_mc_group/cas_dbuf_fifo[0][0]_i_1__1_n_0
    SLICE_X89Y330        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[1].u_ddr_mc_group/cas_dbuf_fifo_reg[3][0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      3.001     3.001 r  
    J19                                               0.000     3.001 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.555 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.595    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.595 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     3.892    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.916 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.364     5.280    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.910 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.214     6.124    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     6.148 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.703     7.851    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[1].u_ddr_mc_group/cmdGroupP_reg[0]_0
    SLICE_X89Y330        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[1].u_ddr_mc_group/cas_dbuf_fifo_reg[3][0]/C
                         clock pessimism             -0.318     7.532    
                         clock uncertainty           -0.062     7.470    
    SLICE_X89Y330        FDRE (Setup_DFF_SLICEM_C_D)
                                                      0.025     7.495    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[1].u_ddr_mc_group/cas_dbuf_fifo_reg[3][0]
  -------------------------------------------------------------------
                         required time                          7.495    
                         arrival time                          -7.421    
  -------------------------------------------------------------------
                         slack                                  0.074    

Slack (MET) :             0.083ns  (required time - arrival time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr_axi/axi_w_channel_0/wready_reg_rep__1/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_ui/u_ddr_ui_wr_data/wr_buffer_ram[75].RAM32M0/RAMB_D1/I
                            (rising edge-triggered cell RAMD32 clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (mmcm_clkout0 rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        2.605ns  (logic 0.345ns (13.245%)  route 2.260ns (86.755%))
  Logic Levels:           2  (LUT3=1 LUT5=1)
  Clock Path Skew:        -0.169ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.849ns = ( 7.850 - 3.001 ) 
    Source Clock Delay      (SCD):    4.692ns
    Clock Pessimism Removal (CPR):    -0.326ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.937ns (routing 0.696ns, distribution 1.241ns)
  Clock Net Delay (Destination): 1.702ns (routing 0.630ns, distribution 1.072ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.524     2.610    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.483 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.244     2.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.755 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.937     4.692    d_1_i/ddr4_0/inst/u_ddr_axi/axi_w_channel_0/wready_reg_rep__6_0
    SLICE_X83Y260        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr_axi/axi_w_channel_0/wready_reg_rep__1/C
  -------------------------------------------------------------------    -------------------
    SLICE_X83Y260        FDRE (Prop_CFF2_SLICEM_C_Q)
                                                      0.077     4.769 r  d_1_i/ddr4_0/inst/u_ddr_axi/axi_w_channel_0/wready_reg_rep__1/Q
                         net (fo=192, routed)         1.398     6.167    d_1_i/ddr4_0/inst/u_ddr_axi/axi_w_channel_0/wready_reg_rep__1_n_0
    SLICE_X90Y197        LUT5 (Prop_D6LUT_SLICEM_I1_O)
                                                      0.145     6.312 r  d_1_i/ddr4_0/inst/u_ddr_axi/axi_w_channel_0/app_wdf_data_r1[453]_i_1/O
                         net (fo=2, routed)           0.385     6.697    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_ui/u_ddr_ui_wr_data/c0_ddr4_app_wdf_data[453]
    SLICE_X91Y188        LUT3 (Prop_C6LUT_SLICEL_I0_O)
                                                      0.123     6.820 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_ui/u_ddr_ui_wr_data/wr_buffer_ram[75].RAM32M0_i_3/O
                         net (fo=1, routed)           0.477     7.297    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_ui/u_ddr_ui_wr_data/wr_buffer_ram[75].RAM32M0/DIB1
    SLICE_X90Y188        RAMD32                                       r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_ui/u_ddr_ui_wr_data/wr_buffer_ram[75].RAM32M0/RAMB_D1/I
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      3.001     3.001 r  
    J19                                               0.000     3.001 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.555 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.595    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.595 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     3.892    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.916 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.364     5.280    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.910 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.214     6.124    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     6.148 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.702     7.850    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_ui/u_ddr_ui_wr_data/wr_buffer_ram[75].RAM32M0/WCLK
    SLICE_X90Y188        RAMD32                                       r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_ui/u_ddr_ui_wr_data/wr_buffer_ram[75].RAM32M0/RAMB_D1/CLK
                         clock pessimism             -0.326     7.523    
                         clock uncertainty           -0.062     7.461    
    SLICE_X90Y188        RAMD32 (Setup_F6LUT_SLICEM_CLK_I)
                                                     -0.081     7.380    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_ui/u_ddr_ui_wr_data/wr_buffer_ram[75].RAM32M0/RAMB_D1
  -------------------------------------------------------------------
                         required time                          7.380    
                         arrival time                          -7.297    
  -------------------------------------------------------------------
                         slack                                  0.083    

Slack (MET) :             0.085ns  (required time - arrival time)
  Source:                 d_1_i/axi_smc_1/inst/s01_nodes/s01_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_rd_addrb/count_r_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/axi_smc_1/inst/s01_nodes/s01_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[49]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (mmcm_clkout0 rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        2.750ns  (logic 0.180ns (6.545%)  route 2.570ns (93.455%))
  Logic Levels:           1  (RAMD32=1)
  Clock Path Skew:        -0.128ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.008ns = ( 8.008 - 3.001 ) 
    Source Clock Delay      (SCD):    4.891ns
    Clock Pessimism Removal (CPR):    -0.245ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.136ns (routing 0.696ns, distribution 1.440ns)
  Clock Net Delay (Destination): 1.861ns (routing 0.630ns, distribution 1.231ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.524     2.610    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.483 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.244     2.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.755 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       2.136     4.891    d_1_i/axi_smc_1/inst/s01_nodes/s01_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_rd_addrb/s_sc_aclk
    SLICE_X38Y219        FDRE                                         r  d_1_i/axi_smc_1/inst/s01_nodes/s01_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_rd_addrb/count_r_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X38Y219        FDRE (Prop_DFF2_SLICEL_C_Q)
                                                      0.081     4.972 r  d_1_i/axi_smc_1/inst/s01_nodes/s01_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_rd_addrb/count_r_reg[2]/Q
                         net (fo=206, routed)         2.498     7.470    d_1_i/axi_smc_1/inst/s01_nodes/s01_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_42_55/ADDRD2
    SLICE_X54Y235        RAMD32 (Prop_D6LUT_SLICEM_RADR2_O)
                                                      0.099     7.569 r  d_1_i/axi_smc_1/inst/s01_nodes/s01_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_42_55/RAMD_D1/O
                         net (fo=1, routed)           0.072     7.641    d_1_i/axi_smc_1/inst/s01_nodes/s01_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg0[49]
    SLICE_X54Y235        FDRE                                         r  d_1_i/axi_smc_1/inst/s01_nodes/s01_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[49]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      3.001     3.001 r  
    J19                                               0.000     3.001 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.555 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.595    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.595 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     3.892    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.916 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.364     5.280    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.910 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.214     6.124    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     6.148 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.861     8.008    d_1_i/axi_smc_1/inst/s01_nodes/s01_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/clka
    SLICE_X54Y235        FDRE                                         r  d_1_i/axi_smc_1/inst/s01_nodes/s01_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[49]/C
                         clock pessimism             -0.245     7.763    
                         clock uncertainty           -0.062     7.701    
    SLICE_X54Y235        FDRE (Setup_DFF_SLICEM_C_D)
                                                      0.025     7.726    d_1_i/axi_smc_1/inst/s01_nodes/s01_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[49]
  -------------------------------------------------------------------
                         required time                          7.726    
                         arrival time                          -7.641    
  -------------------------------------------------------------------
                         slack                                  0.085    

Slack (MET) :             0.086ns  (required time - arrival time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_write_data_sync/SYNC[5].sync_reg_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/cal_DQPat_A_reg[37]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (mmcm_clkout0 rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        2.754ns  (logic 0.081ns (2.941%)  route 2.673ns (97.059%))
  Logic Levels:           0  
  Clock Path Skew:        -0.124ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.874ns = ( 7.875 - 3.001 ) 
    Source Clock Delay      (SCD):    4.680ns
    Clock Pessimism Removal (CPR):    -0.318ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.925ns (routing 0.696ns, distribution 1.229ns)
  Clock Net Delay (Destination): 1.727ns (routing 0.630ns, distribution 1.097ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.524     2.610    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.483 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.244     2.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.755 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.925     4.680    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_write_data_sync/SYNC[30].sync_reg_reg[1]_0
    SLICE_X81Y323        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_write_data_sync/SYNC[5].sync_reg_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y323        FDRE (Prop_AFF2_SLICEL_C_Q)
                                                      0.081     4.761 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_write_data_sync/SYNC[5].sync_reg_reg[1]/Q
                         net (fo=43, routed)          2.673     7.434    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_write_data[5]
    SLICE_X95Y245        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/cal_DQPat_A_reg[37]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      3.001     3.001 r  
    J19                                               0.000     3.001 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.555 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.595    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.595 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     3.892    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.916 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.364     5.280    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.910 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.214     6.124    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     6.148 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.727     7.875    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/odt_shift_reg[0][17]
    SLICE_X95Y245        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/cal_DQPat_A_reg[37]/C
                         clock pessimism             -0.318     7.557    
                         clock uncertainty           -0.062     7.494    
    SLICE_X95Y245        FDRE (Setup_GFF2_SLICEL_C_D)
                                                      0.025     7.519    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/cal_DQPat_A_reg[37]
  -------------------------------------------------------------------
                         required time                          7.519    
                         arrival time                          -7.434    
  -------------------------------------------------------------------
                         slack                                  0.086    

Slack (MET) :             0.087ns  (required time - arrival time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[2].u_ddr_mc_group/txn_fifo_output_reg[26]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[2].u_ddr_mc_group/txn_fifo_output_reg[13]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (mmcm_clkout0 rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        2.790ns  (logic 0.800ns (28.676%)  route 1.990ns (71.324%))
  Logic Levels:           7  (CARRY8=1 LUT5=1 LUT6=5)
  Clock Path Skew:        -0.087ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.850ns = ( 7.850 - 3.001 ) 
    Source Clock Delay      (SCD):    4.684ns
    Clock Pessimism Removal (CPR):    -0.253ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.929ns (routing 0.696ns, distribution 1.233ns)
  Clock Net Delay (Destination): 1.703ns (routing 0.630ns, distribution 1.073ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.524     2.610    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.483 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.244     2.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.755 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.929     4.684    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[2].u_ddr_mc_group/rst_r1_reg_0
    SLICE_X83Y330        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[2].u_ddr_mc_group/txn_fifo_output_reg[26]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X83Y330        FDRE (Prop_CFF_SLICEM_C_Q)
                                                      0.078     4.762 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[2].u_ddr_mc_group/txn_fifo_output_reg[26]/Q
                         net (fo=11, routed)          0.760     5.522    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[2].u_ddr_mc_group/Q[5]
    SLICE_X88Y350        LUT6 (Prop_A6LUT_SLICEL_I2_O)
                                                      0.090     5.612 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[2].u_ddr_mc_group/i__carry_i_6__1/O
                         net (fo=1, routed)           0.009     5.621    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[2].u_ddr_mc_group/i__carry_i_6__1_n_0
    SLICE_X88Y350        CARRY8 (Prop_CARRY8_SLICEL_S[0]_CO[5])
                                                      0.199     5.820 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[2].u_ddr_mc_group/issue_cas3_inferred__0/i__carry/CO[5]
                         net (fo=5, routed)           0.483     6.303    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[2].u_ddr_mc_group/issue_cas3_inferred__0/i__carry_n_2
    SLICE_X86Y337        LUT5 (Prop_A6LUT_SLICEM_I2_O)
                                                      0.038     6.341 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[2].u_ddr_mc_group/FSM_sequential_grSt[1]_i_6__0/O
                         net (fo=1, routed)           0.043     6.384    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[2].u_ddr_mc_group/FSM_sequential_grSt[1]_i_6__0_n_0
    SLICE_X86Y337        LUT6 (Prop_C6LUT_SLICEM_I3_O)
                                                      0.037     6.421 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[2].u_ddr_mc_group/FSM_sequential_grSt[1]_i_2__1/O
                         net (fo=4, routed)           0.039     6.460    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[2].u_ddr_mc_group/FSM_sequential_grSt[1]_i_2__1_n_0
    SLICE_X86Y337        LUT6 (Prop_B6LUT_SLICEM_I0_O)
                                                      0.089     6.549 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[2].u_ddr_mc_group/cas_fifo_wptr[1]_i_2__1/O
                         net (fo=75, routed)          0.367     6.917    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[2].u_ddr_mc_group/cas_fifo_wptr[1]_i_2__1_n_0
    SLICE_X86Y329        LUT6 (Prop_C6LUT_SLICEM_I4_O)
                                                      0.145     7.062 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[2].u_ddr_mc_group/txn_fifo_output[13]_i_2__1/O
                         net (fo=1, routed)           0.237     7.299    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[2].u_ddr_mc_group/txn_fifo_output[13]_i_2__1_n_0
    SLICE_X85Y333        LUT6 (Prop_H6LUT_SLICEL_I2_O)
                                                      0.124     7.423 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[2].u_ddr_mc_group/txn_fifo_output[13]_i_1__1/O
                         net (fo=1, routed)           0.051     7.474    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[2].u_ddr_mc_group/txn_fifo_output[13]_i_1__1_n_0
    SLICE_X85Y333        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[2].u_ddr_mc_group/txn_fifo_output_reg[13]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      3.001     3.001 r  
    J19                                               0.000     3.001 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.555 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.595    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.595 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     3.892    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.916 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.364     5.280    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.910 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.214     6.124    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     6.148 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.703     7.850    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[2].u_ddr_mc_group/rst_r1_reg_0
    SLICE_X85Y333        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[2].u_ddr_mc_group/txn_fifo_output_reg[13]/C
                         clock pessimism             -0.253     7.598    
                         clock uncertainty           -0.062     7.535    
    SLICE_X85Y333        FDRE (Setup_HFF_SLICEL_C_D)
                                                      0.025     7.560    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[2].u_ddr_mc_group/txn_fifo_output_reg[13]
  -------------------------------------------------------------------
                         required time                          7.560    
                         arrival time                          -7.474    
  -------------------------------------------------------------------
                         slack                                  0.087    

Slack (MET) :             0.089ns  (required time - arrival time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/txn_fifo_output_reg[0]_replica/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/txn_fifo_output_reg[14]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (mmcm_clkout0 rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        2.698ns  (logic 0.899ns (33.318%)  route 1.799ns (66.682%))
  Logic Levels:           8  (CARRY8=1 LUT5=1 LUT6=6)
  Clock Path Skew:        -0.176ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.858ns = ( 7.859 - 3.001 ) 
    Source Clock Delay      (SCD):    4.716ns
    Clock Pessimism Removal (CPR):    -0.318ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.961ns (routing 0.696ns, distribution 1.265ns)
  Clock Net Delay (Destination): 1.711ns (routing 0.630ns, distribution 1.081ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.524     2.610    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.483 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.244     2.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.755 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.961     4.716    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/cmdGroupP_reg[0]_0
    SLICE_X84Y302        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/txn_fifo_output_reg[0]_replica/C
  -------------------------------------------------------------------    -------------------
    SLICE_X84Y302        FDRE (Prop_AFF2_SLICEL_C_Q)
                                                      0.081     4.797 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/txn_fifo_output_reg[0]_replica/Q
                         net (fo=11, routed)          0.286     5.083    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/Q[0]_repN
    SLICE_X83Y309        LUT6 (Prop_F6LUT_SLICEM_I3_O)
                                                      0.098     5.181 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/i__carry_i_17__2/O
                         net (fo=1, routed)           0.253     5.434    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/i__carry_i_17__2_n_0
    SLICE_X82Y309        LUT6 (Prop_B6LUT_SLICEM_I0_O)
                                                      0.100     5.534 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/i__carry_i_5__2/O
                         net (fo=1, routed)           0.016     5.550    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/i__carry_i_5__2_n_0
    SLICE_X82Y309        CARRY8 (Prop_CARRY8_SLICEM_S[1]_CO[5])
                                                      0.199     5.749 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/issue_cas3_inferred__0/i__carry/CO[5]
                         net (fo=5, routed)           0.380     6.129    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/issue_cas3_inferred__0/i__carry_n_2
    SLICE_X87Y306        LUT5 (Prop_F6LUT_SLICEM_I2_O)
                                                      0.051     6.180 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/FSM_sequential_grSt[1]_i_6/O
                         net (fo=1, routed)           0.042     6.222    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/FSM_sequential_grSt[1]_i_6_n_0
    SLICE_X87Y306        LUT6 (Prop_H6LUT_SLICEM_I3_O)
                                                      0.039     6.261 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/FSM_sequential_grSt[1]_i_3__0/O
                         net (fo=4, routed)           0.216     6.477    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/FSM_sequential_grSt[1]_i_3__0_n_0
    SLICE_X85Y305        LUT6 (Prop_C6LUT_SLICEL_I0_O)
                                                      0.035     6.512 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/cas_fifo_wptr[1]_i_2__0/O
                         net (fo=75, routed)          0.399     6.911    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/cas_fifo_wptr[1]_i_2__0_n_0
    SLICE_X84Y289        LUT6 (Prop_F6LUT_SLICEL_I4_O)
                                                      0.148     7.059 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/txn_fifo_output[14]_i_3__0/O
                         net (fo=1, routed)           0.156     7.215    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/txn_fifo_output[14]_i_3__0_n_0
    SLICE_X84Y291        LUT6 (Prop_F6LUT_SLICEL_I3_O)
                                                      0.148     7.363 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/txn_fifo_output[14]_i_1__0/O
                         net (fo=1, routed)           0.051     7.414    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/txn_fifo_output[14]_i_1__0_n_0
    SLICE_X84Y291        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/txn_fifo_output_reg[14]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      3.001     3.001 r  
    J19                                               0.000     3.001 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.555 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.595    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.595 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     3.892    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.916 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.364     5.280    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.910 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.214     6.124    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     6.148 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.711     7.859    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/cmdGroupP_reg[0]_0
    SLICE_X84Y291        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/txn_fifo_output_reg[14]/C
                         clock pessimism             -0.318     7.540    
                         clock uncertainty           -0.062     7.478    
    SLICE_X84Y291        FDRE (Setup_FFF_SLICEL_C_D)
                                                      0.025     7.503    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/txn_fifo_output_reg[14]
  -------------------------------------------------------------------
                         required time                          7.503    
                         arrival time                          -7.414    
  -------------------------------------------------------------------
                         slack                                  0.089    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.010ns  (arrival time - required time)
  Source:                 d_1_i/axi_smc_1/inst/m00_nodes/m00_r_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[129]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/axi_smc_1/inst/switchboards/r_switchboard/inst/gen_mi[0].inst_opipe_payld/gen_pipe[1].pipe_reg[1][129]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (mmcm_clkout0 rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.172ns  (logic 0.058ns (33.721%)  route 0.114ns (66.279%))
  Logic Levels:           0  
  Clock Path Skew:        0.102ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    4.822ns
    Source Clock Delay      (SCD):    4.975ns
    Clock Pessimism Removal (CPR):    -0.254ns
  Clock Net Delay (Source):      1.828ns (routing 0.630ns, distribution 1.198ns)
  Clock Net Delay (Destination): 2.067ns (routing 0.696ns, distribution 1.371ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.364     2.279    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.909 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.214     3.123    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.147 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.828     4.975    d_1_i/axi_smc_1/inst/m00_nodes/m00_r_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/clka
    SLICE_X72Y263        FDRE                                         r  d_1_i/axi_smc_1/inst/m00_nodes/m00_r_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[129]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X72Y263        FDRE (Prop_BFF_SLICEM_C_Q)
                                                      0.058     5.033 r  d_1_i/axi_smc_1/inst/m00_nodes/m00_r_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[129]/Q
                         net (fo=1, routed)           0.114     5.147    d_1_i/axi_smc_1/inst/switchboards/r_switchboard/inst/gen_mi[0].inst_opipe_payld/s_sc_payld[118]
    SLICE_X71Y262        FDRE                                         r  d_1_i/axi_smc_1/inst/switchboards/r_switchboard/inst/gen_mi[0].inst_opipe_payld/gen_pipe[1].pipe_reg[1][129]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.524     2.610    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.483 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.244     2.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.755 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       2.067     4.822    d_1_i/axi_smc_1/inst/switchboards/r_switchboard/inst/gen_mi[0].inst_opipe_payld/aclk
    SLICE_X71Y262        FDRE                                         r  d_1_i/axi_smc_1/inst/switchboards/r_switchboard/inst/gen_mi[0].inst_opipe_payld/gen_pipe[1].pipe_reg[1][129]/C
                         clock pessimism              0.254     5.076    
    SLICE_X71Y262        FDRE (Hold_EFF_SLICEL_C_D)
                                                      0.060     5.136    d_1_i/axi_smc_1/inst/switchboards/r_switchboard/inst/gen_mi[0].inst_opipe_payld/gen_pipe[1].pipe_reg[1][129]
  -------------------------------------------------------------------
                         required time                         -5.136    
                         arrival time                           5.147    
  -------------------------------------------------------------------
                         slack                                  0.010    

Slack (MET) :             0.011ns  (arrival time - required time)
  Source:                 d_1_i/axi_smc_1/inst/switchboards/r_switchboard/inst/gen_mi[0].inst_opipe_payld/gen_pipe[1].pipe_reg[1][13]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/axi_smc_1/inst/s00_nodes/s00_r_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[2].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_168_181/RAME_D1/I
                            (rising edge-triggered cell RAMD32 clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (mmcm_clkout0 rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.188ns  (logic 0.058ns (30.827%)  route 0.130ns (69.173%))
  Logic Levels:           0  
  Clock Path Skew:        0.117ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    4.853ns
    Source Clock Delay      (SCD):    4.990ns
    Clock Pessimism Removal (CPR):    -0.255ns
  Clock Net Delay (Source):      1.843ns (routing 0.630ns, distribution 1.213ns)
  Clock Net Delay (Destination): 2.098ns (routing 0.696ns, distribution 1.402ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.364     2.279    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.909 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.214     3.123    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.147 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.843     4.990    d_1_i/axi_smc_1/inst/switchboards/r_switchboard/inst/gen_mi[0].inst_opipe_payld/aclk
    SLICE_X66Y250        FDRE                                         r  d_1_i/axi_smc_1/inst/switchboards/r_switchboard/inst/gen_mi[0].inst_opipe_payld/gen_pipe[1].pipe_reg[1][13]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X66Y250        FDRE (Prop_DFF_SLICEM_C_Q)
                                                      0.058     5.048 r  d_1_i/axi_smc_1/inst/switchboards/r_switchboard/inst/gen_mi[0].inst_opipe_payld/gen_pipe[1].pipe_reg[1][13]/Q
                         net (fo=3, routed)           0.130     5.178    d_1_i/axi_smc_1/inst/s00_nodes/s00_r_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[2].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_168_181/DIE1
    SLICE_X67Y248        RAMD32                                       r  d_1_i/axi_smc_1/inst/s00_nodes/s00_r_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[2].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_168_181/RAME_D1/I
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.524     2.610    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.483 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.244     2.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.755 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       2.098     4.853    d_1_i/axi_smc_1/inst/s00_nodes/s00_r_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[2].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_168_181/WCLK
    SLICE_X67Y248        RAMD32                                       r  d_1_i/axi_smc_1/inst/s00_nodes/s00_r_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[2].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_168_181/RAME_D1/CLK
                         clock pessimism              0.255     5.107    
    SLICE_X67Y248        RAMD32 (Hold_E6LUT_SLICEM_CLK_I)
                                                      0.060     5.167    d_1_i/axi_smc_1/inst/s00_nodes/s00_r_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[2].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_168_181/RAME_D1
  -------------------------------------------------------------------
                         required time                         -5.167    
                         arrival time                           5.178    
  -------------------------------------------------------------------
                         slack                                  0.011    

Slack (MET) :             0.011ns  (arrival time - required time)
  Source:                 d_1_i/axi_smc_1/inst/m00_nodes/m00_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[1].inst_xpm_memory/xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[53]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/axi_smc_1/inst/m00_exit_pipeline/m00_exit/inst/w_reg/skid_buffer_reg[1193]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (mmcm_clkout0 rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.280ns  (logic 0.057ns (20.377%)  route 0.223ns (79.623%))
  Logic Levels:           0  
  Clock Path Skew:        0.206ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    4.883ns
    Source Clock Delay      (SCD):    5.003ns
    Clock Pessimism Removal (CPR):    -0.326ns
  Clock Net Delay (Source):      1.856ns (routing 0.630ns, distribution 1.226ns)
  Clock Net Delay (Destination): 2.128ns (routing 0.696ns, distribution 1.432ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.364     2.279    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.909 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.214     3.123    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.147 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.856     5.003    d_1_i/axi_smc_1/inst/m00_nodes/m00_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[1].inst_xpm_memory/xpm_memory_base_inst/clka
    SLICE_X56Y237        FDRE                                         r  d_1_i/axi_smc_1/inst/m00_nodes/m00_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[1].inst_xpm_memory/xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[53]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X56Y237        FDRE (Prop_FFF_SLICEM_C_Q)
                                                      0.057     5.060 r  d_1_i/axi_smc_1/inst/m00_nodes/m00_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[1].inst_xpm_memory/xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_reg.doutb_reg_reg[53]/Q
                         net (fo=2, routed)           0.223     5.282    d_1_i/axi_smc_1/inst/m00_exit_pipeline/m00_exit/inst/w_reg/D[169]
    SLICE_X58Y251        FDRE                                         r  d_1_i/axi_smc_1/inst/m00_exit_pipeline/m00_exit/inst/w_reg/skid_buffer_reg[1193]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.524     2.610    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.483 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.244     2.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.755 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       2.128     4.883    d_1_i/axi_smc_1/inst/m00_exit_pipeline/m00_exit/inst/w_reg/aclk
    SLICE_X58Y251        FDRE                                         r  d_1_i/axi_smc_1/inst/m00_exit_pipeline/m00_exit/inst/w_reg/skid_buffer_reg[1193]/C
                         clock pessimism              0.326     5.209    
    SLICE_X58Y251        FDRE (Hold_FFF2_SLICEL_C_D)
                                                      0.062     5.271    d_1_i/axi_smc_1/inst/m00_exit_pipeline/m00_exit/inst/w_reg/skid_buffer_reg[1193]
  -------------------------------------------------------------------
                         required time                         -5.271    
                         arrival time                           5.282    
  -------------------------------------------------------------------
                         slack                                  0.011    

Slack (MET) :             0.012ns  (arrival time - required time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_clb2phy_fifo_rden_reg[28]/C
                            (rising edge-triggered cell FDSE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/FIFO_RD_EN
                            (rising edge-triggered cell RXTX_BITSLICE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (mmcm_clkout0 rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.192ns  (logic 0.039ns (20.313%)  route 0.153ns (79.688%))
  Logic Levels:           0  
  Clock Path Skew:        0.158ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.947ns
    Source Clock Delay      (SCD):    2.906ns
    Clock Pessimism Removal (CPR):    -0.117ns
  Clock Net Delay (Source):      1.058ns (routing 0.384ns, distribution 0.674ns)
  Clock Net Delay (Destination): 1.331ns (routing 0.432ns, distribution 0.899ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.839     1.456    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.686 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.145     1.831    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.848 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.058     2.906    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/dReg_reg[10]
    SLICE_X81Y259        FDSE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_clb2phy_fifo_rden_reg[28]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y259        FDSE (Prop_EFF_SLICEL_C_Q)
                                                      0.039     2.945 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_clb2phy_fifo_rden_reg[28]/Q
                         net (fo=1, routed)           0.153     3.098    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/ch0_mcal_clb2phy_fifo_rden[0]
    BITSLICE_RX_TX_X0Y223
                         RXTX_BITSLICE                                r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/FIFO_RD_EN
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.940     1.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.432 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.165     1.597    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.616 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.331     2.947    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/div_clk
    BITSLICE_RX_TX_X0Y223
                         RXTX_BITSLICE                                r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/FIFO_RD_CLK
                         clock pessimism              0.117     3.064    
    BITSLICE_RX_TX_X0Y223
                         RXTX_BITSLICE (Hold_RXTX_BITSLICE_BITSLICE_RX_TX_FIFO_RD_CLK_FIFO_RD_EN)
                                                      0.022     3.086    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                         -3.086    
                         arrival time                           3.098    
  -------------------------------------------------------------------
                         slack                                  0.012    

Slack (MET) :             0.013ns  (arrival time - required time)
  Source:                 d_1_i/axi_smc_1/inst/m00_exit_pipeline/m00_exit/inst/w_reg/skid_buffer_reg[1094]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/axi_smc_1/inst/m00_exit_pipeline/m00_exit/inst/w_reg/m_vector_i_reg[1094]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (mmcm_clkout0 rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.179ns  (logic 0.093ns (51.955%)  route 0.086ns (48.045%))
  Logic Levels:           1  (LUT3=1)
  Clock Path Skew:        0.106ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    4.802ns
    Source Clock Delay      (SCD):    4.954ns
    Clock Pessimism Removal (CPR):    -0.259ns
  Clock Net Delay (Source):      1.807ns (routing 0.630ns, distribution 1.177ns)
  Clock Net Delay (Destination): 2.047ns (routing 0.696ns, distribution 1.351ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.364     2.279    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.909 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.214     3.123    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.147 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.807     4.954    d_1_i/axi_smc_1/inst/m00_exit_pipeline/m00_exit/inst/w_reg/aclk
    SLICE_X64Y230        FDRE                                         r  d_1_i/axi_smc_1/inst/m00_exit_pipeline/m00_exit/inst/w_reg/skid_buffer_reg[1094]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X64Y230        FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.058     5.012 r  d_1_i/axi_smc_1/inst/m00_exit_pipeline/m00_exit/inst/w_reg/skid_buffer_reg[1094]/Q
                         net (fo=1, routed)           0.062     5.074    d_1_i/axi_smc_1/inst/m00_exit_pipeline/m00_exit/inst/w_reg/skid_buffer_reg_n_0_[1094]
    SLICE_X62Y230        LUT3 (Prop_C6LUT_SLICEL_I0_O)
                                                      0.035     5.109 r  d_1_i/axi_smc_1/inst/m00_exit_pipeline/m00_exit/inst/w_reg/m_vector_i[1094]_i_1/O
                         net (fo=1, routed)           0.024     5.133    d_1_i/axi_smc_1/inst/m00_exit_pipeline/m00_exit/inst/w_reg/m_vector_i[1094]_i_1_n_0
    SLICE_X62Y230        FDRE                                         r  d_1_i/axi_smc_1/inst/m00_exit_pipeline/m00_exit/inst/w_reg/m_vector_i_reg[1094]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.524     2.610    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.483 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.244     2.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.755 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       2.047     4.802    d_1_i/axi_smc_1/inst/m00_exit_pipeline/m00_exit/inst/w_reg/aclk
    SLICE_X62Y230        FDRE                                         r  d_1_i/axi_smc_1/inst/m00_exit_pipeline/m00_exit/inst/w_reg/m_vector_i_reg[1094]/C
                         clock pessimism              0.259     5.061    
    SLICE_X62Y230        FDRE (Hold_CFF_SLICEL_C_D)
                                                      0.060     5.121    d_1_i/axi_smc_1/inst/m00_exit_pipeline/m00_exit/inst/w_reg/m_vector_i_reg[1094]
  -------------------------------------------------------------------
                         required time                         -5.121    
                         arrival time                           5.133    
  -------------------------------------------------------------------
                         slack                                  0.013    

Slack (MET) :             0.013ns  (arrival time - required time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/mcal_DMIn_n_r_reg[37]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/mcal_DMIn_bit_r1_reg[5]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (mmcm_clkout0 rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.265ns  (logic 0.101ns (38.113%)  route 0.164ns (61.887%))
  Logic Levels:           2  (LUT6=1 MUXF7=1)
  Clock Path Skew:        0.192ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    4.684ns
    Source Clock Delay      (SCD):    4.818ns
    Clock Pessimism Removal (CPR):    -0.326ns
  Clock Net Delay (Source):      1.671ns (routing 0.630ns, distribution 1.041ns)
  Clock Net Delay (Destination): 1.929ns (routing 0.696ns, distribution 1.233ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.364     2.279    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.909 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.214     3.123    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.147 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.671     4.818    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/odt_shift_reg[0][17]
    SLICE_X81Y239        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/mcal_DMIn_n_r_reg[37]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y239        FDRE (Prop_FFF2_SLICEL_C_Q)
                                                      0.060     4.878 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/mcal_DMIn_n_r_reg[37]/Q
                         net (fo=1, routed)           0.144     5.022    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/mcal_DMIn_n_r[37]
    SLICE_X81Y246        LUT6 (Prop_C6LUT_SLICEL_I5_O)
                                                      0.022     5.044 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/mcal_DMIn_bit_r1[5]_i_3/O
                         net (fo=1, routed)           0.010     5.054    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/mcal_DMIn_bit_r1[5]_i_3_n_0
    SLICE_X81Y246        MUXF7 (Prop_F7MUX_CD_SLICEL_I1_O)
                                                      0.019     5.073 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/mcal_DMIn_bit_r1_reg[5]_i_1/O
                         net (fo=1, routed)           0.010     5.083    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/mcal_DMIn_bit_r1_reg[5]_i_1_n_0
    SLICE_X81Y246        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/mcal_DMIn_bit_r1_reg[5]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.524     2.610    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.483 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.244     2.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.755 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.929     4.684    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/odt_shift_reg[0][17]
    SLICE_X81Y246        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/mcal_DMIn_bit_r1_reg[5]/C
                         clock pessimism              0.326     5.010    
    SLICE_X81Y246        FDRE (Hold_DFF_SLICEL_C_D)
                                                      0.060     5.070    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/mcal_DMIn_bit_r1_reg[5]
  -------------------------------------------------------------------
                         required time                         -5.070    
                         arrival time                           5.083    
  -------------------------------------------------------------------
                         slack                                  0.013    

Slack (MET) :             0.014ns  (arrival time - required time)
  Source:                 d_1_i/axi_smc_1/inst/s00_nodes/s00_w_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_wr_addra/count_r_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/axi_smc_1/inst/s00_nodes/s00_w_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13/RAMA/WADR1
                            (rising edge-triggered cell RAMD32 clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (mmcm_clkout0 rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.213ns  (logic 0.059ns (27.701%)  route 0.154ns (72.299%))
  Logic Levels:           0  
  Clock Path Skew:        0.111ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    4.897ns
    Source Clock Delay      (SCD):    5.031ns
    Clock Pessimism Removal (CPR):    -0.245ns
  Clock Net Delay (Source):      1.884ns (routing 0.630ns, distribution 1.254ns)
  Clock Net Delay (Destination): 2.142ns (routing 0.696ns, distribution 1.446ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.364     2.279    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.909 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.214     3.123    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.147 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.884     5.031    d_1_i/axi_smc_1/inst/s00_nodes/s00_w_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_wr_addra/s_sc_aclk
    SLICE_X46Y205        FDRE                                         r  d_1_i/axi_smc_1/inst/s00_nodes/s00_w_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_wr_addra/count_r_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X46Y205        FDRE (Prop_HFF2_SLICEM_C_Q)
                                                      0.059     5.090 r  d_1_i/axi_smc_1/inst/s00_nodes/s00_w_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_wr_addra/count_r_reg[1]/Q
                         net (fo=22, routed)          0.154     5.244    d_1_i/axi_smc_1/inst/s00_nodes/s00_w_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13/ADDRH1
    SLICE_X45Y206        RAMD32                                       r  d_1_i/axi_smc_1/inst/s00_nodes/s00_w_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13/RAMA/WADR1
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.524     2.610    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.483 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.244     2.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.755 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       2.142     4.897    d_1_i/axi_smc_1/inst/s00_nodes/s00_w_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13/WCLK
    SLICE_X45Y206        RAMD32                                       r  d_1_i/axi_smc_1/inst/s00_nodes/s00_w_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13/RAMA/CLK
                         clock pessimism              0.245     5.142    
    SLICE_X45Y206        RAMD32 (Hold_A5LUT_SLICEM_CLK_WADR1)
                                                      0.088     5.230    d_1_i/axi_smc_1/inst/s00_nodes/s00_w_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13/RAMA
  -------------------------------------------------------------------
                         required time                         -5.230    
                         arrival time                           5.244    
  -------------------------------------------------------------------
                         slack                                  0.014    

Slack (MET) :             0.014ns  (arrival time - required time)
  Source:                 d_1_i/axi_smc_1/inst/s00_nodes/s00_w_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_wr_addra/count_r_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/axi_smc_1/inst/s00_nodes/s00_w_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13/RAMA_D1/WADR1
                            (rising edge-triggered cell RAMD32 clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (mmcm_clkout0 rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.213ns  (logic 0.059ns (27.701%)  route 0.154ns (72.299%))
  Logic Levels:           0  
  Clock Path Skew:        0.111ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    4.897ns
    Source Clock Delay      (SCD):    5.031ns
    Clock Pessimism Removal (CPR):    -0.245ns
  Clock Net Delay (Source):      1.884ns (routing 0.630ns, distribution 1.254ns)
  Clock Net Delay (Destination): 2.142ns (routing 0.696ns, distribution 1.446ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.364     2.279    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.909 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.214     3.123    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.147 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.884     5.031    d_1_i/axi_smc_1/inst/s00_nodes/s00_w_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_wr_addra/s_sc_aclk
    SLICE_X46Y205        FDRE                                         r  d_1_i/axi_smc_1/inst/s00_nodes/s00_w_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_wr_addra/count_r_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X46Y205        FDRE (Prop_HFF2_SLICEM_C_Q)
                                                      0.059     5.090 r  d_1_i/axi_smc_1/inst/s00_nodes/s00_w_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_wr_addra/count_r_reg[1]/Q
                         net (fo=22, routed)          0.154     5.244    d_1_i/axi_smc_1/inst/s00_nodes/s00_w_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13/ADDRH1
    SLICE_X45Y206        RAMD32                                       r  d_1_i/axi_smc_1/inst/s00_nodes/s00_w_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13/RAMA_D1/WADR1
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.524     2.610    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.483 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.244     2.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.755 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       2.142     4.897    d_1_i/axi_smc_1/inst/s00_nodes/s00_w_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13/WCLK
    SLICE_X45Y206        RAMD32                                       r  d_1_i/axi_smc_1/inst/s00_nodes/s00_w_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13/RAMA_D1/CLK
                         clock pessimism              0.245     5.142    
    SLICE_X45Y206        RAMD32 (Hold_A6LUT_SLICEM_CLK_WADR1)
                                                      0.088     5.230    d_1_i/axi_smc_1/inst/s00_nodes/s00_w_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13/RAMA_D1
  -------------------------------------------------------------------
                         required time                         -5.230    
                         arrival time                           5.244    
  -------------------------------------------------------------------
                         slack                                  0.014    

Slack (MET) :             0.014ns  (arrival time - required time)
  Source:                 d_1_i/axi_smc_1/inst/s00_nodes/s00_w_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_wr_addra/count_r_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/axi_smc_1/inst/s00_nodes/s00_w_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13/RAMB/WADR1
                            (rising edge-triggered cell RAMD32 clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (mmcm_clkout0 rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.213ns  (logic 0.059ns (27.701%)  route 0.154ns (72.299%))
  Logic Levels:           0  
  Clock Path Skew:        0.111ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    4.897ns
    Source Clock Delay      (SCD):    5.031ns
    Clock Pessimism Removal (CPR):    -0.245ns
  Clock Net Delay (Source):      1.884ns (routing 0.630ns, distribution 1.254ns)
  Clock Net Delay (Destination): 2.142ns (routing 0.696ns, distribution 1.446ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.364     2.279    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.909 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.214     3.123    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.147 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.884     5.031    d_1_i/axi_smc_1/inst/s00_nodes/s00_w_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_wr_addra/s_sc_aclk
    SLICE_X46Y205        FDRE                                         r  d_1_i/axi_smc_1/inst/s00_nodes/s00_w_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_wr_addra/count_r_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X46Y205        FDRE (Prop_HFF2_SLICEM_C_Q)
                                                      0.059     5.090 r  d_1_i/axi_smc_1/inst/s00_nodes/s00_w_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_wr_addra/count_r_reg[1]/Q
                         net (fo=22, routed)          0.154     5.244    d_1_i/axi_smc_1/inst/s00_nodes/s00_w_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13/ADDRH1
    SLICE_X45Y206        RAMD32                                       r  d_1_i/axi_smc_1/inst/s00_nodes/s00_w_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13/RAMB/WADR1
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.524     2.610    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.483 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.244     2.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.755 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       2.142     4.897    d_1_i/axi_smc_1/inst/s00_nodes/s00_w_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13/WCLK
    SLICE_X45Y206        RAMD32                                       r  d_1_i/axi_smc_1/inst/s00_nodes/s00_w_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13/RAMB/CLK
                         clock pessimism              0.245     5.142    
    SLICE_X45Y206        RAMD32 (Hold_B5LUT_SLICEM_CLK_WADR1)
                                                      0.088     5.230    d_1_i/axi_smc_1/inst/s00_nodes/s00_w_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13/RAMB
  -------------------------------------------------------------------
                         required time                         -5.230    
                         arrival time                           5.244    
  -------------------------------------------------------------------
                         slack                                  0.014    

Slack (MET) :             0.014ns  (arrival time - required time)
  Source:                 d_1_i/axi_smc_1/inst/s00_nodes/s00_w_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_wr_addra/count_r_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/axi_smc_1/inst/s00_nodes/s00_w_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13/RAMB_D1/WADR1
                            (rising edge-triggered cell RAMD32 clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (mmcm_clkout0 rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.213ns  (logic 0.059ns (27.701%)  route 0.154ns (72.299%))
  Logic Levels:           0  
  Clock Path Skew:        0.111ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    4.897ns
    Source Clock Delay      (SCD):    5.031ns
    Clock Pessimism Removal (CPR):    -0.245ns
  Clock Net Delay (Source):      1.884ns (routing 0.630ns, distribution 1.254ns)
  Clock Net Delay (Destination): 2.142ns (routing 0.696ns, distribution 1.446ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.364     2.279    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.909 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.214     3.123    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.147 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.884     5.031    d_1_i/axi_smc_1/inst/s00_nodes/s00_w_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_wr_addra/s_sc_aclk
    SLICE_X46Y205        FDRE                                         r  d_1_i/axi_smc_1/inst/s00_nodes/s00_w_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_wr_addra/count_r_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X46Y205        FDRE (Prop_HFF2_SLICEM_C_Q)
                                                      0.059     5.090 r  d_1_i/axi_smc_1/inst/s00_nodes/s00_w_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_wr_addra/count_r_reg[1]/Q
                         net (fo=22, routed)          0.154     5.244    d_1_i/axi_smc_1/inst/s00_nodes/s00_w_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13/ADDRH1
    SLICE_X45Y206        RAMD32                                       r  d_1_i/axi_smc_1/inst/s00_nodes/s00_w_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13/RAMB_D1/WADR1
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.524     2.610    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.483 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.244     2.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.755 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       2.142     4.897    d_1_i/axi_smc_1/inst/s00_nodes/s00_w_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13/WCLK
    SLICE_X45Y206        RAMD32                                       r  d_1_i/axi_smc_1/inst/s00_nodes/s00_w_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13/RAMB_D1/CLK
                         clock pessimism              0.245     5.142    
    SLICE_X45Y206        RAMD32 (Hold_B6LUT_SLICEM_CLK_WADR1)
                                                      0.088     5.230    d_1_i/axi_smc_1/inst/s00_nodes/s00_w_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13/RAMB_D1
  -------------------------------------------------------------------
                         required time                         -5.230    
                         arrival time                           5.244    
  -------------------------------------------------------------------
                         slack                                  0.014    





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         mmcm_clkout0
Waveform(ns):       { 0.000 1.500 }
Period(ns):         3.001
Sources:            { d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0 }

Check Type        Corner  Lib Pin                    Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location               Pin
Min Period        n/a     PS8/MAXIGP1ACLK            n/a            3.000         3.001       0.001      PS8_X0Y0               d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/MAXIGP1ACLK
Min Period        n/a     RXTX_BITSLICE/FIFO_RD_CLK  n/a            1.694         3.001       1.307      BITSLICE_RX_TX_X0Y156  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/FIFO_RD_CLK
Min Period        n/a     RXTX_BITSLICE/FIFO_RD_CLK  n/a            1.694         3.001       1.307      BITSLICE_RX_TX_X0Y158  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/FIFO_RD_CLK
Min Period        n/a     RXTX_BITSLICE/FIFO_RD_CLK  n/a            1.694         3.001       1.307      BITSLICE_RX_TX_X0Y159  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/FIFO_RD_CLK
Min Period        n/a     RXTX_BITSLICE/FIFO_RD_CLK  n/a            1.694         3.001       1.307      BITSLICE_RX_TX_X0Y160  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/FIFO_RD_CLK
Min Period        n/a     RXTX_BITSLICE/FIFO_RD_CLK  n/a            1.694         3.001       1.307      BITSLICE_RX_TX_X0Y161  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/FIFO_RD_CLK
Min Period        n/a     RXTX_BITSLICE/FIFO_RD_CLK  n/a            1.694         3.001       1.307      BITSLICE_RX_TX_X0Y162  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/FIFO_RD_CLK
Min Period        n/a     RXTX_BITSLICE/FIFO_RD_CLK  n/a            1.694         3.001       1.307      BITSLICE_RX_TX_X0Y164  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/FIFO_RD_CLK
Min Period        n/a     RXTX_BITSLICE/FIFO_RD_CLK  n/a            1.694         3.001       1.307      BITSLICE_RX_TX_X0Y165  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/FIFO_RD_CLK
Min Period        n/a     RXTX_BITSLICE/FIFO_RD_CLK  n/a            1.694         3.001       1.307      BITSLICE_RX_TX_X0Y166  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/FIFO_RD_CLK
Max Period        n/a     PLLE4_ADV/CLKIN            n/a            14.286        3.001       11.285     PLL_X0Y6               d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[0].gen_plle4.PLLE4_BASE_INST_OTHER/CLKIN
Max Period        n/a     PLLE4_ADV/CLKIN            n/a            14.286        3.001       11.285     PLL_X0Y8               d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[1].gen_plle4.PLLE4_BASE_INST_OTHER/CLKIN
Max Period        n/a     PLLE4_ADV/CLKIN            n/a            14.286        3.001       11.285     PLL_X0Y10              d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[2].gen_plle4.PLLE4_BASE_INST_OTHER/CLKIN
Low Pulse Width   Fast    PS8/MAXIGP1ACLK            n/a            1.500         1.500       0.000      PS8_X0Y0               d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/MAXIGP1ACLK
Low Pulse Width   Slow    PS8/MAXIGP1ACLK            n/a            1.500         1.500       0.000      PS8_X0Y0               d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/MAXIGP1ACLK
Low Pulse Width   Slow    PLLE4_ADV/CLKIN            n/a            1.050         1.500       0.450      PLL_X0Y6               d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[0].gen_plle4.PLLE4_BASE_INST_OTHER/CLKIN
Low Pulse Width   Fast    PLLE4_ADV/CLKIN            n/a            1.050         1.500       0.450      PLL_X0Y6               d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[0].gen_plle4.PLLE4_BASE_INST_OTHER/CLKIN
Low Pulse Width   Slow    PLLE4_ADV/CLKIN            n/a            1.050         1.500       0.450      PLL_X0Y8               d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[1].gen_plle4.PLLE4_BASE_INST_OTHER/CLKIN
Low Pulse Width   Fast    PLLE4_ADV/CLKIN            n/a            1.050         1.500       0.450      PLL_X0Y8               d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[1].gen_plle4.PLLE4_BASE_INST_OTHER/CLKIN
Low Pulse Width   Slow    PLLE4_ADV/CLKIN            n/a            1.050         1.500       0.450      PLL_X0Y10              d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[2].gen_plle4.PLLE4_BASE_INST_OTHER/CLKIN
Low Pulse Width   Fast    PLLE4_ADV/CLKIN            n/a            1.050         1.500       0.450      PLL_X0Y10              d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[2].gen_plle4.PLLE4_BASE_INST_OTHER/CLKIN
Low Pulse Width   Slow    RXTX_BITSLICE/FIFO_RD_CLK  n/a            0.762         1.500       0.738      BITSLICE_RX_TX_X0Y156  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/FIFO_RD_CLK
Low Pulse Width   Fast    RXTX_BITSLICE/FIFO_RD_CLK  n/a            0.762         1.500       0.738      BITSLICE_RX_TX_X0Y156  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/FIFO_RD_CLK
High Pulse Width  Slow    PS8/MAXIGP1ACLK            n/a            1.500         1.500       0.000      PS8_X0Y0               d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/MAXIGP1ACLK
High Pulse Width  Fast    PS8/MAXIGP1ACLK            n/a            1.500         1.500       0.000      PS8_X0Y0               d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/MAXIGP1ACLK
High Pulse Width  Slow    PLLE4_ADV/CLKIN            n/a            1.050         1.500       0.450      PLL_X0Y6               d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[0].gen_plle4.PLLE4_BASE_INST_OTHER/CLKIN
High Pulse Width  Fast    PLLE4_ADV/CLKIN            n/a            1.050         1.500       0.450      PLL_X0Y6               d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[0].gen_plle4.PLLE4_BASE_INST_OTHER/CLKIN
High Pulse Width  Slow    PLLE4_ADV/CLKIN            n/a            1.050         1.500       0.450      PLL_X0Y8               d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[1].gen_plle4.PLLE4_BASE_INST_OTHER/CLKIN
High Pulse Width  Fast    PLLE4_ADV/CLKIN            n/a            1.050         1.500       0.450      PLL_X0Y8               d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[1].gen_plle4.PLLE4_BASE_INST_OTHER/CLKIN
High Pulse Width  Slow    PLLE4_ADV/CLKIN            n/a            1.050         1.500       0.450      PLL_X0Y10              d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[2].gen_plle4.PLLE4_BASE_INST_OTHER/CLKIN
High Pulse Width  Fast    PLLE4_ADV/CLKIN            n/a            1.050         1.500       0.450      PLL_X0Y10              d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[2].gen_plle4.PLLE4_BASE_INST_OTHER/CLKIN
High Pulse Width  Slow    RXTX_BITSLICE/FIFO_RD_CLK  n/a            0.762         1.500       0.738      BITSLICE_RX_TX_X0Y156  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/FIFO_RD_CLK
High Pulse Width  Fast    RXTX_BITSLICE/FIFO_RD_CLK  n/a            0.762         1.500       0.738      BITSLICE_RX_TX_X0Y156  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/FIFO_RD_CLK



---------------------------------------------------------------------------------------------------
From Clock:  pll_clk[0]
  To Clock:  pll_clk[0]

Setup :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
PW    :            0  Failing Endpoints,  Worst Slack        0.000ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         pll_clk[0]
Waveform(ns):       { 0.000 0.188 }
Period(ns):         0.375
Sources:            { d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[0].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY }

Check Type        Corner  Lib Pin                   Reference Pin             Required(ns)  Actual(ns)  Slack(ns)  Location                Pin
Min Period        n/a     BITSLICE_CONTROL/PLL_CLK  n/a                       0.375         0.375       0.000      BITSLICE_CONTROL_X0Y24  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Min Period        n/a     BITSLICE_CONTROL/PLL_CLK  n/a                       0.375         0.375       0.000      BITSLICE_CONTROL_X0Y25  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Min Period        n/a     BITSLICE_CONTROL/PLL_CLK  n/a                       0.375         0.375       0.000      BITSLICE_CONTROL_X0Y26  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Min Period        n/a     BITSLICE_CONTROL/PLL_CLK  n/a                       0.375         0.375       0.000      BITSLICE_CONTROL_X0Y27  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Min Period        n/a     BITSLICE_CONTROL/PLL_CLK  n/a                       0.375         0.375       0.000      BITSLICE_CONTROL_X0Y28  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Min Period        n/a     BITSLICE_CONTROL/PLL_CLK  n/a                       0.375         0.375       0.000      BITSLICE_CONTROL_X0Y29  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Min Period        n/a     BITSLICE_CONTROL/PLL_CLK  n/a                       0.375         0.375       0.000      BITSLICE_CONTROL_X0Y30  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Min Period        n/a     BITSLICE_CONTROL/PLL_CLK  n/a                       0.375         0.375       0.000      BITSLICE_CONTROL_X0Y31  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Min Period        n/a     PLLE4_ADV/CLKOUTPHY       n/a                       0.333         0.375       0.042      PLL_X0Y6                d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[0].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
Low Pulse Width   Slow    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y24  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Low Pulse Width   Fast    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y24  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Low Pulse Width   Slow    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y25  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Low Pulse Width   Fast    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y25  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Low Pulse Width   Fast    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y30  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Low Pulse Width   Slow    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y31  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Low Pulse Width   Fast    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y31  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Low Pulse Width   Fast    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y26  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Low Pulse Width   Fast    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y27  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Low Pulse Width   Slow    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y28  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
High Pulse Width  Slow    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y25  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
High Pulse Width  Fast    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y25  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
High Pulse Width  Slow    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y26  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
High Pulse Width  Slow    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y27  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
High Pulse Width  Slow    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y30  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
High Pulse Width  Slow    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y31  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
High Pulse Width  Fast    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y31  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
High Pulse Width  Slow    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y24  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
High Pulse Width  Fast    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y24  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
High Pulse Width  Fast    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y26  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Max Skew          Fast    BITSLICE_CONTROL/PLL_CLK  BITSLICE_CONTROL/RIU_CLK  -0.300        -1.301      1.001      BITSLICE_CONTROL_X0Y28  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Max Skew          Fast    BITSLICE_CONTROL/PLL_CLK  BITSLICE_CONTROL/RIU_CLK  -0.300        -1.305      1.005      BITSLICE_CONTROL_X0Y30  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Max Skew          Fast    BITSLICE_CONTROL/PLL_CLK  BITSLICE_CONTROL/RIU_CLK  -0.300        -1.307      1.007      BITSLICE_CONTROL_X0Y29  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Max Skew          Fast    BITSLICE_CONTROL/PLL_CLK  BITSLICE_CONTROL/RIU_CLK  -0.300        -1.308      1.008      BITSLICE_CONTROL_X0Y26  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Max Skew          Fast    BITSLICE_CONTROL/PLL_CLK  BITSLICE_CONTROL/RIU_CLK  -0.300        -1.308      1.008      BITSLICE_CONTROL_X0Y27  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Max Skew          Fast    BITSLICE_CONTROL/PLL_CLK  BITSLICE_CONTROL/RIU_CLK  -0.300        -1.309      1.009      BITSLICE_CONTROL_X0Y24  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Max Skew          Fast    BITSLICE_CONTROL/PLL_CLK  BITSLICE_CONTROL/RIU_CLK  -0.300        -1.309      1.009      BITSLICE_CONTROL_X0Y31  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Max Skew          Fast    BITSLICE_CONTROL/PLL_CLK  BITSLICE_CONTROL/RIU_CLK  -0.300        -1.311      1.011      BITSLICE_CONTROL_X0Y25  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Max Skew          Slow    BITSLICE_CONTROL/PLL_CLK  BITSLICE_CONTROL/RIU_CLK  -0.300        -1.442      1.142      BITSLICE_CONTROL_X0Y28  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Max Skew          Slow    BITSLICE_CONTROL/PLL_CLK  BITSLICE_CONTROL/RIU_CLK  -0.300        -1.450      1.150      BITSLICE_CONTROL_X0Y30  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK



---------------------------------------------------------------------------------------------------
From Clock:  pll_clk[0]_DIV
  To Clock:  pll_clk[0]_DIV

Setup :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
PW    :            0  Failing Endpoints,  Worst Slack        0.300ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         pll_clk[0]_DIV
Waveform(ns):       { 0.000 1.500 }
Period(ns):         3.001
Sources:            { d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV4_CLK_Q d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV4_CLK_Q d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV4_CLK_Q d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV4_CLK_Q d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV4_CLK_Q d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV4_CLK_Q d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV4_CLK_Q d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV4_CLK_Q d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q }

Check Type        Corner  Lib Pin                           Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location               Pin
Min Period        n/a     RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            2.667         3.001       0.334      BITSLICE_RX_TX_X0Y156  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Min Period        n/a     RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            2.667         3.001       0.334      BITSLICE_RX_TX_X0Y158  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Min Period        n/a     RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            2.667         3.001       0.334      BITSLICE_RX_TX_X0Y159  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Min Period        n/a     RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            2.667         3.001       0.334      BITSLICE_RX_TX_X0Y160  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Min Period        n/a     RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            2.667         3.001       0.334      BITSLICE_RX_TX_X0Y161  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Min Period        n/a     RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            2.667         3.001       0.334      BITSLICE_RX_TX_X0Y162  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Min Period        n/a     RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            2.667         3.001       0.334      BITSLICE_RX_TX_X0Y164  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Min Period        n/a     RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            2.667         3.001       0.334      BITSLICE_RX_TX_X0Y165  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Min Period        n/a     RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            2.667         3.001       0.334      BITSLICE_RX_TX_X0Y166  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Min Period        n/a     RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            2.667         3.001       0.334      BITSLICE_RX_TX_X0Y167  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Low Pulse Width   Slow    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y156  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Low Pulse Width   Fast    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y156  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Low Pulse Width   Slow    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y158  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Low Pulse Width   Fast    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y158  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Low Pulse Width   Slow    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y159  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Low Pulse Width   Fast    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y159  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Low Pulse Width   Slow    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y160  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Low Pulse Width   Fast    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y160  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Low Pulse Width   Slow    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y161  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Low Pulse Width   Fast    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y161  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
High Pulse Width  Slow    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y156  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
High Pulse Width  Fast    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y156  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
High Pulse Width  Slow    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y158  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
High Pulse Width  Fast    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y158  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
High Pulse Width  Slow    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y159  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
High Pulse Width  Fast    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y159  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
High Pulse Width  Slow    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y160  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
High Pulse Width  Fast    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y160  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
High Pulse Width  Slow    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y161  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
High Pulse Width  Fast    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y161  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]



---------------------------------------------------------------------------------------------------
From Clock:  pll_clk[1]
  To Clock:  pll_clk[1]

Setup :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
PW    :            0  Failing Endpoints,  Worst Slack        0.000ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         pll_clk[1]
Waveform(ns):       { 0.000 0.188 }
Period(ns):         0.375
Sources:            { d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[1].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY }

Check Type        Corner  Lib Pin                   Reference Pin             Required(ns)  Actual(ns)  Slack(ns)  Location                Pin
Min Period        n/a     BITSLICE_CONTROL/PLL_CLK  n/a                       0.375         0.375       0.000      BITSLICE_CONTROL_X0Y32  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Min Period        n/a     BITSLICE_CONTROL/PLL_CLK  n/a                       0.375         0.375       0.000      BITSLICE_CONTROL_X0Y33  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Min Period        n/a     BITSLICE_CONTROL/PLL_CLK  n/a                       0.375         0.375       0.000      BITSLICE_CONTROL_X0Y34  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Min Period        n/a     BITSLICE_CONTROL/PLL_CLK  n/a                       0.375         0.375       0.000      BITSLICE_CONTROL_X0Y35  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Min Period        n/a     BITSLICE_CONTROL/PLL_CLK  n/a                       0.375         0.375       0.000      BITSLICE_CONTROL_X0Y36  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Min Period        n/a     BITSLICE_CONTROL/PLL_CLK  n/a                       0.375         0.375       0.000      BITSLICE_CONTROL_X0Y37  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Min Period        n/a     BITSLICE_CONTROL/PLL_CLK  n/a                       0.375         0.375       0.000      BITSLICE_CONTROL_X0Y38  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Min Period        n/a     BITSLICE_CONTROL/PLL_CLK  n/a                       0.375         0.375       0.000      BITSLICE_CONTROL_X0Y39  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Min Period        n/a     PLLE4_ADV/CLKOUTPHY       n/a                       0.333         0.375       0.042      PLL_X0Y8                d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[1].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
Low Pulse Width   Slow    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y32  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Low Pulse Width   Fast    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y32  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Low Pulse Width   Slow    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y33  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Low Pulse Width   Fast    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y33  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Low Pulse Width   Fast    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y34  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Low Pulse Width   Fast    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y35  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Low Pulse Width   Slow    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y36  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Low Pulse Width   Fast    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y36  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Low Pulse Width   Slow    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y37  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Low Pulse Width   Fast    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y37  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
High Pulse Width  Slow    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y34  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
High Pulse Width  Slow    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y35  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
High Pulse Width  Slow    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y38  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
High Pulse Width  Slow    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y33  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
High Pulse Width  Fast    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y33  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
High Pulse Width  Fast    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y34  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
High Pulse Width  Fast    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y35  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
High Pulse Width  Slow    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y36  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
High Pulse Width  Fast    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y36  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
High Pulse Width  Slow    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y37  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Max Skew          Fast    BITSLICE_CONTROL/PLL_CLK  BITSLICE_CONTROL/RIU_CLK  -0.300        -1.300      1.000      BITSLICE_CONTROL_X0Y36  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Max Skew          Fast    BITSLICE_CONTROL/PLL_CLK  BITSLICE_CONTROL/RIU_CLK  -0.300        -1.304      1.004      BITSLICE_CONTROL_X0Y38  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Max Skew          Fast    BITSLICE_CONTROL/PLL_CLK  BITSLICE_CONTROL/RIU_CLK  -0.300        -1.306      1.006      BITSLICE_CONTROL_X0Y37  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Max Skew          Fast    BITSLICE_CONTROL/PLL_CLK  BITSLICE_CONTROL/RIU_CLK  -0.300        -1.307      1.007      BITSLICE_CONTROL_X0Y34  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Max Skew          Fast    BITSLICE_CONTROL/PLL_CLK  BITSLICE_CONTROL/RIU_CLK  -0.300        -1.307      1.007      BITSLICE_CONTROL_X0Y35  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Max Skew          Fast    BITSLICE_CONTROL/PLL_CLK  BITSLICE_CONTROL/RIU_CLK  -0.300        -1.308      1.008      BITSLICE_CONTROL_X0Y32  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Max Skew          Fast    BITSLICE_CONTROL/PLL_CLK  BITSLICE_CONTROL/RIU_CLK  -0.300        -1.308      1.008      BITSLICE_CONTROL_X0Y39  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Max Skew          Fast    BITSLICE_CONTROL/PLL_CLK  BITSLICE_CONTROL/RIU_CLK  -0.300        -1.310      1.010      BITSLICE_CONTROL_X0Y33  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Max Skew          Slow    BITSLICE_CONTROL/PLL_CLK  BITSLICE_CONTROL/RIU_CLK  -0.300        -1.440      1.140      BITSLICE_CONTROL_X0Y36  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Max Skew          Slow    BITSLICE_CONTROL/PLL_CLK  BITSLICE_CONTROL/RIU_CLK  -0.300        -1.448      1.148      BITSLICE_CONTROL_X0Y38  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK



---------------------------------------------------------------------------------------------------
From Clock:  pll_clk[1]_DIV
  To Clock:  pll_clk[1]_DIV

Setup :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
PW    :            0  Failing Endpoints,  Worst Slack        0.300ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         pll_clk[1]_DIV
Waveform(ns):       { 0.000 1.500 }
Period(ns):         3.001
Sources:            { d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV4_CLK_Q d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV4_CLK_Q d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV4_CLK_Q d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV4_CLK_Q d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV4_CLK_Q d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV4_CLK_Q d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV4_CLK_Q d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV4_CLK_Q d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q }

Check Type        Corner  Lib Pin                           Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location               Pin
Min Period        n/a     RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            2.667         3.001       0.334      BITSLICE_RX_TX_X0Y208  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Min Period        n/a     RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            2.667         3.001       0.334      BITSLICE_RX_TX_X0Y210  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Min Period        n/a     RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            2.667         3.001       0.334      BITSLICE_RX_TX_X0Y211  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Min Period        n/a     RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            2.667         3.001       0.334      BITSLICE_RX_TX_X0Y212  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Min Period        n/a     RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            2.667         3.001       0.334      BITSLICE_RX_TX_X0Y213  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Min Period        n/a     RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            2.667         3.001       0.334      BITSLICE_RX_TX_X0Y214  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Min Period        n/a     RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            2.667         3.001       0.334      BITSLICE_RX_TX_X0Y216  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Min Period        n/a     RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            2.667         3.001       0.334      BITSLICE_RX_TX_X0Y217  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Min Period        n/a     RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            2.667         3.001       0.334      BITSLICE_RX_TX_X0Y218  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Min Period        n/a     RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            2.667         3.001       0.334      BITSLICE_RX_TX_X0Y219  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Low Pulse Width   Slow    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y208  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Low Pulse Width   Fast    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y208  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Low Pulse Width   Slow    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y210  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Low Pulse Width   Fast    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y210  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Low Pulse Width   Slow    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y211  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Low Pulse Width   Fast    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y211  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Low Pulse Width   Slow    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y212  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Low Pulse Width   Fast    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y212  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Low Pulse Width   Slow    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y213  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Low Pulse Width   Fast    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y213  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
High Pulse Width  Slow    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y208  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
High Pulse Width  Fast    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y208  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
High Pulse Width  Slow    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y210  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
High Pulse Width  Fast    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y210  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
High Pulse Width  Slow    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y211  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
High Pulse Width  Fast    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y211  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
High Pulse Width  Slow    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y212  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
High Pulse Width  Fast    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y212  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
High Pulse Width  Slow    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y213  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
High Pulse Width  Fast    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y213  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]



---------------------------------------------------------------------------------------------------
From Clock:  pll_clk[2]
  To Clock:  pll_clk[2]

Setup :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
PW    :            0  Failing Endpoints,  Worst Slack        0.000ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         pll_clk[2]
Waveform(ns):       { 0.000 0.188 }
Period(ns):         0.375
Sources:            { d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[2].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY }

Check Type        Corner  Lib Pin                   Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location                Pin
Min Period        n/a     BITSLICE_CONTROL/PLL_CLK  n/a            0.375         0.375       0.000      BITSLICE_CONTROL_X0Y44  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Min Period        n/a     BITSLICE_CONTROL/PLL_CLK  n/a            0.375         0.375       0.000      BITSLICE_CONTROL_X0Y45  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Min Period        n/a     BITSLICE_CONTROL/PLL_CLK  n/a            0.375         0.375       0.000      BITSLICE_CONTROL_X0Y46  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Min Period        n/a     BITSLICE_CONTROL/PLL_CLK  n/a            0.375         0.375       0.000      BITSLICE_CONTROL_X0Y47  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Min Period        n/a     BITSLICE_CONTROL/PLL_CLK  n/a            0.375         0.375       0.000      BITSLICE_CONTROL_X0Y42  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Min Period        n/a     BITSLICE_CONTROL/PLL_CLK  n/a            0.375         0.375       0.000      BITSLICE_CONTROL_X0Y43  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Min Period        n/a     PLLE4_ADV/CLKOUTPHY       n/a            0.333         0.375       0.042      PLL_X0Y10               d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[2].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
Low Pulse Width   Slow    BITSLICE_CONTROL/PLL_CLK  n/a            0.169         0.188       0.019      BITSLICE_CONTROL_X0Y44  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Low Pulse Width   Fast    BITSLICE_CONTROL/PLL_CLK  n/a            0.169         0.188       0.019      BITSLICE_CONTROL_X0Y44  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Low Pulse Width   Slow    BITSLICE_CONTROL/PLL_CLK  n/a            0.169         0.188       0.019      BITSLICE_CONTROL_X0Y45  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Low Pulse Width   Fast    BITSLICE_CONTROL/PLL_CLK  n/a            0.169         0.188       0.019      BITSLICE_CONTROL_X0Y45  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Low Pulse Width   Fast    BITSLICE_CONTROL/PLL_CLK  n/a            0.169         0.188       0.019      BITSLICE_CONTROL_X0Y46  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Low Pulse Width   Slow    BITSLICE_CONTROL/PLL_CLK  n/a            0.169         0.188       0.019      BITSLICE_CONTROL_X0Y47  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Low Pulse Width   Fast    BITSLICE_CONTROL/PLL_CLK  n/a            0.169         0.188       0.019      BITSLICE_CONTROL_X0Y47  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Low Pulse Width   Slow    BITSLICE_CONTROL/PLL_CLK  n/a            0.169         0.188       0.019      BITSLICE_CONTROL_X0Y46  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Low Pulse Width   Fast    BITSLICE_CONTROL/PLL_CLK  n/a            0.169         0.188       0.019      BITSLICE_CONTROL_X0Y42  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Low Pulse Width   Fast    BITSLICE_CONTROL/PLL_CLK  n/a            0.169         0.188       0.019      BITSLICE_CONTROL_X0Y43  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
High Pulse Width  Slow    BITSLICE_CONTROL/PLL_CLK  n/a            0.169         0.188       0.019      BITSLICE_CONTROL_X0Y46  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
High Pulse Width  Slow    BITSLICE_CONTROL/PLL_CLK  n/a            0.169         0.188       0.019      BITSLICE_CONTROL_X0Y44  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
High Pulse Width  Fast    BITSLICE_CONTROL/PLL_CLK  n/a            0.169         0.188       0.019      BITSLICE_CONTROL_X0Y44  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
High Pulse Width  Slow    BITSLICE_CONTROL/PLL_CLK  n/a            0.169         0.188       0.019      BITSLICE_CONTROL_X0Y45  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
High Pulse Width  Fast    BITSLICE_CONTROL/PLL_CLK  n/a            0.169         0.188       0.019      BITSLICE_CONTROL_X0Y45  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
High Pulse Width  Slow    BITSLICE_CONTROL/PLL_CLK  n/a            0.169         0.188       0.019      BITSLICE_CONTROL_X0Y42  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
High Pulse Width  Slow    BITSLICE_CONTROL/PLL_CLK  n/a            0.169         0.188       0.019      BITSLICE_CONTROL_X0Y43  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
High Pulse Width  Fast    BITSLICE_CONTROL/PLL_CLK  n/a            0.169         0.188       0.019      BITSLICE_CONTROL_X0Y46  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
High Pulse Width  Slow    BITSLICE_CONTROL/PLL_CLK  n/a            0.169         0.188       0.019      BITSLICE_CONTROL_X0Y47  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
High Pulse Width  Fast    BITSLICE_CONTROL/PLL_CLK  n/a            0.169         0.188       0.019      BITSLICE_CONTROL_X0Y47  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK



---------------------------------------------------------------------------------------------------
From Clock:  pll_clk[2]_DIV
  To Clock:  pll_clk[2]_DIV

Setup :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
PW    :            0  Failing Endpoints,  Worst Slack        0.300ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         pll_clk[2]_DIV
Waveform(ns):       { 0.000 1.500 }
Period(ns):         3.001
Sources:            { d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV4_CLK_Q d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV4_CLK_Q d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV4_CLK_Q d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV4_CLK_Q d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV4_CLK_Q d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV4_CLK_Q d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q }

Check Type        Corner  Lib Pin                           Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location               Pin
Min Period        n/a     RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            2.667         3.001       0.334      BITSLICE_RX_TX_X0Y286  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Min Period        n/a     RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            2.667         3.001       0.334      BITSLICE_RX_TX_X0Y288  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Min Period        n/a     RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            2.667         3.001       0.334      BITSLICE_RX_TX_X0Y289  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Min Period        n/a     RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            2.667         3.001       0.334      BITSLICE_RX_TX_X0Y290  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Min Period        n/a     RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            2.667         3.001       0.334      BITSLICE_RX_TX_X0Y291  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Min Period        n/a     RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            2.667         3.001       0.334      BITSLICE_RX_TX_X0Y292  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Min Period        n/a     RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            2.667         3.001       0.334      BITSLICE_RX_TX_X0Y293  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[1].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Min Period        n/a     RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            2.667         3.001       0.334      BITSLICE_RX_TX_X0Y294  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Min Period        n/a     RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            2.667         3.001       0.334      BITSLICE_RX_TX_X0Y295  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Min Period        n/a     RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            2.667         3.001       0.334      BITSLICE_RX_TX_X0Y296  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Low Pulse Width   Slow    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y286  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Low Pulse Width   Fast    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y286  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Low Pulse Width   Slow    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y288  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Low Pulse Width   Fast    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y288  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Low Pulse Width   Slow    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y289  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Low Pulse Width   Fast    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y289  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Low Pulse Width   Slow    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y290  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Low Pulse Width   Fast    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y290  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Low Pulse Width   Slow    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y291  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Low Pulse Width   Fast    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y291  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
High Pulse Width  Slow    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y286  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
High Pulse Width  Fast    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y286  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
High Pulse Width  Slow    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y288  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
High Pulse Width  Fast    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y288  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
High Pulse Width  Slow    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y289  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
High Pulse Width  Fast    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y289  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
High Pulse Width  Slow    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y290  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
High Pulse Width  Fast    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y290  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
High Pulse Width  Slow    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y291  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
High Pulse Width  Fast    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y291  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]



---------------------------------------------------------------------------------------------------
From Clock:  mmcm_clkout5
  To Clock:  mmcm_clkout5

Setup :            0  Failing Endpoints,  Worst Slack        9.803ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.031ns,  Total Violation        0.000ns
PW    :            0  Failing Endpoints,  Worst Slack        5.469ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             9.803ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i_reg/C
                            (rising edge-triggered cell FDPE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/dec_wdc_r_reg/D
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.002ns  (mmcm_clkout5 rise@12.002ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        1.976ns  (logic 0.503ns (25.451%)  route 1.473ns (74.549%))
  Logic Levels:           5  (LUT3=1 LUT4=1 LUT5=1 LUT6=2)
  Clock Path Skew:        -0.173ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.484ns = ( 16.487 - 12.002 ) 
    Source Clock Delay      (SCD):    4.321ns
    Clock Pessimism Removal (CPR):    -0.336ns
  Clock Uncertainty:      0.076ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.574ns (routing 0.632ns, distribution 0.942ns)
  Clock Net Delay (Destination): 1.344ns (routing 0.575ns, distribution 0.769ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.524     2.610    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     2.483 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.236     2.719    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y115        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.747 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.574     4.321    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/rd_clk
    SLICE_X105Y371       FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X105Y371       FDPE (Prop_GFF2_SLICEL_C_Q)
                                                      0.081     4.402 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i_reg/Q
                         net (fo=11, routed)          0.505     4.906    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/EMPTY_O
    SLICE_X105Y351       LUT4 (Prop_D5LUT_SLICEL_I2_O)
                                                      0.066     4.972 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/g0_b0__9_i_12/O
                         net (fo=2, routed)           0.233     5.205    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/ma_err_r_reg[0]_1
    SLICE_X105Y351       LUT6 (Prop_C6LUT_SLICEL_I0_O)
                                                      0.035     5.240 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/g0_b0__9_i_10/O
                         net (fo=2, routed)           0.209     5.449    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/g0_b0__9_i_10_n_0
    SLICE_X104Y354       LUT6 (Prop_C6LUT_SLICEM_I5_O)
                                                      0.037     5.486 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/g0_b0__9_i_2/O
                         net (fo=23, routed)          0.168     5.654    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/timeout_reg_0
    SLICE_X105Y353       LUT5 (Prop_E5LUT_SLICEL_I1_O)
                                                      0.138     5.792 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/g0_b0__7/O
                         net (fo=1, routed)           0.309     6.101    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/g0_b0__7_n_0
    SLICE_X105Y353       LUT3 (Prop_C6LUT_SLICEL_I0_O)
                                                      0.146     6.247 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/dec_wdc_r_i_1/O
                         net (fo=1, routed)           0.050     6.297    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER_n_10
    SLICE_X105Y353       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/dec_wdc_r_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                     12.002    12.002 r  
    J19                                               0.000    12.002 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079    12.081    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475    12.556 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040    12.596    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000    12.596 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297    12.893    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    12.917 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.364    14.281    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630    14.911 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.207    15.118    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y115        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    15.142 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.344    16.487    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/clk
    SLICE_X105Y353       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/dec_wdc_r_reg/C
                         clock pessimism             -0.336    16.150    
                         clock uncertainty           -0.076    16.075    
    SLICE_X105Y353       FDCE (Setup_CFF_SLICEL_C_D)
                                                      0.025    16.100    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/dec_wdc_r_reg
  -------------------------------------------------------------------
                         required time                         16.100    
                         arrival time                          -6.297    
  -------------------------------------------------------------------
                         slack                                  9.803    

Slack (MET) :             9.899ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i_reg/C
                            (rising edge-triggered cell FDPE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/auto_sl_drdy_reg/D
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.002ns  (mmcm_clkout5 rise@12.002ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        1.878ns  (logic 0.506ns (26.939%)  route 1.372ns (73.061%))
  Logic Levels:           5  (LUT3=1 LUT4=1 LUT5=1 LUT6=2)
  Clock Path Skew:        -0.174ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.483ns = ( 16.485 - 12.002 ) 
    Source Clock Delay      (SCD):    4.321ns
    Clock Pessimism Removal (CPR):    -0.336ns
  Clock Uncertainty:      0.076ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.574ns (routing 0.632ns, distribution 0.942ns)
  Clock Net Delay (Destination): 1.343ns (routing 0.575ns, distribution 0.768ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.524     2.610    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     2.483 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.236     2.719    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y115        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.747 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.574     4.321    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/rd_clk
    SLICE_X105Y371       FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X105Y371       FDPE (Prop_GFF2_SLICEL_C_Q)
                                                      0.081     4.402 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i_reg/Q
                         net (fo=11, routed)          0.505     4.906    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/EMPTY_O
    SLICE_X105Y351       LUT4 (Prop_D5LUT_SLICEL_I2_O)
                                                      0.066     4.972 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/g0_b0__9_i_12/O
                         net (fo=2, routed)           0.233     5.205    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/ma_err_r_reg[0]_1
    SLICE_X105Y351       LUT6 (Prop_C6LUT_SLICEL_I0_O)
                                                      0.035     5.240 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/g0_b0__9_i_10/O
                         net (fo=2, routed)           0.209     5.449    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/g0_b0__9_i_10_n_0
    SLICE_X104Y354       LUT6 (Prop_C6LUT_SLICEM_I5_O)
                                                      0.037     5.486 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/g0_b0__9_i_2/O
                         net (fo=23, routed)          0.215     5.701    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/timeout_reg_0
    SLICE_X104Y350       LUT5 (Prop_D5LUT_SLICEM_I1_O)
                                                      0.135     5.836 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/g0_b0__1/O
                         net (fo=1, routed)           0.153     5.989    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/g0_b0__1_n_0
    SLICE_X104Y351       LUT3 (Prop_H6LUT_SLICEM_I1_O)
                                                      0.152     6.141 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/auto_sl_drdy_i_1/O
                         net (fo=1, routed)           0.058     6.199    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER_n_8
    SLICE_X104Y351       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/auto_sl_drdy_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                     12.002    12.002 r  
    J19                                               0.000    12.002 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079    12.081    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475    12.556 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040    12.596    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000    12.596 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297    12.893    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    12.917 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.364    14.281    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630    14.911 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.207    15.118    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y115        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    15.142 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.343    16.485    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/clk
    SLICE_X104Y351       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/auto_sl_drdy_reg/C
                         clock pessimism             -0.336    16.149    
                         clock uncertainty           -0.076    16.073    
    SLICE_X104Y351       FDCE (Setup_HFF_SLICEM_C_D)
                                                      0.025    16.098    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/auto_sl_drdy_reg
  -------------------------------------------------------------------
                         required time                         16.098    
                         arrival time                          -6.199    
  -------------------------------------------------------------------
                         slack                                  9.899    

Slack (MET) :             9.908ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i_reg/C
                            (rising edge-triggered cell FDPE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/sl_den_r_reg[0]/D
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.002ns  (mmcm_clkout5 rise@12.002ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        1.869ns  (logic 0.465ns (24.881%)  route 1.404ns (75.119%))
  Logic Levels:           5  (LUT4=1 LUT5=1 LUT6=3)
  Clock Path Skew:        -0.175ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.482ns = ( 16.484 - 12.002 ) 
    Source Clock Delay      (SCD):    4.321ns
    Clock Pessimism Removal (CPR):    -0.336ns
  Clock Uncertainty:      0.076ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.574ns (routing 0.632ns, distribution 0.942ns)
  Clock Net Delay (Destination): 1.342ns (routing 0.575ns, distribution 0.767ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.524     2.610    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     2.483 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.236     2.719    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y115        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.747 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.574     4.321    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/rd_clk
    SLICE_X105Y371       FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X105Y371       FDPE (Prop_GFF2_SLICEL_C_Q)
                                                      0.081     4.402 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i_reg/Q
                         net (fo=11, routed)          0.505     4.906    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/EMPTY_O
    SLICE_X105Y351       LUT4 (Prop_D5LUT_SLICEL_I2_O)
                                                      0.066     4.972 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/g0_b0__9_i_12/O
                         net (fo=2, routed)           0.233     5.205    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/ma_err_r_reg[0]_1
    SLICE_X105Y351       LUT6 (Prop_C6LUT_SLICEL_I0_O)
                                                      0.035     5.240 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/g0_b0__9_i_10/O
                         net (fo=2, routed)           0.209     5.449    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/g0_b0__9_i_10_n_0
    SLICE_X104Y354       LUT6 (Prop_C6LUT_SLICEM_I5_O)
                                                      0.037     5.486 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/g0_b0__9_i_2/O
                         net (fo=23, routed)          0.259     5.746    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/timeout_reg_0
    SLICE_X105Y350       LUT5 (Prop_D6LUT_SLICEL_I1_O)
                                                      0.099     5.845 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/g0_b0__8/O
                         net (fo=1, routed)           0.152     5.997    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/g0_b0__8_n_0
    SLICE_X105Y351       LUT6 (Prop_E6LUT_SLICEL_I4_O)
                                                      0.147     6.144 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/sl_den_r[0]_i_1/O
                         net (fo=1, routed)           0.046     6.190    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER_n_12
    SLICE_X105Y351       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/sl_den_r_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                     12.002    12.002 r  
    J19                                               0.000    12.002 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079    12.081    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475    12.556 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040    12.596    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000    12.596 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297    12.893    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    12.917 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.364    14.281    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630    14.911 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.207    15.118    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y115        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    15.142 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.342    16.484    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/clk
    SLICE_X105Y351       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/sl_den_r_reg[0]/C
                         clock pessimism             -0.336    16.148    
                         clock uncertainty           -0.076    16.072    
    SLICE_X105Y351       FDCE (Setup_EFF_SLICEL_C_D)
                                                      0.025    16.097    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/sl_den_r_reg[0]
  -------------------------------------------------------------------
                         required time                         16.097    
                         arrival time                          -6.190    
  -------------------------------------------------------------------
                         slack                                  9.908    

Slack (MET) :             9.908ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i_reg/C
                            (rising edge-triggered cell FDPE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/sl_dwe_r_reg[0]/D
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.002ns  (mmcm_clkout5 rise@12.002ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        1.873ns  (logic 0.452ns (24.133%)  route 1.421ns (75.867%))
  Logic Levels:           5  (LUT4=1 LUT5=1 LUT6=3)
  Clock Path Skew:        -0.171ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.486ns = ( 16.489 - 12.002 ) 
    Source Clock Delay      (SCD):    4.321ns
    Clock Pessimism Removal (CPR):    -0.336ns
  Clock Uncertainty:      0.076ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.574ns (routing 0.632ns, distribution 0.942ns)
  Clock Net Delay (Destination): 1.346ns (routing 0.575ns, distribution 0.771ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.524     2.610    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     2.483 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.236     2.719    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y115        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.747 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.574     4.321    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/rd_clk
    SLICE_X105Y371       FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X105Y371       FDPE (Prop_GFF2_SLICEL_C_Q)
                                                      0.081     4.402 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i_reg/Q
                         net (fo=11, routed)          0.505     4.906    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/EMPTY_O
    SLICE_X105Y351       LUT4 (Prop_D5LUT_SLICEL_I2_O)
                                                      0.066     4.972 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/g0_b0__9_i_12/O
                         net (fo=2, routed)           0.233     5.205    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/ma_err_r_reg[0]_1
    SLICE_X105Y351       LUT6 (Prop_C6LUT_SLICEL_I0_O)
                                                      0.035     5.240 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/g0_b0__9_i_10/O
                         net (fo=2, routed)           0.209     5.449    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/g0_b0__9_i_10_n_0
    SLICE_X104Y354       LUT6 (Prop_C6LUT_SLICEM_I5_O)
                                                      0.037     5.486 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/g0_b0__9_i_2/O
                         net (fo=23, routed)          0.259     5.746    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/timeout_reg_0
    SLICE_X105Y350       LUT5 (Prop_D5LUT_SLICEL_I1_O)
                                                      0.110     5.856 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/g0_b0__9/O
                         net (fo=1, routed)           0.164     6.020    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/g0_b0__9_n_0
    SLICE_X105Y353       LUT6 (Prop_F6LUT_SLICEL_I4_O)
                                                      0.123     6.143 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/sl_dwe_r[0]_i_1/O
                         net (fo=1, routed)           0.051     6.194    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER_n_13
    SLICE_X105Y353       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/sl_dwe_r_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                     12.002    12.002 r  
    J19                                               0.000    12.002 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079    12.081    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475    12.556 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040    12.596    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000    12.596 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297    12.893    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    12.917 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.364    14.281    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630    14.911 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.207    15.118    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y115        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    15.142 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.346    16.489    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/clk
    SLICE_X105Y353       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/sl_dwe_r_reg[0]/C
                         clock pessimism             -0.336    16.152    
                         clock uncertainty           -0.076    16.077    
    SLICE_X105Y353       FDCE (Setup_FFF_SLICEL_C_D)
                                                      0.025    16.102    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/sl_dwe_r_reg[0]
  -------------------------------------------------------------------
                         required time                         16.102    
                         arrival time                          -6.194    
  -------------------------------------------------------------------
                         slack                                  9.908    

Slack (MET) :             9.921ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i_reg/C
                            (rising edge-triggered cell FDPE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/in_normal_mode_reg/CE
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.002ns  (mmcm_clkout5 rise@12.002ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        1.771ns  (logic 0.344ns (19.428%)  route 1.427ns (80.572%))
  Logic Levels:           4  (LUT4=1 LUT5=1 LUT6=2)
  Clock Path Skew:        -0.174ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.483ns = ( 16.485 - 12.002 ) 
    Source Clock Delay      (SCD):    4.321ns
    Clock Pessimism Removal (CPR):    -0.336ns
  Clock Uncertainty:      0.076ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.574ns (routing 0.632ns, distribution 0.942ns)
  Clock Net Delay (Destination): 1.343ns (routing 0.575ns, distribution 0.768ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.524     2.610    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     2.483 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.236     2.719    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y115        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.747 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.574     4.321    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/rd_clk
    SLICE_X105Y371       FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X105Y371       FDPE (Prop_GFF2_SLICEL_C_Q)
                                                      0.081     4.402 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i_reg/Q
                         net (fo=11, routed)          0.505     4.906    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/EMPTY_O
    SLICE_X105Y351       LUT4 (Prop_D5LUT_SLICEL_I2_O)
                                                      0.066     4.972 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/g0_b0__9_i_12/O
                         net (fo=2, routed)           0.233     5.205    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/ma_err_r_reg[0]_1
    SLICE_X105Y351       LUT6 (Prop_C6LUT_SLICEL_I0_O)
                                                      0.035     5.240 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/g0_b0__9_i_10/O
                         net (fo=2, routed)           0.209     5.449    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/g0_b0__9_i_10_n_0
    SLICE_X104Y354       LUT6 (Prop_C6LUT_SLICEM_I5_O)
                                                      0.037     5.486 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/g0_b0__9_i_2/O
                         net (fo=23, routed)          0.172     5.658    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/timeout_reg_0
    SLICE_X104Y350       LUT5 (Prop_H6LUT_SLICEM_I4_O)
                                                      0.125     5.783 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/sl_rst_r[0]_i_1/O
                         net (fo=2, routed)           0.308     6.091    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/in_normal_mode
    SLICE_X104Y351       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/in_normal_mode_reg/CE
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                     12.002    12.002 r  
    J19                                               0.000    12.002 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079    12.081    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475    12.556 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040    12.596    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000    12.596 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297    12.893    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    12.917 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.364    14.281    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630    14.911 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.207    15.118    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y115        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    15.142 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.343    16.485    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/clk
    SLICE_X104Y351       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/in_normal_mode_reg/C
                         clock pessimism             -0.336    16.149    
                         clock uncertainty           -0.076    16.073    
    SLICE_X104Y351       FDCE (Setup_HFF2_SLICEM_C_CE)
                                                     -0.061    16.012    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/in_normal_mode_reg
  -------------------------------------------------------------------
                         required time                         16.012    
                         arrival time                          -6.091    
  -------------------------------------------------------------------
                         slack                                  9.921    

Slack (MET) :             9.971ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i_reg/C
                            (rising edge-triggered cell FDPE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/sl_berr_r_reg[0]/D
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.002ns  (mmcm_clkout5 rise@12.002ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        1.812ns  (logic 0.429ns (23.672%)  route 1.383ns (76.328%))
  Logic Levels:           5  (LUT4=1 LUT5=1 LUT6=3)
  Clock Path Skew:        -0.169ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.488ns = ( 16.490 - 12.002 ) 
    Source Clock Delay      (SCD):    4.321ns
    Clock Pessimism Removal (CPR):    -0.336ns
  Clock Uncertainty:      0.076ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.574ns (routing 0.632ns, distribution 0.942ns)
  Clock Net Delay (Destination): 1.348ns (routing 0.575ns, distribution 0.773ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.524     2.610    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     2.483 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.236     2.719    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y115        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.747 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.574     4.321    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/rd_clk
    SLICE_X105Y371       FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X105Y371       FDPE (Prop_GFF2_SLICEL_C_Q)
                                                      0.081     4.402 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i_reg/Q
                         net (fo=11, routed)          0.505     4.906    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/EMPTY_O
    SLICE_X105Y351       LUT4 (Prop_D5LUT_SLICEL_I2_O)
                                                      0.066     4.972 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/g0_b0__9_i_12/O
                         net (fo=2, routed)           0.233     5.205    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/ma_err_r_reg[0]_1
    SLICE_X105Y351       LUT6 (Prop_C6LUT_SLICEL_I0_O)
                                                      0.035     5.240 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/g0_b0__9_i_10/O
                         net (fo=2, routed)           0.209     5.449    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/g0_b0__9_i_10_n_0
    SLICE_X104Y354       LUT6 (Prop_C6LUT_SLICEM_I5_O)
                                                      0.037     5.486 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/g0_b0__9_i_2/O
                         net (fo=23, routed)          0.215     5.701    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/timeout_reg_0
    SLICE_X104Y350       LUT5 (Prop_D6LUT_SLICEM_I1_O)
                                                      0.122     5.823 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/g0_b0__0/O
                         net (fo=1, routed)           0.172     5.995    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/g0_b0__0_n_0
    SLICE_X106Y350       LUT6 (Prop_C6LUT_SLICEL_I4_O)
                                                      0.088     6.083 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/sl_berr_r[0]_i_1/O
                         net (fo=1, routed)           0.050     6.133    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER_n_5
    SLICE_X106Y350       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/sl_berr_r_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                     12.002    12.002 r  
    J19                                               0.000    12.002 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079    12.081    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475    12.556 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040    12.596    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000    12.596 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297    12.893    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    12.917 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.364    14.281    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630    14.911 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.207    15.118    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y115        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    15.142 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.348    16.490    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/clk
    SLICE_X106Y350       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/sl_berr_r_reg[0]/C
                         clock pessimism             -0.336    16.154    
                         clock uncertainty           -0.076    16.079    
    SLICE_X106Y350       FDCE (Setup_CFF_SLICEL_C_D)
                                                      0.025    16.104    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/sl_berr_r_reg[0]
  -------------------------------------------------------------------
                         required time                         16.104    
                         arrival time                          -6.133    
  -------------------------------------------------------------------
                         slack                                  9.971    

Slack (MET) :             10.063ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i_reg/C
                            (rising edge-triggered cell FDPE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/inc_addr_r_reg/D
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.002ns  (mmcm_clkout5 rise@12.002ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        1.716ns  (logic 0.492ns (28.666%)  route 1.224ns (71.334%))
  Logic Levels:           5  (LUT3=1 LUT4=1 LUT5=1 LUT6=2)
  Clock Path Skew:        -0.173ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.484ns = ( 16.487 - 12.002 ) 
    Source Clock Delay      (SCD):    4.321ns
    Clock Pessimism Removal (CPR):    -0.336ns
  Clock Uncertainty:      0.076ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.574ns (routing 0.632ns, distribution 0.942ns)
  Clock Net Delay (Destination): 1.344ns (routing 0.575ns, distribution 0.769ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.524     2.610    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     2.483 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.236     2.719    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y115        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.747 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.574     4.321    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/rd_clk
    SLICE_X105Y371       FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X105Y371       FDPE (Prop_GFF2_SLICEL_C_Q)
                                                      0.081     4.402 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i_reg/Q
                         net (fo=11, routed)          0.505     4.906    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/EMPTY_O
    SLICE_X105Y351       LUT4 (Prop_D5LUT_SLICEL_I2_O)
                                                      0.066     4.972 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/g0_b0__9_i_12/O
                         net (fo=2, routed)           0.233     5.205    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/ma_err_r_reg[0]_1
    SLICE_X105Y351       LUT6 (Prop_C6LUT_SLICEL_I0_O)
                                                      0.035     5.240 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/g0_b0__9_i_10/O
                         net (fo=2, routed)           0.209     5.449    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/g0_b0__9_i_10_n_0
    SLICE_X104Y354       LUT6 (Prop_C6LUT_SLICEM_I5_O)
                                                      0.037     5.486 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/g0_b0__9_i_2/O
                         net (fo=23, routed)          0.181     5.667    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/timeout_reg_0
    SLICE_X105Y353       LUT5 (Prop_G6LUT_SLICEL_I1_O)
                                                      0.149     5.816 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/g0_b0__4/O
                         net (fo=1, routed)           0.048     5.864    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/g0_b0__4_n_0
    SLICE_X105Y353       LUT3 (Prop_B6LUT_SLICEL_I1_O)
                                                      0.124     5.988 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/inc_addr_r_i_1/O
                         net (fo=1, routed)           0.049     6.037    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER_n_9
    SLICE_X105Y353       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/inc_addr_r_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                     12.002    12.002 r  
    J19                                               0.000    12.002 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079    12.081    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475    12.556 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040    12.596    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000    12.596 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297    12.893    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    12.917 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.364    14.281    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630    14.911 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.207    15.118    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y115        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    15.142 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.344    16.487    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/clk
    SLICE_X105Y353       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/inc_addr_r_reg/C
                         clock pessimism             -0.336    16.150    
                         clock uncertainty           -0.076    16.075    
    SLICE_X105Y353       FDCE (Setup_BFF_SLICEL_C_D)
                                                      0.025    16.100    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/inc_addr_r_reg
  -------------------------------------------------------------------
                         required time                         16.100    
                         arrival time                          -6.037    
  -------------------------------------------------------------------
                         slack                                 10.063    

Slack (MET) :             10.085ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i_reg/C
                            (rising edge-triggered cell FDPE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/sl_rst_r_reg[0]/CE
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.002ns  (mmcm_clkout5 rise@12.002ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        1.610ns  (logic 0.344ns (21.371%)  route 1.266ns (78.629%))
  Logic Levels:           4  (LUT4=1 LUT5=1 LUT6=2)
  Clock Path Skew:        -0.172ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.485ns = ( 16.488 - 12.002 ) 
    Source Clock Delay      (SCD):    4.321ns
    Clock Pessimism Removal (CPR):    -0.336ns
  Clock Uncertainty:      0.076ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.574ns (routing 0.632ns, distribution 0.942ns)
  Clock Net Delay (Destination): 1.345ns (routing 0.575ns, distribution 0.770ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.524     2.610    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     2.483 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.236     2.719    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y115        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.747 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.574     4.321    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/rd_clk
    SLICE_X105Y371       FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X105Y371       FDPE (Prop_GFF2_SLICEL_C_Q)
                                                      0.081     4.402 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i_reg/Q
                         net (fo=11, routed)          0.505     4.906    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/EMPTY_O
    SLICE_X105Y351       LUT4 (Prop_D5LUT_SLICEL_I2_O)
                                                      0.066     4.972 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/g0_b0__9_i_12/O
                         net (fo=2, routed)           0.233     5.205    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/ma_err_r_reg[0]_1
    SLICE_X105Y351       LUT6 (Prop_C6LUT_SLICEL_I0_O)
                                                      0.035     5.240 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/g0_b0__9_i_10/O
                         net (fo=2, routed)           0.209     5.449    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/g0_b0__9_i_10_n_0
    SLICE_X104Y354       LUT6 (Prop_C6LUT_SLICEM_I5_O)
                                                      0.037     5.486 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/g0_b0__9_i_2/O
                         net (fo=23, routed)          0.172     5.658    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/timeout_reg_0
    SLICE_X104Y350       LUT5 (Prop_H6LUT_SLICEM_I4_O)
                                                      0.125     5.783 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/sl_rst_r[0]_i_1/O
                         net (fo=2, routed)           0.147     5.930    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/in_normal_mode
    SLICE_X105Y350       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/sl_rst_r_reg[0]/CE
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                     12.002    12.002 r  
    J19                                               0.000    12.002 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079    12.081    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475    12.556 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040    12.596    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000    12.596 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297    12.893    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    12.917 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.364    14.281    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630    14.911 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.207    15.118    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y115        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    15.142 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.345    16.488    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/clk
    SLICE_X105Y350       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/sl_rst_r_reg[0]/C
                         clock pessimism             -0.336    16.151    
                         clock uncertainty           -0.076    16.076    
    SLICE_X105Y350       FDCE (Setup_HFF2_SLICEL_C_CE)
                                                     -0.060    16.016    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/sl_rst_r_reg[0]
  -------------------------------------------------------------------
                         required time                         16.016    
                         arrival time                          -5.930    
  -------------------------------------------------------------------
                         slack                                 10.085    

Slack (MET) :             10.186ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i_reg/C
                            (rising edge-triggered cell FDPE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/active_sl_den_mask_reg[0]/D
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.002ns  (mmcm_clkout5 rise@12.002ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        1.597ns  (logic 0.420ns (26.305%)  route 1.177ns (73.695%))
  Logic Levels:           4  (LUT4=1 LUT6=3)
  Clock Path Skew:        -0.169ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.488ns = ( 16.490 - 12.002 ) 
    Source Clock Delay      (SCD):    4.321ns
    Clock Pessimism Removal (CPR):    -0.336ns
  Clock Uncertainty:      0.076ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.574ns (routing 0.632ns, distribution 0.942ns)
  Clock Net Delay (Destination): 1.348ns (routing 0.575ns, distribution 0.773ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.524     2.610    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     2.483 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.236     2.719    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y115        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.747 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.574     4.321    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/rd_clk
    SLICE_X105Y371       FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X105Y371       FDPE (Prop_GFF2_SLICEL_C_Q)
                                                      0.081     4.402 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i_reg/Q
                         net (fo=11, routed)          0.505     4.906    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/EMPTY_O
    SLICE_X105Y351       LUT4 (Prop_D5LUT_SLICEL_I2_O)
                                                      0.066     4.972 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/g0_b0__9_i_12/O
                         net (fo=2, routed)           0.233     5.205    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/ma_err_r_reg[0]_1
    SLICE_X105Y351       LUT6 (Prop_C6LUT_SLICEL_I0_O)
                                                      0.035     5.240 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/g0_b0__9_i_10/O
                         net (fo=2, routed)           0.203     5.443    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/g0_b0__9_i_10_n_0
    SLICE_X106Y353       LUT6 (Prop_G6LUT_SLICEL_I2_O)
                                                      0.149     5.592 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/active_sl_den_mask[0]_i_2/O
                         net (fo=1, routed)           0.187     5.779    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/active_sl_den_mask[0]_i_2_n_0
    SLICE_X106Y350       LUT6 (Prop_D6LUT_SLICEL_I1_O)
                                                      0.089     5.868 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/active_sl_den_mask[0]_i_1/O
                         net (fo=1, routed)           0.049     5.917    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER_n_11
    SLICE_X106Y350       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/active_sl_den_mask_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                     12.002    12.002 r  
    J19                                               0.000    12.002 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079    12.081    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475    12.556 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040    12.596    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000    12.596 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297    12.893    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    12.917 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.364    14.281    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630    14.911 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.207    15.118    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y115        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    15.142 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.348    16.490    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/clk
    SLICE_X106Y350       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/active_sl_den_mask_reg[0]/C
                         clock pessimism             -0.336    16.154    
                         clock uncertainty           -0.076    16.079    
    SLICE_X106Y350       FDCE (Setup_DFF_SLICEL_C_D)
                                                      0.025    16.104    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/active_sl_den_mask_reg[0]
  -------------------------------------------------------------------
                         required time                         16.104    
                         arrival time                          -5.917    
  -------------------------------------------------------------------
                         slack                                 10.186    

Slack (MET) :             10.191ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i_reg/C
                            (rising edge-triggered cell FDPE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/in_idle_mode_reg/D
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.002ns  (mmcm_clkout5 rise@12.002ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        1.585ns  (logic 0.308ns (19.427%)  route 1.277ns (80.573%))
  Logic Levels:           4  (LUT4=1 LUT6=3)
  Clock Path Skew:        -0.175ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.482ns = ( 16.484 - 12.002 ) 
    Source Clock Delay      (SCD):    4.321ns
    Clock Pessimism Removal (CPR):    -0.336ns
  Clock Uncertainty:      0.076ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.574ns (routing 0.632ns, distribution 0.942ns)
  Clock Net Delay (Destination): 1.342ns (routing 0.575ns, distribution 0.767ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.524     2.610    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     2.483 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.236     2.719    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y115        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.747 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.574     4.321    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/rd_clk
    SLICE_X105Y371       FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X105Y371       FDPE (Prop_GFF2_SLICEL_C_Q)
                                                      0.081     4.402 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i_reg/Q
                         net (fo=11, routed)          0.505     4.906    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/EMPTY_O
    SLICE_X105Y351       LUT4 (Prop_D5LUT_SLICEL_I2_O)
                                                      0.066     4.972 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/g0_b0__9_i_12/O
                         net (fo=2, routed)           0.233     5.205    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/ma_err_r_reg[0]_1
    SLICE_X105Y351       LUT6 (Prop_C6LUT_SLICEL_I0_O)
                                                      0.035     5.240 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/g0_b0__9_i_10/O
                         net (fo=2, routed)           0.209     5.449    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/g0_b0__9_i_10_n_0
    SLICE_X104Y354       LUT6 (Prop_C6LUT_SLICEM_I5_O)
                                                      0.037     5.486 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/g0_b0__9_i_2/O
                         net (fo=23, routed)          0.280     5.766    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/timeout_reg_0
    SLICE_X105Y351       LUT6 (Prop_F6LUT_SLICEL_I2_O)
                                                      0.089     5.855 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/in_idle_mode_i_1/O
                         net (fo=1, routed)           0.051     5.906    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER_n_0
    SLICE_X105Y351       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/in_idle_mode_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                     12.002    12.002 r  
    J19                                               0.000    12.002 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079    12.081    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475    12.556 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040    12.596    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000    12.596 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297    12.893    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    12.917 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.364    14.281    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630    14.911 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.207    15.118    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y115        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    15.142 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.342    16.484    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/clk
    SLICE_X105Y351       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/in_idle_mode_reg/C
                         clock pessimism             -0.336    16.148    
                         clock uncertainty           -0.076    16.072    
    SLICE_X105Y351       FDCE (Setup_FFF_SLICEL_C_D)
                                                      0.025    16.097    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/in_idle_mode_reg
  -------------------------------------------------------------------
                         required time                         16.097    
                         arrival time                          -5.906    
  -------------------------------------------------------------------
                         slack                                 10.191    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.031ns  (arrival time - required time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[77]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[77]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (mmcm_clkout5 rise@0.000ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        0.083ns  (logic 0.039ns (47.074%)  route 0.044ns (52.926%))
  Logic Levels:           0  
  Clock Path Skew:        0.006ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.516ns
    Source Clock Delay      (SCD):    2.639ns
    Clock Pessimism Removal (CPR):    -0.129ns
  Clock Net Delay (Source):      0.796ns (routing 0.347ns, distribution 0.449ns)
  Clock Net Delay (Destination): 0.906ns (routing 0.388ns, distribution 0.518ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.839     1.456    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     1.686 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.140     1.826    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y115        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.843 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.796     2.639    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/sl_iport_i[1]
    SLICE_X96Y352        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[77]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X96Y352        FDRE (Prop_HFF_SLICEM_C_Q)
                                                      0.039     2.678 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[77]/Q
                         net (fo=2, routed)           0.044     2.722    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp[77]
    SLICE_X96Y352        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[77]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.940     1.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     1.432 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.159     1.591    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y115        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.610 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.906     2.516    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/sl_iport_i[1]
    SLICE_X96Y352        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[77]/C
                         clock pessimism              0.129     2.645    
    SLICE_X96Y352        FDRE (Hold_HFF_SLICEM_C_D)
                                                      0.046     2.691    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[77]
  -------------------------------------------------------------------
                         required time                         -2.691    
                         arrival time                           2.722    
  -------------------------------------------------------------------
                         slack                                  0.031    

Slack (MET) :             0.031ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/ma_wr_pop_r_reg/C
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i_reg/D
                            (rising edge-triggered cell FDPE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (mmcm_clkout5 rise@0.000ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        0.274ns  (logic 0.080ns (29.197%)  route 0.194ns (70.802%))
  Logic Levels:           1  (LUT6=1)
  Clock Path Skew:        0.181ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    4.321ns
    Source Clock Delay      (SCD):    4.476ns
    Clock Pessimism Removal (CPR):    -0.336ns
  Clock Net Delay (Source):      1.336ns (routing 0.575ns, distribution 0.761ns)
  Clock Net Delay (Destination): 1.574ns (routing 0.632ns, distribution 0.942ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.364     2.279    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630     2.909 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.207     3.116    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y115        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.140 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.336     4.476    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/clk
    SLICE_X105Y355       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/ma_wr_pop_r_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X105Y355       FDCE (Prop_CFF_SLICEL_C_Q)
                                                      0.058     4.534 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/ma_wr_pop_r_reg/Q
                         net (fo=4, routed)           0.174     4.708    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/rd_en
    SLICE_X105Y371       LUT6 (Prop_G6LUT_SLICEL_I2_O)
                                                      0.022     4.730 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/ram_empty_i_i_1/O
                         net (fo=2, routed)           0.020     4.750    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i_reg_1
    SLICE_X105Y371       FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.524     2.610    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     2.483 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.236     2.719    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y115        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.747 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.574     4.321    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/rd_clk
    SLICE_X105Y371       FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i_reg/C
                         clock pessimism              0.336     4.657    
    SLICE_X105Y371       FDPE (Hold_GFF2_SLICEL_C_D)
                                                      0.062     4.719    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i_reg
  -------------------------------------------------------------------
                         required time                         -4.719    
                         arrival time                           4.750    
  -------------------------------------------------------------------
                         slack                                  0.031    

Slack (MET) :             0.031ns  (arrival time - required time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[6]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[6]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (mmcm_clkout5 rise@0.000ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        0.083ns  (logic 0.039ns (46.935%)  route 0.044ns (53.065%))
  Logic Levels:           0  
  Clock Path Skew:        0.006ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.525ns
    Source Clock Delay      (SCD):    2.646ns
    Clock Pessimism Removal (CPR):    -0.127ns
  Clock Net Delay (Source):      0.803ns (routing 0.347ns, distribution 0.456ns)
  Clock Net Delay (Destination): 0.915ns (routing 0.388ns, distribution 0.527ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.839     1.456    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     1.686 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.140     1.826    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y115        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.843 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.803     2.646    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/sl_iport_i[1]
    SLICE_X94Y358        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[6]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X94Y358        FDRE (Prop_HFF_SLICEM_C_Q)
                                                      0.039     2.685 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[6]/Q
                         net (fo=2, routed)           0.044     2.729    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp[6]
    SLICE_X94Y358        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[6]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.940     1.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     1.432 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.159     1.591    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y115        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.610 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.915     2.525    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/sl_iport_i[1]
    SLICE_X94Y358        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[6]/C
                         clock pessimism              0.127     2.652    
    SLICE_X94Y358        FDRE (Hold_HFF_SLICEM_C_D)
                                                      0.046     2.698    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[6]
  -------------------------------------------------------------------
                         required time                         -2.698    
                         arrival time                           2.729    
  -------------------------------------------------------------------
                         slack                                  0.031    

Slack (MET) :             0.031ns  (arrival time - required time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[91]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[91]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (mmcm_clkout5 rise@0.000ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        0.083ns  (logic 0.039ns (46.935%)  route 0.044ns (53.065%))
  Logic Levels:           0  
  Clock Path Skew:        0.006ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.521ns
    Source Clock Delay      (SCD):    2.644ns
    Clock Pessimism Removal (CPR):    -0.129ns
  Clock Net Delay (Source):      0.801ns (routing 0.347ns, distribution 0.454ns)
  Clock Net Delay (Destination): 0.911ns (routing 0.388ns, distribution 0.523ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.839     1.456    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     1.686 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.140     1.826    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y115        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.843 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.801     2.644    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/sl_iport_i[1]
    SLICE_X96Y354        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[91]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X96Y354        FDRE (Prop_HFF_SLICEM_C_Q)
                                                      0.039     2.683 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[91]/Q
                         net (fo=2, routed)           0.044     2.727    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp[91]
    SLICE_X96Y354        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[91]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.940     1.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     1.432 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.159     1.591    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y115        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.610 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.911     2.521    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/sl_iport_i[1]
    SLICE_X96Y354        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[91]/C
                         clock pessimism              0.129     2.650    
    SLICE_X96Y354        FDRE (Hold_HFF_SLICEM_C_D)
                                                      0.046     2.696    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[91]
  -------------------------------------------------------------------
                         required time                         -2.696    
                         arrival time                           2.727    
  -------------------------------------------------------------------
                         slack                                  0.031    

Slack (MET) :             0.034ns  (arrival time - required time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[41]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[41]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (mmcm_clkout5 rise@0.000ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        0.086ns  (logic 0.039ns (45.517%)  route 0.047ns (54.483%))
  Logic Levels:           0  
  Clock Path Skew:        0.006ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.517ns
    Source Clock Delay      (SCD):    2.640ns
    Clock Pessimism Removal (CPR):    -0.129ns
  Clock Net Delay (Source):      0.797ns (routing 0.347ns, distribution 0.450ns)
  Clock Net Delay (Destination): 0.907ns (routing 0.388ns, distribution 0.519ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.839     1.456    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     1.686 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.140     1.826    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y115        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.843 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.797     2.640    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/sl_iport_i[1]
    SLICE_X95Y351        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[41]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X95Y351        FDRE (Prop_FFF_SLICEL_C_Q)
                                                      0.039     2.679 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[41]/Q
                         net (fo=2, routed)           0.047     2.725    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp[41]
    SLICE_X95Y351        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[41]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.940     1.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     1.432 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.159     1.591    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y115        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.610 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.907     2.517    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/sl_iport_i[1]
    SLICE_X95Y351        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[41]/C
                         clock pessimism              0.129     2.646    
    SLICE_X95Y351        FDRE (Hold_FFF_SLICEL_C_D)
                                                      0.046     2.692    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[41]
  -------------------------------------------------------------------
                         required time                         -2.692    
                         arrival time                           2.725    
  -------------------------------------------------------------------
                         slack                                  0.034    

Slack (MET) :             0.037ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_reg[2]/C
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[2]/D
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (mmcm_clkout5 rise@0.000ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        0.143ns  (logic 0.059ns (41.149%)  route 0.084ns (58.851%))
  Logic Levels:           0  
  Clock Path Skew:        0.046ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    4.332ns
    Source Clock Delay      (SCD):    4.527ns
    Clock Pessimism Removal (CPR):    -0.241ns
  Clock Net Delay (Source):      1.387ns (routing 0.575ns, distribution 0.812ns)
  Clock Net Delay (Destination): 1.585ns (routing 0.632ns, distribution 0.953ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.364     2.279    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630     2.909 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.207     3.116    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y115        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.140 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.387     4.527    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/rd_clk
    SLICE_X105Y371       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X105Y371       FDCE (Prop_GFF_SLICEL_C_Q)
                                                      0.059     4.586 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_reg[2]/Q
                         net (fo=4, routed)           0.084     4.670    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/rd_pntr_plus1[2]
    SLICE_X105Y370       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[2]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.524     2.610    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     2.483 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.236     2.719    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y115        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.747 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.585     4.332    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/rd_clk
    SLICE_X105Y370       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[2]/C
                         clock pessimism              0.241     4.573    
    SLICE_X105Y370       FDCE (Hold_FFF_SLICEL_C_D)
                                                      0.060     4.633    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[2]
  -------------------------------------------------------------------
                         required time                         -4.633    
                         arrival time                           4.670    
  -------------------------------------------------------------------
                         slack                                  0.037    

Slack (MET) :             0.038ns  (arrival time - required time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/G_1PIPE_IFACE.s_do_r_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_MSTR2SL_PORT_IFACE/MA_RD_DIN_O_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (mmcm_clkout5 rise@0.000ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        0.246ns  (logic 0.058ns (23.577%)  route 0.188ns (76.423%))
  Logic Levels:           0  
  Clock Path Skew:        0.148ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    4.261ns
    Source Clock Delay      (SCD):    4.411ns
    Clock Pessimism Removal (CPR):    -0.298ns
  Clock Net Delay (Source):      1.271ns (routing 0.575ns, distribution 0.696ns)
  Clock Net Delay (Destination): 1.514ns (routing 0.632ns, distribution 0.882ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.364     2.279    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630     2.909 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.207     3.116    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y115        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.140 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.271     4.411    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/sl_iport_i[1]
    SLICE_X96Y355        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/G_1PIPE_IFACE.s_do_r_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X96Y355        FDRE (Prop_HFF_SLICEM_C_Q)
                                                      0.058     4.469 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/G_1PIPE_IFACE.s_do_r_reg[0]/Q
                         net (fo=1, routed)           0.188     4.657    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_MSTR2SL_PORT_IFACE/rd_din_mux[0]
    SLICE_X99Y354        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_MSTR2SL_PORT_IFACE/MA_RD_DIN_O_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.524     2.610    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     2.483 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.236     2.719    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y115        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.747 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.514     4.261    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_MSTR2SL_PORT_IFACE/clk
    SLICE_X99Y354        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_MSTR2SL_PORT_IFACE/MA_RD_DIN_O_reg[0]/C
                         clock pessimism              0.298     4.559    
    SLICE_X99Y354        FDRE (Hold_AFF_SLICEM_C_D)
                                                      0.060     4.619    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_MSTR2SL_PORT_IFACE/MA_RD_DIN_O_reg[0]
  -------------------------------------------------------------------
                         required time                         -4.619    
                         arrival time                           4.657    
  -------------------------------------------------------------------
                         slack                                  0.038    

Slack (MET) :             0.038ns  (arrival time - required time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/G_1PIPE_IFACE.s_do_r_reg[7]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_MSTR2SL_PORT_IFACE/MA_RD_DIN_O_reg[7]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (mmcm_clkout5 rise@0.000ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        0.242ns  (logic 0.060ns (24.793%)  route 0.182ns (75.207%))
  Logic Levels:           0  
  Clock Path Skew:        0.142ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    4.250ns
    Source Clock Delay      (SCD):    4.406ns
    Clock Pessimism Removal (CPR):    -0.298ns
  Clock Net Delay (Source):      1.266ns (routing 0.575ns, distribution 0.691ns)
  Clock Net Delay (Destination): 1.503ns (routing 0.632ns, distribution 0.871ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.364     2.279    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630     2.909 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.207     3.116    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y115        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.140 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.266     4.406    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/sl_iport_i[1]
    SLICE_X95Y355        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/G_1PIPE_IFACE.s_do_r_reg[7]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X95Y355        FDRE (Prop_GFF2_SLICEL_C_Q)
                                                      0.060     4.466 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/G_1PIPE_IFACE.s_do_r_reg[7]/Q
                         net (fo=1, routed)           0.182     4.648    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_MSTR2SL_PORT_IFACE/rd_din_mux[7]
    SLICE_X99Y353        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_MSTR2SL_PORT_IFACE/MA_RD_DIN_O_reg[7]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.524     2.610    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     2.483 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.236     2.719    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y115        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.747 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.503     4.250    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_MSTR2SL_PORT_IFACE/clk
    SLICE_X99Y353        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_MSTR2SL_PORT_IFACE/MA_RD_DIN_O_reg[7]/C
                         clock pessimism              0.298     4.548    
    SLICE_X99Y353        FDRE (Hold_CFF2_SLICEM_C_D)
                                                      0.062     4.610    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_MSTR2SL_PORT_IFACE/MA_RD_DIN_O_reg[7]
  -------------------------------------------------------------------
                         required time                         -4.610    
                         arrival time                           4.648    
  -------------------------------------------------------------------
                         slack                                  0.038    

Slack (MET) :             0.040ns  (arrival time - required time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/G_1PIPE_IFACE.s_do_r_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_MSTR2SL_PORT_IFACE/MA_RD_DIN_O_reg[1]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (mmcm_clkout5 rise@0.000ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        0.238ns  (logic 0.059ns (24.790%)  route 0.179ns (75.210%))
  Logic Levels:           0  
  Clock Path Skew:        0.136ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    4.249ns
    Source Clock Delay      (SCD):    4.411ns
    Clock Pessimism Removal (CPR):    -0.298ns
  Clock Net Delay (Source):      1.271ns (routing 0.575ns, distribution 0.696ns)
  Clock Net Delay (Destination): 1.502ns (routing 0.632ns, distribution 0.870ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.364     2.279    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630     2.909 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.207     3.116    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y115        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.140 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.271     4.411    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/sl_iport_i[1]
    SLICE_X96Y355        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/G_1PIPE_IFACE.s_do_r_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X96Y355        FDRE (Prop_HFF2_SLICEM_C_Q)
                                                      0.059     4.470 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/G_1PIPE_IFACE.s_do_r_reg[1]/Q
                         net (fo=1, routed)           0.179     4.649    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_MSTR2SL_PORT_IFACE/rd_din_mux[1]
    SLICE_X99Y352        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_MSTR2SL_PORT_IFACE/MA_RD_DIN_O_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.524     2.610    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     2.483 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.236     2.719    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y115        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.747 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.502     4.249    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_MSTR2SL_PORT_IFACE/clk
    SLICE_X99Y352        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_MSTR2SL_PORT_IFACE/MA_RD_DIN_O_reg[1]/C
                         clock pessimism              0.298     4.547    
    SLICE_X99Y352        FDRE (Hold_BFF2_SLICEM_C_D)
                                                      0.062     4.609    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_MSTR2SL_PORT_IFACE/MA_RD_DIN_O_reg[1]
  -------------------------------------------------------------------
                         required time                         -4.609    
                         arrival time                           4.649    
  -------------------------------------------------------------------
                         slack                                  0.040    

Slack (MET) :             0.040ns  (arrival time - required time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[119]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[119]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (mmcm_clkout5 rise@0.000ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        0.092ns  (logic 0.037ns (40.284%)  route 0.055ns (59.716%))
  Logic Levels:           0  
  Clock Path Skew:        0.006ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.521ns
    Source Clock Delay      (SCD):    2.643ns
    Clock Pessimism Removal (CPR):    -0.128ns
  Clock Net Delay (Source):      0.800ns (routing 0.347ns, distribution 0.453ns)
  Clock Net Delay (Destination): 0.911ns (routing 0.388ns, distribution 0.523ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.839     1.456    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     1.686 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.140     1.826    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y115        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.843 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.800     2.643    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/sl_iport_i[1]
    SLICE_X94Y359        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[119]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X94Y359        FDRE (Prop_FFF_SLICEM_C_Q)
                                                      0.037     2.680 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[119]/Q
                         net (fo=2, routed)           0.055     2.734    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp[119]
    SLICE_X94Y359        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[119]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.940     1.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     1.432 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.159     1.591    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y115        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.610 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.911     2.521    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/sl_iport_i[1]
    SLICE_X94Y359        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[119]/C
                         clock pessimism              0.128     2.649    
    SLICE_X94Y359        FDRE (Hold_FFF_SLICEM_C_D)
                                                      0.046     2.695    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[119]
  -------------------------------------------------------------------
                         required time                         -2.695    
                         arrival time                           2.734    
  -------------------------------------------------------------------
                         slack                                  0.040    





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         mmcm_clkout5
Waveform(ns):       { 0.000 6.001 }
Period(ns):         12.002
Sources:            { d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5 }

Check Type        Corner  Lib Pin             Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location       Pin
Min Period        n/a     BUFGCE/I            n/a            1.290         12.002      10.712     BUFGCE_X0Y115  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/I
Min Period        n/a     MMCME4_ADV/CLKOUT5  n/a            1.071         12.002      10.931     MMCM_X0Y4      d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
Min Period        n/a     RAMD32/CLK          n/a            1.064         12.002      10.938     SLICE_X99Y351  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMA/CLK
Min Period        n/a     RAMD32/CLK          n/a            1.064         12.002      10.938     SLICE_X99Y351  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMA_D1/CLK
Min Period        n/a     RAMD32/CLK          n/a            1.064         12.002      10.938     SLICE_X99Y351  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMB/CLK
Min Period        n/a     RAMD32/CLK          n/a            1.064         12.002      10.938     SLICE_X99Y351  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMB_D1/CLK
Min Period        n/a     RAMD32/CLK          n/a            1.064         12.002      10.938     SLICE_X99Y351  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMC/CLK
Min Period        n/a     RAMD32/CLK          n/a            1.064         12.002      10.938     SLICE_X99Y351  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMC_D1/CLK
Min Period        n/a     RAMD32/CLK          n/a            1.064         12.002      10.938     SLICE_X99Y351  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMD/CLK
Min Period        n/a     RAMD32/CLK          n/a            1.064         12.002      10.938     SLICE_X99Y351  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMD_D1/CLK
Low Pulse Width   Slow    RAMD32/CLK          n/a            0.532         6.001       5.469      SLICE_X99Y351  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMA/CLK
Low Pulse Width   Fast    RAMD32/CLK          n/a            0.532         6.001       5.469      SLICE_X99Y351  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMA/CLK
Low Pulse Width   Slow    RAMD32/CLK          n/a            0.532         6.001       5.469      SLICE_X99Y351  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMA_D1/CLK
Low Pulse Width   Fast    RAMD32/CLK          n/a            0.532         6.001       5.469      SLICE_X99Y351  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMA_D1/CLK
Low Pulse Width   Slow    RAMD32/CLK          n/a            0.532         6.001       5.469      SLICE_X99Y351  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMB/CLK
Low Pulse Width   Fast    RAMD32/CLK          n/a            0.532         6.001       5.469      SLICE_X99Y351  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMB/CLK
Low Pulse Width   Slow    RAMD32/CLK          n/a            0.532         6.001       5.469      SLICE_X99Y351  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMB_D1/CLK
Low Pulse Width   Fast    RAMD32/CLK          n/a            0.532         6.001       5.469      SLICE_X99Y351  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMB_D1/CLK
Low Pulse Width   Slow    RAMD32/CLK          n/a            0.532         6.001       5.469      SLICE_X99Y351  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMC/CLK
Low Pulse Width   Fast    RAMD32/CLK          n/a            0.532         6.001       5.469      SLICE_X99Y351  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMC/CLK
High Pulse Width  Slow    RAMD32/CLK          n/a            0.532         6.001       5.469      SLICE_X99Y351  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMA/CLK
High Pulse Width  Fast    RAMD32/CLK          n/a            0.532         6.001       5.469      SLICE_X99Y351  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMA/CLK
High Pulse Width  Slow    RAMD32/CLK          n/a            0.532         6.001       5.469      SLICE_X99Y351  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMA_D1/CLK
High Pulse Width  Fast    RAMD32/CLK          n/a            0.532         6.001       5.469      SLICE_X99Y351  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMA_D1/CLK
High Pulse Width  Slow    RAMD32/CLK          n/a            0.532         6.001       5.469      SLICE_X99Y351  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMB/CLK
High Pulse Width  Fast    RAMD32/CLK          n/a            0.532         6.001       5.469      SLICE_X99Y351  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMB/CLK
High Pulse Width  Slow    RAMD32/CLK          n/a            0.532         6.001       5.469      SLICE_X99Y351  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMB_D1/CLK
High Pulse Width  Fast    RAMD32/CLK          n/a            0.532         6.001       5.469      SLICE_X99Y351  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMB_D1/CLK
High Pulse Width  Slow    RAMD32/CLK          n/a            0.532         6.001       5.469      SLICE_X99Y351  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMC/CLK
High Pulse Width  Fast    RAMD32/CLK          n/a            0.532         6.001       5.469      SLICE_X99Y351  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMC/CLK



---------------------------------------------------------------------------------------------------
From Clock:  mmcm_clkout6
  To Clock:  mmcm_clkout6

Setup :            0  Failing Endpoints,  Worst Slack        0.731ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.027ns,  Total Violation        0.000ns
PW    :            0  Failing Endpoints,  Worst Slack        0.997ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.731ns  (required time - arrival time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[4]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data_reg[11]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             mmcm_clkout6
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.001ns  (mmcm_clkout6 rise@6.001ns - mmcm_clkout6 rise@0.000ns)
  Data Path Delay:        5.052ns  (logic 0.709ns (14.033%)  route 4.343ns (85.967%))
  Logic Levels:           7  (LUT2=1 LUT6=4 MUXF7=2)
  Clock Path Skew:        -0.174ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.879ns = ( 10.880 - 6.001 ) 
    Source Clock Delay      (SCD):    4.740ns
    Clock Pessimism Removal (CPR):    -0.313ns
  Clock Uncertainty:      0.068ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.968ns (routing 0.708ns, distribution 1.260ns)
  Clock Net Delay (Destination): 1.720ns (routing 0.642ns, distribution 1.078ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.524     2.610    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.127     2.483 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.261     2.744    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y104        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.772 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.968     4.740    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/CLK
    SLICE_X93Y321        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X93Y321        FDRE (Prop_BFF2_SLICEM_C_Q)
                                                      0.080     4.820 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[4]/Q
                         net (fo=40, routed)          0.564     5.384    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/io_address_riuclk[4]
    SLICE_X92Y309        LUT2 (Prop_D6LUT_SLICEL_I0_O)
                                                      0.050     5.434 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_nibble_8[0]_INST_0_i_11/O
                         net (fo=4, routed)           0.441     5.875    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_nibble_8[0]_INST_0_i_11_n_0
    SLICE_X90Y302        LUT6 (Prop_C6LUT_SLICEM_I3_O)
                                                      0.088     5.963 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_nibble_8[1]_INST_0_i_15/O
                         net (fo=1, routed)           0.021     5.984    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_nibble_8[1]_INST_0_i_15_n_0
    SLICE_X90Y302        MUXF7 (Prop_F7MUX_CD_SLICEM_I1_O)
                                                      0.068     6.052 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_nibble_8[1]_INST_0_i_9/O
                         net (fo=1, routed)           0.308     6.360    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_nibble_8[1]_INST_0_i_9_n_0
    SLICE_X91Y302        LUT6 (Prop_G6LUT_SLICEL_I4_O)
                                                      0.123     6.483 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_nibble_8[1]_INST_0_i_2/O
                         net (fo=65, routed)          1.919     8.402    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_nibble_8[1]_INST_0_i_2_n_0
    SLICE_X82Y193        LUT6 (Prop_F6LUT_SLICEM_I2_O)
                                                      0.148     8.550 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data[11]_i_4/O
                         net (fo=1, routed)           1.050     9.600    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data[11]_i_4_n_0
    SLICE_X81Y299        LUT6 (Prop_D6LUT_SLICEL_I0_O)
                                                      0.089     9.689 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data[11]_i_2/O
                         net (fo=1, routed)           0.009     9.698    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data[11]_i_2_n_0
    SLICE_X81Y299        MUXF7 (Prop_F7MUX_CD_SLICEL_I0_O)
                                                      0.063     9.761 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data_reg[11]_i_1/O
                         net (fo=1, routed)           0.031     9.792    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data_reg[11]_i_1_n_0
    SLICE_X81Y299        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data_reg[11]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      6.001     6.001 r  
    J19                                               0.000     6.001 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     6.080    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     6.555 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     6.595    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     6.595 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     6.892    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     6.916 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.364     8.280    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.630     8.910 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.226     9.136    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y104        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     9.160 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.720    10.880    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_clk
    SLICE_X81Y299        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data_reg[11]/C
                         clock pessimism             -0.313    10.567    
                         clock uncertainty           -0.068    10.499    
    SLICE_X81Y299        FDRE (Setup_DFF_SLICEL_C_D)
                                                      0.025    10.524    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data_reg[11]
  -------------------------------------------------------------------
                         required time                         10.524    
                         arrival time                          -9.792    
  -------------------------------------------------------------------
                         slack                                  0.731    

Slack (MET) :             0.830ns  (required time - arrival time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[4]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data_reg[3]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             mmcm_clkout6
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.001ns  (mmcm_clkout6 rise@6.001ns - mmcm_clkout6 rise@0.000ns)
  Data Path Delay:        5.037ns  (logic 0.653ns (12.964%)  route 4.384ns (87.036%))
  Logic Levels:           7  (LUT2=1 LUT6=4 MUXF7=2)
  Clock Path Skew:        -0.091ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.899ns = ( 10.900 - 6.001 ) 
    Source Clock Delay      (SCD):    4.740ns
    Clock Pessimism Removal (CPR):    -0.250ns
  Clock Uncertainty:      0.068ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.968ns (routing 0.708ns, distribution 1.260ns)
  Clock Net Delay (Destination): 1.740ns (routing 0.642ns, distribution 1.098ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.524     2.610    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.127     2.483 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.261     2.744    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y104        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.772 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.968     4.740    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/CLK
    SLICE_X93Y321        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X93Y321        FDRE (Prop_BFF2_SLICEM_C_Q)
                                                      0.080     4.820 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[4]/Q
                         net (fo=40, routed)          0.564     5.384    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/io_address_riuclk[4]
    SLICE_X92Y309        LUT2 (Prop_D6LUT_SLICEL_I0_O)
                                                      0.050     5.434 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_nibble_8[0]_INST_0_i_11/O
                         net (fo=4, routed)           0.441     5.875    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_nibble_8[0]_INST_0_i_11_n_0
    SLICE_X90Y302        LUT6 (Prop_C6LUT_SLICEM_I3_O)
                                                      0.088     5.963 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_nibble_8[1]_INST_0_i_15/O
                         net (fo=1, routed)           0.021     5.984    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_nibble_8[1]_INST_0_i_15_n_0
    SLICE_X90Y302        MUXF7 (Prop_F7MUX_CD_SLICEM_I1_O)
                                                      0.068     6.052 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_nibble_8[1]_INST_0_i_9/O
                         net (fo=1, routed)           0.308     6.360    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_nibble_8[1]_INST_0_i_9_n_0
    SLICE_X91Y302        LUT6 (Prop_G6LUT_SLICEL_I4_O)
                                                      0.123     6.483 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_nibble_8[1]_INST_0_i_2/O
                         net (fo=65, routed)          1.794     8.277    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_nibble_8[1]_INST_0_i_2_n_0
    SLICE_X82Y194        LUT6 (Prop_F6LUT_SLICEM_I2_O)
                                                      0.088     8.365 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data[3]_i_4/O
                         net (fo=1, routed)           1.210     9.575    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data[3]_i_4_n_0
    SLICE_X82Y307        LUT6 (Prop_H6LUT_SLICEM_I0_O)
                                                      0.090     9.665 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data[3]_i_2/O
                         net (fo=1, routed)           0.014     9.679    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data[3]_i_2_n_0
    SLICE_X82Y307        MUXF7 (Prop_F7MUX_GH_SLICEM_I0_O)
                                                      0.066     9.745 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data_reg[3]_i_1/O
                         net (fo=1, routed)           0.032     9.777    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data_reg[3]_i_1_n_0
    SLICE_X82Y307        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data_reg[3]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      6.001     6.001 r  
    J19                                               0.000     6.001 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     6.080    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     6.555 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     6.595    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     6.595 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     6.892    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     6.916 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.364     8.280    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.630     8.910 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.226     9.136    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y104        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     9.160 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.740    10.900    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_clk
    SLICE_X82Y307        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data_reg[3]/C
                         clock pessimism             -0.250    10.650    
                         clock uncertainty           -0.068    10.582    
    SLICE_X82Y307        FDRE (Setup_HFF_SLICEM_C_D)
                                                      0.025    10.607    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data_reg[3]
  -------------------------------------------------------------------
                         required time                         10.607    
                         arrival time                          -9.777    
  -------------------------------------------------------------------
                         slack                                  0.830    

Slack (MET) :             0.884ns  (required time - arrival time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[4]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data_reg[8]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             mmcm_clkout6
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.001ns  (mmcm_clkout6 rise@6.001ns - mmcm_clkout6 rise@0.000ns)
  Data Path Delay:        4.905ns  (logic 0.559ns (11.397%)  route 4.346ns (88.603%))
  Logic Levels:           7  (LUT2=1 LUT6=4 MUXF7=2)
  Clock Path Skew:        -0.169ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.884ns = ( 10.885 - 6.001 ) 
    Source Clock Delay      (SCD):    4.740ns
    Clock Pessimism Removal (CPR):    -0.313ns
  Clock Uncertainty:      0.068ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.968ns (routing 0.708ns, distribution 1.260ns)
  Clock Net Delay (Destination): 1.725ns (routing 0.642ns, distribution 1.083ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.524     2.610    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.127     2.483 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.261     2.744    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y104        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.772 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.968     4.740    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/CLK
    SLICE_X93Y321        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X93Y321        FDRE (Prop_BFF2_SLICEM_C_Q)
                                                      0.080     4.820 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[4]/Q
                         net (fo=40, routed)          0.564     5.384    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/io_address_riuclk[4]
    SLICE_X92Y309        LUT2 (Prop_D6LUT_SLICEL_I0_O)
                                                      0.050     5.434 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_nibble_8[0]_INST_0_i_11/O
                         net (fo=4, routed)           0.441     5.875    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_nibble_8[0]_INST_0_i_11_n_0
    SLICE_X90Y302        LUT6 (Prop_C6LUT_SLICEM_I3_O)
                                                      0.088     5.963 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_nibble_8[1]_INST_0_i_15/O
                         net (fo=1, routed)           0.021     5.984    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_nibble_8[1]_INST_0_i_15_n_0
    SLICE_X90Y302        MUXF7 (Prop_F7MUX_CD_SLICEM_I1_O)
                                                      0.068     6.052 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_nibble_8[1]_INST_0_i_9/O
                         net (fo=1, routed)           0.308     6.360    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_nibble_8[1]_INST_0_i_9_n_0
    SLICE_X91Y302        LUT6 (Prop_G6LUT_SLICEL_I4_O)
                                                      0.123     6.483 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_nibble_8[1]_INST_0_i_2/O
                         net (fo=65, routed)          1.775     8.258    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_nibble_8[1]_INST_0_i_2_n_0
    SLICE_X81Y193        LUT6 (Prop_H6LUT_SLICEL_I2_O)
                                                      0.036     8.294 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data[8]_i_4/O
                         net (fo=1, routed)           1.197     9.491    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data[8]_i_4_n_0
    SLICE_X81Y296        LUT6 (Prop_B6LUT_SLICEL_I0_O)
                                                      0.051     9.542 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data[8]_i_2/O
                         net (fo=1, routed)           0.009     9.551    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data[8]_i_2_n_0
    SLICE_X81Y296        MUXF7 (Prop_F7MUX_AB_SLICEL_I0_O)
                                                      0.063     9.614 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data_reg[8]_i_1/O
                         net (fo=1, routed)           0.030     9.644    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data_reg[8]_i_1_n_0
    SLICE_X81Y296        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data_reg[8]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      6.001     6.001 r  
    J19                                               0.000     6.001 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     6.080    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     6.555 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     6.595    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     6.595 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     6.892    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     6.916 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.364     8.280    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.630     8.910 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.226     9.136    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y104        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     9.160 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.725    10.885    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_clk
    SLICE_X81Y296        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data_reg[8]/C
                         clock pessimism             -0.313    10.572    
                         clock uncertainty           -0.068    10.503    
    SLICE_X81Y296        FDRE (Setup_BFF_SLICEL_C_D)
                                                      0.025    10.528    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data_reg[8]
  -------------------------------------------------------------------
                         required time                         10.528    
                         arrival time                          -9.644    
  -------------------------------------------------------------------
                         slack                                  0.884    

Slack (MET) :             0.887ns  (required time - arrival time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[4]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data_reg[12]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             mmcm_clkout6
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.001ns  (mmcm_clkout6 rise@6.001ns - mmcm_clkout6 rise@0.000ns)
  Data Path Delay:        4.903ns  (logic 0.623ns (12.706%)  route 4.280ns (87.294%))
  Logic Levels:           7  (LUT2=1 LUT6=4 MUXF7=2)
  Clock Path Skew:        -0.167ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.886ns = ( 10.887 - 6.001 ) 
    Source Clock Delay      (SCD):    4.740ns
    Clock Pessimism Removal (CPR):    -0.313ns
  Clock Uncertainty:      0.068ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.968ns (routing 0.708ns, distribution 1.260ns)
  Clock Net Delay (Destination): 1.727ns (routing 0.642ns, distribution 1.085ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.524     2.610    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.127     2.483 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.261     2.744    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y104        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.772 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.968     4.740    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/CLK
    SLICE_X93Y321        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X93Y321        FDRE (Prop_BFF2_SLICEM_C_Q)
                                                      0.080     4.820 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[4]/Q
                         net (fo=40, routed)          0.564     5.384    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/io_address_riuclk[4]
    SLICE_X92Y309        LUT2 (Prop_D6LUT_SLICEL_I0_O)
                                                      0.050     5.434 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_nibble_8[0]_INST_0_i_11/O
                         net (fo=4, routed)           0.441     5.875    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_nibble_8[0]_INST_0_i_11_n_0
    SLICE_X90Y302        LUT6 (Prop_C6LUT_SLICEM_I3_O)
                                                      0.088     5.963 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_nibble_8[1]_INST_0_i_15/O
                         net (fo=1, routed)           0.021     5.984    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_nibble_8[1]_INST_0_i_15_n_0
    SLICE_X90Y302        MUXF7 (Prop_F7MUX_CD_SLICEM_I1_O)
                                                      0.068     6.052 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_nibble_8[1]_INST_0_i_9/O
                         net (fo=1, routed)           0.308     6.360    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_nibble_8[1]_INST_0_i_9_n_0
    SLICE_X91Y302        LUT6 (Prop_G6LUT_SLICEL_I4_O)
                                                      0.123     6.483 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_nibble_8[1]_INST_0_i_2/O
                         net (fo=65, routed)          1.740     8.223    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_nibble_8[1]_INST_0_i_2_n_0
    SLICE_X81Y194        LUT6 (Prop_H6LUT_SLICEL_I2_O)
                                                      0.051     8.274 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data[12]_i_4/O
                         net (fo=1, routed)           1.165     9.439    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data[12]_i_4_n_0
    SLICE_X81Y296        LUT6 (Prop_H6LUT_SLICEL_I0_O)
                                                      0.099     9.538 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data[12]_i_2/O
                         net (fo=1, routed)           0.010     9.548    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data[12]_i_2_n_0
    SLICE_X81Y296        MUXF7 (Prop_F7MUX_GH_SLICEL_I0_O)
                                                      0.064     9.612 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data_reg[12]_i_1/O
                         net (fo=1, routed)           0.031     9.643    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data_reg[12]_i_1_n_0
    SLICE_X81Y296        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data_reg[12]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      6.001     6.001 r  
    J19                                               0.000     6.001 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     6.080    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     6.555 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     6.595    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     6.595 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     6.892    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     6.916 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.364     8.280    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.630     8.910 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.226     9.136    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y104        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     9.160 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.727    10.887    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_clk
    SLICE_X81Y296        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data_reg[12]/C
                         clock pessimism             -0.313    10.574    
                         clock uncertainty           -0.068    10.505    
    SLICE_X81Y296        FDRE (Setup_HFF_SLICEL_C_D)
                                                      0.025    10.530    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data_reg[12]
  -------------------------------------------------------------------
                         required time                         10.530    
                         arrival time                          -9.643    
  -------------------------------------------------------------------
                         slack                                  0.887    

Slack (MET) :             0.907ns  (required time - arrival time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_clk_rst_r1_reg/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2riu_nibble_sel_low_reg[0]/R
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             mmcm_clkout6
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.001ns  (mmcm_clkout6 rise@6.001ns - mmcm_clkout6 rise@0.000ns)
  Data Path Delay:        4.744ns  (logic 0.080ns (1.686%)  route 4.664ns (98.314%))
  Logic Levels:           0  
  Clock Path Skew:        -0.207ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.829ns = ( 10.830 - 6.001 ) 
    Source Clock Delay      (SCD):    4.715ns
    Clock Pessimism Removal (CPR):    -0.321ns
  Clock Uncertainty:      0.068ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.943ns (routing 0.708ns, distribution 1.235ns)
  Clock Net Delay (Destination): 1.670ns (routing 0.642ns, distribution 1.028ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.524     2.610    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.127     2.483 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.261     2.744    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y104        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.772 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.943     4.715    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_clk
    SLICE_X91Y339        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_clk_rst_r1_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X91Y339        FDRE (Prop_CFF2_SLICEL_C_Q)
                                                      0.080     4.795 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_clk_rst_r1_reg/Q
                         net (fo=56, routed)          4.664     9.459    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_clk_rst_r1
    SLICE_X82Y202        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2riu_nibble_sel_low_reg[0]/R
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      6.001     6.001 r  
    J19                                               0.000     6.001 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     6.080    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     6.555 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     6.595    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     6.595 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     6.892    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     6.916 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.364     8.280    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.630     8.910 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.226     9.136    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y104        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     9.160 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.670    10.830    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_clk
    SLICE_X82Y202        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2riu_nibble_sel_low_reg[0]/C
                         clock pessimism             -0.321    10.509    
                         clock uncertainty           -0.068    10.441    
    SLICE_X82Y202        FDRE (Setup_GFF_SLICEM_C_R)
                                                     -0.074    10.367    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2riu_nibble_sel_low_reg[0]
  -------------------------------------------------------------------
                         required time                         10.367    
                         arrival time                          -9.459    
  -------------------------------------------------------------------
                         slack                                  0.907    

Slack (MET) :             0.907ns  (required time - arrival time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_clk_rst_r1_reg/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2riu_nibble_sel_low_reg[1]/R
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             mmcm_clkout6
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.001ns  (mmcm_clkout6 rise@6.001ns - mmcm_clkout6 rise@0.000ns)
  Data Path Delay:        4.744ns  (logic 0.080ns (1.686%)  route 4.664ns (98.314%))
  Logic Levels:           0  
  Clock Path Skew:        -0.207ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.829ns = ( 10.830 - 6.001 ) 
    Source Clock Delay      (SCD):    4.715ns
    Clock Pessimism Removal (CPR):    -0.321ns
  Clock Uncertainty:      0.068ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.943ns (routing 0.708ns, distribution 1.235ns)
  Clock Net Delay (Destination): 1.670ns (routing 0.642ns, distribution 1.028ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.524     2.610    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.127     2.483 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.261     2.744    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y104        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.772 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.943     4.715    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_clk
    SLICE_X91Y339        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_clk_rst_r1_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X91Y339        FDRE (Prop_CFF2_SLICEL_C_Q)
                                                      0.080     4.795 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_clk_rst_r1_reg/Q
                         net (fo=56, routed)          4.664     9.459    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_clk_rst_r1
    SLICE_X82Y202        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2riu_nibble_sel_low_reg[1]/R
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      6.001     6.001 r  
    J19                                               0.000     6.001 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     6.080    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     6.555 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     6.595    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     6.595 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     6.892    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     6.916 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.364     8.280    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.630     8.910 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.226     9.136    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y104        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     9.160 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.670    10.830    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_clk
    SLICE_X82Y202        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2riu_nibble_sel_low_reg[1]/C
                         clock pessimism             -0.321    10.509    
                         clock uncertainty           -0.068    10.441    
    SLICE_X82Y202        FDRE (Setup_HFF_SLICEM_C_R)
                                                     -0.074    10.367    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2riu_nibble_sel_low_reg[1]
  -------------------------------------------------------------------
                         required time                         10.367    
                         arrival time                          -9.459    
  -------------------------------------------------------------------
                         slack                                  0.907    

Slack (MET) :             0.913ns  (required time - arrival time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[4]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data_reg[6]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             mmcm_clkout6
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.001ns  (mmcm_clkout6 rise@6.001ns - mmcm_clkout6 rise@0.000ns)
  Data Path Delay:        4.953ns  (logic 0.717ns (14.475%)  route 4.236ns (85.525%))
  Logic Levels:           7  (LUT2=1 LUT6=4 MUXF7=2)
  Clock Path Skew:        -0.092ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.898ns = ( 10.899 - 6.001 ) 
    Source Clock Delay      (SCD):    4.740ns
    Clock Pessimism Removal (CPR):    -0.250ns
  Clock Uncertainty:      0.068ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.968ns (routing 0.708ns, distribution 1.260ns)
  Clock Net Delay (Destination): 1.739ns (routing 0.642ns, distribution 1.097ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.524     2.610    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.127     2.483 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.261     2.744    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y104        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.772 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.968     4.740    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/CLK
    SLICE_X93Y321        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X93Y321        FDRE (Prop_BFF2_SLICEM_C_Q)
                                                      0.080     4.820 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[4]/Q
                         net (fo=40, routed)          0.564     5.384    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/io_address_riuclk[4]
    SLICE_X92Y309        LUT2 (Prop_D6LUT_SLICEL_I0_O)
                                                      0.050     5.434 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_nibble_8[0]_INST_0_i_11/O
                         net (fo=4, routed)           0.441     5.875    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_nibble_8[0]_INST_0_i_11_n_0
    SLICE_X90Y302        LUT6 (Prop_C6LUT_SLICEM_I3_O)
                                                      0.088     5.963 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_nibble_8[1]_INST_0_i_15/O
                         net (fo=1, routed)           0.021     5.984    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_nibble_8[1]_INST_0_i_15_n_0
    SLICE_X90Y302        MUXF7 (Prop_F7MUX_CD_SLICEM_I1_O)
                                                      0.068     6.052 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_nibble_8[1]_INST_0_i_9/O
                         net (fo=1, routed)           0.308     6.360    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_nibble_8[1]_INST_0_i_9_n_0
    SLICE_X91Y302        LUT6 (Prop_G6LUT_SLICEL_I4_O)
                                                      0.123     6.483 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_nibble_8[1]_INST_0_i_2/O
                         net (fo=65, routed)          1.855     8.338    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_nibble_8[1]_INST_0_i_2_n_0
    SLICE_X82Y193        LUT6 (Prop_D6LUT_SLICEM_I2_O)
                                                      0.099     8.437 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data[6]_i_4/O
                         net (fo=1, routed)           1.007     9.444    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data[6]_i_4_n_0
    SLICE_X81Y307        LUT6 (Prop_D6LUT_SLICEL_I0_O)
                                                      0.146     9.590 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data[6]_i_2/O
                         net (fo=1, routed)           0.009     9.599    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data[6]_i_2_n_0
    SLICE_X81Y307        MUXF7 (Prop_F7MUX_CD_SLICEL_I0_O)
                                                      0.063     9.662 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data_reg[6]_i_1/O
                         net (fo=1, routed)           0.031     9.693    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data_reg[6]_i_1_n_0
    SLICE_X81Y307        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data_reg[6]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      6.001     6.001 r  
    J19                                               0.000     6.001 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     6.080    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     6.555 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     6.595    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     6.595 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     6.892    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     6.916 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.364     8.280    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.630     8.910 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.226     9.136    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y104        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     9.160 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.739    10.899    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_clk
    SLICE_X81Y307        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data_reg[6]/C
                         clock pessimism             -0.250    10.649    
                         clock uncertainty           -0.068    10.581    
    SLICE_X81Y307        FDRE (Setup_DFF_SLICEL_C_D)
                                                      0.025    10.606    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data_reg[6]
  -------------------------------------------------------------------
                         required time                         10.606    
                         arrival time                          -9.693    
  -------------------------------------------------------------------
                         slack                                  0.913    

Slack (MET) :             0.954ns  (required time - arrival time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[4]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data_reg[5]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             mmcm_clkout6
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.001ns  (mmcm_clkout6 rise@6.001ns - mmcm_clkout6 rise@0.000ns)
  Data Path Delay:        4.913ns  (logic 0.631ns (12.844%)  route 4.282ns (87.156%))
  Logic Levels:           7  (LUT2=1 LUT6=4 MUXF7=2)
  Clock Path Skew:        -0.091ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.899ns = ( 10.900 - 6.001 ) 
    Source Clock Delay      (SCD):    4.740ns
    Clock Pessimism Removal (CPR):    -0.250ns
  Clock Uncertainty:      0.068ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.968ns (routing 0.708ns, distribution 1.260ns)
  Clock Net Delay (Destination): 1.740ns (routing 0.642ns, distribution 1.098ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.524     2.610    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.127     2.483 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.261     2.744    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y104        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.772 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.968     4.740    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/CLK
    SLICE_X93Y321        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X93Y321        FDRE (Prop_BFF2_SLICEM_C_Q)
                                                      0.080     4.820 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[4]/Q
                         net (fo=40, routed)          0.564     5.384    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/io_address_riuclk[4]
    SLICE_X92Y309        LUT2 (Prop_D6LUT_SLICEL_I0_O)
                                                      0.050     5.434 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_nibble_8[0]_INST_0_i_11/O
                         net (fo=4, routed)           0.441     5.875    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_nibble_8[0]_INST_0_i_11_n_0
    SLICE_X90Y302        LUT6 (Prop_C6LUT_SLICEM_I3_O)
                                                      0.088     5.963 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_nibble_8[1]_INST_0_i_15/O
                         net (fo=1, routed)           0.021     5.984    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_nibble_8[1]_INST_0_i_15_n_0
    SLICE_X90Y302        MUXF7 (Prop_F7MUX_CD_SLICEM_I1_O)
                                                      0.068     6.052 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_nibble_8[1]_INST_0_i_9/O
                         net (fo=1, routed)           0.308     6.360    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_nibble_8[1]_INST_0_i_9_n_0
    SLICE_X91Y302        LUT6 (Prop_G6LUT_SLICEL_I4_O)
                                                      0.123     6.483 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_nibble_8[1]_INST_0_i_2/O
                         net (fo=65, routed)          1.789     8.273    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_nibble_8[1]_INST_0_i_2_n_0
    SLICE_X82Y194        LUT6 (Prop_C6LUT_SLICEM_I2_O)
                                                      0.123     8.396 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data[5]_i_4/O
                         net (fo=1, routed)           1.119     9.515    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data[5]_i_4_n_0
    SLICE_X81Y303        LUT6 (Prop_B6LUT_SLICEL_I0_O)
                                                      0.036     9.551 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data[5]_i_2/O
                         net (fo=1, routed)           0.009     9.560    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data[5]_i_2_n_0
    SLICE_X81Y303        MUXF7 (Prop_F7MUX_AB_SLICEL_I0_O)
                                                      0.063     9.623 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data_reg[5]_i_1/O
                         net (fo=1, routed)           0.030     9.653    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data_reg[5]_i_1_n_0
    SLICE_X81Y303        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data_reg[5]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      6.001     6.001 r  
    J19                                               0.000     6.001 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     6.080    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     6.555 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     6.595    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     6.595 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     6.892    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     6.916 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.364     8.280    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.630     8.910 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.226     9.136    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y104        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     9.160 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.740    10.900    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_clk
    SLICE_X81Y303        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data_reg[5]/C
                         clock pessimism             -0.250    10.650    
                         clock uncertainty           -0.068    10.582    
    SLICE_X81Y303        FDRE (Setup_BFF_SLICEL_C_D)
                                                      0.025    10.607    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data_reg[5]
  -------------------------------------------------------------------
                         required time                         10.607    
                         arrival time                          -9.653    
  -------------------------------------------------------------------
                         slack                                  0.954    

Slack (MET) :             0.997ns  (required time - arrival time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[4]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data_reg[2]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             mmcm_clkout6
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.001ns  (mmcm_clkout6 rise@6.001ns - mmcm_clkout6 rise@0.000ns)
  Data Path Delay:        4.793ns  (logic 0.628ns (13.102%)  route 4.165ns (86.898%))
  Logic Levels:           7  (LUT2=1 LUT6=4 MUXF7=2)
  Clock Path Skew:        -0.167ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.886ns = ( 10.887 - 6.001 ) 
    Source Clock Delay      (SCD):    4.740ns
    Clock Pessimism Removal (CPR):    -0.313ns
  Clock Uncertainty:      0.068ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.968ns (routing 0.708ns, distribution 1.260ns)
  Clock Net Delay (Destination): 1.727ns (routing 0.642ns, distribution 1.085ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.524     2.610    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.127     2.483 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.261     2.744    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y104        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.772 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.968     4.740    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/CLK
    SLICE_X93Y321        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X93Y321        FDRE (Prop_BFF2_SLICEM_C_Q)
                                                      0.080     4.820 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[4]/Q
                         net (fo=40, routed)          0.564     5.384    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/io_address_riuclk[4]
    SLICE_X92Y309        LUT2 (Prop_D6LUT_SLICEL_I0_O)
                                                      0.050     5.434 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_nibble_8[0]_INST_0_i_11/O
                         net (fo=4, routed)           0.441     5.875    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_nibble_8[0]_INST_0_i_11_n_0
    SLICE_X90Y302        LUT6 (Prop_C6LUT_SLICEM_I3_O)
                                                      0.088     5.963 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_nibble_8[1]_INST_0_i_15/O
                         net (fo=1, routed)           0.021     5.984    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_nibble_8[1]_INST_0_i_15_n_0
    SLICE_X90Y302        MUXF7 (Prop_F7MUX_CD_SLICEM_I1_O)
                                                      0.068     6.052 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_nibble_8[1]_INST_0_i_9/O
                         net (fo=1, routed)           0.308     6.360    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_nibble_8[1]_INST_0_i_9_n_0
    SLICE_X91Y302        LUT6 (Prop_G6LUT_SLICEL_I4_O)
                                                      0.123     6.483 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_nibble_8[1]_INST_0_i_2/O
                         net (fo=65, routed)          1.886     8.369    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_nibble_8[1]_INST_0_i_2_n_0
    SLICE_X82Y193        LUT6 (Prop_E6LUT_SLICEM_I2_O)
                                                      0.052     8.421 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data[2]_i_4/O
                         net (fo=1, routed)           0.897     9.318    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data[2]_i_4_n_0
    SLICE_X82Y296        LUT6 (Prop_B6LUT_SLICEM_I0_O)
                                                      0.100     9.418 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data[2]_i_2/O
                         net (fo=1, routed)           0.017     9.435    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data[2]_i_2_n_0
    SLICE_X82Y296        MUXF7 (Prop_F7MUX_AB_SLICEM_I0_O)
                                                      0.067     9.502 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data_reg[2]_i_1/O
                         net (fo=1, routed)           0.031     9.533    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data_reg[2]_i_1_n_0
    SLICE_X82Y296        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data_reg[2]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      6.001     6.001 r  
    J19                                               0.000     6.001 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     6.080    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     6.555 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     6.595    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     6.595 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     6.892    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     6.916 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.364     8.280    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.630     8.910 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.226     9.136    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y104        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     9.160 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.727    10.887    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_clk
    SLICE_X82Y296        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data_reg[2]/C
                         clock pessimism             -0.313    10.574    
                         clock uncertainty           -0.068    10.505    
    SLICE_X82Y296        FDRE (Setup_BFF_SLICEM_C_D)
                                                      0.025    10.530    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data_reg[2]
  -------------------------------------------------------------------
                         required time                         10.530    
                         arrival time                          -9.533    
  -------------------------------------------------------------------
                         slack                                  0.997    

Slack (MET) :             0.997ns  (required time - arrival time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[4]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             mmcm_clkout6
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.001ns  (mmcm_clkout6 rise@6.001ns - mmcm_clkout6 rise@0.000ns)
  Data Path Delay:        4.791ns  (logic 0.610ns (12.732%)  route 4.181ns (87.268%))
  Logic Levels:           7  (LUT2=1 LUT6=4 MUXF7=2)
  Clock Path Skew:        -0.169ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.884ns = ( 10.885 - 6.001 ) 
    Source Clock Delay      (SCD):    4.740ns
    Clock Pessimism Removal (CPR):    -0.313ns
  Clock Uncertainty:      0.068ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.968ns (routing 0.708ns, distribution 1.260ns)
  Clock Net Delay (Destination): 1.725ns (routing 0.642ns, distribution 1.083ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.524     2.610    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.127     2.483 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.261     2.744    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y104        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.772 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.968     4.740    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/CLK
    SLICE_X93Y321        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X93Y321        FDRE (Prop_BFF2_SLICEM_C_Q)
                                                      0.080     4.820 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[4]/Q
                         net (fo=40, routed)          0.564     5.384    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/io_address_riuclk[4]
    SLICE_X92Y309        LUT2 (Prop_D6LUT_SLICEL_I0_O)
                                                      0.050     5.434 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_nibble_8[0]_INST_0_i_11/O
                         net (fo=4, routed)           0.441     5.875    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_nibble_8[0]_INST_0_i_11_n_0
    SLICE_X90Y302        LUT6 (Prop_C6LUT_SLICEM_I3_O)
                                                      0.088     5.963 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_nibble_8[1]_INST_0_i_15/O
                         net (fo=1, routed)           0.021     5.984    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_nibble_8[1]_INST_0_i_15_n_0
    SLICE_X90Y302        MUXF7 (Prop_F7MUX_CD_SLICEM_I1_O)
                                                      0.068     6.052 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_nibble_8[1]_INST_0_i_9/O
                         net (fo=1, routed)           0.308     6.360    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_nibble_8[1]_INST_0_i_9_n_0
    SLICE_X91Y302        LUT6 (Prop_G6LUT_SLICEL_I4_O)
                                                      0.123     6.483 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_nibble_8[1]_INST_0_i_2/O
                         net (fo=65, routed)          1.797     8.280    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_nibble_8[1]_INST_0_i_2_n_0
    SLICE_X82Y194        LUT6 (Prop_H6LUT_SLICEM_I2_O)
                                                      0.039     8.319 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data[0]_i_4/O
                         net (fo=1, routed)           1.010     9.329    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data[0]_i_4_n_0
    SLICE_X81Y295        LUT6 (Prop_D6LUT_SLICEL_I0_O)
                                                      0.099     9.428 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data[0]_i_2/O
                         net (fo=1, routed)           0.009     9.437    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data[0]_i_2_n_0
    SLICE_X81Y295        MUXF7 (Prop_F7MUX_CD_SLICEL_I0_O)
                                                      0.063     9.500 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data_reg[0]_i_1/O
                         net (fo=1, routed)           0.031     9.531    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data_reg[0]_i_1_n_0
    SLICE_X81Y295        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      6.001     6.001 r  
    J19                                               0.000     6.001 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     6.080    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     6.555 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     6.595    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     6.595 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     6.892    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     6.916 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.364     8.280    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.630     8.910 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.226     9.136    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y104        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     9.160 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.725    10.885    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_clk
    SLICE_X81Y295        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data_reg[0]/C
                         clock pessimism             -0.313    10.572    
                         clock uncertainty           -0.068    10.503    
    SLICE_X81Y295        FDRE (Setup_DFF_SLICEL_C_D)
                                                      0.025    10.528    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data_reg[0]
  -------------------------------------------------------------------
                         required time                         10.528    
                         arrival time                          -9.531    
  -------------------------------------------------------------------
                         slack                                  0.997    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.027ns  (arrival time - required time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_read_data_ub_reg[19]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/iomodule_0/U0/Using_IO_Bus.io_bus_read_data_reg[19]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             mmcm_clkout6
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (mmcm_clkout6 rise@0.000ns - mmcm_clkout6 rise@0.000ns)
  Data Path Delay:        0.143ns  (logic 0.059ns (41.259%)  route 0.084ns (58.741%))
  Logic Levels:           0  
  Clock Path Skew:        0.056ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    4.748ns
    Source Clock Delay      (SCD):    4.893ns
    Clock Pessimism Removal (CPR):    -0.201ns
  Clock Net Delay (Source):      1.734ns (routing 0.642ns, distribution 1.092ns)
  Clock Net Delay (Destination): 1.976ns (routing 0.708ns, distribution 1.268ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.364     2.279    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.630     2.909 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.226     3.135    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y104        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.159 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.734     4.893    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/CLK
    SLICE_X92Y319        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_read_data_ub_reg[19]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X92Y319        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.059     4.952 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_read_data_ub_reg[19]/Q
                         net (fo=1, routed)           0.084     5.036    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/iomodule_0/U0/IO_Read_Data[19]
    SLICE_X92Y321        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/iomodule_0/U0/Using_IO_Bus.io_bus_read_data_reg[19]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.524     2.610    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.127     2.483 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.261     2.744    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y104        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.772 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.976     4.748    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/iomodule_0/U0/Clk
    SLICE_X92Y321        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/iomodule_0/U0/Using_IO_Bus.io_bus_read_data_reg[19]/C
                         clock pessimism              0.201     4.949    
    SLICE_X92Y321        FDRE (Hold_EFF_SLICEL_C_D)
                                                      0.060     5.009    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/iomodule_0/U0/Using_IO_Bus.io_bus_read_data_reg[19]
  -------------------------------------------------------------------
                         required time                         -5.009    
                         arrival time                           5.036    
  -------------------------------------------------------------------
                         slack                                  0.027    

Slack (MET) :             0.036ns  (arrival time - required time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_read_data_ub_reg[4]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/iomodule_0/U0/Using_IO_Bus.io_bus_read_data_reg[4]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             mmcm_clkout6
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (mmcm_clkout6 rise@0.000ns - mmcm_clkout6 rise@0.000ns)
  Data Path Delay:        0.103ns  (logic 0.039ns (37.864%)  route 0.064ns (62.136%))
  Logic Levels:           0  
  Clock Path Skew:        0.021ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.845ns
    Source Clock Delay      (SCD):    2.933ns
    Clock Pessimism Removal (CPR):    -0.109ns
  Clock Net Delay (Source):      1.075ns (routing 0.391ns, distribution 0.684ns)
  Clock Net Delay (Destination): 1.218ns (routing 0.438ns, distribution 0.780ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.839     1.456    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.230     1.686 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.155     1.841    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y104        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.858 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.075     2.933    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/CLK
    SLICE_X91Y315        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_read_data_ub_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X91Y315        FDRE (Prop_CFF_SLICEL_C_Q)
                                                      0.039     2.972 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_read_data_ub_reg[4]/Q
                         net (fo=1, routed)           0.064     3.036    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/iomodule_0/U0/IO_Read_Data[4]
    SLICE_X91Y316        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/iomodule_0/U0/Using_IO_Bus.io_bus_read_data_reg[4]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.940     1.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.295     1.432 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.176     1.608    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y104        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.627 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.218     2.845    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/iomodule_0/U0/Clk
    SLICE_X91Y316        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/iomodule_0/U0/Using_IO_Bus.io_bus_read_data_reg[4]/C
                         clock pessimism              0.109     2.954    
    SLICE_X91Y316        FDRE (Hold_DFF_SLICEL_C_D)
                                                      0.046     3.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/iomodule_0/U0/Using_IO_Bus.io_bus_read_data_reg[4]
  -------------------------------------------------------------------
                         required time                         -3.000    
                         arrival time                           3.036    
  -------------------------------------------------------------------
                         slack                                  0.036    

Slack (MET) :             0.036ns  (arrival time - required time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/iomodule_0/U0/Using_IO_Bus.IO_Write_Data_reg[28]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_write_data_riuclk_reg[28]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             mmcm_clkout6
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (mmcm_clkout6 rise@0.000ns - mmcm_clkout6 rise@0.000ns)
  Data Path Delay:        0.105ns  (logic 0.038ns (36.190%)  route 0.067ns (63.810%))
  Logic Levels:           0  
  Clock Path Skew:        0.022ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.848ns
    Source Clock Delay      (SCD):    2.934ns
    Clock Pessimism Removal (CPR):    -0.108ns
  Clock Net Delay (Source):      1.076ns (routing 0.391ns, distribution 0.685ns)
  Clock Net Delay (Destination): 1.221ns (routing 0.438ns, distribution 0.783ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.839     1.456    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.230     1.686 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.155     1.841    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y104        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.858 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.076     2.934    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/iomodule_0/U0/Clk
    SLICE_X94Y322        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/iomodule_0/U0/Using_IO_Bus.IO_Write_Data_reg[28]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X94Y322        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.038     2.972 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/iomodule_0/U0/Using_IO_Bus.IO_Write_Data_reg[28]/Q
                         net (fo=1, routed)           0.067     3.039    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_write_data_ub[28]
    SLICE_X94Y321        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_write_data_riuclk_reg[28]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.940     1.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.295     1.432 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.176     1.608    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y104        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.627 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.221     2.848    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/CLK
    SLICE_X94Y321        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_write_data_riuclk_reg[28]/C
                         clock pessimism              0.108     2.956    
    SLICE_X94Y321        FDRE (Hold_GFF2_SLICEM_C_D)
                                                      0.047     3.003    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_write_data_riuclk_reg[28]
  -------------------------------------------------------------------
                         required time                         -3.003    
                         arrival time                           3.039    
  -------------------------------------------------------------------
                         slack                                  0.036    

Slack (MET) :             0.037ns  (arrival time - required time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_read_data_ub_reg[12]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/iomodule_0/U0/Using_IO_Bus.io_bus_read_data_reg[12]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             mmcm_clkout6
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (mmcm_clkout6 rise@0.000ns - mmcm_clkout6 rise@0.000ns)
  Data Path Delay:        0.101ns  (logic 0.039ns (38.614%)  route 0.062ns (61.386%))
  Logic Levels:           0  
  Clock Path Skew:        0.017ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.842ns
    Source Clock Delay      (SCD):    2.935ns
    Clock Pessimism Removal (CPR):    -0.109ns
  Clock Net Delay (Source):      1.077ns (routing 0.391ns, distribution 0.686ns)
  Clock Net Delay (Destination): 1.215ns (routing 0.438ns, distribution 0.777ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.839     1.456    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.230     1.686 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.155     1.841    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y104        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.858 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.077     2.935    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/CLK
    SLICE_X91Y320        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_read_data_ub_reg[12]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X91Y320        FDRE (Prop_CFF_SLICEL_C_Q)
                                                      0.039     2.974 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_read_data_ub_reg[12]/Q
                         net (fo=1, routed)           0.062     3.036    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/iomodule_0/U0/IO_Read_Data[12]
    SLICE_X91Y322        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/iomodule_0/U0/Using_IO_Bus.io_bus_read_data_reg[12]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.940     1.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.295     1.432 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.176     1.608    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y104        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.627 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.215     2.842    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/iomodule_0/U0/Clk
    SLICE_X91Y322        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/iomodule_0/U0/Using_IO_Bus.io_bus_read_data_reg[12]/C
                         clock pessimism              0.109     2.951    
    SLICE_X91Y322        FDRE (Hold_AFF2_SLICEL_C_D)
                                                      0.047     2.998    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/iomodule_0/U0/Using_IO_Bus.io_bus_read_data_reg[12]
  -------------------------------------------------------------------
                         required time                         -2.998    
                         arrival time                           3.036    
  -------------------------------------------------------------------
                         slack                                  0.037    

Slack (MET) :             0.038ns  (arrival time - required time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_write_data_riuclk_reg[7]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2riu_wr_data_reg[7]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             mmcm_clkout6
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (mmcm_clkout6 rise@0.000ns - mmcm_clkout6 rise@0.000ns)
  Data Path Delay:        0.134ns  (logic 0.060ns (44.642%)  route 0.074ns (55.358%))
  Logic Levels:           0  
  Clock Path Skew:        0.035ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    4.725ns
    Source Clock Delay      (SCD):    4.889ns
    Clock Pessimism Removal (CPR):    -0.199ns
  Clock Net Delay (Source):      1.730ns (routing 0.642ns, distribution 1.088ns)
  Clock Net Delay (Destination): 1.953ns (routing 0.708ns, distribution 1.245ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.364     2.279    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.630     2.909 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.226     3.135    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y104        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.159 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.730     4.889    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/CLK
    SLICE_X81Y322        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_write_data_riuclk_reg[7]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y322        FDRE (Prop_EFF2_SLICEL_C_Q)
                                                      0.060     4.949 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_write_data_riuclk_reg[7]/Q
                         net (fo=2, routed)           0.074     5.023    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/io_write_data_riuclk[7]
    SLICE_X81Y320        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2riu_wr_data_reg[7]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.524     2.610    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.127     2.483 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.261     2.744    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y104        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.772 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.953     4.725    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_clk
    SLICE_X81Y320        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2riu_wr_data_reg[7]/C
                         clock pessimism              0.199     4.924    
    SLICE_X81Y320        FDRE (Hold_AFF2_SLICEL_C_D)
                                                      0.062     4.986    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2riu_wr_data_reg[7]
  -------------------------------------------------------------------
                         required time                         -4.986    
                         arrival time                           5.023    
  -------------------------------------------------------------------
                         slack                                  0.038    

Slack (MET) :             0.038ns  (arrival time - required time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_read_data_ub_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/iomodule_0/U0/Using_IO_Bus.io_bus_read_data_reg[2]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             mmcm_clkout6
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (mmcm_clkout6 rise@0.000ns - mmcm_clkout6 rise@0.000ns)
  Data Path Delay:        0.105ns  (logic 0.039ns (37.143%)  route 0.066ns (62.857%))
  Logic Levels:           0  
  Clock Path Skew:        0.021ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.845ns
    Source Clock Delay      (SCD):    2.933ns
    Clock Pessimism Removal (CPR):    -0.109ns
  Clock Net Delay (Source):      1.075ns (routing 0.391ns, distribution 0.684ns)
  Clock Net Delay (Destination): 1.218ns (routing 0.438ns, distribution 0.780ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.839     1.456    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.230     1.686 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.155     1.841    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y104        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.858 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.075     2.933    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/CLK
    SLICE_X91Y315        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_read_data_ub_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X91Y315        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.039     2.972 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_read_data_ub_reg[2]/Q
                         net (fo=1, routed)           0.066     3.038    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/iomodule_0/U0/IO_Read_Data[2]
    SLICE_X91Y316        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/iomodule_0/U0/Using_IO_Bus.io_bus_read_data_reg[2]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.940     1.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.295     1.432 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.176     1.608    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y104        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.627 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.218     2.845    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/iomodule_0/U0/Clk
    SLICE_X91Y316        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/iomodule_0/U0/Using_IO_Bus.io_bus_read_data_reg[2]/C
                         clock pessimism              0.109     2.954    
    SLICE_X91Y316        FDRE (Hold_CFF_SLICEL_C_D)
                                                      0.046     3.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/iomodule_0/U0/Using_IO_Bus.io_bus_read_data_reg[2]
  -------------------------------------------------------------------
                         required time                         -3.000    
                         arrival time                           3.038    
  -------------------------------------------------------------------
                         slack                                  0.038    

Slack (MET) :             0.039ns  (arrival time - required time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/iomodule_0/U0/Using_IO_Bus.IO_Write_Data_reg[17]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_write_data_riuclk_reg[17]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             mmcm_clkout6
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (mmcm_clkout6 rise@0.000ns - mmcm_clkout6 rise@0.000ns)
  Data Path Delay:        0.096ns  (logic 0.039ns (40.625%)  route 0.057ns (59.375%))
  Logic Levels:           0  
  Clock Path Skew:        0.010ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.840ns
    Source Clock Delay      (SCD):    2.934ns
    Clock Pessimism Removal (CPR):    -0.103ns
  Clock Net Delay (Source):      1.076ns (routing 0.391ns, distribution 0.685ns)
  Clock Net Delay (Destination): 1.213ns (routing 0.438ns, distribution 0.775ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.839     1.456    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.230     1.686 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.155     1.841    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y104        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.858 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.076     2.934    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/iomodule_0/U0/Clk
    SLICE_X90Y339        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/iomodule_0/U0/Using_IO_Bus.IO_Write_Data_reg[17]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X90Y339        FDRE (Prop_EFF2_SLICEM_C_Q)
                                                      0.039     2.973 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/iomodule_0/U0/Using_IO_Bus.IO_Write_Data_reg[17]/Q
                         net (fo=1, routed)           0.057     3.030    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_write_data_ub[17]
    SLICE_X91Y339        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_write_data_riuclk_reg[17]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.940     1.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.295     1.432 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.176     1.608    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y104        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.627 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.213     2.840    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/CLK
    SLICE_X91Y339        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_write_data_riuclk_reg[17]/C
                         clock pessimism              0.103     2.943    
    SLICE_X91Y339        FDRE (Hold_AFF2_SLICEL_C_D)
                                                      0.047     2.990    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_write_data_riuclk_reg[17]
  -------------------------------------------------------------------
                         required time                         -2.990    
                         arrival time                           3.030    
  -------------------------------------------------------------------
                         slack                                  0.039    

Slack (MET) :             0.041ns  (arrival time - required time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_riu_rst_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_riu_rst_reg[2]/D
                            (rising edge-triggered cell FDSE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             mmcm_clkout6
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (mmcm_clkout6 rise@0.000ns - mmcm_clkout6 rise@0.000ns)
  Data Path Delay:        0.114ns  (logic 0.059ns (51.725%)  route 0.055ns (48.275%))
  Logic Levels:           1  (LUT5=1)
  Clock Path Skew:        0.026ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.856ns
    Source Clock Delay      (SCD):    2.939ns
    Clock Pessimism Removal (CPR):    -0.109ns
  Clock Net Delay (Source):      1.081ns (routing 0.391ns, distribution 0.690ns)
  Clock Net Delay (Destination): 1.229ns (routing 0.438ns, distribution 0.791ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.839     1.456    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.230     1.686 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.155     1.841    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y104        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.858 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.081     2.939    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/c0_riu_clk
    SLICE_X92Y357        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_riu_rst_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X92Y357        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.039     2.978 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_riu_rst_reg[1]/Q
                         net (fo=6, routed)           0.049     3.027    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_riu_rst_reg_n_0_[1]
    SLICE_X92Y356        LUT5 (Prop_H5LUT_SLICEL_I2_O)
                                                      0.020     3.047 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_riu_rst[2]_i_1/O
                         net (fo=1, routed)           0.006     3.053    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_riu_rst[2]_i_1_n_0
    SLICE_X92Y356        FDSE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_riu_rst_reg[2]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.940     1.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.295     1.432 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.176     1.608    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y104        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.627 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.229     2.856    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/c0_riu_clk
    SLICE_X92Y356        FDSE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_riu_rst_reg[2]/C
                         clock pessimism              0.109     2.965    
    SLICE_X92Y356        FDSE (Hold_HFF2_SLICEL_C_D)
                                                      0.047     3.012    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_riu_rst_reg[2]
  -------------------------------------------------------------------
                         required time                         -3.012    
                         arrival time                           3.053    
  -------------------------------------------------------------------
                         slack                                  0.041    

Slack (MET) :             0.044ns  (arrival time - required time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/rst_0/U0/SEQ/SEQ_COUNTER/q_int_reg[5]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/rst_0/U0/SEQ/SEQ_COUNTER/q_int_reg[5]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             mmcm_clkout6
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (mmcm_clkout6 rise@0.000ns - mmcm_clkout6 rise@0.000ns)
  Data Path Delay:        0.096ns  (logic 0.054ns (56.436%)  route 0.042ns (43.564%))
  Logic Levels:           1  (LUT6=1)
  Clock Path Skew:        0.006ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.845ns
    Source Clock Delay      (SCD):    2.936ns
    Clock Pessimism Removal (CPR):    -0.097ns
  Clock Net Delay (Source):      1.078ns (routing 0.391ns, distribution 0.687ns)
  Clock Net Delay (Destination): 1.218ns (routing 0.438ns, distribution 0.780ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.839     1.456    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.230     1.686 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.155     1.841    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y104        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.858 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.078     2.936    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/rst_0/U0/SEQ/SEQ_COUNTER/slowest_sync_clk
    SLICE_X95Y343        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/rst_0/U0/SEQ/SEQ_COUNTER/q_int_reg[5]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X95Y343        FDRE (Prop_BFF_SLICEL_C_Q)
                                                      0.039     2.975 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/rst_0/U0/SEQ/SEQ_COUNTER/q_int_reg[5]/Q
                         net (fo=4, routed)           0.027     3.001    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/rst_0/U0/SEQ/SEQ_COUNTER/Q[5]
    SLICE_X95Y343        LUT6 (Prop_B6LUT_SLICEL_I5_O)
                                                      0.015     3.016 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/rst_0/U0/SEQ/SEQ_COUNTER/q_int[5]_i_2/O
                         net (fo=1, routed)           0.015     3.031    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/rst_0/U0/SEQ/SEQ_COUNTER/q_int0[5]
    SLICE_X95Y343        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/rst_0/U0/SEQ/SEQ_COUNTER/q_int_reg[5]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.940     1.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.295     1.432 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.176     1.608    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y104        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.627 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.218     2.845    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/rst_0/U0/SEQ/SEQ_COUNTER/slowest_sync_clk
    SLICE_X95Y343        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/rst_0/U0/SEQ/SEQ_COUNTER/q_int_reg[5]/C
                         clock pessimism              0.097     2.942    
    SLICE_X95Y343        FDRE (Hold_BFF_SLICEL_C_D)
                                                      0.046     2.988    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/rst_0/U0/SEQ/SEQ_COUNTER/q_int_reg[5]
  -------------------------------------------------------------------
                         required time                         -2.988    
                         arrival time                           3.031    
  -------------------------------------------------------------------
                         slack                                  0.044    

Slack (MET) :             0.044ns  (arrival time - required time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_write_data_riuclk_reg[6]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2riu_wr_data_reg[6]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             mmcm_clkout6
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (mmcm_clkout6 rise@0.000ns - mmcm_clkout6 rise@0.000ns)
  Data Path Delay:        0.108ns  (logic 0.038ns (35.185%)  route 0.070ns (64.815%))
  Logic Levels:           0  
  Clock Path Skew:        0.017ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.840ns
    Source Clock Delay      (SCD):    2.931ns
    Clock Pessimism Removal (CPR):    -0.108ns
  Clock Net Delay (Source):      1.073ns (routing 0.391ns, distribution 0.682ns)
  Clock Net Delay (Destination): 1.213ns (routing 0.438ns, distribution 0.775ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.839     1.456    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.230     1.686 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.155     1.841    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y104        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.858 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.073     2.931    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/CLK
    SLICE_X82Y325        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_write_data_riuclk_reg[6]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X82Y325        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.038     2.969 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_write_data_riuclk_reg[6]/Q
                         net (fo=2, routed)           0.070     3.039    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/io_write_data_riuclk[6]
    SLICE_X82Y326        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2riu_wr_data_reg[6]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.940     1.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.295     1.432 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.176     1.608    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y104        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.627 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.213     2.840    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_clk
    SLICE_X82Y326        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2riu_wr_data_reg[6]/C
                         clock pessimism              0.108     2.948    
    SLICE_X82Y326        FDRE (Hold_FFF2_SLICEM_C_D)
                                                      0.047     2.995    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2riu_wr_data_reg[6]
  -------------------------------------------------------------------
                         required time                         -2.995    
                         arrival time                           3.039    
  -------------------------------------------------------------------
                         slack                                  0.044    





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         mmcm_clkout6
Waveform(ns):       { 0.000 3.001 }
Period(ns):         6.001
Sources:            { d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6 }

Check Type        Corner  Lib Pin                   Reference Pin             Required(ns)  Actual(ns)  Slack(ns)  Location                Pin
Min Period        n/a     BITSLICE_CONTROL/RIU_CLK  n/a                       3.846         6.001       2.155      BITSLICE_CONTROL_X0Y24  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
Min Period        n/a     BITSLICE_CONTROL/RIU_CLK  n/a                       3.846         6.001       2.155      BITSLICE_CONTROL_X0Y25  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
Min Period        n/a     BITSLICE_CONTROL/RIU_CLK  n/a                       3.846         6.001       2.155      BITSLICE_CONTROL_X0Y44  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
Min Period        n/a     BITSLICE_CONTROL/RIU_CLK  n/a                       3.846         6.001       2.155      BITSLICE_CONTROL_X0Y45  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
Min Period        n/a     BITSLICE_CONTROL/RIU_CLK  n/a                       3.846         6.001       2.155      BITSLICE_CONTROL_X0Y46  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
Min Period        n/a     BITSLICE_CONTROL/RIU_CLK  n/a                       3.846         6.001       2.155      BITSLICE_CONTROL_X0Y47  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
Min Period        n/a     BITSLICE_CONTROL/RIU_CLK  n/a                       3.846         6.001       2.155      BITSLICE_CONTROL_X0Y26  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
Min Period        n/a     BITSLICE_CONTROL/RIU_CLK  n/a                       3.846         6.001       2.155      BITSLICE_CONTROL_X0Y27  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
Min Period        n/a     BITSLICE_CONTROL/RIU_CLK  n/a                       3.846         6.001       2.155      BITSLICE_CONTROL_X0Y28  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
Min Period        n/a     BITSLICE_CONTROL/RIU_CLK  n/a                       3.846         6.001       2.155      BITSLICE_CONTROL_X0Y29  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
Low Pulse Width   Slow    BITSLICE_CONTROL/RIU_CLK  n/a                       1.731         3.001       1.270      BITSLICE_CONTROL_X0Y24  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
Low Pulse Width   Fast    BITSLICE_CONTROL/RIU_CLK  n/a                       1.731         3.001       1.270      BITSLICE_CONTROL_X0Y24  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
Low Pulse Width   Slow    BITSLICE_CONTROL/RIU_CLK  n/a                       1.731         3.001       1.270      BITSLICE_CONTROL_X0Y25  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
Low Pulse Width   Fast    BITSLICE_CONTROL/RIU_CLK  n/a                       1.731         3.001       1.270      BITSLICE_CONTROL_X0Y25  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
Low Pulse Width   Slow    BITSLICE_CONTROL/RIU_CLK  n/a                       1.731         3.001       1.270      BITSLICE_CONTROL_X0Y44  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
Low Pulse Width   Fast    BITSLICE_CONTROL/RIU_CLK  n/a                       1.731         3.001       1.270      BITSLICE_CONTROL_X0Y44  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
Low Pulse Width   Slow    BITSLICE_CONTROL/RIU_CLK  n/a                       1.731         3.001       1.270      BITSLICE_CONTROL_X0Y45  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
Low Pulse Width   Fast    BITSLICE_CONTROL/RIU_CLK  n/a                       1.731         3.001       1.270      BITSLICE_CONTROL_X0Y45  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
Low Pulse Width   Slow    BITSLICE_CONTROL/RIU_CLK  n/a                       1.731         3.001       1.270      BITSLICE_CONTROL_X0Y46  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
Low Pulse Width   Fast    BITSLICE_CONTROL/RIU_CLK  n/a                       1.731         3.001       1.270      BITSLICE_CONTROL_X0Y46  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
High Pulse Width  Slow    BITSLICE_CONTROL/RIU_CLK  n/a                       1.731         3.001       1.270      BITSLICE_CONTROL_X0Y24  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
High Pulse Width  Fast    BITSLICE_CONTROL/RIU_CLK  n/a                       1.731         3.001       1.270      BITSLICE_CONTROL_X0Y24  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
High Pulse Width  Slow    BITSLICE_CONTROL/RIU_CLK  n/a                       1.731         3.001       1.270      BITSLICE_CONTROL_X0Y25  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
High Pulse Width  Fast    BITSLICE_CONTROL/RIU_CLK  n/a                       1.731         3.001       1.270      BITSLICE_CONTROL_X0Y25  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
High Pulse Width  Slow    BITSLICE_CONTROL/RIU_CLK  n/a                       1.731         3.001       1.270      BITSLICE_CONTROL_X0Y44  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
High Pulse Width  Fast    BITSLICE_CONTROL/RIU_CLK  n/a                       1.731         3.001       1.270      BITSLICE_CONTROL_X0Y44  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
High Pulse Width  Slow    BITSLICE_CONTROL/RIU_CLK  n/a                       1.731         3.001       1.270      BITSLICE_CONTROL_X0Y45  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
High Pulse Width  Fast    BITSLICE_CONTROL/RIU_CLK  n/a                       1.731         3.001       1.270      BITSLICE_CONTROL_X0Y45  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
High Pulse Width  Slow    BITSLICE_CONTROL/RIU_CLK  n/a                       1.731         3.001       1.270      BITSLICE_CONTROL_X0Y46  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
High Pulse Width  Fast    BITSLICE_CONTROL/RIU_CLK  n/a                       1.731         3.001       1.270      BITSLICE_CONTROL_X0Y46  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
Max Skew          Fast    BITSLICE_CONTROL/RIU_CLK  BITSLICE_CONTROL/PLL_CLK  1.818         0.821       0.997      BITSLICE_CONTROL_X0Y32  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
Max Skew          Fast    BITSLICE_CONTROL/RIU_CLK  BITSLICE_CONTROL/PLL_CLK  1.818         0.821       0.997      BITSLICE_CONTROL_X0Y33  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
Max Skew          Fast    BITSLICE_CONTROL/RIU_CLK  BITSLICE_CONTROL/PLL_CLK  1.818         0.818       1.000      BITSLICE_CONTROL_X0Y34  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
Max Skew          Fast    BITSLICE_CONTROL/RIU_CLK  BITSLICE_CONTROL/PLL_CLK  1.818         0.818       1.000      BITSLICE_CONTROL_X0Y39  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
Max Skew          Fast    BITSLICE_CONTROL/RIU_CLK  BITSLICE_CONTROL/PLL_CLK  1.818         0.817       1.001      BITSLICE_CONTROL_X0Y24  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
Max Skew          Fast    BITSLICE_CONTROL/RIU_CLK  BITSLICE_CONTROL/PLL_CLK  1.818         0.817       1.001      BITSLICE_CONTROL_X0Y25  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
Max Skew          Fast    BITSLICE_CONTROL/RIU_CLK  BITSLICE_CONTROL/PLL_CLK  1.818         0.816       1.002      BITSLICE_CONTROL_X0Y35  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
Max Skew          Fast    BITSLICE_CONTROL/RIU_CLK  BITSLICE_CONTROL/PLL_CLK  1.818         0.816       1.002      BITSLICE_CONTROL_X0Y37  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
Max Skew          Fast    BITSLICE_CONTROL/RIU_CLK  BITSLICE_CONTROL/PLL_CLK  1.818         0.815       1.003      BITSLICE_CONTROL_X0Y38  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
Max Skew          Fast    BITSLICE_CONTROL/RIU_CLK  BITSLICE_CONTROL/PLL_CLK  1.818         0.814       1.004      BITSLICE_CONTROL_X0Y26  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK



---------------------------------------------------------------------------------------------------
From Clock:  mmcm_clkout5
  To Clock:  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK

Setup :            0  Failing Endpoints,  Worst Slack       11.583ns,  Total Violation        0.000ns
Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             11.583ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[2]/C
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[2]/D
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.002ns  (MaxDelay Path 12.002ns)
  Data Path Delay:        0.444ns  (logic 0.076ns (17.117%)  route 0.368ns (82.883%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 12.002ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X104Y369                                    0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[2]/C
    SLICE_X104Y369       FDCE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     0.076 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[2]/Q
                         net (fo=1, routed)           0.368     0.444    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q[2]
    SLICE_X104Y372       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[2]/D
  -------------------------------------------------------------------    -------------------

                         max delay                   12.002    12.002    
    SLICE_X104Y372       FDCE (Setup_CFF2_SLICEM_C_D)
                                                      0.025    12.027    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[2]
  -------------------------------------------------------------------
                         required time                         12.027    
                         arrival time                          -0.444    
  -------------------------------------------------------------------
                         slack                                 11.583    

Slack (MET) :             11.627ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[0]/C
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[0]/D
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.002ns  (MaxDelay Path 12.002ns)
  Data Path Delay:        0.400ns  (logic 0.076ns (19.000%)  route 0.324ns (81.000%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 12.002ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X104Y370                                    0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[0]/C
    SLICE_X104Y370       FDCE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     0.076 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[0]/Q
                         net (fo=1, routed)           0.324     0.400    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q[0]
    SLICE_X104Y370       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                   12.002    12.002    
    SLICE_X104Y370       FDCE (Setup_DFF2_SLICEM_C_D)
                                                      0.025    12.027    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[0]
  -------------------------------------------------------------------
                         required time                         12.027    
                         arrival time                          -0.400    
  -------------------------------------------------------------------
                         slack                                 11.627    

Slack (MET) :             11.645ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[0]/C
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[0]/D
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.002ns  (MaxDelay Path 12.002ns)
  Data Path Delay:        0.382ns  (logic 0.079ns (20.681%)  route 0.303ns (79.319%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 12.002ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X102Y349                                    0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[0]/C
    SLICE_X102Y349       FDCE (Prop_HFF_SLICEL_C_Q)
                                                      0.079     0.079 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[0]/Q
                         net (fo=1, routed)           0.303     0.382    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q[0]
    SLICE_X103Y349       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                   12.002    12.002    
    SLICE_X103Y349       FDCE (Setup_GFF2_SLICEM_C_D)
                                                      0.025    12.027    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[0]
  -------------------------------------------------------------------
                         required time                         12.027    
                         arrival time                          -0.382    
  -------------------------------------------------------------------
                         slack                                 11.645    

Slack (MET) :             11.685ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[3]/C
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[3]/D
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.002ns  (MaxDelay Path 12.002ns)
  Data Path Delay:        0.342ns  (logic 0.076ns (22.222%)  route 0.266ns (77.778%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 12.002ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X104Y370                                    0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[3]/C
    SLICE_X104Y370       FDCE (Prop_FFF_SLICEM_C_Q)
                                                      0.076     0.076 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[3]/Q
                         net (fo=1, routed)           0.266     0.342    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q[3]
    SLICE_X104Y372       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[3]/D
  -------------------------------------------------------------------    -------------------

                         max delay                   12.002    12.002    
    SLICE_X104Y372       FDCE (Setup_BFF2_SLICEM_C_D)
                                                      0.025    12.027    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[3]
  -------------------------------------------------------------------
                         required time                         12.027    
                         arrival time                          -0.342    
  -------------------------------------------------------------------
                         slack                                 11.685    

Slack (MET) :             11.694ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[1]/C
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[1]/D
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.002ns  (MaxDelay Path 12.002ns)
  Data Path Delay:        0.333ns  (logic 0.081ns (24.324%)  route 0.252ns (75.676%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 12.002ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X105Y370                                    0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[1]/C
    SLICE_X105Y370       FDCE (Prop_DFF2_SLICEL_C_Q)
                                                      0.081     0.081 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[1]/Q
                         net (fo=1, routed)           0.252     0.333    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q[1]
    SLICE_X105Y373       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         max delay                   12.002    12.002    
    SLICE_X105Y373       FDCE (Setup_CFF2_SLICEL_C_D)
                                                      0.025    12.027    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[1]
  -------------------------------------------------------------------
                         required time                         12.027    
                         arrival time                          -0.333    
  -------------------------------------------------------------------
                         slack                                 11.694    

Slack (MET) :             11.703ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[2]/C
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[2]/D
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.002ns  (MaxDelay Path 12.002ns)
  Data Path Delay:        0.324ns  (logic 0.079ns (24.383%)  route 0.245ns (75.617%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 12.002ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X102Y349                                    0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[2]/C
    SLICE_X102Y349       FDCE (Prop_GFF_SLICEL_C_Q)
                                                      0.079     0.079 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[2]/Q
                         net (fo=1, routed)           0.245     0.324    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q[2]
    SLICE_X102Y349       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[2]/D
  -------------------------------------------------------------------    -------------------

                         max delay                   12.002    12.002    
    SLICE_X102Y349       FDCE (Setup_CFF2_SLICEL_C_D)
                                                      0.025    12.027    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[2]
  -------------------------------------------------------------------
                         required time                         12.027    
                         arrival time                          -0.324    
  -------------------------------------------------------------------
                         slack                                 11.703    

Slack (MET) :             11.726ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[1]/C
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[1]/D
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.002ns  (MaxDelay Path 12.002ns)
  Data Path Delay:        0.301ns  (logic 0.080ns (26.578%)  route 0.221ns (73.422%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 12.002ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X102Y349                                    0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[1]/C
    SLICE_X102Y349       FDCE (Prop_HFF2_SLICEL_C_Q)
                                                      0.080     0.080 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[1]/Q
                         net (fo=1, routed)           0.221     0.301    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q[1]
    SLICE_X102Y349       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         max delay                   12.002    12.002    
    SLICE_X102Y349       FDCE (Setup_DFF2_SLICEL_C_D)
                                                      0.025    12.027    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[1]
  -------------------------------------------------------------------
                         required time                         12.027    
                         arrival time                          -0.301    
  -------------------------------------------------------------------
                         slack                                 11.726    

Slack (MET) :             11.736ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[3]/C
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[3]/D
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.002ns  (MaxDelay Path 12.002ns)
  Data Path Delay:        0.291ns  (logic 0.079ns (27.148%)  route 0.212ns (72.852%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 12.002ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X102Y349                                    0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[3]/C
    SLICE_X102Y349       FDCE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     0.079 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[3]/Q
                         net (fo=1, routed)           0.212     0.291    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q[3]
    SLICE_X101Y349       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[3]/D
  -------------------------------------------------------------------    -------------------

                         max delay                   12.002    12.002    
    SLICE_X101Y349       FDCE (Setup_GFF2_SLICEL_C_D)
                                                      0.025    12.027    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[3]
  -------------------------------------------------------------------
                         required time                         12.027    
                         arrival time                          -0.291    
  -------------------------------------------------------------------
                         slack                                 11.736    





---------------------------------------------------------------------------------------------------
From Clock:  mmcm_clkout5
  To Clock:  mmcm_clkout0

Setup :            0  Failing Endpoints,  Worst Slack        2.504ns,  Total Violation        0.000ns
Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             2.504ns  (required time - arrival time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[4]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[4].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.000ns  (MaxDelay Path 3.000ns)
  Data Path Delay:        0.521ns  (logic 0.079ns (15.163%)  route 0.442ns (84.837%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 3.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X95Y358                                     0.000     0.000 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[4]/C
    SLICE_X95Y358        FDRE (Prop_CFF_SLICEL_C_Q)
                                                      0.079     0.079 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[4]/Q
                         net (fo=1, routed)           0.442     0.521    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/out[4]
    SLICE_X93Y357        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[4].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    3.000     3.000    
    SLICE_X93Y357        FDRE (Setup_CFF2_SLICEM_C_D)
                                                      0.025     3.025    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[4].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                          3.025    
                         arrival time                          -0.521    
  -------------------------------------------------------------------
                         slack                                  2.504    

Slack (MET) :             2.506ns  (required time - arrival time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_di_r_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_di_sync/SYNC[1].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.000ns  (MaxDelay Path 3.000ns)
  Data Path Delay:        0.519ns  (logic 0.080ns (15.414%)  route 0.439ns (84.586%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 3.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X96Y359                                     0.000     0.000 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_di_r_reg[1]/C
    SLICE_X96Y359        FDRE (Prop_DFF2_SLICEM_C_Q)
                                                      0.080     0.080 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_di_r_reg[1]/Q
                         net (fo=1, routed)           0.439     0.519    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_di_sync/out[1]
    SLICE_X93Y358        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_di_sync/SYNC[1].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    3.000     3.000    
    SLICE_X93Y358        FDRE (Setup_HFF2_SLICEM_C_D)
                                                      0.025     3.025    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_di_sync/SYNC[1].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                          3.025    
                         arrival time                          -0.519    
  -------------------------------------------------------------------
                         slack                                  2.506    

Slack (MET) :             2.507ns  (required time - arrival time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[14]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[14].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.000ns  (MaxDelay Path 3.000ns)
  Data Path Delay:        0.518ns  (logic 0.080ns (15.444%)  route 0.438ns (84.556%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 3.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X95Y358                                     0.000     0.000 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[14]/C
    SLICE_X95Y358        FDRE (Prop_BFF2_SLICEL_C_Q)
                                                      0.080     0.080 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[14]/Q
                         net (fo=1, routed)           0.438     0.518    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/out[14]
    SLICE_X94Y358        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[14].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    3.000     3.000    
    SLICE_X94Y358        FDRE (Setup_CFF2_SLICEM_C_D)
                                                      0.025     3.025    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[14].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                          3.025    
                         arrival time                          -0.518    
  -------------------------------------------------------------------
                         slack                                  2.507    

Slack (MET) :             2.523ns  (required time - arrival time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[6]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[6].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.000ns  (MaxDelay Path 3.000ns)
  Data Path Delay:        0.502ns  (logic 0.076ns (15.139%)  route 0.426ns (84.861%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 3.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X96Y355                                     0.000     0.000 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[6]/C
    SLICE_X96Y355        FDRE (Prop_FFF_SLICEM_C_Q)
                                                      0.076     0.076 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[6]/Q
                         net (fo=1, routed)           0.426     0.502    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/out[6]
    SLICE_X92Y354        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[6].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    3.000     3.000    
    SLICE_X92Y354        FDRE (Setup_DFF2_SLICEL_C_D)
                                                      0.025     3.025    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[6].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                          3.025    
                         arrival time                          -0.502    
  -------------------------------------------------------------------
                         slack                                  2.523    

Slack (MET) :             2.529ns  (required time - arrival time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[7]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[7].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.000ns  (MaxDelay Path 3.000ns)
  Data Path Delay:        0.496ns  (logic 0.078ns (15.726%)  route 0.418ns (84.274%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 3.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X93Y357                                     0.000     0.000 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[7]/C
    SLICE_X93Y357        FDRE (Prop_HFF2_SLICEM_C_Q)
                                                      0.078     0.078 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[7]/Q
                         net (fo=1, routed)           0.418     0.496    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/out[7]
    SLICE_X92Y355        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[7].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    3.000     3.000    
    SLICE_X92Y355        FDRE (Setup_DFF2_SLICEL_C_D)
                                                      0.025     3.025    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[7].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                          3.025    
                         arrival time                          -0.496    
  -------------------------------------------------------------------
                         slack                                  2.529    

Slack (MET) :             2.544ns  (required time - arrival time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[8]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[8].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.000ns  (MaxDelay Path 3.000ns)
  Data Path Delay:        0.481ns  (logic 0.079ns (16.424%)  route 0.402ns (83.576%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 3.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X94Y356                                     0.000     0.000 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[8]/C
    SLICE_X94Y356        FDRE (Prop_HFF_SLICEM_C_Q)
                                                      0.079     0.079 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[8]/Q
                         net (fo=1, routed)           0.402     0.481    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/out[8]
    SLICE_X90Y356        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[8].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    3.000     3.000    
    SLICE_X90Y356        FDRE (Setup_CFF2_SLICEM_C_D)
                                                      0.025     3.025    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[8].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                          3.025    
                         arrival time                          -0.481    
  -------------------------------------------------------------------
                         slack                                  2.544    

Slack (MET) :             2.545ns  (required time - arrival time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[15]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[15].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.000ns  (MaxDelay Path 3.000ns)
  Data Path Delay:        0.480ns  (logic 0.078ns (16.250%)  route 0.402ns (83.750%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 3.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X96Y358                                     0.000     0.000 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[15]/C
    SLICE_X96Y358        FDRE (Prop_DFF_SLICEM_C_Q)
                                                      0.078     0.078 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[15]/Q
                         net (fo=1, routed)           0.402     0.480    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/out[15]
    SLICE_X94Y351        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[15].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    3.000     3.000    
    SLICE_X94Y351        FDRE (Setup_DFF2_SLICEM_C_D)
                                                      0.025     3.025    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[15].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                          3.025    
                         arrival time                          -0.480    
  -------------------------------------------------------------------
                         slack                                  2.545    

Slack (MET) :             2.555ns  (required time - arrival time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_di_r_reg[5]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_di_sync/SYNC[5].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.000ns  (MaxDelay Path 3.000ns)
  Data Path Delay:        0.470ns  (logic 0.078ns (16.596%)  route 0.392ns (83.404%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 3.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X94Y359                                     0.000     0.000 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_di_r_reg[5]/C
    SLICE_X94Y359        FDRE (Prop_HFF2_SLICEM_C_Q)
                                                      0.078     0.078 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_di_r_reg[5]/Q
                         net (fo=1, routed)           0.392     0.470    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_di_sync/out[5]
    SLICE_X92Y355        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_di_sync/SYNC[5].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    3.000     3.000    
    SLICE_X92Y355        FDRE (Setup_GFF2_SLICEL_C_D)
                                                      0.025     3.025    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_di_sync/SYNC[5].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                          3.025    
                         arrival time                          -0.470    
  -------------------------------------------------------------------
                         slack                                  2.555    

Slack (MET) :             2.559ns  (required time - arrival time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[0].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.000ns  (MaxDelay Path 3.000ns)
  Data Path Delay:        0.466ns  (logic 0.079ns (16.953%)  route 0.387ns (83.047%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 3.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X94Y351                                     0.000     0.000 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[0]/C
    SLICE_X94Y351        FDRE (Prop_FFF2_SLICEM_C_Q)
                                                      0.079     0.079 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[0]/Q
                         net (fo=1, routed)           0.387     0.466    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/out[0]
    SLICE_X92Y349        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[0].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    3.000     3.000    
    SLICE_X92Y349        FDRE (Setup_DFF2_SLICEL_C_D)
                                                      0.025     3.025    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[0].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                          3.025    
                         arrival time                          -0.466    
  -------------------------------------------------------------------
                         slack                                  2.559    

Slack (MET) :             2.585ns  (required time - arrival time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[1].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.000ns  (MaxDelay Path 3.000ns)
  Data Path Delay:        0.440ns  (logic 0.078ns (17.727%)  route 0.362ns (82.273%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 3.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X94Y352                                     0.000     0.000 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[1]/C
    SLICE_X94Y352        FDRE (Prop_GFF_SLICEM_C_Q)
                                                      0.078     0.078 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[1]/Q
                         net (fo=1, routed)           0.362     0.440    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/out[1]
    SLICE_X92Y349        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[1].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    3.000     3.000    
    SLICE_X92Y349        FDRE (Setup_HFF2_SLICEL_C_D)
                                                      0.025     3.025    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[1].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                          3.025    
                         arrival time                          -0.440    
  -------------------------------------------------------------------
                         slack                                  2.585    





---------------------------------------------------------------------------------------------------
From Clock:  mmcm_clkout6
  To Clock:  mmcm_clkout0

Setup :            0  Failing Endpoints,  Worst Slack        1.139ns,  Total Violation        0.000ns
Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             1.139ns  (required time - arrival time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_write_strobe_riuclk_reg/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_write_strobe_sync/SYNC[0].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.000ns  (MaxDelay Path 3.000ns)
  Data Path Delay:        1.886ns  (logic 0.079ns (4.188%)  route 1.807ns (95.812%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 3.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X85Y328                                     0.000     0.000 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_write_strobe_riuclk_reg/C
    SLICE_X85Y328        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     0.079 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_write_strobe_riuclk_reg/Q
                         net (fo=16, routed)          1.807     1.886    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_write_strobe_sync/D[0]
    SLICE_X93Y272        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_write_strobe_sync/SYNC[0].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    3.000     3.000    
    SLICE_X93Y272        FDRE (Setup_CFF2_SLICEM_C_D)
                                                      0.025     3.025    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_write_strobe_sync/SYNC[0].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                          3.025    
                         arrival time                          -1.886    
  -------------------------------------------------------------------
                         slack                                  1.139    

Slack (MET) :             1.312ns  (required time - arrival time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[21]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[21].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.000ns  (MaxDelay Path 3.000ns)
  Data Path Delay:        1.713ns  (logic 0.080ns (4.669%)  route 1.633ns (95.331%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 3.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X96Y325                                     0.000     0.000 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[21]/C
    SLICE_X96Y325        FDRE (Prop_AFF2_SLICEM_C_Q)
                                                      0.080     0.080 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[21]/Q
                         net (fo=41, routed)          1.633     1.713    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[31].sync_reg_reg[0]_0[21]
    SLICE_X92Y297        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[21].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    3.000     3.000    
    SLICE_X92Y297        FDRE (Setup_CFF2_SLICEL_C_D)
                                                      0.025     3.025    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[21].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                          3.025    
                         arrival time                          -1.713    
  -------------------------------------------------------------------
                         slack                                  1.312    

Slack (MET) :             1.562ns  (required time - arrival time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_write_data_riuclk_reg[12]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_write_data_sync/SYNC[12].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.000ns  (MaxDelay Path 3.000ns)
  Data Path Delay:        1.463ns  (logic 0.076ns (5.195%)  route 1.387ns (94.805%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 3.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X82Y330                                     0.000     0.000 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_write_data_riuclk_reg[12]/C
    SLICE_X82Y330        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     0.076 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_write_data_riuclk_reg[12]/Q
                         net (fo=2, routed)           1.387     1.463    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_write_data_sync/SYNC[31].sync_reg_reg[0]_0[12]
    SLICE_X83Y325        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_write_data_sync/SYNC[12].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    3.000     3.000    
    SLICE_X83Y325        FDRE (Setup_BFF2_SLICEM_C_D)
                                                      0.025     3.025    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_write_data_sync/SYNC[12].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                          3.025    
                         arrival time                          -1.463    
  -------------------------------------------------------------------
                         slack                                  1.562    

Slack (MET) :             1.584ns  (required time - arrival time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_write_data_riuclk_reg[27]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_write_data_sync/SYNC[27].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.000ns  (MaxDelay Path 3.000ns)
  Data Path Delay:        1.441ns  (logic 0.081ns (5.621%)  route 1.360ns (94.379%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 3.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X88Y331                                     0.000     0.000 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_write_data_riuclk_reg[27]/C
    SLICE_X88Y331        FDRE (Prop_EFF2_SLICEL_C_Q)
                                                      0.081     0.081 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_write_data_riuclk_reg[27]/Q
                         net (fo=1, routed)           1.360     1.441    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_write_data_sync/SYNC[31].sync_reg_reg[0]_0[27]
    SLICE_X88Y331        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_write_data_sync/SYNC[27].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    3.000     3.000    
    SLICE_X88Y331        FDRE (Setup_CFF2_SLICEL_C_D)
                                                      0.025     3.025    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_write_data_sync/SYNC[27].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                          3.025    
                         arrival time                          -1.441    
  -------------------------------------------------------------------
                         slack                                  1.584    

Slack (MET) :             1.676ns  (required time - arrival time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[22]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[22].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.000ns  (MaxDelay Path 3.000ns)
  Data Path Delay:        1.349ns  (logic 0.078ns (5.781%)  route 1.271ns (94.219%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 3.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X96Y325                                     0.000     0.000 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[22]/C
    SLICE_X96Y325        FDRE (Prop_BFF_SLICEM_C_Q)
                                                      0.078     0.078 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[22]/Q
                         net (fo=41, routed)          1.271     1.349    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[31].sync_reg_reg[0]_0[22]
    SLICE_X94Y300        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[22].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    3.000     3.000    
    SLICE_X94Y300        FDRE (Setup_BFF2_SLICEM_C_D)
                                                      0.025     3.025    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[22].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                          3.025    
                         arrival time                          -1.349    
  -------------------------------------------------------------------
                         slack                                  1.676    

Slack (MET) :             1.709ns  (required time - arrival time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[23]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[23].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.000ns  (MaxDelay Path 3.000ns)
  Data Path Delay:        1.316ns  (logic 0.080ns (6.079%)  route 1.236ns (93.921%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 3.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X96Y325                                     0.000     0.000 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[23]/C
    SLICE_X96Y325        FDRE (Prop_BFF2_SLICEM_C_Q)
                                                      0.080     0.080 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[23]/Q
                         net (fo=46, routed)          1.236     1.316    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[31].sync_reg_reg[0]_0[23]
    SLICE_X95Y289        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[23].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    3.000     3.000    
    SLICE_X95Y289        FDRE (Setup_HFF2_SLICEL_C_D)
                                                      0.025     3.025    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[23].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                          3.025    
                         arrival time                          -1.316    
  -------------------------------------------------------------------
                         slack                                  1.709    

Slack (MET) :             1.725ns  (required time - arrival time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[3].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.000ns  (MaxDelay Path 3.000ns)
  Data Path Delay:        1.300ns  (logic 0.076ns (5.848%)  route 1.224ns (94.152%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 3.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X94Y321                                     0.000     0.000 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[3]/C
    SLICE_X94Y321        FDRE (Prop_FFF_SLICEM_C_Q)
                                                      0.076     0.076 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[3]/Q
                         net (fo=39, routed)          1.224     1.300    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[31].sync_reg_reg[0]_0[3]
    SLICE_X94Y282        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[3].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    3.000     3.000    
    SLICE_X94Y282        FDRE (Setup_HFF2_SLICEM_C_D)
                                                      0.025     3.025    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[3].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                          3.025    
                         arrival time                          -1.300    
  -------------------------------------------------------------------
                         slack                                  1.725    

Slack (MET) :             1.851ns  (required time - arrival time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[24]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[24].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.000ns  (MaxDelay Path 3.000ns)
  Data Path Delay:        1.174ns  (logic 0.078ns (6.645%)  route 1.096ns (93.355%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 3.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X96Y325                                     0.000     0.000 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[24]/C
    SLICE_X96Y325        FDRE (Prop_CFF_SLICEM_C_Q)
                                                      0.078     0.078 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[24]/Q
                         net (fo=8, routed)           1.096     1.174    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[31].sync_reg_reg[0]_0[24]
    SLICE_X96Y274        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[24].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    3.000     3.000    
    SLICE_X96Y274        FDRE (Setup_DFF2_SLICEM_C_D)
                                                      0.025     3.025    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[24].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                          3.025    
                         arrival time                          -1.174    
  -------------------------------------------------------------------
                         slack                                  1.851    

Slack (MET) :             1.852ns  (required time - arrival time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2phy_t_b_addr_riuclk_reg/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2phy_t_b_addr_i_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.000ns  (MaxDelay Path 3.000ns)
  Data Path Delay:        1.173ns  (logic 0.076ns (6.479%)  route 1.097ns (93.521%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 3.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X82Y313                                     0.000     0.000 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2phy_t_b_addr_riuclk_reg/C
    SLICE_X82Y313        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     0.076 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2phy_t_b_addr_riuclk_reg/Q
                         net (fo=1, routed)           1.097     1.173    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2phy_t_b_addr_riuclk
    SLICE_X81Y323        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2phy_t_b_addr_i_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    3.000     3.000    
    SLICE_X81Y323        FDRE (Setup_CFF2_SLICEL_C_D)
                                                      0.025     3.025    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2phy_t_b_addr_i_reg[0]
  -------------------------------------------------------------------
                         required time                          3.025    
                         arrival time                          -1.173    
  -------------------------------------------------------------------
                         slack                                  1.852    

Slack (MET) :             1.856ns  (required time - arrival time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[0].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.000ns  (MaxDelay Path 3.000ns)
  Data Path Delay:        1.169ns  (logic 0.077ns (6.587%)  route 1.092ns (93.413%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 3.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X93Y321                                     0.000     0.000 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[0]/C
    SLICE_X93Y321        FDRE (Prop_AFF_SLICEM_C_Q)
                                                      0.077     0.077 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[0]/Q
                         net (fo=34, routed)          1.092     1.169    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[31].sync_reg_reg[0]_0[0]
    SLICE_X83Y247        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[0].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    3.000     3.000    
    SLICE_X83Y247        FDRE (Setup_HFF2_SLICEM_C_D)
                                                      0.025     3.025    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[0].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                          3.025    
                         arrival time                          -1.169    
  -------------------------------------------------------------------
                         slack                                  1.856    





---------------------------------------------------------------------------------------------------
From Clock:  mmcm_clkout0
  To Clock:  pll_clk[0]_DIV

Setup :            0  Failing Endpoints,  Worst Slack        0.424ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.579ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.424ns  (required time - arrival time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/oe_upp_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TBYTE_IN[0]
                            (rising edge-triggered cell BITSLICE_CONTROL clocked by pll_clk[0]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[0]_DIV
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (pll_clk[0]_DIV rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        1.584ns  (logic 0.079ns (4.989%)  route 1.505ns (95.011%))
  Logic Levels:           0  
  Clock Path Skew:        -0.665ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.342ns = ( 7.343 - 3.001 ) 
    Source Clock Delay      (SCD):    4.676ns
    Clock Pessimism Removal (CPR):    -0.331ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.921ns (routing 0.696ns, distribution 1.225ns)
  Clock Net Delay (Destination): 1.542ns (routing 0.630ns, distribution 0.912ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.524     2.610    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.483 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.244     2.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.755 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.921     4.676    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/dReg_reg[10]
    SLICE_X81Y286        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/oe_upp_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y286        FDRE (Prop_CFF_SLICEL_C_Q)
                                                      0.079     4.755 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/oe_upp_reg[0]/Q
                         net (fo=8, routed)           1.505     6.259    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/ch0_mcal_clb2phy_t_b_upp[0]
    BITSLICE_CONTROL_X0Y25
                         BITSLICE_CONTROL                             r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TBYTE_IN[0]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[0]_DIV rise edge)
                                                      3.001     3.001 r  
    J19                                               0.000     3.001 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.555 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.595    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.595 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     3.892    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.916 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.364     5.280    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.910 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.214     6.124    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     6.148 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.542     7.690    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y6             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -0.630     7.060 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[0].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.102     7.162    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y25
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.106     7.268 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y25
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.075     7.343 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
                         clock pessimism             -0.331     7.012    
                         clock uncertainty           -0.170     6.842    
    BITSLICE_CONTROL_X0Y25
                         BITSLICE_CONTROL (Setup_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TBYTE_IN[0])
                                                     -0.158     6.684    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control
  -------------------------------------------------------------------
                         required time                          6.684    
                         arrival time                          -6.259    
  -------------------------------------------------------------------
                         slack                                  0.424    

Slack (MET) :             0.543ns  (required time - arrival time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/oe_upp_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TBYTE_IN[1]
                            (rising edge-triggered cell BITSLICE_CONTROL clocked by pll_clk[0]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[0]_DIV
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (pll_clk[0]_DIV rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        1.453ns  (logic 0.078ns (5.370%)  route 1.375ns (94.630%))
  Logic Levels:           0  
  Clock Path Skew:        -0.682ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.342ns = ( 7.343 - 3.001 ) 
    Source Clock Delay      (SCD):    4.693ns
    Clock Pessimism Removal (CPR):    -0.331ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.938ns (routing 0.696ns, distribution 1.242ns)
  Clock Net Delay (Destination): 1.542ns (routing 0.630ns, distribution 0.912ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.524     2.610    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.483 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.244     2.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.755 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.938     4.693    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/dReg_reg[10]
    SLICE_X83Y284        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/oe_upp_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X83Y284        FDRE (Prop_BFF_SLICEM_C_Q)
                                                      0.078     4.771 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/oe_upp_reg[1]/Q
                         net (fo=8, routed)           1.375     6.145    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/ch0_mcal_clb2phy_t_b_upp[1]
    BITSLICE_CONTROL_X0Y25
                         BITSLICE_CONTROL                             r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TBYTE_IN[1]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[0]_DIV rise edge)
                                                      3.001     3.001 r  
    J19                                               0.000     3.001 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.555 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.595    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.595 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     3.892    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.916 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.364     5.280    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.910 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.214     6.124    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     6.148 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.542     7.690    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y6             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -0.630     7.060 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[0].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.102     7.162    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y25
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.106     7.268 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y25
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.075     7.343 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
                         clock pessimism             -0.331     7.012    
                         clock uncertainty           -0.170     6.842    
    BITSLICE_CONTROL_X0Y25
                         BITSLICE_CONTROL (Setup_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TBYTE_IN[1])
                                                     -0.153     6.689    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control
  -------------------------------------------------------------------
                         required time                          6.689    
                         arrival time                          -6.145    
  -------------------------------------------------------------------
                         slack                                  0.543    

Slack (MET) :             0.598ns  (required time - arrival time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[7].u_ddr_mc_rd_en_low/rdEn_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PHY_RDEN[0]
                            (rising edge-triggered cell BITSLICE_CONTROL clocked by pll_clk[0]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[0]_DIV
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (pll_clk[0]_DIV rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        1.562ns  (logic 0.079ns (5.058%)  route 1.483ns (94.942%))
  Logic Levels:           0  
  Clock Path Skew:        -0.645ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.370ns = ( 7.371 - 3.001 ) 
    Source Clock Delay      (SCD):    4.684ns
    Clock Pessimism Removal (CPR):    -0.331ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.929ns (routing 0.696ns, distribution 1.233ns)
  Clock Net Delay (Destination): 1.542ns (routing 0.630ns, distribution 0.912ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.524     2.610    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.483 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.244     2.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.755 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.929     4.684    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[7].u_ddr_mc_rd_en_low/rsMask_reg[7][9]_0
    SLICE_X81Y291        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[7].u_ddr_mc_rd_en_low/rdEn_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y291        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     4.763 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[7].u_ddr_mc_rd_en_low/rdEn_reg[0]/Q
                         net (fo=1, routed)           1.483     6.246    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/ch0_mcal_clb2phy_rden_low[0]
    BITSLICE_CONTROL_X0Y24
                         BITSLICE_CONTROL                             r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PHY_RDEN[0]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[0]_DIV rise edge)
                                                      3.001     3.001 f  
    J19                                               0.000     3.001 f  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.555 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.595    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.595 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     3.892    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.916 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.364     5.280    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.910 f  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.214     6.124    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     6.148 f  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.542     7.690    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y6             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -0.630     7.060 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[0].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.103     7.163    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y24
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_RX_DIV2_CLK_Q)
                                                      0.126     7.289 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y24
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_RX_DIV2_CLK_Q_RX_DIV4_CLK_Q)
                                                      0.082     7.371 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV4_CLK_Q
                         clock pessimism             -0.331     7.040    
                         clock uncertainty           -0.170     6.870    
    BITSLICE_CONTROL_X0Y24
                         BITSLICE_CONTROL (Setup_CONTROL_BITSLICE_CONTROL_RX_DIV4_CLK_Q_PHY_RDEN[0])
                                                     -0.026     6.844    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control
  -------------------------------------------------------------------
                         required time                          6.844    
                         arrival time                          -6.246    
  -------------------------------------------------------------------
                         slack                                  0.598    

Slack (MET) :             0.608ns  (required time - arrival time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/oe_low_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TBYTE_IN[0]
                            (rising edge-triggered cell BITSLICE_CONTROL clocked by pll_clk[0]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[0]_DIV
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (pll_clk[0]_DIV rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        1.430ns  (logic 0.079ns (5.523%)  route 1.351ns (94.477%))
  Logic Levels:           0  
  Clock Path Skew:        -0.653ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.354ns = ( 7.355 - 3.001 ) 
    Source Clock Delay      (SCD):    4.676ns
    Clock Pessimism Removal (CPR):    -0.331ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.921ns (routing 0.696ns, distribution 1.225ns)
  Clock Net Delay (Destination): 1.542ns (routing 0.630ns, distribution 0.912ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.524     2.610    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.483 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.244     2.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.755 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.921     4.676    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/dReg_reg[10]
    SLICE_X81Y286        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/oe_low_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y286        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.079     4.755 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/oe_low_reg[0]/Q
                         net (fo=8, routed)           1.351     6.106    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/ch0_mcal_clb2phy_t_b_low[0]
    BITSLICE_CONTROL_X0Y24
                         BITSLICE_CONTROL                             r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TBYTE_IN[0]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[0]_DIV rise edge)
                                                      3.001     3.001 r  
    J19                                               0.000     3.001 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.555 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.595    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.595 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     3.892    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.916 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.364     5.280    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.910 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.214     6.124    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     6.148 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.542     7.690    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y6             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -0.630     7.060 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[0].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.103     7.163    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y24
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.117     7.280 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y24
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.075     7.355 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
                         clock pessimism             -0.331     7.024    
                         clock uncertainty           -0.170     6.854    
    BITSLICE_CONTROL_X0Y24
                         BITSLICE_CONTROL (Setup_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TBYTE_IN[0])
                                                     -0.140     6.714    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control
  -------------------------------------------------------------------
                         required time                          6.714    
                         arrival time                          -6.106    
  -------------------------------------------------------------------
                         slack                                  0.608    

Slack (MET) :             0.609ns  (required time - arrival time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/oe_upp_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TBYTE_IN[2]
                            (rising edge-triggered cell BITSLICE_CONTROL clocked by pll_clk[0]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[0]_DIV
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (pll_clk[0]_DIV rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        1.389ns  (logic 0.079ns (5.688%)  route 1.310ns (94.312%))
  Logic Levels:           0  
  Clock Path Skew:        -0.665ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.342ns = ( 7.343 - 3.001 ) 
    Source Clock Delay      (SCD):    4.676ns
    Clock Pessimism Removal (CPR):    -0.331ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.921ns (routing 0.696ns, distribution 1.225ns)
  Clock Net Delay (Destination): 1.542ns (routing 0.630ns, distribution 0.912ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.524     2.610    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.483 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.244     2.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.755 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.921     4.676    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/dReg_reg[10]
    SLICE_X81Y286        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/oe_upp_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y286        FDRE (Prop_BFF_SLICEL_C_Q)
                                                      0.079     4.755 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/oe_upp_reg[2]/Q
                         net (fo=8, routed)           1.310     6.065    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/ch0_mcal_clb2phy_t_b_upp[2]
    BITSLICE_CONTROL_X0Y25
                         BITSLICE_CONTROL                             r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TBYTE_IN[2]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[0]_DIV rise edge)
                                                      3.001     3.001 r  
    J19                                               0.000     3.001 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.555 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.595    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.595 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     3.892    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.916 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.364     5.280    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.910 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.214     6.124    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     6.148 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.542     7.690    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y6             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -0.630     7.060 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[0].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.102     7.162    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y25
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.106     7.268 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y25
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.075     7.343 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
                         clock pessimism             -0.331     7.012    
                         clock uncertainty           -0.170     6.842    
    BITSLICE_CONTROL_X0Y25
                         BITSLICE_CONTROL (Setup_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TBYTE_IN[2])
                                                     -0.168     6.674    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control
  -------------------------------------------------------------------
                         required time                          6.674    
                         arrival time                          -6.065    
  -------------------------------------------------------------------
                         slack                                  0.609    

Slack (MET) :             0.613ns  (required time - arrival time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/oe_low_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TBYTE_IN[3]
                            (rising edge-triggered cell BITSLICE_CONTROL clocked by pll_clk[0]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[0]_DIV
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (pll_clk[0]_DIV rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        1.419ns  (logic 0.079ns (5.568%)  route 1.340ns (94.432%))
  Logic Levels:           0  
  Clock Path Skew:        -0.643ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.354ns = ( 7.355 - 3.001 ) 
    Source Clock Delay      (SCD):    4.666ns
    Clock Pessimism Removal (CPR):    -0.331ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.911ns (routing 0.696ns, distribution 1.215ns)
  Clock Net Delay (Destination): 1.542ns (routing 0.630ns, distribution 0.912ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.524     2.610    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.483 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.244     2.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.755 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.911     4.666    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/dReg_reg[10]
    SLICE_X81Y287        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/oe_low_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y287        FDRE (Prop_BFF_SLICEL_C_Q)
                                                      0.079     4.745 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/oe_low_reg[3]/Q
                         net (fo=8, routed)           1.340     6.085    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/ch0_mcal_clb2phy_t_b_low[3]
    BITSLICE_CONTROL_X0Y24
                         BITSLICE_CONTROL                             r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TBYTE_IN[3]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[0]_DIV rise edge)
                                                      3.001     3.001 r  
    J19                                               0.000     3.001 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.555 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.595    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.595 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     3.892    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.916 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.364     5.280    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.910 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.214     6.124    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     6.148 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.542     7.690    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y6             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -0.630     7.060 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[0].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.103     7.163    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y24
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.117     7.280 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y24
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.075     7.355 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
                         clock pessimism             -0.331     7.024    
                         clock uncertainty           -0.170     6.854    
    BITSLICE_CONTROL_X0Y24
                         BITSLICE_CONTROL (Setup_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TBYTE_IN[3])
                                                     -0.156     6.698    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control
  -------------------------------------------------------------------
                         required time                          6.698    
                         arrival time                          -6.085    
  -------------------------------------------------------------------
                         slack                                  0.613    

Slack (MET) :             0.619ns  (required time - arrival time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/oe_upp_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TBYTE_IN[0]
                            (rising edge-triggered cell BITSLICE_CONTROL clocked by pll_clk[0]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[0]_DIV
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (pll_clk[0]_DIV rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        1.384ns  (logic 0.079ns (5.708%)  route 1.305ns (94.292%))
  Logic Levels:           0  
  Clock Path Skew:        -0.670ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.337ns = ( 7.338 - 3.001 ) 
    Source Clock Delay      (SCD):    4.676ns
    Clock Pessimism Removal (CPR):    -0.331ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.921ns (routing 0.696ns, distribution 1.225ns)
  Clock Net Delay (Destination): 1.542ns (routing 0.630ns, distribution 0.912ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.524     2.610    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.483 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.244     2.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.755 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.921     4.676    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/dReg_reg[10]
    SLICE_X81Y286        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/oe_upp_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y286        FDRE (Prop_CFF_SLICEL_C_Q)
                                                      0.079     4.755 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/oe_upp_reg[0]/Q
                         net (fo=8, routed)           1.305     6.060    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/ch0_mcal_clb2phy_t_b_upp[0]
    BITSLICE_CONTROL_X0Y27
                         BITSLICE_CONTROL                             r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TBYTE_IN[0]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[0]_DIV rise edge)
                                                      3.001     3.001 f  
    J19                                               0.000     3.001 f  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.555 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.595    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.595 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     3.892    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.916 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.364     5.280    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.910 f  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.214     6.124    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     6.148 f  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.542     7.690    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y6             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -0.630     7.060 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[0].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.097     7.157    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y27
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.106     7.263 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y27
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.075     7.338 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
                         clock pessimism             -0.331     7.007    
                         clock uncertainty           -0.170     6.837    
    BITSLICE_CONTROL_X0Y27
                         BITSLICE_CONTROL (Setup_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TBYTE_IN[0])
                                                     -0.158     6.679    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control
  -------------------------------------------------------------------
                         required time                          6.679    
                         arrival time                          -6.060    
  -------------------------------------------------------------------
                         slack                                  0.619    

Slack (MET) :             0.641ns  (required time - arrival time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/oe_upp_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TBYTE_IN[3]
                            (rising edge-triggered cell BITSLICE_CONTROL clocked by pll_clk[0]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[0]_DIV
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (pll_clk[0]_DIV rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        1.432ns  (logic 0.079ns (5.516%)  route 1.353ns (94.484%))
  Logic Levels:           0  
  Clock Path Skew:        -0.665ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.342ns = ( 7.343 - 3.001 ) 
    Source Clock Delay      (SCD):    4.676ns
    Clock Pessimism Removal (CPR):    -0.331ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.921ns (routing 0.696ns, distribution 1.225ns)
  Clock Net Delay (Destination): 1.542ns (routing 0.630ns, distribution 0.912ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.524     2.610    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.483 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.244     2.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.755 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.921     4.676    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/dReg_reg[10]
    SLICE_X81Y286        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/oe_upp_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y286        FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.079     4.755 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/oe_upp_reg[3]/Q
                         net (fo=8, routed)           1.353     6.108    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/ch0_mcal_clb2phy_t_b_upp[3]
    BITSLICE_CONTROL_X0Y25
                         BITSLICE_CONTROL                             r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TBYTE_IN[3]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[0]_DIV rise edge)
                                                      3.001     3.001 r  
    J19                                               0.000     3.001 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.555 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.595    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.595 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     3.892    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.916 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.364     5.280    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.910 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.214     6.124    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     6.148 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.542     7.690    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y6             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -0.630     7.060 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[0].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.102     7.162    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y25
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.106     7.268 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y25
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.075     7.343 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
                         clock pessimism             -0.331     7.012    
                         clock uncertainty           -0.170     6.842    
    BITSLICE_CONTROL_X0Y25
                         BITSLICE_CONTROL (Setup_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TBYTE_IN[3])
                                                     -0.093     6.749    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control
  -------------------------------------------------------------------
                         required time                          6.749    
                         arrival time                          -6.108    
  -------------------------------------------------------------------
                         slack                                  0.641    

Slack (MET) :             0.677ns  (required time - arrival time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[4].u_ddr_mc_rd_en_upp/rdEn_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PHY_RDEN[3]
                            (rising edge-triggered cell BITSLICE_CONTROL clocked by pll_clk[0]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[0]_DIV
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (pll_clk[0]_DIV rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        1.547ns  (logic 0.079ns (5.107%)  route 1.468ns (94.893%))
  Logic Levels:           0  
  Clock Path Skew:        -0.558ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.354ns = ( 7.355 - 3.001 ) 
    Source Clock Delay      (SCD):    4.644ns
    Clock Pessimism Removal (CPR):    -0.268ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.889ns (routing 0.696ns, distribution 1.193ns)
  Clock Net Delay (Destination): 1.542ns (routing 0.630ns, distribution 0.912ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.524     2.610    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.483 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.244     2.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.755 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.889     4.644    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[4].u_ddr_mc_rd_en_upp/rsMask_reg[7][9]_0
    SLICE_X91Y236        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[4].u_ddr_mc_rd_en_upp/rdEn_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X91Y236        FDRE (Prop_FFF_SLICEL_C_Q)
                                                      0.079     4.723 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[4].u_ddr_mc_rd_en_upp/rdEn_reg[3]/Q
                         net (fo=1, routed)           1.468     6.191    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/ch0_mcal_clb2phy_rden_upp[3]
    BITSLICE_CONTROL_X0Y31
                         BITSLICE_CONTROL                             r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PHY_RDEN[3]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[0]_DIV rise edge)
                                                      3.001     3.001 f  
    J19                                               0.000     3.001 f  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.555 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.595    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.595 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     3.892    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.916 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.364     5.280    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.910 f  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.214     6.124    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     6.148 f  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.542     7.690    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y6             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -0.630     7.060 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[0].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.105     7.165    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y31
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_RX_DIV2_CLK_Q)
                                                      0.112     7.277 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y31
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_RX_DIV2_CLK_Q_RX_DIV4_CLK_Q)
                                                      0.078     7.355 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV4_CLK_Q
                         clock pessimism             -0.268     7.087    
                         clock uncertainty           -0.170     6.917    
    BITSLICE_CONTROL_X0Y31
                         BITSLICE_CONTROL (Setup_CONTROL_BITSLICE_CONTROL_RX_DIV4_CLK_Q_PHY_RDEN[3])
                                                     -0.049     6.868    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control
  -------------------------------------------------------------------
                         required time                          6.868    
                         arrival time                          -6.191    
  -------------------------------------------------------------------
                         slack                                  0.677    

Slack (MET) :             0.681ns  (required time - arrival time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/oe_upp_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TBYTE_IN[1]
                            (rising edge-triggered cell BITSLICE_CONTROL clocked by pll_clk[0]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[0]_DIV
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (pll_clk[0]_DIV rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        1.310ns  (logic 0.078ns (5.956%)  route 1.232ns (94.044%))
  Logic Levels:           0  
  Clock Path Skew:        -0.687ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.337ns = ( 7.338 - 3.001 ) 
    Source Clock Delay      (SCD):    4.693ns
    Clock Pessimism Removal (CPR):    -0.331ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.938ns (routing 0.696ns, distribution 1.242ns)
  Clock Net Delay (Destination): 1.542ns (routing 0.630ns, distribution 0.912ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.524     2.610    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.483 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.244     2.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.755 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.938     4.693    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/dReg_reg[10]
    SLICE_X83Y284        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/oe_upp_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X83Y284        FDRE (Prop_BFF_SLICEM_C_Q)
                                                      0.078     4.771 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/oe_upp_reg[1]/Q
                         net (fo=8, routed)           1.232     6.002    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/ch0_mcal_clb2phy_t_b_upp[1]
    BITSLICE_CONTROL_X0Y27
                         BITSLICE_CONTROL                             r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TBYTE_IN[1]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[0]_DIV rise edge)
                                                      3.001     3.001 f  
    J19                                               0.000     3.001 f  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.555 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.595    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.595 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     3.892    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.916 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.364     5.280    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.910 f  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.214     6.124    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     6.148 f  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.542     7.690    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y6             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -0.630     7.060 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[0].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.097     7.157    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y27
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.106     7.263 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y27
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.075     7.338 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
                         clock pessimism             -0.331     7.007    
                         clock uncertainty           -0.170     6.837    
    BITSLICE_CONTROL_X0Y27
                         BITSLICE_CONTROL (Setup_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TBYTE_IN[1])
                                                     -0.153     6.684    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control
  -------------------------------------------------------------------
                         required time                          6.684    
                         arrival time                          -6.002    
  -------------------------------------------------------------------
                         slack                                  0.681    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.579ns  (arrival time - required time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[6].u_ddr_mc_rd_en_low/rdEn_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PHY_RDEN[2]
                            (rising edge-triggered cell BITSLICE_CONTROL clocked by pll_clk[0]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[0]_DIV
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (pll_clk[0]_DIV rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.347ns  (logic 0.058ns (16.715%)  route 0.289ns (83.285%))
  Logic Levels:           0  
  Clock Path Skew:        -0.672ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.871ns
    Source Clock Delay      (SCD):    4.811ns
    Clock Pessimism Removal (CPR):    -0.268ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.664ns (routing 0.630ns, distribution 1.034ns)
  Clock Net Delay (Destination): 1.719ns (routing 0.696ns, distribution 1.023ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.364     2.279    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.909 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.214     3.123    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.147 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.664     4.811    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[6].u_ddr_mc_rd_en_low/rsMask_reg[7][12]_0
    SLICE_X86Y200        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[6].u_ddr_mc_rd_en_low/rdEn_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X86Y200        FDRE (Prop_GFF_SLICEM_C_Q)
                                                      0.058     4.869 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[6].u_ddr_mc_rd_en_low/rdEn_reg[2]/Q
                         net (fo=1, routed)           0.289     5.158    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/ch0_mcal_clb2phy_rden_low[2]
    BITSLICE_CONTROL_X0Y26
                         BITSLICE_CONTROL                             r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PHY_RDEN[2]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[0]_DIV rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.524     2.610    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.483 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.244     2.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.755 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.719     4.474    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y6             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -1.058     3.416 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[0].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.143     3.559    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y26
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_RX_DIV2_CLK_Q)
                                                      0.193     3.752 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y26
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_RX_DIV2_CLK_Q_RX_DIV4_CLK_Q)
                                                      0.119     3.871 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV4_CLK_Q
                         clock pessimism              0.268     4.138    
                         clock uncertainty            0.170     4.309    
    BITSLICE_CONTROL_X0Y26
                         BITSLICE_CONTROL (Hold_CONTROL_BITSLICE_CONTROL_RX_DIV4_CLK_Q_PHY_RDEN[2])
                                                      0.270     4.579    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control
  -------------------------------------------------------------------
                         required time                         -4.579    
                         arrival time                           5.158    
  -------------------------------------------------------------------
                         slack                                  0.579    

Slack (MET) :             0.612ns  (arrival time - required time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[6].u_ddr_mc_rd_en_low/rdEn_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PHY_RDEN[0]
                            (rising edge-triggered cell BITSLICE_CONTROL clocked by pll_clk[0]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[0]_DIV
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (pll_clk[0]_DIV rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.376ns  (logic 0.057ns (15.160%)  route 0.319ns (84.840%))
  Logic Levels:           0  
  Clock Path Skew:        -0.673ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.871ns
    Source Clock Delay      (SCD):    4.812ns
    Clock Pessimism Removal (CPR):    -0.268ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.665ns (routing 0.630ns, distribution 1.035ns)
  Clock Net Delay (Destination): 1.719ns (routing 0.696ns, distribution 1.023ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.364     2.279    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.909 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.214     3.123    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.147 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.665     4.812    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[6].u_ddr_mc_rd_en_low/rsMask_reg[7][12]_0
    SLICE_X86Y199        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[6].u_ddr_mc_rd_en_low/rdEn_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X86Y199        FDRE (Prop_FFF_SLICEM_C_Q)
                                                      0.057     4.869 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[6].u_ddr_mc_rd_en_low/rdEn_reg[0]/Q
                         net (fo=1, routed)           0.319     5.188    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/ch0_mcal_clb2phy_rden_low[0]
    BITSLICE_CONTROL_X0Y26
                         BITSLICE_CONTROL                             r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PHY_RDEN[0]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[0]_DIV rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.524     2.610    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.483 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.244     2.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.755 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.719     4.474    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y6             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -1.058     3.416 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[0].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.143     3.559    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y26
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_RX_DIV2_CLK_Q)
                                                      0.193     3.752 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y26
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_RX_DIV2_CLK_Q_RX_DIV4_CLK_Q)
                                                      0.119     3.871 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV4_CLK_Q
                         clock pessimism              0.268     4.138    
                         clock uncertainty            0.170     4.309    
    BITSLICE_CONTROL_X0Y26
                         BITSLICE_CONTROL (Hold_CONTROL_BITSLICE_CONTROL_RX_DIV4_CLK_Q_PHY_RDEN[0])
                                                      0.267     4.576    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control
  -------------------------------------------------------------------
                         required time                         -4.576    
                         arrival time                           5.188    
  -------------------------------------------------------------------
                         slack                                  0.612    

Slack (MET) :             0.630ns  (arrival time - required time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[4].u_ddr_mc_rd_en_low/rdEn_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PHY_RDEN[3]
                            (rising edge-triggered cell BITSLICE_CONTROL clocked by pll_clk[0]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[0]_DIV
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (pll_clk[0]_DIV rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.451ns  (logic 0.059ns (13.082%)  route 0.392ns (86.918%))
  Logic Levels:           0  
  Clock Path Skew:        -0.617ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.876ns
    Source Clock Delay      (SCD):    4.824ns
    Clock Pessimism Removal (CPR):    -0.331ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.677ns (routing 0.630ns, distribution 1.047ns)
  Clock Net Delay (Destination): 1.719ns (routing 0.696ns, distribution 1.023ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.364     2.279    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.909 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.214     3.123    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.147 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.677     4.824    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[4].u_ddr_mc_rd_en_low/rsMask_reg[6][9]_0
    SLICE_X81Y272        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[4].u_ddr_mc_rd_en_low/rdEn_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y272        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.059     4.883 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[4].u_ddr_mc_rd_en_low/rdEn_reg[3]/Q
                         net (fo=1, routed)           0.392     5.275    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/ch0_mcal_clb2phy_rden_low[3]
    BITSLICE_CONTROL_X0Y30
                         BITSLICE_CONTROL                             r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PHY_RDEN[3]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[0]_DIV rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.524     2.610    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.483 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.244     2.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.755 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.719     4.474    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y6             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -1.058     3.416 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[0].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.148     3.564    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y30
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_RX_DIV2_CLK_Q)
                                                      0.193     3.757 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y30
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_RX_DIV2_CLK_Q_RX_DIV4_CLK_Q)
                                                      0.119     3.876 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV4_CLK_Q
                         clock pessimism              0.331     4.207    
                         clock uncertainty            0.170     4.377    
    BITSLICE_CONTROL_X0Y30
                         BITSLICE_CONTROL (Hold_CONTROL_BITSLICE_CONTROL_RX_DIV4_CLK_Q_PHY_RDEN[3])
                                                      0.268     4.645    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control
  -------------------------------------------------------------------
                         required time                         -4.645    
                         arrival time                           5.275    
  -------------------------------------------------------------------
                         slack                                  0.630    

Slack (MET) :             0.658ns  (arrival time - required time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[4].u_ddr_mc_rd_en_upp/rdEn_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PHY_RDEN[1]
                            (rising edge-triggered cell BITSLICE_CONTROL clocked by pll_clk[0]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[0]_DIV
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (pll_clk[0]_DIV rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.315ns  (logic 0.059ns (18.730%)  route 0.256ns (81.270%))
  Logic Levels:           0  
  Clock Path Skew:        -0.702ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.846ns
    Source Clock Delay      (SCD):    4.816ns
    Clock Pessimism Removal (CPR):    -0.268ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.669ns (routing 0.630ns, distribution 1.039ns)
  Clock Net Delay (Destination): 1.719ns (routing 0.696ns, distribution 1.023ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.364     2.279    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.909 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.214     3.123    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.147 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.669     4.816    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[4].u_ddr_mc_rd_en_upp/rsMask_reg[7][9]_0
    SLICE_X84Y234        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[4].u_ddr_mc_rd_en_upp/rdEn_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X84Y234        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.059     4.875 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[4].u_ddr_mc_rd_en_upp/rdEn_reg[1]/Q
                         net (fo=1, routed)           0.256     5.131    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/ch0_mcal_clb2phy_rden_upp[1]
    BITSLICE_CONTROL_X0Y31
                         BITSLICE_CONTROL                             r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PHY_RDEN[1]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[0]_DIV rise edge)
                                                      0.000     0.000 f  
    J19                                               0.000     0.000 f  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.524     2.610    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.483 f  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.244     2.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.755 f  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.719     4.474    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y6             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -1.058     3.416 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[0].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.150     3.566    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y31
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_RX_DIV2_CLK_Q)
                                                      0.162     3.728 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y31
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_RX_DIV2_CLK_Q_RX_DIV4_CLK_Q)
                                                      0.118     3.846 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV4_CLK_Q
                         clock pessimism              0.268     4.113    
                         clock uncertainty            0.170     4.284    
    BITSLICE_CONTROL_X0Y31
                         BITSLICE_CONTROL (Hold_CONTROL_BITSLICE_CONTROL_RX_DIV4_CLK_Q_PHY_RDEN[1])
                                                      0.189     4.473    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control
  -------------------------------------------------------------------
                         required time                         -4.473    
                         arrival time                           5.131    
  -------------------------------------------------------------------
                         slack                                  0.658    

Slack (MET) :             0.668ns  (arrival time - required time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[6].u_ddr_mc_rd_en_low/rdEn_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PHY_RDEN[1]
                            (rising edge-triggered cell BITSLICE_CONTROL clocked by pll_clk[0]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[0]_DIV
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (pll_clk[0]_DIV rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.402ns  (logic 0.057ns (14.179%)  route 0.345ns (85.821%))
  Logic Levels:           0  
  Clock Path Skew:        -0.672ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.871ns
    Source Clock Delay      (SCD):    4.811ns
    Clock Pessimism Removal (CPR):    -0.268ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.664ns (routing 0.630ns, distribution 1.034ns)
  Clock Net Delay (Destination): 1.719ns (routing 0.696ns, distribution 1.023ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.364     2.279    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.909 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.214     3.123    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.147 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.664     4.811    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[6].u_ddr_mc_rd_en_low/rsMask_reg[7][12]_0
    SLICE_X86Y200        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[6].u_ddr_mc_rd_en_low/rdEn_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X86Y200        FDRE (Prop_FFF_SLICEM_C_Q)
                                                      0.057     4.868 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[6].u_ddr_mc_rd_en_low/rdEn_reg[1]/Q
                         net (fo=1, routed)           0.345     5.213    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/ch0_mcal_clb2phy_rden_low[1]
    BITSLICE_CONTROL_X0Y26
                         BITSLICE_CONTROL                             r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PHY_RDEN[1]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[0]_DIV rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.524     2.610    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.483 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.244     2.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.755 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.719     4.474    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y6             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -1.058     3.416 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[0].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.143     3.559    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y26
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_RX_DIV2_CLK_Q)
                                                      0.193     3.752 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y26
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_RX_DIV2_CLK_Q_RX_DIV4_CLK_Q)
                                                      0.119     3.871 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV4_CLK_Q
                         clock pessimism              0.268     4.138    
                         clock uncertainty            0.170     4.309    
    BITSLICE_CONTROL_X0Y26
                         BITSLICE_CONTROL (Hold_CONTROL_BITSLICE_CONTROL_RX_DIV4_CLK_Q_PHY_RDEN[1])
                                                      0.236     4.545    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control
  -------------------------------------------------------------------
                         required time                         -4.545    
                         arrival time                           5.213    
  -------------------------------------------------------------------
                         slack                                  0.668    

Slack (MET) :             0.672ns  (arrival time - required time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[6].u_ddr_mc_wr_byte/genBit[4].u_ddr_mc_wr_bit/dReg_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[0]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[0]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[0]_DIV
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (pll_clk[0]_DIV rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.395ns  (logic 0.059ns (14.937%)  route 0.336ns (85.063%))
  Logic Levels:           0  
  Clock Path Skew:        -0.492ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    4.053ns
    Source Clock Delay      (SCD):    4.812ns
    Clock Pessimism Removal (CPR):    -0.268ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.665ns (routing 0.630ns, distribution 1.035ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.364     2.279    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.909 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.214     3.123    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.147 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.665     4.812    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[6].u_ddr_mc_wr_byte/genBit[4].u_ddr_mc_wr_bit/dReg_reg[10]_0
    SLICE_X81Y194        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[6].u_ddr_mc_wr_byte/genBit[4].u_ddr_mc_wr_bit/dReg_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y194        FDRE (Prop_HFF2_SLICEL_C_Q)
                                                      0.059     4.871 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[6].u_ddr_mc_wr_byte/genBit[4].u_ddr_mc_wr_bit/dReg_reg[0]/Q
                         net (fo=1, routed)           0.336     5.207    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/ch0_mcal_DQOut[0]
    BITSLICE_RX_TX_X0Y173
                         RXTX_BITSLICE                                r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[0]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[0]_DIV rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.524     2.610    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.483 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.244     2.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.755 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=41385, routed)       1.719     4.474    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y6             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -1.058     3.416 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[0].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.143     3.559    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y26
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.177     3.736 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y26
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.109     3.845 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y26
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT4[26])
                                                      0.186     4.031 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT4[26]
                         net (fo=1, routed)           0.022     4.053    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/TX_BIT_CTRL_OUT4[26]
    BITSLICE_RX_TX_X0Y173
                         RXTX_BITSLICE                                r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism              0.268     4.320    
                         clock uncertainty            0.170     4.491    
    BITSLICE_RX_TX_X0Y173
                         RXTX_BITSLICE (Hold_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[0])
                                                      0.045     4.536    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                         -4.536    
                         arrival time                           5.207    
  -------------------------------------------------------------------
                         slack                                  0.672    

Slack (MET) :             0.672ns  (arrival time - required time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[6].u_ddr_mc_wr_byte/genBit[2].u_ddr_mc_wr_bit/dReg_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[0]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[0]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[0]_DIV
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (pll_clk[0]_DIV rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.404ns  (logic 0.059ns (14.604%)  route 0.345ns (85.396%))
  Logic Levels:           0  
  Clock Path Skew:        -0.490ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    4.053ns
    Source Clock Delay      (SCD):    4.811ns
    Clock Pessimism Removal (CPR):    -0.268ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.664ns (routing 0.630ns, distribution 1.034ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.364     2.279    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.909 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.214     3.123    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.147 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.664     4.811    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[6].u_ddr_mc_wr_byte/genBit[2].u_ddr_mc_wr_bit/dReg_reg[10]_0
    SLICE_X84Y199        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[6].u_ddr_mc_wr_byte/genBit[2].u_ddr_mc_wr_bit/dReg_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X84Y199        FDRE (Prop_CFF2_SLICEL_C_Q)
                                                      0.059     4.870 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[6].u_ddr_mc_wr_byte/genBit[2].u_ddr_mc_wr_bit/dReg_reg[0]/Q
                         net (fo=1, routed)           0.345     5.215    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/ch0_mcal_DQOut[0]
    BITSLICE_RX_TX_X0Y172
                         RXTX_BITSLICE                                r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[0]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[0]_DIV rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.524     2.610    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.483 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.244     2.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.755 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=41385, routed)       1.719     4.474    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y6             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -1.058     3.416 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[0].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.143     3.559    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y26
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.177     3.736 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y26
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.109     3.845 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y26
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT3[26])
                                                      0.187     4.032 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT3[26]
                         net (fo=1, routed)           0.021     4.053    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/TX_BIT_CTRL_OUT3[26]
    BITSLICE_RX_TX_X0Y172
                         RXTX_BITSLICE                                r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism              0.268     4.320    
                         clock uncertainty            0.170     4.491    
    BITSLICE_RX_TX_X0Y172
                         RXTX_BITSLICE (Hold_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[0])
                                                      0.052     4.543    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                         -4.543    
                         arrival time                           5.215    
  -------------------------------------------------------------------
                         slack                                  0.672    

Slack (MET) :             0.675ns  (arrival time - required time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[4].u_ddr_mc_wr_byte/genBit[1].u_ddr_mc_wr_bit/dReg_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/D[0]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[0]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[0]_DIV
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (pll_clk[0]_DIV rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.382ns  (logic 0.057ns (14.921%)  route 0.325ns (85.078%))
  Logic Levels:           0  
  Clock Path Skew:        -0.523ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    4.028ns
    Source Clock Delay      (SCD):    4.819ns
    Clock Pessimism Removal (CPR):    -0.268ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.672ns (routing 0.630ns, distribution 1.042ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.364     2.279    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.909 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.214     3.123    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.147 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.672     4.819    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[4].u_ddr_mc_wr_byte/genBit[1].u_ddr_mc_wr_bit/dReg_reg[10]_0
    SLICE_X83Y235        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[4].u_ddr_mc_wr_byte/genBit[1].u_ddr_mc_wr_bit/dReg_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X83Y235        FDRE (Prop_FFF_SLICEM_C_Q)
                                                      0.057     4.876 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[4].u_ddr_mc_wr_byte/genBit[1].u_ddr_mc_wr_bit/dReg_reg[0]/Q
                         net (fo=1, routed)           0.325     5.201    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/ch0_mcal_DQOut[0]
    BITSLICE_RX_TX_X0Y205
                         RXTX_BITSLICE                                r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/D[0]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[0]_DIV rise edge)
                                                      0.000     0.000 f  
    J19                                               0.000     0.000 f  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.524     2.610    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.483 f  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.244     2.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.755 f  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=41385, routed)       1.719     4.474    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y6             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -1.058     3.416 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[0].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.150     3.566    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y31
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.151     3.717 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y31
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.109     3.826 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y31
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT4[26])
                                                      0.180     4.006 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT4[26]
                         net (fo=1, routed)           0.022     4.028    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/TX_BIT_CTRL_OUT4[26]
    BITSLICE_RX_TX_X0Y205
                         RXTX_BITSLICE                                r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism              0.268     4.295    
                         clock uncertainty            0.170     4.466    
    BITSLICE_RX_TX_X0Y205
                         RXTX_BITSLICE (Hold_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[0])
                                                      0.060     4.526    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                         -4.526    
                         arrival time                           5.201    
  -------------------------------------------------------------------
                         slack                                  0.675    

Slack (MET) :             0.700ns  (arrival time - required time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[4].u_ddr_mc_wr_byte/genBit[0].u_ddr_mc_wr_bit/dReg_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[1]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[0]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[0]_DIV
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (pll_clk[0]_DIV rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.431ns  (logic 0.059ns (13.689%)  route 0.372ns (86.311%))
  Logic Levels:           0  
  Clock Path Skew:        -0.474ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    4.066ns
    Source Clock Delay      (SCD):    4.807ns
    Clock Pessimism Removal (CPR):    -0.268ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.660ns (routing 0.630ns, distribution 1.030ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.364     2.279    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.909 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.214     3.123    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.147 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.660     4.807    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[4].u_ddr_mc_wr_byte/genBit[0].u_ddr_mc_wr_bit/dReg_reg[10]_0
    SLICE_X81Y224        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[4].u_ddr_mc_wr_byte/genBit[0].u_ddr_mc_wr_bit/dReg_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y224        FDRE (Prop_GFF_SLICEL_C_Q)
                                                      0.059     4.866 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[4].u_ddr_mc_wr_byte/genBit[0].u_ddr_mc_wr_bit/dReg_reg[1]/Q
                         net (fo=1, routed)           0.372     5.238    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/ch0_mcal_DQOut[1]
    BITSLICE_RX_TX_X0Y200
                         RXTX_BITSLICE                                r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[1]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[0]_DIV rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.524     2.610    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.483 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.244     2.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.755 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=41385, routed)       1.719     4.474    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y6             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -1.058     3.416 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[0].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.148     3.564    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y30
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.177     3.741 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y30
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.109     3.850 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y30
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT5[26])
                                                      0.192     4.042 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT5[26]
                         net (fo=1, routed)           0.024     4.066    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/TX_BIT_CTRL_OUT5[26]
    BITSLICE_RX_TX_X0Y200
                         RXTX_BITSLICE                                r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism              0.268     4.333    
                         clock uncertainty            0.170     4.504    
    BITSLICE_RX_TX_X0Y200
                         RXTX_BITSLICE (Hold_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[1])
                                                      0.035     4.539    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                         -4.539    
                         arrival time                           5.238    
  -------------------------------------------------------------------
                         slack                                  0.700    

Slack (MET) :             0.705ns  (arrival time - required time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[6].u_ddr_mc_wr_byte/genBit[2].u_ddr_mc_wr_bit/dReg_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[1]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[0]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[0]_DIV
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (pll_clk[0]_DIV rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.440ns  (logic 0.058ns (13.182%)  route 0.382ns (86.818%))
  Logic Levels:           0  
  Clock Path Skew:        -0.486ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    4.053ns
    Source Clock Delay      (SCD):    4.807ns
    Clock Pessimism Removal (CPR):    -0.268ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.660ns (routing 0.630ns, distribution 1.030ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.364     2.279    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.909 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.214     3.123    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.147 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.660     4.807    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[6].u_ddr_mc_wr_byte/genBit[2].u_ddr_mc_wr_bit/dReg_reg[10]_0
    SLICE_X85Y199        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[6].u_ddr_mc_wr_byte/genBit[2].u_ddr_mc_wr_bit/dReg_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X85Y199        FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.058     4.865 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[6].u_ddr_mc_wr_byte/genBit[2].u_ddr_mc_wr_bit/dReg_reg[1]/Q
                         net (fo=1, routed)           0.382     5.247    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/ch0_mcal_DQOut[1]
    BITSLICE_RX_TX_X0Y172
                         RXTX_BITSLICE                                r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[1]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[0]_DIV rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.524     2.610    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.483 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.244     2.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.755 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=41385, routed)       1.719     4.474    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y6             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -1.058     3.416 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[0].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.143     3.559    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y26
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.177     3.736 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y26
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.109     3.845 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y26
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT3[26])
                                                      0.187     4.032 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT3[26]
                         net (fo=1, routed)           0.021     4.053    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/TX_BIT_CTRL_OUT3[26]
    BITSLICE_RX_TX_X0Y172
                         RXTX_BITSLICE                                r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism              0.268     4.320    
                         clock uncertainty            0.170     4.491    
    BITSLICE_RX_TX_X0Y172
                         RXTX_BITSLICE (Hold_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[1])
                                                      0.051     4.542    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                         -4.542    
                         arrival time                           5.247    
  -------------------------------------------------------------------
                         slack                                  0.705    





---------------------------------------------------------------------------------------------------
From Clock:  mmcm_clkout0
  To Clock:  pll_clk[1]_DIV

Setup :            0  Failing Endpoints,  Worst Slack        0.695ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.504ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.695ns  (required time - arrival time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[2].u_ddr_mc_wr_byte/genBit[6].u_ddr_mc_wr_bit/dReg_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/D[2]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[1]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[1]_DIV
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (pll_clk[1]_DIV rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        1.686ns  (logic 0.079ns (4.686%)  route 1.607ns (95.314%))
  Logic Levels:           0  
  Clock Path Skew:        -0.428ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.512ns = ( 7.513 - 3.001 ) 
    Source Clock Delay      (SCD):    4.676ns
    Clock Pessimism Removal (CPR):    -0.264ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.921ns (routing 0.696ns, distribution 1.225ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.524     2.610    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.483 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.244     2.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.755 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.921     4.676    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[2].u_ddr_mc_wr_byte/genBit[6].u_ddr_mc_wr_bit/dReg_reg[10]_0
    SLICE_X88Y262        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[2].u_ddr_mc_wr_byte/genBit[6].u_ddr_mc_wr_bit/dReg_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X88Y262        FDRE (Prop_GFF_SLICEL_C_Q)
                                                      0.079     4.755 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[2].u_ddr_mc_wr_byte/genBit[6].u_ddr_mc_wr_bit/dReg_reg[2]/Q
                         net (fo=1, routed)           1.607     6.362    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/ch0_mcal_DQOut[2]
    BITSLICE_RX_TX_X0Y230
                         RXTX_BITSLICE                                r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/D[2]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[1]_DIV rise edge)
                                                      3.001     3.001 r  
    J19                                               0.000     3.001 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.555 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.595    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.595 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     3.892    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.916 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.364     5.280    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.910 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.214     6.124    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     6.148 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=41385, routed)       1.583     7.731    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y8             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -0.630     7.101 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[1].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.097     7.198    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y35
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.106     7.304 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y35
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.075     7.379 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y35
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT3[26])
                                                      0.122     7.501 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT3[26]
                         net (fo=1, routed)           0.012     7.513    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/TX_BIT_CTRL_OUT3[26]
    BITSLICE_RX_TX_X0Y230
                         RXTX_BITSLICE                                r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism             -0.264     7.249    
                         clock uncertainty           -0.170     7.079    
    BITSLICE_RX_TX_X0Y230
                         RXTX_BITSLICE (Setup_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[2])
                                                     -0.022     7.057    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                          7.057    
                         arrival time                          -6.362    
  -------------------------------------------------------------------
                         slack                                  0.695    

Slack (MET) :             0.702ns  (required time - arrival time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[2].u_ddr_mc_wr_byte/u_ddr_mc_wr_dm/dReg_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[2]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[1]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[1]_DIV
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (pll_clk[1]_DIV rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        1.596ns  (logic 0.078ns (4.887%)  route 1.518ns (95.113%))
  Logic Levels:           0  
  Clock Path Skew:        -0.464ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.515ns = ( 7.516 - 3.001 ) 
    Source Clock Delay      (SCD):    4.648ns
    Clock Pessimism Removal (CPR):    -0.331ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.893ns (routing 0.696ns, distribution 1.197ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.524     2.610    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.483 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.244     2.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.755 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.893     4.648    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[2].u_ddr_mc_wr_byte/u_ddr_mc_wr_dm/dReg_reg[10]_0
    SLICE_X94Y210        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[2].u_ddr_mc_wr_byte/u_ddr_mc_wr_dm/dReg_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X94Y210        FDRE (Prop_DFF_SLICEM_C_Q)
                                                      0.078     4.726 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[2].u_ddr_mc_wr_byte/u_ddr_mc_wr_dm/dReg_reg[2]/Q
                         net (fo=1, routed)           1.518     6.244    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/clb2phy_wr_dq0[2]
    BITSLICE_RX_TX_X0Y221
                         RXTX_BITSLICE                                r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[2]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[1]_DIV rise edge)
                                                      3.001     3.001 f  
    J19                                               0.000     3.001 f  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.555 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.595    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.595 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     3.892    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.916 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.364     5.280    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.910 f  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.214     6.124    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     6.148 f  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=41385, routed)       1.583     7.731    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y8             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -0.630     7.101 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[1].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.100     7.201    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y34
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.117     7.318 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y34
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.075     7.393 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y34
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT0[26])
                                                      0.109     7.502 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT0[26]
                         net (fo=1, routed)           0.014     7.516    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/TX_BIT_CTRL_OUT0[26]
    BITSLICE_RX_TX_X0Y221
                         RXTX_BITSLICE                                r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism             -0.331     7.185    
                         clock uncertainty           -0.170     7.014    
    BITSLICE_RX_TX_X0Y221
                         RXTX_BITSLICE (Setup_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[2])
                                                     -0.069     6.945    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                          6.945    
                         arrival time                          -6.244    
  -------------------------------------------------------------------
                         slack                                  0.702    

Slack (MET) :             0.704ns  (required time - arrival time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[0].u_ddr_mc_wr_byte/u_ddr_mc_wr_dm/dReg_reg[7]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[7]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[1]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[1]_DIV
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (pll_clk[1]_DIV rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        1.644ns  (logic 0.078ns (4.745%)  route 1.566ns (95.255%))
  Logic Levels:           0  
  Clock Path Skew:        -0.434ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.514ns = ( 7.515 - 3.001 ) 
    Source Clock Delay      (SCD):    4.617ns
    Clock Pessimism Removal (CPR):    -0.331ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.862ns (routing 0.696ns, distribution 1.166ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.524     2.610    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.483 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.244     2.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.755 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.862     4.617    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[0].u_ddr_mc_wr_byte/u_ddr_mc_wr_dm/dReg_reg[10]_0
    SLICE_X93Y211        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[0].u_ddr_mc_wr_byte/u_ddr_mc_wr_dm/dReg_reg[7]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X93Y211        FDRE (Prop_BFF_SLICEM_C_Q)
                                                      0.078     4.695 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[0].u_ddr_mc_wr_byte/u_ddr_mc_wr_dm/dReg_reg[7]/Q
                         net (fo=1, routed)           1.566     6.261    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/clb2phy_wr_dq0[7]
    BITSLICE_RX_TX_X0Y234
                         RXTX_BITSLICE                                r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[7]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[1]_DIV rise edge)
                                                      3.001     3.001 r  
    J19                                               0.000     3.001 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.555 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.595    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.595 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     3.892    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.916 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.364     5.280    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.910 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.214     6.124    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     6.148 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=41385, routed)       1.583     7.731    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y8             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -0.630     7.101 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[1].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.099     7.200    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y36
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.117     7.317 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y36
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.075     7.392 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y36
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT0[26])
                                                      0.109     7.501 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT0[26]
                         net (fo=1, routed)           0.014     7.515    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/TX_BIT_CTRL_OUT0[26]
    BITSLICE_RX_TX_X0Y234
                         RXTX_BITSLICE                                r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism             -0.331     7.184    
                         clock uncertainty           -0.170     7.013    
    BITSLICE_RX_TX_X0Y234
                         RXTX_BITSLICE (Setup_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[7])
                                                     -0.049     6.964    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                          6.964    
                         arrival time                          -6.261    
  -------------------------------------------------------------------
                         slack                                  0.704    

Slack (MET) :             0.706ns  (required time - arrival time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[0].u_ddr_mc_wr_byte/genBit[7].u_ddr_mc_wr_bit/dReg_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[3]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[1]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[1]_DIV
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (pll_clk[1]_DIV rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        1.640ns  (logic 0.079ns (4.817%)  route 1.561ns (95.183%))
  Logic Levels:           0  
  Clock Path Skew:        -0.450ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.533ns = ( 7.534 - 3.001 ) 
    Source Clock Delay      (SCD):    4.652ns
    Clock Pessimism Removal (CPR):    -0.331ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.897ns (routing 0.696ns, distribution 1.201ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.524     2.610    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.483 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.244     2.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.755 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.897     4.652    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[0].u_ddr_mc_wr_byte/genBit[7].u_ddr_mc_wr_bit/dReg_reg[10]_0
    SLICE_X88Y226        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[0].u_ddr_mc_wr_byte/genBit[7].u_ddr_mc_wr_bit/dReg_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X88Y226        FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.079     4.731 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[0].u_ddr_mc_wr_byte/genBit[7].u_ddr_mc_wr_bit/dReg_reg[3]/Q
                         net (fo=1, routed)           1.561     6.292    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/ch0_mcal_DQOut[3]
    BITSLICE_RX_TX_X0Y236
                         RXTX_BITSLICE                                r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[3]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[1]_DIV rise edge)
                                                      3.001     3.001 r  
    J19                                               0.000     3.001 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.555 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.595    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.595 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     3.892    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.916 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.364     5.280    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.910 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.214     6.124    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     6.148 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=41385, routed)       1.583     7.731    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y8             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -0.630     7.101 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[1].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.099     7.200    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y36
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.117     7.317 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y36
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.075     7.392 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y36
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT2[26])
                                                      0.129     7.521 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT2[26]
                         net (fo=1, routed)           0.013     7.534    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/TX_BIT_CTRL_OUT2[26]
    BITSLICE_RX_TX_X0Y236
                         RXTX_BITSLICE                                r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism             -0.331     7.203    
                         clock uncertainty           -0.170     7.032    
    BITSLICE_RX_TX_X0Y236
                         RXTX_BITSLICE (Setup_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[3])
                                                     -0.035     6.997    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                          6.997    
                         arrival time                          -6.292    
  -------------------------------------------------------------------
                         slack                                  0.706    

Slack (MET) :             0.707ns  (required time - arrival time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[1].u_ddr_mc_wr_byte/genBit[2].u_ddr_mc_wr_bit/dReg_reg[6]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/D[6]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[1]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[1]_DIV
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (pll_clk[1]_DIV rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        1.678ns  (logic 0.078ns (4.648%)  route 1.600ns (95.352%))
  Logic Levels:           0  
  Clock Path Skew:        -0.420ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.523ns = ( 7.524 - 3.001 ) 
    Source Clock Delay      (SCD):    4.679ns
    Clock Pessimism Removal (CPR):    -0.264ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.924ns (routing 0.696ns, distribution 1.228ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.524     2.610    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.483 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.244     2.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.755 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.924     4.679    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[1].u_ddr_mc_wr_byte/genBit[2].u_ddr_mc_wr_bit/dReg_reg[10]_0
    SLICE_X82Y244        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[1].u_ddr_mc_wr_byte/genBit[2].u_ddr_mc_wr_bit/dReg_reg[6]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X82Y244        FDRE (Prop_DFF_SLICEM_C_Q)
                                                      0.078     4.757 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[1].u_ddr_mc_wr_byte/genBit[2].u_ddr_mc_wr_bit/dReg_reg[6]/Q
                         net (fo=1, routed)           1.600     6.357    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/ch0_mcal_DQOut[6]
    BITSLICE_RX_TX_X0Y255
                         RXTX_BITSLICE                                r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/D[6]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[1]_DIV rise edge)
                                                      3.001     3.001 f  
    J19                                               0.000     3.001 f  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.555 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.595    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.595 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     3.892    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.916 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.364     5.280    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.910 f  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.214     6.124    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     6.148 f  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=41385, routed)       1.583     7.731    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y8             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -0.630     7.101 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[1].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.105     7.206    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y39
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.106     7.312 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y39
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.075     7.387 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y39
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT2[26])
                                                      0.124     7.511 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT2[26]
                         net (fo=1, routed)           0.013     7.524    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/TX_BIT_CTRL_OUT2[26]
    BITSLICE_RX_TX_X0Y255
                         RXTX_BITSLICE                                r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism             -0.264     7.260    
                         clock uncertainty           -0.170     7.090    
    BITSLICE_RX_TX_X0Y255
                         RXTX_BITSLICE (Setup_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[6])
                                                     -0.026     7.064    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                          7.064    
                         arrival time                          -6.357    
  -------------------------------------------------------------------
                         slack                                  0.707    

Slack (MET) :             0.710ns  (required time - arrival time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[2].u_ddr_mc_wr_byte/genBit[1].u_ddr_mc_wr_bit/dReg_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/D[3]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[1]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[1]_DIV
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (pll_clk[1]_DIV rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        1.653ns  (logic 0.079ns (4.779%)  route 1.574ns (95.221%))
  Logic Levels:           0  
  Clock Path Skew:        -0.443ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.515ns = ( 7.516 - 3.001 ) 
    Source Clock Delay      (SCD):    4.694ns
    Clock Pessimism Removal (CPR):    -0.264ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.939ns (routing 0.696ns, distribution 1.243ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.524     2.610    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.483 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.244     2.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.755 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.939     4.694    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[2].u_ddr_mc_wr_byte/genBit[1].u_ddr_mc_wr_bit/dReg_reg[10]_0
    SLICE_X84Y256        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[2].u_ddr_mc_wr_byte/genBit[1].u_ddr_mc_wr_bit/dReg_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X84Y256        FDRE (Prop_GFF_SLICEL_C_Q)
                                                      0.079     4.773 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[2].u_ddr_mc_wr_byte/genBit[1].u_ddr_mc_wr_bit/dReg_reg[3]/Q
                         net (fo=1, routed)           1.574     6.347    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/ch0_mcal_DQOut[3]
    BITSLICE_RX_TX_X0Y229
                         RXTX_BITSLICE                                r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/D[3]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[1]_DIV rise edge)
                                                      3.001     3.001 r  
    J19                                               0.000     3.001 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.555 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.595    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.595 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     3.892    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.916 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.364     5.280    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.910 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.214     6.124    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     6.148 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=41385, routed)       1.583     7.731    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y8             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -0.630     7.101 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[1].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.097     7.198    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y35
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.106     7.304 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y35
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.075     7.379 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y35
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT2[26])
                                                      0.124     7.503 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT2[26]
                         net (fo=1, routed)           0.013     7.516    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/TX_BIT_CTRL_OUT2[26]
    BITSLICE_RX_TX_X0Y229
                         RXTX_BITSLICE                                r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism             -0.264     7.252    
                         clock uncertainty           -0.170     7.082    
    BITSLICE_RX_TX_X0Y229
                         RXTX_BITSLICE (Setup_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[3])
                                                     -0.025     7.057    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                          7.057    
                         arrival time                          -6.347    
  -------------------------------------------------------------------
                         slack                                  0.710    

Slack (MET) :             0.719ns  (required time - arrival time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[1].u_ddr_mc_wr_byte/genBit[6].u_ddr_mc_wr_bit/dReg_reg[6]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/D[6]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[1]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[1]_DIV
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (pll_clk[1]_DIV rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        1.631ns  (logic 0.076ns (4.660%)  route 1.555ns (95.340%))
  Logic Levels:           0  
  Clock Path Skew:        -0.463ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.520ns = ( 7.521 - 3.001 ) 
    Source Clock Delay      (SCD):    4.652ns
    Clock Pessimism Removal (CPR):    -0.331ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.897ns (routing 0.696ns, distribution 1.201ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.524     2.610    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.483 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.244     2.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.755 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.897     4.652    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[1].u_ddr_mc_wr_byte/genBit[6].u_ddr_mc_wr_bit/dReg_reg[10]_0
    SLICE_X83Y237        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[1].u_ddr_mc_wr_byte/genBit[6].u_ddr_mc_wr_bit/dReg_reg[6]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X83Y237        FDRE (Prop_FFF_SLICEM_C_Q)
                                                      0.076     4.728 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[1].u_ddr_mc_wr_byte/genBit[6].u_ddr_mc_wr_bit/dReg_reg[6]/Q
                         net (fo=1, routed)           1.555     6.283    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/ch0_mcal_DQOut[6]
    BITSLICE_RX_TX_X0Y256
                         RXTX_BITSLICE                                r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/D[6]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[1]_DIV rise edge)
                                                      3.001     3.001 f  
    J19                                               0.000     3.001 f  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.555 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.595    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.595 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     3.892    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.916 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.364     5.280    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.910 f  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.214     6.124    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     6.148 f  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=41385, routed)       1.583     7.731    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y8             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -0.630     7.101 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[1].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.105     7.206    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y39
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.106     7.312 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y39
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.075     7.387 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y39
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT3[26])
                                                      0.122     7.509 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT3[26]
                         net (fo=1, routed)           0.012     7.521    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/TX_BIT_CTRL_OUT3[26]
    BITSLICE_RX_TX_X0Y256
                         RXTX_BITSLICE                                r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism             -0.331     7.190    
                         clock uncertainty           -0.170     7.019    
    BITSLICE_RX_TX_X0Y256
                         RXTX_BITSLICE (Setup_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[6])
                                                     -0.018     7.001    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                          7.001    
                         arrival time                          -6.283    
  -------------------------------------------------------------------
                         slack                                  0.719    

Slack (MET) :             0.720ns  (required time - arrival time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[2].u_ddr_mc_wr_byte/genBit[7].u_ddr_mc_wr_bit/dReg_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/D[3]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[1]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[1]_DIV
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (pll_clk[1]_DIV rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        1.646ns  (logic 0.079ns (4.800%)  route 1.567ns (95.201%))
  Logic Levels:           0  
  Clock Path Skew:        -0.443ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.516ns = ( 7.517 - 3.001 ) 
    Source Clock Delay      (SCD):    4.628ns
    Clock Pessimism Removal (CPR):    -0.331ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.873ns (routing 0.696ns, distribution 1.177ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.524     2.610    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.483 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.244     2.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.755 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.873     4.628    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[2].u_ddr_mc_wr_byte/genBit[7].u_ddr_mc_wr_bit/dReg_reg[10]_0
    SLICE_X85Y230        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[2].u_ddr_mc_wr_byte/genBit[7].u_ddr_mc_wr_bit/dReg_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X85Y230        FDRE (Prop_CFF_SLICEL_C_Q)
                                                      0.079     4.707 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[2].u_ddr_mc_wr_byte/genBit[7].u_ddr_mc_wr_bit/dReg_reg[3]/Q
                         net (fo=1, routed)           1.567     6.274    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/ch0_mcal_DQOut[3]
    BITSLICE_RX_TX_X0Y231
                         RXTX_BITSLICE                                r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/D[3]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[1]_DIV rise edge)
                                                      3.001     3.001 r  
    J19                                               0.000     3.001 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.555 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.595    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.595 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     3.892    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.916 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.364     5.280    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.910 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.214     6.124    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     6.148 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=41385, routed)       1.583     7.731    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y8             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -0.630     7.101 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[1].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.097     7.198    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y35
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.106     7.304 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y35
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.075     7.379 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y35
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT4[26])
                                                      0.125     7.504 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT4[26]
                         net (fo=1, routed)           0.013     7.517    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/TX_BIT_CTRL_OUT4[26]
    BITSLICE_RX_TX_X0Y231
                         RXTX_BITSLICE                                r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism             -0.331     7.186    
                         clock uncertainty           -0.170     7.015    
    BITSLICE_RX_TX_X0Y231
                         RXTX_BITSLICE (Setup_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[3])
                                                     -0.022     6.993    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                          6.993    
                         arrival time                          -6.274    
  -------------------------------------------------------------------
                         slack                                  0.720    

Slack (MET) :             0.720ns  (required time - arrival time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[2].u_ddr_mc_wr_byte/genBit[5].u_ddr_mc_wr_bit/dReg_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[2]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[1]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[1]_DIV
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (pll_clk[1]_DIV rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        1.641ns  (logic 0.079ns (4.814%)  route 1.562ns (95.186%))
  Logic Levels:           0  
  Clock Path Skew:        -0.398ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.538ns = ( 7.539 - 3.001 ) 
    Source Clock Delay      (SCD):    4.672ns
    Clock Pessimism Removal (CPR):    -0.264ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.917ns (routing 0.696ns, distribution 1.221ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.524     2.610    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.483 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.244     2.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.755 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.917     4.672    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[2].u_ddr_mc_wr_byte/genBit[5].u_ddr_mc_wr_bit/dReg_reg[10]_0
    SLICE_X88Y261        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[2].u_ddr_mc_wr_byte/genBit[5].u_ddr_mc_wr_bit/dReg_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X88Y261        FDRE (Prop_CFF_SLICEL_C_Q)
                                                      0.079     4.751 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[2].u_ddr_mc_wr_byte/genBit[5].u_ddr_mc_wr_bit/dReg_reg[2]/Q
                         net (fo=1, routed)           1.562     6.313    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/ch0_mcal_DQOut[2]
    BITSLICE_RX_TX_X0Y226
                         RXTX_BITSLICE                                r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[2]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[1]_DIV rise edge)
                                                      3.001     3.001 f  
    J19                                               0.000     3.001 f  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.555 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.595    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.595 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     3.892    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.916 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.364     5.280    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.910 f  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.214     6.124    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     6.148 f  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=41385, routed)       1.583     7.731    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y8             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -0.630     7.101 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[1].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.100     7.201    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y34
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.117     7.318 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y34
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.075     7.393 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y34
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT5[26])
                                                      0.131     7.524 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT5[26]
                         net (fo=1, routed)           0.015     7.539    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/TX_BIT_CTRL_OUT5[26]
    BITSLICE_RX_TX_X0Y226
                         RXTX_BITSLICE                                r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism             -0.264     7.275    
                         clock uncertainty           -0.170     7.105    
    BITSLICE_RX_TX_X0Y226
                         RXTX_BITSLICE (Setup_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[2])
                                                     -0.072     7.033    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                          7.033    
                         arrival time                          -6.313    
  -------------------------------------------------------------------
                         slack                                  0.720    

Slack (MET) :             0.743ns  (required time - arrival time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[0].u_ddr_mc_wr_byte/u_ddr_mc_wr_dm/dReg_reg[5]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[5]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[1]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[1]_DIV
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (pll_clk[1]_DIV rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        1.608ns  (logic 0.078ns (4.851%)  route 1.530ns (95.149%))
  Logic Levels:           0  
  Clock Path Skew:        -0.453ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.514ns = ( 7.515 - 3.001 ) 
    Source Clock Delay      (SCD):    4.636ns
    Clock Pessimism Removal (CPR):    -0.331ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.881ns (routing 0.696ns, distribution 1.185ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.524     2.610    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.483 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.244     2.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.755 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.881     4.636    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[0].u_ddr_mc_wr_byte/u_ddr_mc_wr_dm/dReg_reg[10]_0
    SLICE_X93Y208        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[0].u_ddr_mc_wr_byte/u_ddr_mc_wr_dm/dReg_reg[5]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X93Y208        FDRE (Prop_BFF_SLICEM_C_Q)
                                                      0.078     4.714 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[0].u_ddr_mc_wr_byte/u_ddr_mc_wr_dm/dReg_reg[5]/Q
                         net (fo=1, routed)           1.530     6.244    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/clb2phy_wr_dq0[5]
    BITSLICE_RX_TX_X0Y234
                         RXTX_BITSLICE                                r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[5]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[1]_DIV rise edge)
                                                      3.001     3.001 r  
    J19                                               0.000     3.001 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.555 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.595    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.595 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     3.892    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.916 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.364     5.280    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.910 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.214     6.124    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     6.148 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=41385, routed)       1.583     7.731    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y8             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -0.630     7.101 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[1].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.099     7.200    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y36
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.117     7.317 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y36
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.075     7.392 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y36
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT0[26])
                                                      0.109     7.501 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT0[26]
                         net (fo=1, routed)           0.014     7.515    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/TX_BIT_CTRL_OUT0[26]
    BITSLICE_RX_TX_X0Y234
                         RXTX_BITSLICE                                r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism             -0.331     7.184    
                         clock uncertainty           -0.170     7.013    
    BITSLICE_RX_TX_X0Y234
                         RXTX_BITSLICE (Setup_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[5])
                                                     -0.026     6.987    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                          6.987    
                         arrival time                          -6.244    
  -------------------------------------------------------------------
                         slack                                  0.743    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.504ns  (arrival time - required time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[1].u_ddr_mc_rd_en_low/rdEn_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PHY_RDEN[3]
                            (rising edge-triggered cell BITSLICE_CONTROL clocked by pll_clk[1]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[1]_DIV
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (pll_clk[1]_DIV rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.272ns  (logic 0.058ns (21.324%)  route 0.214ns (78.677%))
  Logic Levels:           0  
  Clock Path Skew:        -0.670ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.921ns
    Source Clock Delay      (SCD):    4.854ns
    Clock Pessimism Removal (CPR):    -0.264ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.707ns (routing 0.630ns, distribution 1.077ns)
  Clock Net Delay (Destination): 1.764ns (routing 0.696ns, distribution 1.068ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.364     2.279    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.909 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.214     3.123    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.147 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.707     4.854    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[1].u_ddr_mc_rd_en_low/rsMask_reg[7][9]_0
    SLICE_X81Y294        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[1].u_ddr_mc_rd_en_low/rdEn_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y294        FDRE (Prop_HFF_SLICEL_C_Q)
                                                      0.058     4.912 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[1].u_ddr_mc_rd_en_low/rdEn_reg[3]/Q
                         net (fo=1, routed)           0.214     5.126    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/ch0_mcal_clb2phy_rden_low[3]
    BITSLICE_CONTROL_X0Y38
                         BITSLICE_CONTROL                             r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PHY_RDEN[3]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[1]_DIV rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.524     2.610    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.483 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.244     2.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.755 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.764     4.519    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y8             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -1.058     3.461 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[1].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.148     3.609    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y38
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_RX_DIV2_CLK_Q)
                                                      0.193     3.802 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y38
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_RX_DIV2_CLK_Q_RX_DIV4_CLK_Q)
                                                      0.119     3.921 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV4_CLK_Q
                         clock pessimism              0.264     4.184    
                         clock uncertainty            0.170     4.355    
    BITSLICE_CONTROL_X0Y38
                         BITSLICE_CONTROL (Hold_CONTROL_BITSLICE_CONTROL_RX_DIV4_CLK_Q_PHY_RDEN[3])
                                                      0.268     4.623    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control
  -------------------------------------------------------------------
                         required time                         -4.623    
                         arrival time                           5.126    
  -------------------------------------------------------------------
                         slack                                  0.504    

Slack (MET) :             0.504ns  (arrival time - required time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[1].u_ddr_mc_rd_en_low/rdEn_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PHY_RDEN[0]
                            (rising edge-triggered cell BITSLICE_CONTROL clocked by pll_clk[1]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[1]_DIV
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (pll_clk[1]_DIV rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.273ns  (logic 0.058ns (21.245%)  route 0.215ns (78.755%))
  Logic Levels:           0  
  Clock Path Skew:        -0.668ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.921ns
    Source Clock Delay      (SCD):    4.852ns
    Clock Pessimism Removal (CPR):    -0.264ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.705ns (routing 0.630ns, distribution 1.075ns)
  Clock Net Delay (Destination): 1.764ns (routing 0.696ns, distribution 1.068ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.364     2.279    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.909 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.214     3.123    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.147 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.705     4.852    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[1].u_ddr_mc_rd_en_low/rsMask_reg[7][9]_0
    SLICE_X81Y294        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[1].u_ddr_mc_rd_en_low/rdEn_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y294        FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.058     4.910 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[1].u_ddr_mc_rd_en_low/rdEn_reg[0]/Q
                         net (fo=1, routed)           0.215     5.125    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/ch0_mcal_clb2phy_rden_low[0]
    BITSLICE_CONTROL_X0Y38
                         BITSLICE_CONTROL                             r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PHY_RDEN[0]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[1]_DIV rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.524     2.610    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.483 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.244     2.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.755 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.764     4.519    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y8             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -1.058     3.461 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[1].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.148     3.609    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y38
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_RX_DIV2_CLK_Q)
                                                      0.193     3.802 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y38
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_RX_DIV2_CLK_Q_RX_DIV4_CLK_Q)
                                                      0.119     3.921 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV4_CLK_Q
                         clock pessimism              0.264     4.184    
                         clock uncertainty            0.170     4.355    
    BITSLICE_CONTROL_X0Y38
                         BITSLICE_CONTROL (Hold_CONTROL_BITSLICE_CONTROL_RX_DIV4_CLK_Q_PHY_RDEN[0])
                                                      0.267     4.622    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control
  -------------------------------------------------------------------
                         required time                         -4.622    
                         arrival time                           5.125    
  -------------------------------------------------------------------
                         slack                                  0.504    

Slack (MET) :             0.537ns  (arrival time - required time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[0].u_ddr_mc_rd_en_low/rdEn_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PHY_RDEN[3]
                            (rising edge-triggered cell BITSLICE_CONTROL clocked by pll_clk[1]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[1]_DIV
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (pll_clk[1]_DIV rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.302ns  (logic 0.059ns (19.536%)  route 0.243ns (80.464%))
  Logic Levels:           0  
  Clock Path Skew:        -0.673ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.914ns
    Source Clock Delay      (SCD):    4.850ns
    Clock Pessimism Removal (CPR):    -0.264ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.703ns (routing 0.630ns, distribution 1.073ns)
  Clock Net Delay (Destination): 1.764ns (routing 0.696ns, distribution 1.068ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.364     2.279    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.909 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.214     3.123    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.147 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.703     4.850    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[0].u_ddr_mc_rd_en_low/rsMask_reg[7][9]_0
    SLICE_X81Y290        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[0].u_ddr_mc_rd_en_low/rdEn_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y290        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.059     4.909 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[0].u_ddr_mc_rd_en_low/rdEn_reg[3]/Q
                         net (fo=1, routed)           0.243     5.152    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/ch0_mcal_clb2phy_rden_low[3]
    BITSLICE_CONTROL_X0Y36
                         BITSLICE_CONTROL                             r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PHY_RDEN[3]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[1]_DIV rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.524     2.610    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.483 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.244     2.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.755 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.764     4.519    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y8             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -1.058     3.461 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[1].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.141     3.602    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y36
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_RX_DIV2_CLK_Q)
                                                      0.193     3.795 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y36
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_RX_DIV2_CLK_Q_RX_DIV4_CLK_Q)
                                                      0.119     3.914 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV4_CLK_Q
                         clock pessimism              0.264     4.177    
                         clock uncertainty            0.170     4.348    
    BITSLICE_CONTROL_X0Y36
                         BITSLICE_CONTROL (Hold_CONTROL_BITSLICE_CONTROL_RX_DIV4_CLK_Q_PHY_RDEN[3])
                                                      0.268     4.616    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control
  -------------------------------------------------------------------
                         required time                         -4.616    
                         arrival time                           5.152    
  -------------------------------------------------------------------
                         slack                                  0.537    

Slack (MET) :             0.563ns  (arrival time - required time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[1].u_ddr_mc_rd_en_low/rdEn_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PHY_RDEN[1]
                            (rising edge-triggered cell BITSLICE_CONTROL clocked by pll_clk[1]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[1]_DIV
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (pll_clk[1]_DIV rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.305ns  (logic 0.059ns (19.344%)  route 0.246ns (80.656%))
  Logic Levels:           0  
  Clock Path Skew:        -0.664ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.921ns
    Source Clock Delay      (SCD):    4.849ns
    Clock Pessimism Removal (CPR):    -0.264ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.702ns (routing 0.630ns, distribution 1.072ns)
  Clock Net Delay (Destination): 1.764ns (routing 0.696ns, distribution 1.068ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.364     2.279    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.909 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.214     3.123    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.147 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.702     4.849    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[1].u_ddr_mc_rd_en_low/rsMask_reg[7][9]_0
    SLICE_X81Y293        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[1].u_ddr_mc_rd_en_low/rdEn_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y293        FDRE (Prop_GFF_SLICEL_C_Q)
                                                      0.059     4.908 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[1].u_ddr_mc_rd_en_low/rdEn_reg[1]/Q
                         net (fo=1, routed)           0.246     5.154    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/ch0_mcal_clb2phy_rden_low[1]
    BITSLICE_CONTROL_X0Y38
                         BITSLICE_CONTROL                             r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PHY_RDEN[1]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[1]_DIV rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.524     2.610    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.483 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.244     2.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.755 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.764     4.519    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y8             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -1.058     3.461 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[1].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.148     3.609    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y38
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_RX_DIV2_CLK_Q)
                                                      0.193     3.802 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y38
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_RX_DIV2_CLK_Q_RX_DIV4_CLK_Q)
                                                      0.119     3.921 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV4_CLK_Q
                         clock pessimism              0.264     4.184    
                         clock uncertainty            0.170     4.355    
    BITSLICE_CONTROL_X0Y38
                         BITSLICE_CONTROL (Hold_CONTROL_BITSLICE_CONTROL_RX_DIV4_CLK_Q_PHY_RDEN[1])
                                                      0.236     4.591    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control
  -------------------------------------------------------------------
                         required time                         -4.591    
                         arrival time                           5.154    
  -------------------------------------------------------------------
                         slack                                  0.563    

Slack (MET) :             0.563ns  (arrival time - required time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[0].u_ddr_mc_rd_en_low/rdEn_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PHY_RDEN[2]
                            (rising edge-triggered cell BITSLICE_CONTROL clocked by pll_clk[1]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[1]_DIV
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (pll_clk[1]_DIV rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.334ns  (logic 0.059ns (17.665%)  route 0.275ns (82.335%))
  Logic Levels:           0  
  Clock Path Skew:        -0.669ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.914ns
    Source Clock Delay      (SCD):    4.847ns
    Clock Pessimism Removal (CPR):    -0.264ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.700ns (routing 0.630ns, distribution 1.070ns)
  Clock Net Delay (Destination): 1.764ns (routing 0.696ns, distribution 1.068ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.364     2.279    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.909 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.214     3.123    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.147 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.700     4.847    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[0].u_ddr_mc_rd_en_low/rsMask_reg[7][9]_0
    SLICE_X81Y293        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[0].u_ddr_mc_rd_en_low/rdEn_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y293        FDRE (Prop_BFF_SLICEL_C_Q)
                                                      0.059     4.906 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[0].u_ddr_mc_rd_en_low/rdEn_reg[2]/Q
                         net (fo=1, routed)           0.275     5.181    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/ch0_mcal_clb2phy_rden_low[2]
    BITSLICE_CONTROL_X0Y36
                         BITSLICE_CONTROL                             r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PHY_RDEN[2]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[1]_DIV rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.524     2.610    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.483 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.244     2.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.755 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.764     4.519    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y8             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -1.058     3.461 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[1].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.141     3.602    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y36
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_RX_DIV2_CLK_Q)
                                                      0.193     3.795 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y36
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_RX_DIV2_CLK_Q_RX_DIV4_CLK_Q)
                                                      0.119     3.914 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV4_CLK_Q
                         clock pessimism              0.264     4.177    
                         clock uncertainty            0.170     4.348    
    BITSLICE_CONTROL_X0Y36
                         BITSLICE_CONTROL (Hold_CONTROL_BITSLICE_CONTROL_RX_DIV4_CLK_Q_PHY_RDEN[2])
                                                      0.270     4.618    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control
  -------------------------------------------------------------------
                         required time                         -4.618    
                         arrival time                           5.181    
  -------------------------------------------------------------------
                         slack                                  0.563    

Slack (MET) :             0.572ns  (arrival time - required time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[1].u_ddr_mc_rd_en_upp/rdEn_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PHY_RDEN[3]
                            (rising edge-triggered cell BITSLICE_CONTROL clocked by pll_clk[1]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[1]_DIV
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (pll_clk[1]_DIV rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.264ns  (logic 0.058ns (21.970%)  route 0.206ns (78.030%))
  Logic Levels:           0  
  Clock Path Skew:        -0.694ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.891ns
    Source Clock Delay      (SCD):    4.849ns
    Clock Pessimism Removal (CPR):    -0.264ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.702ns (routing 0.630ns, distribution 1.072ns)
  Clock Net Delay (Destination): 1.764ns (routing 0.696ns, distribution 1.068ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.364     2.279    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.909 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.214     3.123    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.147 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.702     4.849    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[1].u_ddr_mc_rd_en_upp/rsMask_reg[6][9]_0
    SLICE_X82Y297        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[1].u_ddr_mc_rd_en_upp/rdEn_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X82Y297        FDRE (Prop_GFF_SLICEM_C_Q)
                                                      0.058     4.907 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[1].u_ddr_mc_rd_en_upp/rdEn_reg[3]/Q
                         net (fo=1, routed)           0.206     5.113    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/ch0_mcal_clb2phy_rden_upp[3]
    BITSLICE_CONTROL_X0Y39
                         BITSLICE_CONTROL                             r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PHY_RDEN[3]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[1]_DIV rise edge)
                                                      0.000     0.000 f  
    J19                                               0.000     0.000 f  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.524     2.610    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.483 f  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.244     2.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.755 f  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.764     4.519    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y8             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -1.058     3.461 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[1].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.150     3.611    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y39
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_RX_DIV2_CLK_Q)
                                                      0.162     3.773 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y39
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_RX_DIV2_CLK_Q_RX_DIV4_CLK_Q)
                                                      0.118     3.891 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV4_CLK_Q
                         clock pessimism              0.264     4.154    
                         clock uncertainty            0.170     4.325    
    BITSLICE_CONTROL_X0Y39
                         BITSLICE_CONTROL (Hold_CONTROL_BITSLICE_CONTROL_RX_DIV4_CLK_Q_PHY_RDEN[3])
                                                      0.216     4.541    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control
  -------------------------------------------------------------------
                         required time                         -4.541    
                         arrival time                           5.113    
  -------------------------------------------------------------------
                         slack                                  0.572    

Slack (MET) :             0.574ns  (arrival time - required time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[1].u_ddr_mc_rd_en_low/rdEn_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PHY_RDEN[2]
                            (rising edge-triggered cell BITSLICE_CONTROL clocked by pll_clk[1]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[1]_DIV
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (pll_clk[1]_DIV rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.344ns  (logic 0.059ns (17.151%)  route 0.285ns (82.849%))
  Logic Levels:           0  
  Clock Path Skew:        -0.670ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.921ns
    Source Clock Delay      (SCD):    4.854ns
    Clock Pessimism Removal (CPR):    -0.264ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.707ns (routing 0.630ns, distribution 1.077ns)
  Clock Net Delay (Destination): 1.764ns (routing 0.696ns, distribution 1.068ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.364     2.279    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.909 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.214     3.123    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.147 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.707     4.854    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[1].u_ddr_mc_rd_en_low/rsMask_reg[7][9]_0
    SLICE_X81Y294        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[1].u_ddr_mc_rd_en_low/rdEn_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y294        FDRE (Prop_GFF_SLICEL_C_Q)
                                                      0.059     4.913 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[1].u_ddr_mc_rd_en_low/rdEn_reg[2]/Q
                         net (fo=1, routed)           0.285     5.198    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/ch0_mcal_clb2phy_rden_low[2]
    BITSLICE_CONTROL_X0Y38
                         BITSLICE_CONTROL                             r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PHY_RDEN[2]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[1]_DIV rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.524     2.610    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.483 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.244     2.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.755 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.764     4.519    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y8             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -1.058     3.461 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[1].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.148     3.609    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y38
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_RX_DIV2_CLK_Q)
                                                      0.193     3.802 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y38
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_RX_DIV2_CLK_Q_RX_DIV4_CLK_Q)
                                                      0.119     3.921 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV4_CLK_Q
                         clock pessimism              0.264     4.184    
                         clock uncertainty            0.170     4.355    
    BITSLICE_CONTROL_X0Y38
                         BITSLICE_CONTROL (Hold_CONTROL_BITSLICE_CONTROL_RX_DIV4_CLK_Q_PHY_RDEN[2])
                                                      0.270     4.625    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control
  -------------------------------------------------------------------
                         required time                         -4.625    
                         arrival time                           5.198    
  -------------------------------------------------------------------
                         slack                                  0.574    

Slack (MET) :             0.574ns  (arrival time - required time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[3].u_ddr_mc_wr_byte/genBit[5].u_ddr_mc_wr_bit/dReg_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[1]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[1]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[1]_DIV
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (pll_clk[1]_DIV rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.402ns  (logic 0.058ns (14.428%)  route 0.344ns (85.572%))
  Logic Levels:           0  
  Clock Path Skew:        -0.383ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    4.102ns
    Source Clock Delay      (SCD):    4.816ns
    Clock Pessimism Removal (CPR):    -0.331ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.669ns (routing 0.630ns, distribution 1.039ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.364     2.279    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.909 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.214     3.123    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.147 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.669     4.816    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[3].u_ddr_mc_wr_byte/genBit[5].u_ddr_mc_wr_bit/dReg_reg[10]_0
    SLICE_X81Y239        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[3].u_ddr_mc_wr_byte/genBit[5].u_ddr_mc_wr_bit/dReg_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y239        FDRE (Prop_CFF_SLICEL_C_Q)
                                                      0.058     4.874 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[3].u_ddr_mc_wr_byte/genBit[5].u_ddr_mc_wr_bit/dReg_reg[1]/Q
                         net (fo=1, routed)           0.344     5.218    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/ch0_mcal_DQOut[1]
    BITSLICE_RX_TX_X0Y212
                         RXTX_BITSLICE                                r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[1]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[1]_DIV rise edge)
                                                      0.000     0.000 f  
    J19                                               0.000     0.000 f  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.524     2.610    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.483 f  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.244     2.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.755 f  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=41385, routed)       1.764     4.519    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y8             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -1.058     3.461 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[1].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.147     3.608    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y32
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.177     3.785 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y32
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.109     3.894 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y32
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT4[26])
                                                      0.186     4.080 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT4[26]
                         net (fo=1, routed)           0.022     4.102    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/TX_BIT_CTRL_OUT4[26]
    BITSLICE_RX_TX_X0Y212
                         RXTX_BITSLICE                                r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism              0.331     4.433    
                         clock uncertainty            0.170     4.603    
    BITSLICE_RX_TX_X0Y212
                         RXTX_BITSLICE (Hold_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[1])
                                                      0.041     4.644    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                         -4.644    
                         arrival time                           5.218    
  -------------------------------------------------------------------
                         slack                                  0.574    

Slack (MET) :             0.600ns  (arrival time - required time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[3].u_ddr_mc_wr_byte/genBit[4].u_ddr_mc_wr_bit/dReg_reg[6]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[6]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[1]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[1]_DIV
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (pll_clk[1]_DIV rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.455ns  (logic 0.058ns (12.747%)  route 0.397ns (87.253%))
  Logic Levels:           0  
  Clock Path Skew:        -0.358ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    4.110ns
    Source Clock Delay      (SCD):    4.799ns
    Clock Pessimism Removal (CPR):    -0.331ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.652ns (routing 0.630ns, distribution 1.022ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.364     2.279    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.909 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.214     3.123    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.147 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.652     4.799    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[3].u_ddr_mc_wr_byte/genBit[4].u_ddr_mc_wr_bit/dReg_reg[10]_0
    SLICE_X81Y219        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[3].u_ddr_mc_wr_byte/genBit[4].u_ddr_mc_wr_bit/dReg_reg[6]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y219        FDRE (Prop_FFF_SLICEL_C_Q)
                                                      0.058     4.857 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[3].u_ddr_mc_wr_byte/genBit[4].u_ddr_mc_wr_bit/dReg_reg[6]/Q
                         net (fo=1, routed)           0.397     5.254    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/ch0_mcal_DQOut[6]
    BITSLICE_RX_TX_X0Y213
                         RXTX_BITSLICE                                r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[6]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[1]_DIV rise edge)
                                                      0.000     0.000 f  
    J19                                               0.000     0.000 f  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.524     2.610    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.483 f  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.244     2.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.755 f  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=41385, routed)       1.764     4.519    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y8             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -1.058     3.461 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[1].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.147     3.608    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y32
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.177     3.785 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y32
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.109     3.894 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y32
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT5[26])
                                                      0.192     4.086 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT5[26]
                         net (fo=1, routed)           0.024     4.110    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/TX_BIT_CTRL_OUT5[26]
    BITSLICE_RX_TX_X0Y213
                         RXTX_BITSLICE                                r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism              0.331     4.441    
                         clock uncertainty            0.170     4.611    
    BITSLICE_RX_TX_X0Y213
                         RXTX_BITSLICE (Hold_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[6])
                                                      0.043     4.654    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                         -4.654    
                         arrival time                           5.254    
  -------------------------------------------------------------------
                         slack                                  0.600    

Slack (MET) :             0.606ns  (arrival time - required time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[2].u_ddr_mc_wr_byte/genBit[5].u_ddr_mc_wr_bit/dReg_reg[5]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[5]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[1]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[1]_DIV
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (pll_clk[1]_DIV rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.378ns  (logic 0.058ns (15.344%)  route 0.320ns (84.656%))
  Logic Levels:           0  
  Clock Path Skew:        -0.472ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    4.106ns
    Source Clock Delay      (SCD):    4.842ns
    Clock Pessimism Removal (CPR):    -0.264ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.695ns (routing 0.630ns, distribution 1.065ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.364     2.279    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.909 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.214     3.123    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.147 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.695     4.842    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[2].u_ddr_mc_wr_byte/genBit[5].u_ddr_mc_wr_bit/dReg_reg[10]_0
    SLICE_X82Y262        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[2].u_ddr_mc_wr_byte/genBit[5].u_ddr_mc_wr_bit/dReg_reg[5]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X82Y262        FDRE (Prop_CFF_SLICEM_C_Q)
                                                      0.058     4.900 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[2].u_ddr_mc_wr_byte/genBit[5].u_ddr_mc_wr_bit/dReg_reg[5]/Q
                         net (fo=1, routed)           0.320     5.220    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/ch0_mcal_DQOut[5]
    BITSLICE_RX_TX_X0Y226
                         RXTX_BITSLICE                                r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[5]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[1]_DIV rise edge)
                                                      0.000     0.000 f  
    J19                                               0.000     0.000 f  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.524     2.610    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.483 f  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.244     2.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.755 f  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=41385, routed)       1.764     4.519    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y8             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -1.058     3.461 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[1].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.143     3.604    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y34
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.177     3.781 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y34
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.109     3.890 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y34
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT5[26])
                                                      0.192     4.082 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT5[26]
                         net (fo=1, routed)           0.024     4.106    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/TX_BIT_CTRL_OUT5[26]
    BITSLICE_RX_TX_X0Y226
                         RXTX_BITSLICE                                r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism              0.264     4.369    
                         clock uncertainty            0.170     4.540    
    BITSLICE_RX_TX_X0Y226
                         RXTX_BITSLICE (Hold_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[5])
                                                      0.074     4.614    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                         -4.614    
                         arrival time                           5.220    
  -------------------------------------------------------------------
                         slack                                  0.606    





---------------------------------------------------------------------------------------------------
From Clock:  mmcm_clkout0
  To Clock:  pll_clk[2]_DIV

Setup :            0  Failing Endpoints,  Worst Slack        0.491ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.557ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.491ns  (required time - arrival time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ACT_n_dly_reg[0][7]/C
                            (rising edge-triggered cell FDSE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[7]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[2]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[2]_DIV
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (pll_clk[2]_DIV rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        1.852ns  (logic 0.078ns (4.212%)  route 1.774ns (95.788%))
  Logic Levels:           0  
  Clock Path Skew:        -0.434ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.549ns = ( 7.550 - 3.001 ) 
    Source Clock Delay      (SCD):    4.657ns
    Clock Pessimism Removal (CPR):    -0.326ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.902ns (routing 0.696ns, distribution 1.206ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.524     2.610    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.483 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.244     2.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.755 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.902     4.657    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/dReg_reg[10]
    SLICE_X94Y206        FDSE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ACT_n_dly_reg[0][7]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X94Y206        FDSE (Prop_DFF_SLICEM_C_Q)
                                                      0.078     4.735 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ACT_n_dly_reg[0][7]/Q
                         net (fo=1, routed)           1.774     6.509    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/mcal_ACT_n[7]
    BITSLICE_RX_TX_X0Y302
                         RXTX_BITSLICE                                r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[7]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[2]_DIV rise edge)
                                                      3.001     3.001 f  
    J19                                               0.000     3.001 f  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.555 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.595    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.595 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     3.892    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.916 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.364     5.280    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.910 f  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.214     6.124    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     6.148 f  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=41385, routed)       1.596     7.744    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y10            PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -0.630     7.114 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[2].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=6, routed)           0.104     7.218    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y46
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.117     7.335 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y46
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.075     7.410 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y46
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT3[26])
                                                      0.128     7.538 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT3[26]
                         net (fo=1, routed)           0.012     7.550    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/TX_BIT_CTRL_OUT3[26]
    BITSLICE_RX_TX_X0Y302
                         RXTX_BITSLICE                                r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism             -0.326     7.223    
                         clock uncertainty           -0.170     7.053    
    BITSLICE_RX_TX_X0Y302
                         RXTX_BITSLICE (Setup_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[7])
                                                     -0.053     7.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                          7.000    
                         arrival time                          -6.509    
  -------------------------------------------------------------------
                         slack                                  0.491    

Slack (MET) :             0.720ns  (required time - arrival time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2phy_t_b_addr_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TBYTE_IN[2]
                            (rising edge-triggered cell BITSLICE_CONTROL clocked by pll_clk[2]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[2]_DIV
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (pll_clk[2]_DIV rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        1.467ns  (logic 0.080ns (5.455%)  route 1.387ns (94.545%))
  Logic Levels:           0  
  Clock Path Skew:        -0.529ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.404ns = ( 7.405 - 3.001 ) 
    Source Clock Delay      (SCD):    4.677ns
    Clock Pessimism Removal (CPR):    -0.257ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.922ns (routing 0.696ns, distribution 1.226ns)
  Clock Net Delay (Destination): 1.596ns (routing 0.630ns, distribution 0.966ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.524     2.610    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.483 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.244     2.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.755 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.922     4.677    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/div_clk
    SLICE_X81Y325        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2phy_t_b_addr_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y325        FDRE (Prop_BFF2_SLICEL_C_Q)
                                                      0.080     4.757 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2phy_t_b_addr_reg[2]/Q
                         net (fo=6, routed)           1.387     6.143    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/clb2phy_t_b_low[2]
    BITSLICE_CONTROL_X0Y44
                         BITSLICE_CONTROL                             r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TBYTE_IN[2]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[2]_DIV rise edge)
                                                      3.001     3.001 f  
    J19                                               0.000     3.001 f  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.555 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.595    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.595 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     3.892    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.916 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.364     5.280    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.910 f  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.214     6.124    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     6.148 f  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.596     7.744    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y10            PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -0.630     7.114 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[2].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=6, routed)           0.099     7.213    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y44
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.117     7.330 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y44
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.075     7.405 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
                         clock pessimism             -0.257     7.148    
                         clock uncertainty           -0.170     6.978    
    BITSLICE_CONTROL_X0Y44
                         BITSLICE_CONTROL (Setup_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TBYTE_IN[2])
                                                     -0.115     6.863    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control
  -------------------------------------------------------------------
                         required time                          6.863    
                         arrival time                          -6.143    
  -------------------------------------------------------------------
                         slack                                  0.720    

Slack (MET) :             0.727ns  (required time - arrival time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][118]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[1].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/D[6]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[2]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[2]_DIV
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (pll_clk[2]_DIV rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        1.656ns  (logic 0.079ns (4.771%)  route 1.577ns (95.229%))
  Logic Levels:           0  
  Clock Path Skew:        -0.397ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.539ns = ( 7.540 - 3.001 ) 
    Source Clock Delay      (SCD):    4.680ns
    Clock Pessimism Removal (CPR):    -0.257ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.925ns (routing 0.696ns, distribution 1.229ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.524     2.610    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.483 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.244     2.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.755 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.925     4.680    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/dReg_reg[10]
    SLICE_X81Y323        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][118]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y323        FDRE (Prop_BFF_SLICEL_C_Q)
                                                      0.079     4.759 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][118]/Q
                         net (fo=1, routed)           1.577     6.336    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[1].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/mcal_ADR[6]
    BITSLICE_RX_TX_X0Y306
                         RXTX_BITSLICE                                r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[1].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/D[6]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[2]_DIV rise edge)
                                                      3.001     3.001 r  
    J19                                               0.000     3.001 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.555 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.595    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.595 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     3.892    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.916 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.364     5.280    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.910 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.214     6.124    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     6.148 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=41385, routed)       1.596     7.744    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y10            PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -0.630     7.114 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[2].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=6, routed)           0.105     7.219    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y47
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.106     7.325 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y47
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.075     7.400 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y47
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT1[26])
                                                      0.125     7.525 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT1[26]
                         net (fo=1, routed)           0.015     7.540    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[1].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/TX_BIT_CTRL_OUT1[26]
    BITSLICE_RX_TX_X0Y306
                         RXTX_BITSLICE                                r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[1].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism             -0.257     7.283    
                         clock uncertainty           -0.170     7.113    
    BITSLICE_RX_TX_X0Y306
                         RXTX_BITSLICE (Setup_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[6])
                                                     -0.050     7.063    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[1].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                          7.063    
                         arrival time                          -6.336    
  -------------------------------------------------------------------
                         slack                                  0.727    

Slack (MET) :             0.777ns  (required time - arrival time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ACT_n_dly_reg[0][4]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[4]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[2]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[2]_DIV
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (pll_clk[2]_DIV rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        1.609ns  (logic 0.080ns (4.972%)  route 1.529ns (95.028%))
  Logic Levels:           0  
  Clock Path Skew:        -0.398ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.549ns = ( 7.550 - 3.001 ) 
    Source Clock Delay      (SCD):    4.690ns
    Clock Pessimism Removal (CPR):    -0.257ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.935ns (routing 0.696ns, distribution 1.239ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.524     2.610    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.483 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.244     2.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.755 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.935     4.690    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/dReg_reg[10]
    SLICE_X85Y318        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ACT_n_dly_reg[0][4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X85Y318        FDRE (Prop_CFF2_SLICEL_C_Q)
                                                      0.080     4.770 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ACT_n_dly_reg[0][4]/Q
                         net (fo=1, routed)           1.529     6.299    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/mcal_ACT_n[4]
    BITSLICE_RX_TX_X0Y302
                         RXTX_BITSLICE                                r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[4]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[2]_DIV rise edge)
                                                      3.001     3.001 f  
    J19                                               0.000     3.001 f  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.555 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.595    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.595 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     3.892    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.916 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.364     5.280    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.910 f  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.214     6.124    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     6.148 f  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=41385, routed)       1.596     7.744    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y10            PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -0.630     7.114 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[2].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=6, routed)           0.104     7.218    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y46
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.117     7.335 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y46
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.075     7.410 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y46
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT3[26])
                                                      0.128     7.538 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT3[26]
                         net (fo=1, routed)           0.012     7.550    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/TX_BIT_CTRL_OUT3[26]
    BITSLICE_RX_TX_X0Y302
                         RXTX_BITSLICE                                r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism             -0.257     7.293    
                         clock uncertainty           -0.170     7.123    
    BITSLICE_RX_TX_X0Y302
                         RXTX_BITSLICE (Setup_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[4])
                                                     -0.047     7.076    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                          7.076    
                         arrival time                          -6.299    
  -------------------------------------------------------------------
                         slack                                  0.777    

Slack (MET) :             0.809ns  (required time - arrival time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][127]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/D[7]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[2]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[2]_DIV
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (pll_clk[2]_DIV rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        1.595ns  (logic 0.080ns (5.016%)  route 1.515ns (94.984%))
  Logic Levels:           0  
  Clock Path Skew:        -0.421ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.533ns = ( 7.534 - 3.001 ) 
    Source Clock Delay      (SCD):    4.697ns
    Clock Pessimism Removal (CPR):    -0.257ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.942ns (routing 0.696ns, distribution 1.246ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.524     2.610    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.483 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.244     2.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.755 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.942     4.697    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/dReg_reg[10]
    SLICE_X81Y341        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][127]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y341        FDRE (Prop_HFF2_SLICEL_C_Q)
                                                      0.080     4.777 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][127]/Q
                         net (fo=1, routed)           1.515     6.292    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/mcal_ADR[7]
    BITSLICE_RX_TX_X0Y308
                         RXTX_BITSLICE                                r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/D[7]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[2]_DIV rise edge)
                                                      3.001     3.001 r  
    J19                                               0.000     3.001 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.555 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.595    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.595 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     3.892    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.916 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.364     5.280    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.910 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.214     6.124    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     6.148 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=41385, routed)       1.596     7.744    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y10            PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -0.630     7.114 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[2].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=6, routed)           0.105     7.219    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y47
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.106     7.325 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y47
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.075     7.400 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y47
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT3[26])
                                                      0.122     7.522 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT3[26]
                         net (fo=1, routed)           0.012     7.534    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/TX_BIT_CTRL_OUT3[26]
    BITSLICE_RX_TX_X0Y308
                         RXTX_BITSLICE                                r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism             -0.257     7.277    
                         clock uncertainty           -0.170     7.107    
    BITSLICE_RX_TX_X0Y308
                         RXTX_BITSLICE (Setup_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[7])
                                                     -0.006     7.101    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                          7.101    
                         arrival time                          -6.292    
  -------------------------------------------------------------------
                         slack                                  0.809    

Slack (MET) :             0.816ns  (required time - arrival time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_CS_n_dly_reg[0][3]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/D[3]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[2]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[2]_DIV
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (pll_clk[2]_DIV rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        1.553ns  (logic 0.079ns (5.087%)  route 1.474ns (94.913%))
  Logic Levels:           0  
  Clock Path Skew:        -0.437ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.536ns = ( 7.537 - 3.001 ) 
    Source Clock Delay      (SCD):    4.716ns
    Clock Pessimism Removal (CPR):    -0.257ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.961ns (routing 0.696ns, distribution 1.265ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.524     2.610    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.483 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.244     2.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.755 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.961     4.716    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/dReg_reg[10]
    SLICE_X88Y312        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_CS_n_dly_reg[0][3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X88Y312        FDRE (Prop_HFF_SLICEL_C_Q)
                                                      0.079     4.795 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_CS_n_dly_reg[0][3]/Q
                         net (fo=1, routed)           1.474     6.269    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/mcal_CS_n[3]
    BITSLICE_RX_TX_X0Y307
                         RXTX_BITSLICE                                r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/D[3]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[2]_DIV rise edge)
                                                      3.001     3.001 r  
    J19                                               0.000     3.001 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.555 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.595    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.595 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     3.892    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.916 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.364     5.280    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.910 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.214     6.124    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     6.148 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=41385, routed)       1.596     7.744    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y10            PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -0.630     7.114 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[2].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=6, routed)           0.105     7.219    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y47
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.106     7.325 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y47
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.075     7.400 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y47
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT2[26])
                                                      0.124     7.524 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT2[26]
                         net (fo=1, routed)           0.013     7.537    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/TX_BIT_CTRL_OUT2[26]
    BITSLICE_RX_TX_X0Y307
                         RXTX_BITSLICE                                r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism             -0.257     7.280    
                         clock uncertainty           -0.170     7.110    
    BITSLICE_RX_TX_X0Y307
                         RXTX_BITSLICE (Setup_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[3])
                                                     -0.025     7.085    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                          7.085    
                         arrival time                          -6.269    
  -------------------------------------------------------------------
                         slack                                  0.816    

Slack (MET) :             0.850ns  (required time - arrival time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_CS_n_dly_reg[0][7]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/D[7]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[2]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[2]_DIV
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (pll_clk[2]_DIV rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        1.541ns  (logic 0.079ns (5.127%)  route 1.462ns (94.873%))
  Logic Levels:           0  
  Clock Path Skew:        -0.417ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.536ns = ( 7.537 - 3.001 ) 
    Source Clock Delay      (SCD):    4.696ns
    Clock Pessimism Removal (CPR):    -0.257ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.941ns (routing 0.696ns, distribution 1.245ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.524     2.610    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.483 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.244     2.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.755 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.941     4.696    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/dReg_reg[10]
    SLICE_X81Y340        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_CS_n_dly_reg[0][7]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y340        FDRE (Prop_GFF_SLICEL_C_Q)
                                                      0.079     4.775 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_CS_n_dly_reg[0][7]/Q
                         net (fo=1, routed)           1.462     6.237    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/mcal_CS_n[7]
    BITSLICE_RX_TX_X0Y307
                         RXTX_BITSLICE                                r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/D[7]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[2]_DIV rise edge)
                                                      3.001     3.001 r  
    J19                                               0.000     3.001 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.555 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.595    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.595 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     3.892    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.916 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.364     5.280    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.910 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.214     6.124    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     6.148 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=41385, routed)       1.596     7.744    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y10            PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -0.630     7.114 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[2].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=6, routed)           0.105     7.219    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y47
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.106     7.325 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y47
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.075     7.400 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y47
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT2[26])
                                                      0.124     7.524 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT2[26]
                         net (fo=1, routed)           0.013     7.537    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/TX_BIT_CTRL_OUT2[26]
    BITSLICE_RX_TX_X0Y307
                         RXTX_BITSLICE                                r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism             -0.257     7.280    
                         clock uncertainty           -0.170     7.110    
    BITSLICE_RX_TX_X0Y307
                         RXTX_BITSLICE (Setup_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[7])
                                                     -0.023     7.087    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                          7.087    
                         arrival time                          -6.237    
  -------------------------------------------------------------------
                         slack                                  0.850    

Slack (MET) :             0.861ns  (required time - arrival time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][121]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/D[1]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[2]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[2]_DIV
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (pll_clk[2]_DIV rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        1.512ns  (logic 0.079ns (5.225%)  route 1.433ns (94.775%))
  Logic Levels:           0  
  Clock Path Skew:        -0.405ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.533ns = ( 7.534 - 3.001 ) 
    Source Clock Delay      (SCD):    4.682ns
    Clock Pessimism Removal (CPR):    -0.257ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.927ns (routing 0.696ns, distribution 1.231ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.524     2.610    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.483 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.244     2.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.755 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.927     4.682    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/dReg_reg[10]
    SLICE_X81Y321        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][121]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y321        FDRE (Prop_BFF_SLICEL_C_Q)
                                                      0.079     4.761 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][121]/Q
                         net (fo=1, routed)           1.433     6.194    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/mcal_ADR[1]
    BITSLICE_RX_TX_X0Y308
                         RXTX_BITSLICE                                r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/D[1]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[2]_DIV rise edge)
                                                      3.001     3.001 r  
    J19                                               0.000     3.001 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.555 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.595    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.595 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     3.892    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.916 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.364     5.280    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.910 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.214     6.124    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     6.148 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=41385, routed)       1.596     7.744    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y10            PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -0.630     7.114 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[2].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=6, routed)           0.105     7.219    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y47
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.106     7.325 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y47
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.075     7.400 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y47
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT3[26])
                                                      0.122     7.522 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT3[26]
                         net (fo=1, routed)           0.012     7.534    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/TX_BIT_CTRL_OUT3[26]
    BITSLICE_RX_TX_X0Y308
                         RXTX_BITSLICE                                r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism             -0.257     7.277    
                         clock uncertainty           -0.170     7.107    
    BITSLICE_RX_TX_X0Y308
                         RXTX_BITSLICE (Setup_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[1])
                                                     -0.052     7.055    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                          7.055    
                         arrival time                          -6.194    
  -------------------------------------------------------------------
                         slack                                  0.861    

Slack (MET) :             0.888ns  (required time - arrival time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][117]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[1].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/D[5]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[2]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[2]_DIV
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (pll_clk[2]_DIV rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        1.505ns  (logic 0.081ns (5.382%)  route 1.424ns (94.618%))
  Logic Levels:           0  
  Clock Path Skew:        -0.399ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.539ns = ( 7.540 - 3.001 ) 
    Source Clock Delay      (SCD):    4.682ns
    Clock Pessimism Removal (CPR):    -0.257ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.927ns (routing 0.696ns, distribution 1.231ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.524     2.610    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.483 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.244     2.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.755 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.927     4.682    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/dReg_reg[10]
    SLICE_X81Y321        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][117]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y321        FDRE (Prop_DFF2_SLICEL_C_Q)
                                                      0.081     4.763 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][117]/Q
                         net (fo=1, routed)           1.424     6.187    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[1].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/mcal_ADR[5]
    BITSLICE_RX_TX_X0Y306
                         RXTX_BITSLICE                                r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[1].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/D[5]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[2]_DIV rise edge)
                                                      3.001     3.001 r  
    J19                                               0.000     3.001 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.555 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.595    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.595 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     3.892    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.916 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.364     5.280    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.910 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.214     6.124    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     6.148 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=41385, routed)       1.596     7.744    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y10            PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -0.630     7.114 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[2].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=6, routed)           0.105     7.219    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y47
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.106     7.325 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y47
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.075     7.400 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y47
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT1[26])
                                                      0.125     7.525 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT1[26]
                         net (fo=1, routed)           0.015     7.540    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[1].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/TX_BIT_CTRL_OUT1[26]
    BITSLICE_RX_TX_X0Y306
                         RXTX_BITSLICE                                r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[1].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism             -0.257     7.283    
                         clock uncertainty           -0.170     7.113    
    BITSLICE_RX_TX_X0Y306
                         RXTX_BITSLICE (Setup_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[5])
                                                     -0.038     7.075    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[1].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                          7.075    
                         arrival time                          -6.187    
  -------------------------------------------------------------------
                         slack                                  0.888    

Slack (MET) :             0.902ns  (required time - arrival time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_CKE_dly_reg[0][0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/D[0]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[2]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[2]_DIV
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (pll_clk[2]_DIV rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        1.484ns  (logic 0.079ns (5.323%)  route 1.405ns (94.677%))
  Logic Levels:           0  
  Clock Path Skew:        -0.406ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.540ns = ( 7.541 - 3.001 ) 
    Source Clock Delay      (SCD):    4.689ns
    Clock Pessimism Removal (CPR):    -0.257ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.934ns (routing 0.696ns, distribution 1.238ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.524     2.610    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.483 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.244     2.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.755 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.934     4.689    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/dReg_reg[10]
    SLICE_X81Y353        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_CKE_dly_reg[0][0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y353        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.079     4.768 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_CKE_dly_reg[0][0]/Q
                         net (fo=1, routed)           1.405     6.173    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/mcal_CKE[0]
    BITSLICE_RX_TX_X0Y310
                         RXTX_BITSLICE                                r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/D[0]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[2]_DIV rise edge)
                                                      3.001     3.001 r  
    J19                                               0.000     3.001 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.555 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.595    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.595 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     3.892    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.916 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.364     5.280    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.910 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.214     6.124    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     6.148 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=41385, routed)       1.596     7.744    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y10            PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -0.630     7.114 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[2].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=6, routed)           0.105     7.219    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y47
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.106     7.325 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y47
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.075     7.400 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y47
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT5[26])
                                                      0.126     7.526 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT5[26]
                         net (fo=1, routed)           0.015     7.541    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/TX_BIT_CTRL_OUT5[26]
    BITSLICE_RX_TX_X0Y310
                         RXTX_BITSLICE                                r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism             -0.257     7.284    
                         clock uncertainty           -0.170     7.114    
    BITSLICE_RX_TX_X0Y310
                         RXTX_BITSLICE (Setup_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[0])
                                                     -0.039     7.075    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                          7.075    
                         arrival time                          -6.173    
  -------------------------------------------------------------------
                         slack                                  0.902    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.557ns  (arrival time - required time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][68]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[3]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[2]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[2]_DIV
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (pll_clk[2]_DIV rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.327ns  (logic 0.058ns (17.736%)  route 0.269ns (82.264%))
  Logic Levels:           0  
  Clock Path Skew:        -0.473ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    4.124ns
    Source Clock Delay      (SCD):    4.853ns
    Clock Pessimism Removal (CPR):    -0.257ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.706ns (routing 0.630ns, distribution 1.076ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.364     2.279    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.909 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.214     3.123    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.147 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.706     4.853    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/dReg_reg[10]
    SLICE_X81Y336        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][68]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y336        FDRE (Prop_FFF_SLICEL_C_Q)
                                                      0.058     4.911 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][68]/Q
                         net (fo=2, routed)           0.269     5.180    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/mcal_ADR[3]
    BITSLICE_RX_TX_X0Y291
                         RXTX_BITSLICE                                r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[3]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[2]_DIV rise edge)
                                                      0.000     0.000 f  
    J19                                               0.000     0.000 f  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.524     2.610    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.483 f  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.244     2.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.755 f  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=41385, routed)       1.784     4.539    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y10            PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -1.058     3.481 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[2].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=6, routed)           0.141     3.622    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y44
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.177     3.799 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y44
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.109     3.908 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y44
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT5[26])
                                                      0.192     4.100 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT5[26]
                         net (fo=1, routed)           0.024     4.124    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/TX_BIT_CTRL_OUT5[26]
    BITSLICE_RX_TX_X0Y291
                         RXTX_BITSLICE                                r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism              0.257     4.380    
                         clock uncertainty            0.170     4.551    
    BITSLICE_RX_TX_X0Y291
                         RXTX_BITSLICE (Hold_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[3])
                                                      0.073     4.624    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                         -4.624    
                         arrival time                           5.180    
  -------------------------------------------------------------------
                         slack                                  0.557    

Slack (MET) :             0.559ns  (arrival time - required time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][78]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[5]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[2]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[2]_DIV
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (pll_clk[2]_DIV rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.332ns  (logic 0.059ns (17.786%)  route 0.273ns (82.214%))
  Logic Levels:           0  
  Clock Path Skew:        -0.475ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    4.116ns
    Source Clock Delay      (SCD):    4.848ns
    Clock Pessimism Removal (CPR):    -0.257ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.701ns (routing 0.630ns, distribution 1.071ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.364     2.279    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.909 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.214     3.123    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.147 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.701     4.848    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/dReg_reg[10]
    SLICE_X82Y335        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][78]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X82Y335        FDRE (Prop_CFF2_SLICEM_C_Q)
                                                      0.059     4.907 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][78]/Q
                         net (fo=2, routed)           0.273     5.179    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/mcal_ADR[5]
    BITSLICE_RX_TX_X0Y290
                         RXTX_BITSLICE                                r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[5]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[2]_DIV rise edge)
                                                      0.000     0.000 f  
    J19                                               0.000     0.000 f  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.524     2.610    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.483 f  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.244     2.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.755 f  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=41385, routed)       1.784     4.539    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y10            PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -1.058     3.481 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[2].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=6, routed)           0.141     3.622    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y44
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.177     3.799 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y44
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.109     3.908 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y44
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT4[26])
                                                      0.186     4.094 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT4[26]
                         net (fo=1, routed)           0.022     4.116    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/TX_BIT_CTRL_OUT4[26]
    BITSLICE_RX_TX_X0Y290
                         RXTX_BITSLICE                                r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism              0.257     4.372    
                         clock uncertainty            0.170     4.542    
    BITSLICE_RX_TX_X0Y290
                         RXTX_BITSLICE (Hold_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[5])
                                                      0.078     4.620    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                         -4.620    
                         arrival time                           5.179    
  -------------------------------------------------------------------
                         slack                                  0.559    

Slack (MET) :             0.561ns  (arrival time - required time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][92]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[3]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[2]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[2]_DIV
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (pll_clk[2]_DIV rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.305ns  (logic 0.059ns (19.317%)  route 0.246ns (80.683%))
  Logic Levels:           0  
  Clock Path Skew:        -0.480ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    4.113ns
    Source Clock Delay      (SCD):    4.849ns
    Clock Pessimism Removal (CPR):    -0.257ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.702ns (routing 0.630ns, distribution 1.072ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.364     2.279    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.909 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.214     3.123    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.147 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.702     4.849    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/dReg_reg[10]
    SLICE_X81Y333        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][92]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y333        FDRE (Prop_GFF_SLICEL_C_Q)
                                                      0.059     4.908 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][92]/Q
                         net (fo=2, routed)           0.246     5.155    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/mcal_ADR[3]
    BITSLICE_RX_TX_X0Y288
                         RXTX_BITSLICE                                r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[3]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[2]_DIV rise edge)
                                                      0.000     0.000 f  
    J19                                               0.000     0.000 f  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.524     2.610    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.483 f  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.244     2.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.755 f  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=41385, routed)       1.784     4.539    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y10            PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -1.058     3.481 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[2].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=6, routed)           0.141     3.622    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y44
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.177     3.799 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y44
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.109     3.908 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y44
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT2[26])
                                                      0.187     4.095 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT2[26]
                         net (fo=1, routed)           0.018     4.113    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/TX_BIT_CTRL_OUT2[26]
    BITSLICE_RX_TX_X0Y288
                         RXTX_BITSLICE                                r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism              0.257     4.369    
                         clock uncertainty            0.170     4.539    
    BITSLICE_RX_TX_X0Y288
                         RXTX_BITSLICE (Hold_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[3])
                                                      0.054     4.593    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                         -4.593    
                         arrival time                           5.155    
  -------------------------------------------------------------------
                         slack                                  0.561    

Slack (MET) :             0.570ns  (arrival time - required time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][71]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[7]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[2]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[2]_DIV
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (pll_clk[2]_DIV rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.311ns  (logic 0.059ns (18.971%)  route 0.252ns (81.029%))
  Logic Levels:           0  
  Clock Path Skew:        -0.473ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    4.124ns
    Source Clock Delay      (SCD):    4.853ns
    Clock Pessimism Removal (CPR):    -0.257ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.706ns (routing 0.630ns, distribution 1.076ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.364     2.279    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.909 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.214     3.123    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.147 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.706     4.853    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/dReg_reg[10]
    SLICE_X81Y336        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][71]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y336        FDRE (Prop_HFF2_SLICEL_C_Q)
                                                      0.059     4.912 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][71]/Q
                         net (fo=1, routed)           0.252     5.164    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/mcal_ADR[7]
    BITSLICE_RX_TX_X0Y291
                         RXTX_BITSLICE                                r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[7]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[2]_DIV rise edge)
                                                      0.000     0.000 f  
    J19                                               0.000     0.000 f  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.524     2.610    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.483 f  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.244     2.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.755 f  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=41385, routed)       1.784     4.539    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y10            PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -1.058     3.481 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[2].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=6, routed)           0.141     3.622    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y44
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.177     3.799 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y44
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.109     3.908 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y44
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT5[26])
                                                      0.192     4.100 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT5[26]
                         net (fo=1, routed)           0.024     4.124    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/TX_BIT_CTRL_OUT5[26]
    BITSLICE_RX_TX_X0Y291
                         RXTX_BITSLICE                                r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism              0.257     4.380    
                         clock uncertainty            0.170     4.551    
    BITSLICE_RX_TX_X0Y291
                         RXTX_BITSLICE (Hold_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[7])
                                                      0.044     4.595    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                         -4.595    
                         arrival time                           5.164    
  -------------------------------------------------------------------
                         slack                                  0.570    

Slack (MET) :             0.571ns  (arrival time - required time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][92]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[4]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[2]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[2]_DIV
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (pll_clk[2]_DIV rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.312ns  (logic 0.059ns (18.885%)  route 0.253ns (81.116%))
  Logic Levels:           0  
  Clock Path Skew:        -0.480ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    4.113ns
    Source Clock Delay      (SCD):    4.849ns
    Clock Pessimism Removal (CPR):    -0.257ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.702ns (routing 0.630ns, distribution 1.072ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.364     2.279    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.909 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.214     3.123    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.147 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.702     4.849    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/dReg_reg[10]
    SLICE_X81Y333        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][92]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y333        FDRE (Prop_GFF_SLICEL_C_Q)
                                                      0.059     4.908 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][92]/Q
                         net (fo=2, routed)           0.253     5.162    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/mcal_ADR[4]
    BITSLICE_RX_TX_X0Y288
                         RXTX_BITSLICE                                r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[4]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[2]_DIV rise edge)
                                                      0.000     0.000 f  
    J19                                               0.000     0.000 f  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.524     2.610    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.483 f  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.244     2.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.755 f  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=41385, routed)       1.784     4.539    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y10            PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -1.058     3.481 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[2].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=6, routed)           0.141     3.622    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y44
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.177     3.799 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y44
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.109     3.908 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y44
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT2[26])
                                                      0.187     4.095 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT2[26]
                         net (fo=1, routed)           0.018     4.113    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/TX_BIT_CTRL_OUT2[26]
    BITSLICE_RX_TX_X0Y288
                         RXTX_BITSLICE                                r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism              0.257     4.369    
                         clock uncertainty            0.170     4.539    
    BITSLICE_RX_TX_X0Y288
                         RXTX_BITSLICE (Hold_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[4])
                                                      0.051     4.590    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                         -4.590    
                         arrival time                           5.162    
  -------------------------------------------------------------------
                         slack                                  0.571    

Slack (MET) :             0.572ns  (arrival time - required time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][70]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[5]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[2]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[2]_DIV
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (pll_clk[2]_DIV rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.343ns  (logic 0.060ns (17.485%)  route 0.283ns (82.515%))
  Logic Levels:           0  
  Clock Path Skew:        -0.473ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    4.124ns
    Source Clock Delay      (SCD):    4.853ns
    Clock Pessimism Removal (CPR):    -0.257ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.706ns (routing 0.630ns, distribution 1.076ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.364     2.279    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.909 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.214     3.123    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.147 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.706     4.853    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/dReg_reg[10]
    SLICE_X81Y336        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][70]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y336        FDRE (Prop_FFF2_SLICEL_C_Q)
                                                      0.060     4.913 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][70]/Q
                         net (fo=2, routed)           0.283     5.196    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/mcal_ADR[5]
    BITSLICE_RX_TX_X0Y291
                         RXTX_BITSLICE                                r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[5]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[2]_DIV rise edge)
                                                      0.000     0.000 f  
    J19                                               0.000     0.000 f  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.524     2.610    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.483 f  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.244     2.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.755 f  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=41385, routed)       1.784     4.539    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y10            PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -1.058     3.481 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[2].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=6, routed)           0.141     3.622    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y44
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.177     3.799 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y44
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.109     3.908 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y44
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT5[26])
                                                      0.192     4.100 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT5[26]
                         net (fo=1, routed)           0.024     4.124    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/TX_BIT_CTRL_OUT5[26]
    BITSLICE_RX_TX_X0Y291
                         RXTX_BITSLICE                                r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism              0.257     4.380    
                         clock uncertainty            0.170     4.551    
    BITSLICE_RX_TX_X0Y291
                         RXTX_BITSLICE (Hold_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[5])
                                                      0.074     4.625    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                         -4.625    
                         arrival time                           5.196    
  -------------------------------------------------------------------
                         slack                                  0.572    

Slack (MET) :             0.573ns  (arrival time - required time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][108]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[3]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[2]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[2]_DIV
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (pll_clk[2]_DIV rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.305ns  (logic 0.059ns (19.317%)  route 0.246ns (80.683%))
  Logic Levels:           0  
  Clock Path Skew:        -0.492ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    4.115ns
    Source Clock Delay      (SCD):    4.863ns
    Clock Pessimism Removal (CPR):    -0.257ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.716ns (routing 0.630ns, distribution 1.086ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.364     2.279    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.909 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.214     3.123    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.147 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.716     4.863    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/dReg_reg[10]
    SLICE_X81Y318        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][108]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y318        FDRE (Prop_GFF_SLICEL_C_Q)
                                                      0.059     4.922 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][108]/Q
                         net (fo=2, routed)           0.246     5.169    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/mcal_ADR[3]
    BITSLICE_RX_TX_X0Y275
                         RXTX_BITSLICE                                r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[3]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[2]_DIV rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.524     2.610    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.483 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.244     2.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.755 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=41385, routed)       1.784     4.539    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y10            PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -1.058     3.481 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[2].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=6, routed)           0.143     3.624    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y42
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.177     3.801 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y42
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.109     3.910 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y42
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT2[26])
                                                      0.187     4.097 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT2[26]
                         net (fo=1, routed)           0.018     4.115    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/TX_BIT_CTRL_OUT2[26]
    BITSLICE_RX_TX_X0Y275
                         RXTX_BITSLICE                                r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism              0.257     4.371    
                         clock uncertainty            0.170     4.542    
    BITSLICE_RX_TX_X0Y275
                         RXTX_BITSLICE (Hold_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[3])
                                                      0.054     4.596    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                         -4.596    
                         arrival time                           5.169    
  -------------------------------------------------------------------
                         slack                                  0.573    

Slack (MET) :             0.575ns  (arrival time - required time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][6]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[6]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[2]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[2]_DIV
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (pll_clk[2]_DIV rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.337ns  (logic 0.058ns (17.190%)  route 0.279ns (82.810%))
  Logic Levels:           0  
  Clock Path Skew:        -0.479ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    4.120ns
    Source Clock Delay      (SCD):    4.856ns
    Clock Pessimism Removal (CPR):    -0.257ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.709ns (routing 0.630ns, distribution 1.079ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.364     2.279    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.909 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.214     3.123    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.147 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.709     4.856    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/dReg_reg[10]
    SLICE_X82Y343        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][6]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X82Y343        FDRE (Prop_HFF_SLICEM_C_Q)
                                                      0.058     4.914 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][6]/Q
                         net (fo=2, routed)           0.279     5.193    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/clb2phy_wr_dq0[6]
    BITSLICE_RX_TX_X0Y299
                         RXTX_BITSLICE                                r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[6]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[2]_DIV rise edge)
                                                      0.000     0.000 f  
    J19                                               0.000     0.000 f  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.524     2.610    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.483 f  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.244     2.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.755 f  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=41385, routed)       1.784     4.539    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y10            PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -1.058     3.481 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[2].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=6, routed)           0.148     3.629    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y46
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.177     3.806 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y46
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.109     3.915 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y46
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT0[26])
                                                      0.162     4.077 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT0[26]
                         net (fo=1, routed)           0.043     4.120    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/TX_BIT_CTRL_OUT0[26]
    BITSLICE_RX_TX_X0Y299
                         RXTX_BITSLICE                                r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism              0.257     4.376    
                         clock uncertainty            0.170     4.547    
    BITSLICE_RX_TX_X0Y299
                         RXTX_BITSLICE (Hold_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[6])
                                                      0.072     4.619    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                         -4.619    
                         arrival time                           5.193    
  -------------------------------------------------------------------
                         slack                                  0.575    

Slack (MET) :             0.576ns  (arrival time - required time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][14]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[6].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/D[1]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[2]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[2]_DIV
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (pll_clk[2]_DIV rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.321ns  (logic 0.061ns (19.026%)  route 0.260ns (80.974%))
  Logic Levels:           0  
  Clock Path Skew:        -0.499ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    4.092ns
    Source Clock Delay      (SCD):    4.848ns
    Clock Pessimism Removal (CPR):    -0.257ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.701ns (routing 0.630ns, distribution 1.071ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.364     2.279    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.909 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.214     3.123    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.147 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.701     4.848    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/dReg_reg[10]
    SLICE_X81Y337        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][14]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y337        FDRE (Prop_DFF2_SLICEL_C_Q)
                                                      0.061     4.909 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][14]/Q
                         net (fo=4, routed)           0.260     5.168    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[6].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/mcal_ADR[1]
    BITSLICE_RX_TX_X0Y298
                         RXTX_BITSLICE                                r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[6].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/D[1]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[2]_DIV rise edge)
                                                      0.000     0.000 f  
    J19                                               0.000     0.000 f  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.524     2.610    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.483 f  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.244     2.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.755 f  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=41385, routed)       1.784     4.539    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y10            PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -1.058     3.481 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[2].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=6, routed)           0.146     3.627    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y45
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.151     3.778 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y45
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.109     3.887 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y45
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT6[26])
                                                      0.180     4.067 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT6[26]
                         net (fo=1, routed)           0.025     4.092    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[6].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/TX_BIT_CTRL_OUT6[26]
    BITSLICE_RX_TX_X0Y298
                         RXTX_BITSLICE                                r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[6].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism              0.257     4.348    
                         clock uncertainty            0.170     4.518    
    BITSLICE_RX_TX_X0Y298
                         RXTX_BITSLICE (Hold_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[1])
                                                      0.074     4.592    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[6].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                         -4.592    
                         arrival time                           5.168    
  -------------------------------------------------------------------
                         slack                                  0.576    

Slack (MET) :             0.577ns  (arrival time - required time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][86]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[6]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[2]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[2]_DIV
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (pll_clk[2]_DIV rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.308ns  (logic 0.058ns (18.822%)  route 0.250ns (81.178%))
  Logic Levels:           0  
  Clock Path Skew:        -0.478ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    4.116ns
    Source Clock Delay      (SCD):    4.850ns
    Clock Pessimism Removal (CPR):    -0.257ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.703ns (routing 0.630ns, distribution 1.073ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.364     2.279    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.909 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.214     3.123    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.147 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.703     4.850    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/dReg_reg[10]
    SLICE_X81Y335        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][86]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y335        FDRE (Prop_CFF_SLICEL_C_Q)
                                                      0.058     4.908 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][86]/Q
                         net (fo=2, routed)           0.250     5.158    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/mcal_ADR[6]
    BITSLICE_RX_TX_X0Y289
                         RXTX_BITSLICE                                r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[6]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[2]_DIV rise edge)
                                                      0.000     0.000 f  
    J19                                               0.000     0.000 f  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.524     2.610    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.483 f  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.244     2.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.755 f  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=41385, routed)       1.784     4.539    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y10            PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -1.058     3.481 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[2].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=6, routed)           0.141     3.622    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y44
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.177     3.799 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y44
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.109     3.908 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y44
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT3[26])
                                                      0.187     4.095 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT3[26]
                         net (fo=1, routed)           0.021     4.116    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/TX_BIT_CTRL_OUT3[26]
    BITSLICE_RX_TX_X0Y289
                         RXTX_BITSLICE                                r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism              0.257     4.372    
                         clock uncertainty            0.170     4.542    
    BITSLICE_RX_TX_X0Y289
                         RXTX_BITSLICE (Hold_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[6])
                                                      0.039     4.581    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                         -4.581    
                         arrival time                           5.158    
  -------------------------------------------------------------------
                         slack                                  0.577    





---------------------------------------------------------------------------------------------------
From Clock:  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  To Clock:  mmcm_clkout5

Setup :            0  Failing Endpoints,  Worst Slack       49.494ns,  Total Violation        0.000ns
Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             49.494ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[2]/C
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[2]/D
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            50.000ns  (MaxDelay Path 50.000ns)
  Data Path Delay:        0.531ns  (logic 0.078ns (14.689%)  route 0.453ns (85.311%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 50.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X104Y370                                    0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[2]/C
    SLICE_X104Y370       FDCE (Prop_DFF_SLICEM_C_Q)
                                                      0.078     0.078 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[2]/Q
                         net (fo=1, routed)           0.453     0.531    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q[2]
    SLICE_X104Y370       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[2]/D
  -------------------------------------------------------------------    -------------------

                         max delay                   50.000    50.000    
    SLICE_X104Y370       FDCE (Setup_HFF2_SLICEM_C_D)
                                                      0.025    50.025    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[2]
  -------------------------------------------------------------------
                         required time                         50.025    
                         arrival time                          -0.531    
  -------------------------------------------------------------------
                         slack                                 49.494    

Slack (MET) :             49.527ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[1]/C
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[1]/D
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            50.000ns  (MaxDelay Path 50.000ns)
  Data Path Delay:        0.498ns  (logic 0.081ns (16.265%)  route 0.417ns (83.735%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 50.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X102Y369                                    0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[1]/C
    SLICE_X102Y369       FDCE (Prop_DFF2_SLICEL_C_Q)
                                                      0.081     0.081 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[1]/Q
                         net (fo=1, routed)           0.417     0.498    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q[1]
    SLICE_X104Y369       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         max delay                   50.000    50.000    
    SLICE_X104Y369       FDCE (Setup_DFF2_SLICEM_C_D)
                                                      0.025    50.025    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[1]
  -------------------------------------------------------------------
                         required time                         50.025    
                         arrival time                          -0.498    
  -------------------------------------------------------------------
                         slack                                 49.527    

Slack (MET) :             49.556ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[0]/C
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[0]/D
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            50.000ns  (MaxDelay Path 50.000ns)
  Data Path Delay:        0.469ns  (logic 0.079ns (16.844%)  route 0.390ns (83.156%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 50.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X102Y369                                    0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[0]/C
    SLICE_X102Y369       FDCE (Prop_DFF_SLICEL_C_Q)
                                                      0.079     0.079 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[0]/Q
                         net (fo=1, routed)           0.390     0.469    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q[0]
    SLICE_X104Y369       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                   50.000    50.000    
    SLICE_X104Y369       FDCE (Setup_HFF2_SLICEM_C_D)
                                                      0.025    50.025    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[0]
  -------------------------------------------------------------------
                         required time                         50.025    
                         arrival time                          -0.469    
  -------------------------------------------------------------------
                         slack                                 49.556    

Slack (MET) :             49.651ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[2]/C
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[2]/D
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            50.000ns  (MaxDelay Path 50.000ns)
  Data Path Delay:        0.374ns  (logic 0.079ns (21.123%)  route 0.295ns (78.877%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 50.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X101Y349                                    0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[2]/C
    SLICE_X101Y349       FDCE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     0.079 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[2]/Q
                         net (fo=1, routed)           0.295     0.374    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q[2]
    SLICE_X103Y346       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[2]/D
  -------------------------------------------------------------------    -------------------

                         max delay                   50.000    50.000    
    SLICE_X103Y346       FDCE (Setup_BFF2_SLICEM_C_D)
                                                      0.025    50.025    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[2]
  -------------------------------------------------------------------
                         required time                         50.025    
                         arrival time                          -0.374    
  -------------------------------------------------------------------
                         slack                                 49.651    

Slack (MET) :             49.671ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[0]/C
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[0]/D
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            50.000ns  (MaxDelay Path 50.000ns)
  Data Path Delay:        0.354ns  (logic 0.076ns (21.469%)  route 0.278ns (78.531%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 50.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X103Y349                                    0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[0]/C
    SLICE_X103Y349       FDCE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     0.076 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[0]/Q
                         net (fo=1, routed)           0.278     0.354    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q[0]
    SLICE_X103Y346       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                   50.000    50.000    
    SLICE_X103Y346       FDCE (Setup_CFF2_SLICEM_C_D)
                                                      0.025    50.025    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[0]
  -------------------------------------------------------------------
                         required time                         50.025    
                         arrival time                          -0.354    
  -------------------------------------------------------------------
                         slack                                 49.671    

Slack (MET) :             49.678ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[3]/C
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[3]/D
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            50.000ns  (MaxDelay Path 50.000ns)
  Data Path Delay:        0.347ns  (logic 0.079ns (22.767%)  route 0.268ns (77.233%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 50.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X105Y369                                    0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[3]/C
    SLICE_X105Y369       FDCE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     0.079 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[3]/Q
                         net (fo=1, routed)           0.268     0.347    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q[3]
    SLICE_X104Y369       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[3]/D
  -------------------------------------------------------------------    -------------------

                         max delay                   50.000    50.000    
    SLICE_X104Y369       FDCE (Setup_CFF2_SLICEM_C_D)
                                                      0.025    50.025    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[3]
  -------------------------------------------------------------------
                         required time                         50.025    
                         arrival time                          -0.347    
  -------------------------------------------------------------------
                         slack                                 49.678    

Slack (MET) :             49.744ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[3]/C
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[3]/D
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            50.000ns  (MaxDelay Path 50.000ns)
  Data Path Delay:        0.281ns  (logic 0.079ns (28.114%)  route 0.202ns (71.886%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 50.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X102Y349                                    0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[3]/C
    SLICE_X102Y349       FDCE (Prop_AFF_SLICEL_C_Q)
                                                      0.079     0.079 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[3]/Q
                         net (fo=1, routed)           0.202     0.281    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q[3]
    SLICE_X102Y349       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[3]/D
  -------------------------------------------------------------------    -------------------

                         max delay                   50.000    50.000    
    SLICE_X102Y349       FDCE (Setup_GFF2_SLICEL_C_D)
                                                      0.025    50.025    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[3]
  -------------------------------------------------------------------
                         required time                         50.025    
                         arrival time                          -0.281    
  -------------------------------------------------------------------
                         slack                                 49.744    

Slack (MET) :             49.783ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[1]/C
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[1]/D
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            50.000ns  (MaxDelay Path 50.000ns)
  Data Path Delay:        0.242ns  (logic 0.080ns (33.058%)  route 0.162ns (66.942%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 50.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X101Y349                                    0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[1]/C
    SLICE_X101Y349       FDCE (Prop_HFF2_SLICEL_C_Q)
                                                      0.080     0.080 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[1]/Q
                         net (fo=1, routed)           0.162     0.242    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q[1]
    SLICE_X101Y347       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         max delay                   50.000    50.000    
    SLICE_X101Y347       FDCE (Setup_DFF2_SLICEL_C_D)
                                                      0.025    50.025    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[1]
  -------------------------------------------------------------------
                         required time                         50.025    
                         arrival time                          -0.242    
  -------------------------------------------------------------------
                         slack                                 49.783    





---------------------------------------------------------------------------------------------------
From Clock:  mmcm_clkout0
  To Clock:  mmcm_clkout5

Setup :            0  Failing Endpoints,  Worst Slack       11.312ns,  Total Violation        0.000ns
Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             11.312ns  (required time - arrival time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[8]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[8].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.000ns  (MaxDelay Path 12.000ns)
  Data Path Delay:        0.713ns  (logic 0.081ns (11.360%)  route 0.632ns (88.640%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 12.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X91Y352                                     0.000     0.000 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[8]/C
    SLICE_X91Y352        FDRE (Prop_FFF2_SLICEL_C_Q)
                                                      0.081     0.081 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[8]/Q
                         net (fo=1, routed)           0.632     0.713    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/out[8]
    SLICE_X94Y352        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[8].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                   12.000    12.000    
    SLICE_X94Y352        FDRE (Setup_DFF2_SLICEM_C_D)
                                                      0.025    12.025    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[8].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                         12.025    
                         arrival time                          -0.713    
  -------------------------------------------------------------------
                         slack                                 11.312    

Slack (MET) :             11.466ns  (required time - arrival time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[0].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.000ns  (MaxDelay Path 12.000ns)
  Data Path Delay:        0.559ns  (logic 0.080ns (14.311%)  route 0.479ns (85.689%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 12.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X91Y352                                     0.000     0.000 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[0]/C
    SLICE_X91Y352        FDRE (Prop_HFF2_SLICEL_C_Q)
                                                      0.080     0.080 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[0]/Q
                         net (fo=1, routed)           0.479     0.559    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/out[0]
    SLICE_X96Y355        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[0].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                   12.000    12.000    
    SLICE_X96Y355        FDRE (Setup_DFF2_SLICEM_C_D)
                                                      0.025    12.025    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[0].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                         12.025    
                         arrival time                          -0.559    
  -------------------------------------------------------------------
                         slack                                 11.466    

Slack (MET) :             11.594ns  (required time - arrival time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[4]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[4].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.000ns  (MaxDelay Path 12.000ns)
  Data Path Delay:        0.431ns  (logic 0.081ns (18.794%)  route 0.350ns (81.206%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 12.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X91Y352                                     0.000     0.000 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[4]/C
    SLICE_X91Y352        FDRE (Prop_GFF2_SLICEL_C_Q)
                                                      0.081     0.081 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[4]/Q
                         net (fo=1, routed)           0.350     0.431    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/out[4]
    SLICE_X93Y354        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[4].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                   12.000    12.000    
    SLICE_X93Y354        FDRE (Setup_HFF2_SLICEM_C_D)
                                                      0.025    12.025    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[4].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                         12.025    
                         arrival time                          -0.431    
  -------------------------------------------------------------------
                         slack                                 11.594    

Slack (MET) :             11.608ns  (required time - arrival time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[1].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.000ns  (MaxDelay Path 12.000ns)
  Data Path Delay:        0.417ns  (logic 0.078ns (18.705%)  route 0.339ns (81.295%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 12.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X93Y353                                     0.000     0.000 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[1]/C
    SLICE_X93Y353        FDRE (Prop_HFF2_SLICEM_C_Q)
                                                      0.078     0.078 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[1]/Q
                         net (fo=1, routed)           0.339     0.417    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/out[1]
    SLICE_X96Y355        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[1].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                   12.000    12.000    
    SLICE_X96Y355        FDRE (Setup_GFF2_SLICEM_C_D)
                                                      0.025    12.025    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[1].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                         12.025    
                         arrival time                          -0.417    
  -------------------------------------------------------------------
                         slack                                 11.608    

Slack (MET) :             11.629ns  (required time - arrival time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[6]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[6].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.000ns  (MaxDelay Path 12.000ns)
  Data Path Delay:        0.396ns  (logic 0.079ns (19.949%)  route 0.317ns (80.051%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 12.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X93Y353                                     0.000     0.000 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[6]/C
    SLICE_X93Y353        FDRE (Prop_GFF2_SLICEM_C_Q)
                                                      0.079     0.079 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[6]/Q
                         net (fo=1, routed)           0.317     0.396    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/out[6]
    SLICE_X94Y354        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[6].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                   12.000    12.000    
    SLICE_X94Y354        FDRE (Setup_CFF2_SLICEM_C_D)
                                                      0.025    12.025    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[6].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                         12.025    
                         arrival time                          -0.396    
  -------------------------------------------------------------------
                         slack                                 11.629    

Slack (MET) :             11.653ns  (required time - arrival time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[7]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[7].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.000ns  (MaxDelay Path 12.000ns)
  Data Path Delay:        0.372ns  (logic 0.079ns (21.237%)  route 0.293ns (78.763%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 12.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X93Y353                                     0.000     0.000 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[7]/C
    SLICE_X93Y353        FDRE (Prop_FFF2_SLICEM_C_Q)
                                                      0.079     0.079 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[7]/Q
                         net (fo=1, routed)           0.293     0.372    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/out[7]
    SLICE_X94Y355        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[7].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                   12.000    12.000    
    SLICE_X94Y355        FDRE (Setup_CFF2_SLICEM_C_D)
                                                      0.025    12.025    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[7].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                         12.025    
                         arrival time                          -0.372    
  -------------------------------------------------------------------
                         slack                                 11.653    

Slack (MET) :             11.693ns  (required time - arrival time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[5]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[5].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.000ns  (MaxDelay Path 12.000ns)
  Data Path Delay:        0.332ns  (logic 0.081ns (24.398%)  route 0.251ns (75.602%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 12.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X95Y356                                     0.000     0.000 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[5]/C
    SLICE_X95Y356        FDRE (Prop_GFF2_SLICEL_C_Q)
                                                      0.081     0.081 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[5]/Q
                         net (fo=1, routed)           0.251     0.332    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/out[5]
    SLICE_X94Y356        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[5].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                   12.000    12.000    
    SLICE_X94Y356        FDRE (Setup_HFF2_SLICEM_C_D)
                                                      0.025    12.025    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[5].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                         12.025    
                         arrival time                          -0.332    
  -------------------------------------------------------------------
                         slack                                 11.693    

Slack (MET) :             11.694ns  (required time - arrival time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_rdy_lvl_fclk_reg/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_rdy_sync/SYNC[0].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.000ns  (MaxDelay Path 12.000ns)
  Data Path Delay:        0.331ns  (logic 0.080ns (24.167%)  route 0.251ns (75.833%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 12.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X95Y355                                     0.000     0.000 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_rdy_lvl_fclk_reg/C
    SLICE_X95Y355        FDRE (Prop_BFF2_SLICEL_C_Q)
                                                      0.080     0.080 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_rdy_lvl_fclk_reg/Q
                         net (fo=2, routed)           0.251     0.331    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_rdy_sync/D[0]
    SLICE_X94Y357        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_rdy_sync/SYNC[0].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                   12.000    12.000    
    SLICE_X94Y357        FDRE (Setup_HFF2_SLICEM_C_D)
                                                      0.025    12.025    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_rdy_sync/SYNC[0].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                         12.025    
                         arrival time                          -0.331    
  -------------------------------------------------------------------
                         slack                                 11.694    

Slack (MET) :             11.718ns  (required time - arrival time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[3].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.000ns  (MaxDelay Path 12.000ns)
  Data Path Delay:        0.307ns  (logic 0.080ns (26.059%)  route 0.227ns (73.941%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 12.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X95Y356                                     0.000     0.000 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[3]/C
    SLICE_X95Y356        FDRE (Prop_HFF2_SLICEL_C_Q)
                                                      0.080     0.080 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[3]/Q
                         net (fo=1, routed)           0.227     0.307    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/out[3]
    SLICE_X94Y355        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[3].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                   12.000    12.000    
    SLICE_X94Y355        FDRE (Setup_DFF2_SLICEM_C_D)
                                                      0.025    12.025    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[3].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                         12.025    
                         arrival time                          -0.307    
  -------------------------------------------------------------------
                         slack                                 11.718    

Slack (MET) :             11.721ns  (required time - arrival time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[2].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.000ns  (MaxDelay Path 12.000ns)
  Data Path Delay:        0.304ns  (logic 0.081ns (26.645%)  route 0.223ns (73.355%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 12.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X92Y351                                     0.000     0.000 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[2]/C
    SLICE_X92Y351        FDRE (Prop_DFF2_SLICEL_C_Q)
                                                      0.081     0.081 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[2]/Q
                         net (fo=1, routed)           0.223     0.304    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/out[2]
    SLICE_X94Y351        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[2].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                   12.000    12.000    
    SLICE_X94Y351        FDRE (Setup_HFF2_SLICEM_C_D)
                                                      0.025    12.025    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[2].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                         12.025    
                         arrival time                          -0.304    
  -------------------------------------------------------------------
                         slack                                 11.721    





---------------------------------------------------------------------------------------------------
From Clock:  mmcm_clkout0
  To Clock:  mmcm_clkout6

Setup :            0  Failing Endpoints,  Worst Slack        1.452ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.128ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             1.452ns  (required time - arrival time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/sample_gts_reg/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/sample_gts_riu_reg/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             mmcm_clkout6
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (mmcm_clkout6 rise@6.001ns - mmcm_clkout0 rise@3.001ns)
  Data Path Delay:        1.147ns  (logic 0.078ns (6.800%)  route 1.069ns (93.200%))
  Logic Levels:           0  
  Clock Path Skew:        -0.238ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.886ns = ( 10.887 - 6.001 ) 
    Source Clock Delay      (SCD):    4.698ns = ( 7.698 - 3.001 ) 
    Clock Pessimism Removal (CPR):    -0.426ns
  Clock Uncertainty:      0.188ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      1.943ns (routing 0.696ns, distribution 1.247ns)
  Clock Net Delay (Destination): 1.727ns (routing 0.642ns, distribution 1.085ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      3.001     3.001 r  
    J19                                               0.000     3.001 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     3.101    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     3.672 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     3.722    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.722 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     4.058    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     4.086 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.524     5.610    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     5.483 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.244     5.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     5.755 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.943     7.698    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/dReg_reg[10]
    SLICE_X83Y295        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/sample_gts_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X83Y295        FDRE (Prop_DFF_SLICEM_C_Q)
                                                      0.078     7.776 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/sample_gts_reg/Q
                         net (fo=1, routed)           1.069     8.845    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/sample_gts
    SLICE_X81Y295        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/sample_gts_riu_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      6.001     6.001 r  
    J19                                               0.000     6.001 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     6.080    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     6.555 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     6.595    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     6.595 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     6.892    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     6.916 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.364     8.280    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.630     8.910 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.226     9.136    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y104        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     9.160 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.727    10.887    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/CLK
    SLICE_X81Y295        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/sample_gts_riu_reg/C
                         clock pessimism             -0.426    10.461    
                         clock uncertainty           -0.188    10.272    
    SLICE_X81Y295        FDRE (Setup_EFF_SLICEL_C_D)
                                                      0.025    10.297    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/sample_gts_riu_reg
  -------------------------------------------------------------------
                         required time                         10.297    
                         arrival time                          -8.845    
  -------------------------------------------------------------------
                         slack                                  1.452    

Slack (MET) :             4.022ns  (required time - arrival time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[24]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[24].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             mmcm_clkout6
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            5.000ns  (MaxDelay Path 5.000ns)
  Data Path Delay:        1.003ns  (logic 0.080ns (7.976%)  route 0.923ns (92.024%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 5.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X92Y290                                     0.000     0.000 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[24]/C
    SLICE_X92Y290        FDRE (Prop_HFF2_SLICEL_C_Q)
                                                      0.080     0.080 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[24]/Q
                         net (fo=1, routed)           0.923     1.003    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[31].sync_reg_reg[0]_0[24]
    SLICE_X92Y315        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[24].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    5.000     5.000    
    SLICE_X92Y315        FDRE (Setup_DFF2_SLICEL_C_D)
                                                      0.025     5.025    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[24].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                          5.025    
                         arrival time                          -1.003    
  -------------------------------------------------------------------
                         slack                                  4.022    

Slack (MET) :             4.422ns  (required time - arrival time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[18]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[18].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             mmcm_clkout6
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            5.000ns  (MaxDelay Path 5.000ns)
  Data Path Delay:        0.603ns  (logic 0.080ns (13.267%)  route 0.523ns (86.733%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 5.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X93Y281                                     0.000     0.000 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[18]/C
    SLICE_X93Y281        FDRE (Prop_DFF2_SLICEM_C_Q)
                                                      0.080     0.080 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[18]/Q
                         net (fo=1, routed)           0.523     0.603    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[31].sync_reg_reg[0]_0[18]
    SLICE_X92Y315        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[18].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    5.000     5.000    
    SLICE_X92Y315        FDRE (Setup_GFF2_SLICEL_C_D)
                                                      0.025     5.025    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[18].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                          5.025    
                         arrival time                          -0.603    
  -------------------------------------------------------------------
                         slack                                  4.422    

Slack (MET) :             4.460ns  (required time - arrival time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[11]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[11].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             mmcm_clkout6
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            5.000ns  (MaxDelay Path 5.000ns)
  Data Path Delay:        0.565ns  (logic 0.076ns (13.451%)  route 0.489ns (86.549%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 5.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X93Y318                                     0.000     0.000 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[11]/C
    SLICE_X93Y318        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     0.076 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[11]/Q
                         net (fo=1, routed)           0.489     0.565    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[31].sync_reg_reg[0]_0[11]
    SLICE_X89Y319        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[11].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    5.000     5.000    
    SLICE_X89Y319        FDRE (Setup_DFF2_SLICEM_C_D)
                                                      0.025     5.025    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[11].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                          5.025    
                         arrival time                          -0.565    
  -------------------------------------------------------------------
                         slack                                  4.460    

Slack (MET) :             4.465ns  (required time - arrival time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[8]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[8].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             mmcm_clkout6
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            5.000ns  (MaxDelay Path 5.000ns)
  Data Path Delay:        0.560ns  (logic 0.081ns (14.464%)  route 0.479ns (85.536%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 5.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X91Y316                                     0.000     0.000 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[8]/C
    SLICE_X91Y316        FDRE (Prop_EFF2_SLICEL_C_Q)
                                                      0.081     0.081 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[8]/Q
                         net (fo=1, routed)           0.479     0.560    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[31].sync_reg_reg[0]_0[8]
    SLICE_X89Y318        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[8].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    5.000     5.000    
    SLICE_X89Y318        FDRE (Setup_HFF2_SLICEM_C_D)
                                                      0.025     5.025    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[8].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                          5.025    
                         arrival time                          -0.560    
  -------------------------------------------------------------------
                         slack                                  4.465    

Slack (MET) :             4.496ns  (required time - arrival time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[7]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[7].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             mmcm_clkout6
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            5.000ns  (MaxDelay Path 5.000ns)
  Data Path Delay:        0.529ns  (logic 0.081ns (15.312%)  route 0.448ns (84.688%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 5.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X91Y308                                     0.000     0.000 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[7]/C
    SLICE_X91Y308        FDRE (Prop_DFF2_SLICEL_C_Q)
                                                      0.081     0.081 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[7]/Q
                         net (fo=1, routed)           0.448     0.529    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[31].sync_reg_reg[0]_0[7]
    SLICE_X90Y312        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[7].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    5.000     5.000    
    SLICE_X90Y312        FDRE (Setup_DFF2_SLICEM_C_D)
                                                      0.025     5.025    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[7].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                          5.025    
                         arrival time                          -0.529    
  -------------------------------------------------------------------
                         slack                                  4.496    

Slack (MET) :             4.518ns  (required time - arrival time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[6]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[6].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             mmcm_clkout6
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            5.000ns  (MaxDelay Path 5.000ns)
  Data Path Delay:        0.507ns  (logic 0.077ns (15.187%)  route 0.430ns (84.813%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 5.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X90Y316                                     0.000     0.000 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[6]/C
    SLICE_X90Y316        FDRE (Prop_CFF2_SLICEM_C_Q)
                                                      0.077     0.077 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[6]/Q
                         net (fo=1, routed)           0.430     0.507    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[31].sync_reg_reg[0]_0[6]
    SLICE_X89Y316        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[6].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    5.000     5.000    
    SLICE_X89Y316        FDRE (Setup_GFF2_SLICEM_C_D)
                                                      0.025     5.025    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[6].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                          5.025    
                         arrival time                          -0.507    
  -------------------------------------------------------------------
                         slack                                  4.518    

Slack (MET) :             4.523ns  (required time - arrival time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[26]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[26].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             mmcm_clkout6
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            5.000ns  (MaxDelay Path 5.000ns)
  Data Path Delay:        0.502ns  (logic 0.079ns (15.737%)  route 0.423ns (84.263%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 5.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X94Y282                                     0.000     0.000 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[26]/C
    SLICE_X94Y282        FDRE (Prop_HFF_SLICEM_C_Q)
                                                      0.079     0.079 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[26]/Q
                         net (fo=1, routed)           0.423     0.502    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[31].sync_reg_reg[0]_0[26]
    SLICE_X90Y282        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[26].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    5.000     5.000    
    SLICE_X90Y282        FDRE (Setup_DFF2_SLICEM_C_D)
                                                      0.025     5.025    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[26].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                          5.025    
                         arrival time                          -0.502    
  -------------------------------------------------------------------
                         slack                                  4.523    

Slack (MET) :             4.542ns  (required time - arrival time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[29]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[29].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             mmcm_clkout6
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            5.000ns  (MaxDelay Path 5.000ns)
  Data Path Delay:        0.483ns  (logic 0.076ns (15.735%)  route 0.407ns (84.265%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 5.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X93Y318                                     0.000     0.000 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[29]/C
    SLICE_X93Y318        FDRE (Prop_FFF_SLICEM_C_Q)
                                                      0.076     0.076 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[29]/Q
                         net (fo=1, routed)           0.407     0.483    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[31].sync_reg_reg[0]_0[29]
    SLICE_X90Y318        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[29].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    5.000     5.000    
    SLICE_X90Y318        FDRE (Setup_DFF2_SLICEM_C_D)
                                                      0.025     5.025    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[29].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                          5.025    
                         arrival time                          -0.483    
  -------------------------------------------------------------------
                         slack                                  4.542    

Slack (MET) :             4.563ns  (required time - arrival time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[13]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[13].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             mmcm_clkout6
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            5.000ns  (MaxDelay Path 5.000ns)
  Data Path Delay:        0.462ns  (logic 0.078ns (16.883%)  route 0.384ns (83.117%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 5.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X96Y309                                     0.000     0.000 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[13]/C
    SLICE_X96Y309        FDRE (Prop_HFF2_SLICEM_C_Q)
                                                      0.078     0.078 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[13]/Q
                         net (fo=1, routed)           0.384     0.462    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[31].sync_reg_reg[0]_0[13]
    SLICE_X94Y315        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[13].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    5.000     5.000    
    SLICE_X94Y315        FDRE (Setup_HFF2_SLICEM_C_D)
                                                      0.025     5.025    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[13].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                          5.025    
                         arrival time                          -0.462    
  -------------------------------------------------------------------
                         slack                                  4.563    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.128ns  (arrival time - required time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/sample_gts_reg/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/sample_gts_riu_reg/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             mmcm_clkout6
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (mmcm_clkout6 rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.539ns  (logic 0.039ns (7.236%)  route 0.500ns (92.764%))
  Logic Levels:           0  
  Clock Path Skew:        0.177ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.835ns
    Source Clock Delay      (SCD):    2.913ns
    Clock Pessimism Removal (CPR):    -0.254ns
  Clock Uncertainty:      0.188ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      1.065ns (routing 0.384ns, distribution 0.681ns)
  Clock Net Delay (Destination): 1.208ns (routing 0.438ns, distribution 0.770ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.839     1.456    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.686 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.145     1.831    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.848 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.065     2.913    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/dReg_reg[10]
    SLICE_X83Y295        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/sample_gts_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X83Y295        FDRE (Prop_DFF_SLICEM_C_Q)
                                                      0.039     2.952 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/sample_gts_reg/Q
                         net (fo=1, routed)           0.500     3.452    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/sample_gts
    SLICE_X81Y295        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/sample_gts_riu_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.940     1.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.295     1.432 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.176     1.608    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y104        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.627 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.208     2.835    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/CLK
    SLICE_X81Y295        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/sample_gts_riu_reg/C
                         clock pessimism              0.254     3.089    
                         clock uncertainty            0.188     3.278    
    SLICE_X81Y295        FDRE (Hold_EFF_SLICEL_C_D)
                                                      0.046     3.324    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/sample_gts_riu_reg
  -------------------------------------------------------------------
                         required time                         -3.324    
                         arrival time                           3.452    
  -------------------------------------------------------------------
                         slack                                  0.128    





---------------------------------------------------------------------------------------------------
Path Group:  **async_default**
From Clock:  clk_out1_d_1_clk_adc0_x2_0
  To Clock:  clk_out1_d_1_clk_adc0_x2_0

Setup :            0  Failing Endpoints,  Worst Slack        0.518ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.144ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.518ns  (required time - arrival time)
  Source:                 d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_5/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/trigger_resync_i/data_int_reg_reg[1]/CLR
                            (recovery check against rising-edge clock clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            1.953ns  (clk_out1_d_1_clk_adc0_x2_0 rise@1.953ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        1.226ns  (logic 0.079ns (6.446%)  route 1.147ns (93.554%))
  Logic Levels:           0  
  Clock Path Skew:        -0.092ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    6.251ns = ( 8.204 - 1.953 ) 
    Source Clock Delay      (SCD):    6.254ns
    Clock Pessimism Removal (CPR):    -0.089ns
  Clock Uncertainty:      0.051ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.074ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.924ns (routing 1.545ns, distribution 1.379ns)
  Clock Net Delay (Destination): 2.606ns (routing 1.400ns, distribution 1.206ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.657     3.184    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     3.057 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     3.302    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.330 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86296, routed)       2.924     6.254    d_1_i/rst_adc0_x2/U0/slowest_sync_clk
    SLICE_X70Y125        FDRE                                         r  d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_5/C
  -------------------------------------------------------------------    -------------------
    SLICE_X70Y125        FDRE (Prop_EFF2_SLICEM_C_Q)
                                                      0.079     6.333 r  d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_5/Q
                         net (fo=318, routed)         1.147     7.480    d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/trigger_resync_i/peripheral_aresetn[0]_repN_5_alias
    SLICE_X75Y149        FDCE                                         f  d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/trigger_resync_i/data_int_reg_reg[1]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      1.953     1.953 r  
    HSADC_X0Y0           HSADC                        0.000     1.953 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     2.075 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     2.225    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     2.339 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.389     4.728    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.358 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.216     5.574    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     5.598 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86296, routed)       2.606     8.204    d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/trigger_resync_i/s00_axis_aclk
    SLICE_X75Y149        FDCE                                         r  d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/trigger_resync_i/data_int_reg_reg[1]/C
                         clock pessimism             -0.089     8.115    
                         clock uncertainty           -0.051     8.063    
    SLICE_X75Y149        FDCE (Recov_EFF_SLICEM_C_CLR)
                                                     -0.066     7.997    d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/trigger_resync_i/data_int_reg_reg[1]
  -------------------------------------------------------------------
                         required time                          7.997    
                         arrival time                          -7.480    
  -------------------------------------------------------------------
                         slack                                  0.518    

Slack (MET) :             0.551ns  (required time - arrival time)
  Source:                 d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_28/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/DW_CAPTURE_REG_resync_i/data_int_reg_reg[1]/CLR
                            (recovery check against rising-edge clock clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            1.953ns  (clk_out1_d_1_clk_adc0_x2_0 rise@1.953ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        1.114ns  (logic 0.079ns (7.090%)  route 1.035ns (92.910%))
  Logic Levels:           0  
  Clock Path Skew:        -0.170ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    6.391ns = ( 8.344 - 1.953 ) 
    Source Clock Delay      (SCD):    6.414ns
    Clock Pessimism Removal (CPR):    -0.147ns
  Clock Uncertainty:      0.051ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.074ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      3.084ns (routing 1.545ns, distribution 1.539ns)
  Clock Net Delay (Destination): 2.746ns (routing 1.400ns, distribution 1.346ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.657     3.184    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     3.057 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     3.302    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.330 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86296, routed)       3.084     6.414    d_1_i/rst_adc0_x2/U0/slowest_sync_clk
    SLICE_X93Y110        FDRE                                         r  d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_28/C
  -------------------------------------------------------------------    -------------------
    SLICE_X93Y110        FDRE (Prop_EFF2_SLICEM_C_Q)
                                                      0.079     6.493 r  d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_28/Q
                         net (fo=59, routed)          1.035     7.528    d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/DW_CAPTURE_REG_resync_i/peripheral_aresetn[0]_repN_28_alias
    SLICE_X88Y121        FDCE                                         f  d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/DW_CAPTURE_REG_resync_i/data_int_reg_reg[1]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      1.953     1.953 r  
    HSADC_X0Y0           HSADC                        0.000     1.953 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     2.075 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     2.225    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     2.339 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.389     4.728    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.358 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.216     5.574    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     5.598 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86296, routed)       2.746     8.344    d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/DW_CAPTURE_REG_resync_i/s00_axis_aclk
    SLICE_X88Y121        FDCE                                         r  d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/DW_CAPTURE_REG_resync_i/data_int_reg_reg[1]/C
                         clock pessimism             -0.147     8.197    
                         clock uncertainty           -0.051     8.146    
    SLICE_X88Y121        FDCE (Recov_EFF_SLICEL_C_CLR)
                                                     -0.066     8.080    d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/DW_CAPTURE_REG_resync_i/data_int_reg_reg[1]
  -------------------------------------------------------------------
                         required time                          8.080    
                         arrival time                          -7.528    
  -------------------------------------------------------------------
                         slack                                  0.551    

Slack (MET) :             0.734ns  (required time - arrival time)
  Source:                 d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_5/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/trigger_resync_i/data_int_reg_reg[0]/CLR
                            (recovery check against rising-edge clock clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            1.953ns  (clk_out1_d_1_clk_adc0_x2_0 rise@1.953ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        1.046ns  (logic 0.079ns (7.555%)  route 0.967ns (92.445%))
  Logic Levels:           0  
  Clock Path Skew:        -0.056ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    6.239ns = ( 8.192 - 1.953 ) 
    Source Clock Delay      (SCD):    6.254ns
    Clock Pessimism Removal (CPR):    -0.041ns
  Clock Uncertainty:      0.051ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.074ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.924ns (routing 1.545ns, distribution 1.379ns)
  Clock Net Delay (Destination): 2.594ns (routing 1.400ns, distribution 1.194ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.657     3.184    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     3.057 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     3.302    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.330 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86296, routed)       2.924     6.254    d_1_i/rst_adc0_x2/U0/slowest_sync_clk
    SLICE_X70Y125        FDRE                                         r  d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_5/C
  -------------------------------------------------------------------    -------------------
    SLICE_X70Y125        FDRE (Prop_EFF2_SLICEM_C_Q)
                                                      0.079     6.333 r  d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_5/Q
                         net (fo=318, routed)         0.967     7.300    d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/trigger_resync_i/peripheral_aresetn[0]_repN_5_alias
    SLICE_X70Y148        FDCE                                         f  d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/trigger_resync_i/data_int_reg_reg[0]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      1.953     1.953 r  
    HSADC_X0Y0           HSADC                        0.000     1.953 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     2.075 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     2.225    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     2.339 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.389     4.728    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.358 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.216     5.574    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     5.598 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86296, routed)       2.594     8.192    d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/trigger_resync_i/s00_axis_aclk
    SLICE_X70Y148        FDCE                                         r  d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/trigger_resync_i/data_int_reg_reg[0]/C
                         clock pessimism             -0.041     8.151    
                         clock uncertainty           -0.051     8.100    
    SLICE_X70Y148        FDCE (Recov_AFF_SLICEM_C_CLR)
                                                     -0.066     8.034    d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/trigger_resync_i/data_int_reg_reg[0]
  -------------------------------------------------------------------
                         required time                          8.034    
                         arrival time                          -7.300    
  -------------------------------------------------------------------
                         slack                                  0.734    

Slack (MET) :             1.469ns  (required time - arrival time)
  Source:                 d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_6/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/DW_CAPTURE_REG_resync_i/data_int_reg_reg[0]/CLR
                            (recovery check against rising-edge clock clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            1.953ns  (clk_out1_d_1_clk_adc0_x2_0 rise@1.953ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        0.332ns  (logic 0.079ns (23.789%)  route 0.253ns (76.211%))
  Logic Levels:           0  
  Clock Path Skew:        -0.035ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    6.370ns = ( 8.323 - 1.953 ) 
    Source Clock Delay      (SCD):    6.375ns
    Clock Pessimism Removal (CPR):    -0.030ns
  Clock Uncertainty:      0.051ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.074ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      3.045ns (routing 1.545ns, distribution 1.500ns)
  Clock Net Delay (Destination): 2.725ns (routing 1.400ns, distribution 1.325ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.657     3.184    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     3.057 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     3.302    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.330 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86296, routed)       3.045     6.375    d_1_i/rst_adc0_x2/U0/slowest_sync_clk
    SLICE_X81Y120        FDRE                                         r  d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_6/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y120        FDRE (Prop_HFF_SLICEL_C_Q)
                                                      0.079     6.454 r  d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_6/Q
                         net (fo=35, routed)          0.253     6.707    d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/DW_CAPTURE_REG_resync_i/peripheral_aresetn[0]_repN_6_alias
    SLICE_X81Y121        FDCE                                         f  d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/DW_CAPTURE_REG_resync_i/data_int_reg_reg[0]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      1.953     1.953 r  
    HSADC_X0Y0           HSADC                        0.000     1.953 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     2.075 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     2.225    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     2.339 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.389     4.728    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.358 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.216     5.574    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     5.598 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86296, routed)       2.725     8.323    d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/DW_CAPTURE_REG_resync_i/s00_axis_aclk
    SLICE_X81Y121        FDCE                                         r  d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/DW_CAPTURE_REG_resync_i/data_int_reg_reg[0]/C
                         clock pessimism             -0.030     8.293    
                         clock uncertainty           -0.051     8.242    
    SLICE_X81Y121        FDCE (Recov_EFF_SLICEL_C_CLR)
                                                     -0.066     8.176    d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/DW_CAPTURE_REG_resync_i/data_int_reg_reg[0]
  -------------------------------------------------------------------
                         required time                          8.176    
                         arrival time                          -6.707    
  -------------------------------------------------------------------
                         slack                                  1.469    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.144ns  (arrival time - required time)
  Source:                 d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_6/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/DW_CAPTURE_REG_resync_i/data_int_reg_reg[0]/CLR
                            (removal check against rising-edge clock clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        0.144ns  (logic 0.039ns (27.043%)  route 0.105ns (72.957%))
  Logic Levels:           0  
  Clock Path Skew:        0.020ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.748ns
    Source Clock Delay      (SCD):    3.782ns
    Clock Pessimism Removal (CPR):    -0.053ns
  Clock Net Delay (Source):      1.675ns (routing 0.846ns, distribution 0.829ns)
  Clock Net Delay (Destination): 1.882ns (routing 0.950ns, distribution 0.932ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.451     1.714    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.944 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     2.090    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.107 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86296, routed)       1.675     3.782    d_1_i/rst_adc0_x2/U0/slowest_sync_clk
    SLICE_X81Y120        FDRE                                         r  d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_6/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y120        FDRE (Prop_HFF_SLICEL_C_Q)
                                                      0.039     3.821 r  d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_6/Q
                         net (fo=35, routed)          0.105     3.926    d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/DW_CAPTURE_REG_resync_i/peripheral_aresetn[0]_repN_6_alias
    SLICE_X81Y121        FDCE                                         f  d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/DW_CAPTURE_REG_resync_i/data_int_reg_reg[0]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.624     1.976    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.681 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.847    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.866 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86296, routed)       1.882     3.748    d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/DW_CAPTURE_REG_resync_i/s00_axis_aclk
    SLICE_X81Y121        FDCE                                         r  d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/DW_CAPTURE_REG_resync_i/data_int_reg_reg[0]/C
                         clock pessimism              0.053     3.802    
    SLICE_X81Y121        FDCE (Remov_EFF_SLICEL_C_CLR)
                                                     -0.020     3.782    d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/DW_CAPTURE_REG_resync_i/data_int_reg_reg[0]
  -------------------------------------------------------------------
                         required time                         -3.782    
                         arrival time                           3.926    
  -------------------------------------------------------------------
                         slack                                  0.144    

Slack (MET) :             0.484ns  (arrival time - required time)
  Source:                 d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_28/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/DW_CAPTURE_REG_resync_i/data_int_reg_reg[1]/CLR
                            (removal check against rising-edge clock clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        0.542ns  (logic 0.039ns (7.197%)  route 0.503ns (92.803%))
  Logic Levels:           0  
  Clock Path Skew:        0.078ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.758ns
    Source Clock Delay      (SCD):    3.804ns
    Clock Pessimism Removal (CPR):    -0.124ns
  Clock Net Delay (Source):      1.697ns (routing 0.846ns, distribution 0.851ns)
  Clock Net Delay (Destination): 1.892ns (routing 0.950ns, distribution 0.942ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.451     1.714    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.944 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     2.090    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.107 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86296, routed)       1.697     3.804    d_1_i/rst_adc0_x2/U0/slowest_sync_clk
    SLICE_X93Y110        FDRE                                         r  d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_28/C
  -------------------------------------------------------------------    -------------------
    SLICE_X93Y110        FDRE (Prop_EFF2_SLICEM_C_Q)
                                                      0.039     3.843 r  d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_28/Q
                         net (fo=59, routed)          0.503     4.346    d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/DW_CAPTURE_REG_resync_i/peripheral_aresetn[0]_repN_28_alias
    SLICE_X88Y121        FDCE                                         f  d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/DW_CAPTURE_REG_resync_i/data_int_reg_reg[1]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.624     1.976    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.681 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.847    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.866 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86296, routed)       1.892     3.758    d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/DW_CAPTURE_REG_resync_i/s00_axis_aclk
    SLICE_X88Y121        FDCE                                         r  d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/DW_CAPTURE_REG_resync_i/data_int_reg_reg[1]/C
                         clock pessimism              0.124     3.882    
    SLICE_X88Y121        FDCE (Remov_EFF_SLICEL_C_CLR)
                                                     -0.020     3.862    d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/DW_CAPTURE_REG_resync_i/data_int_reg_reg[1]
  -------------------------------------------------------------------
                         required time                         -3.862    
                         arrival time                           4.346    
  -------------------------------------------------------------------
                         slack                                  0.484    

Slack (MET) :             0.524ns  (arrival time - required time)
  Source:                 d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_5/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/trigger_resync_i/data_int_reg_reg[0]/CLR
                            (removal check against rising-edge clock clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        0.510ns  (logic 0.039ns (7.652%)  route 0.471ns (92.348%))
  Logic Levels:           0  
  Clock Path Skew:        0.005ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.660ns
    Source Clock Delay      (SCD):    3.715ns
    Clock Pessimism Removal (CPR):    -0.060ns
  Clock Net Delay (Source):      1.608ns (routing 0.846ns, distribution 0.762ns)
  Clock Net Delay (Destination): 1.794ns (routing 0.950ns, distribution 0.844ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.451     1.714    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.944 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     2.090    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.107 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86296, routed)       1.608     3.715    d_1_i/rst_adc0_x2/U0/slowest_sync_clk
    SLICE_X70Y125        FDRE                                         r  d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_5/C
  -------------------------------------------------------------------    -------------------
    SLICE_X70Y125        FDRE (Prop_EFF2_SLICEM_C_Q)
                                                      0.039     3.754 r  d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_5/Q
                         net (fo=318, routed)         0.471     4.224    d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/trigger_resync_i/peripheral_aresetn[0]_repN_5_alias
    SLICE_X70Y148        FDCE                                         f  d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/trigger_resync_i/data_int_reg_reg[0]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.624     1.976    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.681 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.847    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.866 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86296, routed)       1.794     3.660    d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/trigger_resync_i/s00_axis_aclk
    SLICE_X70Y148        FDCE                                         r  d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/trigger_resync_i/data_int_reg_reg[0]/C
                         clock pessimism              0.060     3.720    
    SLICE_X70Y148        FDCE (Remov_AFF_SLICEM_C_CLR)
                                                     -0.020     3.700    d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/trigger_resync_i/data_int_reg_reg[0]
  -------------------------------------------------------------------
                         required time                         -3.700    
                         arrival time                           4.224    
  -------------------------------------------------------------------
                         slack                                  0.524    

Slack (MET) :             0.584ns  (arrival time - required time)
  Source:                 d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_5/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/trigger_resync_i/data_int_reg_reg[1]/CLR
                            (removal check against rising-edge clock clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        0.604ns  (logic 0.039ns (6.461%)  route 0.565ns (93.539%))
  Logic Levels:           0  
  Clock Path Skew:        0.039ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.666ns
    Source Clock Delay      (SCD):    3.715ns
    Clock Pessimism Removal (CPR):    -0.088ns
  Clock Net Delay (Source):      1.608ns (routing 0.846ns, distribution 0.762ns)
  Clock Net Delay (Destination): 1.800ns (routing 0.950ns, distribution 0.850ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.451     1.714    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.944 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     2.090    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.107 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86296, routed)       1.608     3.715    d_1_i/rst_adc0_x2/U0/slowest_sync_clk
    SLICE_X70Y125        FDRE                                         r  d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_5/C
  -------------------------------------------------------------------    -------------------
    SLICE_X70Y125        FDRE (Prop_EFF2_SLICEM_C_Q)
                                                      0.039     3.754 r  d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_5/Q
                         net (fo=318, routed)         0.565     4.318    d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/trigger_resync_i/peripheral_aresetn[0]_repN_5_alias
    SLICE_X75Y149        FDCE                                         f  d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/trigger_resync_i/data_int_reg_reg[1]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.624     1.976    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.681 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.847    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.866 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86296, routed)       1.800     3.666    d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/trigger_resync_i/s00_axis_aclk
    SLICE_X75Y149        FDCE                                         r  d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/trigger_resync_i/data_int_reg_reg[1]/C
                         clock pessimism              0.088     3.754    
    SLICE_X75Y149        FDCE (Remov_EFF_SLICEM_C_CLR)
                                                     -0.020     3.734    d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/trigger_resync_i/data_int_reg_reg[1]
  -------------------------------------------------------------------
                         required time                         -3.734    
                         arrival time                           4.318    
  -------------------------------------------------------------------
                         slack                                  0.584    





---------------------------------------------------------------------------------------------------
Path Group:  **async_default**
From Clock:  clk_out1_d_1_clk_core_0
  To Clock:  clk_out1_d_1_clk_core_0

Setup :            0  Failing Endpoints,  Worst Slack        1.795ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.111ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             1.795ns  (required time - arrival time)
  Source:                 d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_18/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/dreg_32_dt_reg[0][28]/CLR
                            (recovery check against rising-edge clock clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            5.000ns  (clk_out1_d_1_clk_core_0 rise@5.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        2.921ns  (logic 0.077ns (2.636%)  route 2.844ns (97.363%))
  Logic Levels:           0  
  Clock Path Skew:        -0.156ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.275ns = ( 10.275 - 5.000 ) 
    Source Clock Delay      (SCD):    5.158ns
    Clock Pessimism Removal (CPR):    -0.273ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.102ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.644ns (routing 1.461ns, distribution 1.183ns)
  Clock Net Delay (Destination): 2.293ns (routing 1.325ns, distribution 0.968ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=48236, routed)       2.142     2.368    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.241 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.486    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y133        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.514 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=4540, routed)        2.644     5.158    d_1_i/rst_core/U0/slowest_sync_clk
    SLICE_X96Y127        FDRE                                         r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_18/C
  -------------------------------------------------------------------    -------------------
    SLICE_X96Y127        FDRE (Prop_AFF_SLICEM_C_Q)
                                                      0.077     5.235 r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_18/Q
                         net (fo=240, routed)         2.844     8.079    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/peripheral_aresetn[0]_repN_18_alias
    SLICE_X57Y151        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/dreg_32_dt_reg[0][28]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      5.000     5.000 r  
    PS8_X0Y0             PS8                          0.000     5.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     5.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     5.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=48236, routed)       1.931     7.113    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     7.743 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     7.958    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y133        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     7.982 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=4540, routed)        2.293    10.275    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/c_clk_i
    SLICE_X57Y151        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/dreg_32_dt_reg[0][28]/C
                         clock pessimism             -0.273    10.002    
                         clock uncertainty           -0.062     9.940    
    SLICE_X57Y151        FDCE (Recov_DFF_SLICEL_C_CLR)
                                                     -0.066     9.874    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/dreg_32_dt_reg[0][28]
  -------------------------------------------------------------------
                         required time                          9.874    
                         arrival time                          -8.079    
  -------------------------------------------------------------------
                         slack                                  1.795    

Slack (MET) :             1.795ns  (required time - arrival time)
  Source:                 d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_18/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/dreg_32_dt_reg[2][25]/CLR
                            (recovery check against rising-edge clock clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            5.000ns  (clk_out1_d_1_clk_core_0 rise@5.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        2.921ns  (logic 0.077ns (2.636%)  route 2.844ns (97.363%))
  Logic Levels:           0  
  Clock Path Skew:        -0.156ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.275ns = ( 10.275 - 5.000 ) 
    Source Clock Delay      (SCD):    5.158ns
    Clock Pessimism Removal (CPR):    -0.273ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.102ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.644ns (routing 1.461ns, distribution 1.183ns)
  Clock Net Delay (Destination): 2.293ns (routing 1.325ns, distribution 0.968ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=48236, routed)       2.142     2.368    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.241 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.486    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y133        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.514 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=4540, routed)        2.644     5.158    d_1_i/rst_core/U0/slowest_sync_clk
    SLICE_X96Y127        FDRE                                         r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_18/C
  -------------------------------------------------------------------    -------------------
    SLICE_X96Y127        FDRE (Prop_AFF_SLICEM_C_Q)
                                                      0.077     5.235 r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_18/Q
                         net (fo=240, routed)         2.844     8.079    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/peripheral_aresetn[0]_repN_18_alias
    SLICE_X57Y151        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/dreg_32_dt_reg[2][25]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      5.000     5.000 r  
    PS8_X0Y0             PS8                          0.000     5.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     5.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     5.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=48236, routed)       1.931     7.113    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     7.743 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     7.958    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y133        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     7.982 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=4540, routed)        2.293    10.275    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/c_clk_i
    SLICE_X57Y151        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/dreg_32_dt_reg[2][25]/C
                         clock pessimism             -0.273    10.002    
                         clock uncertainty           -0.062     9.940    
    SLICE_X57Y151        FDCE (Recov_DFF2_SLICEL_C_CLR)
                                                     -0.066     9.874    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/dreg_32_dt_reg[2][25]
  -------------------------------------------------------------------
                         required time                          9.874    
                         arrival time                          -8.079    
  -------------------------------------------------------------------
                         slack                                  1.795    

Slack (MET) :             1.843ns  (required time - arrival time)
  Source:                 d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_18/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/dreg_32_dt_reg[13][22]/CLR
                            (recovery check against rising-edge clock clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            5.000ns  (clk_out1_d_1_clk_core_0 rise@5.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        2.877ns  (logic 0.077ns (2.677%)  route 2.800ns (97.323%))
  Logic Levels:           0  
  Clock Path Skew:        -0.152ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.279ns = ( 10.279 - 5.000 ) 
    Source Clock Delay      (SCD):    5.158ns
    Clock Pessimism Removal (CPR):    -0.273ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.102ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.644ns (routing 1.461ns, distribution 1.183ns)
  Clock Net Delay (Destination): 2.297ns (routing 1.325ns, distribution 0.972ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=48236, routed)       2.142     2.368    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.241 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.486    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y133        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.514 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=4540, routed)        2.644     5.158    d_1_i/rst_core/U0/slowest_sync_clk
    SLICE_X96Y127        FDRE                                         r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_18/C
  -------------------------------------------------------------------    -------------------
    SLICE_X96Y127        FDRE (Prop_AFF_SLICEM_C_Q)
                                                      0.077     5.235 r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_18/Q
                         net (fo=240, routed)         2.800     8.035    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/peripheral_aresetn[0]_repN_18_alias
    SLICE_X59Y146        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/dreg_32_dt_reg[13][22]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      5.000     5.000 r  
    PS8_X0Y0             PS8                          0.000     5.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     5.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     5.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=48236, routed)       1.931     7.113    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     7.743 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     7.958    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y133        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     7.982 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=4540, routed)        2.297    10.279    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/c_clk_i
    SLICE_X59Y146        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/dreg_32_dt_reg[13][22]/C
                         clock pessimism             -0.273    10.006    
                         clock uncertainty           -0.062     9.944    
    SLICE_X59Y146        FDCE (Recov_DFF2_SLICEL_C_CLR)
                                                     -0.066     9.878    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/dreg_32_dt_reg[13][22]
  -------------------------------------------------------------------
                         required time                          9.878    
                         arrival time                          -8.035    
  -------------------------------------------------------------------
                         slack                                  1.843    

Slack (MET) :             1.843ns  (required time - arrival time)
  Source:                 d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_18/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/dreg_32_dt_reg[2][23]/CLR
                            (recovery check against rising-edge clock clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            5.000ns  (clk_out1_d_1_clk_core_0 rise@5.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        2.877ns  (logic 0.077ns (2.677%)  route 2.800ns (97.323%))
  Logic Levels:           0  
  Clock Path Skew:        -0.152ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.279ns = ( 10.279 - 5.000 ) 
    Source Clock Delay      (SCD):    5.158ns
    Clock Pessimism Removal (CPR):    -0.273ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.102ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.644ns (routing 1.461ns, distribution 1.183ns)
  Clock Net Delay (Destination): 2.297ns (routing 1.325ns, distribution 0.972ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=48236, routed)       2.142     2.368    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.241 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.486    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y133        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.514 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=4540, routed)        2.644     5.158    d_1_i/rst_core/U0/slowest_sync_clk
    SLICE_X96Y127        FDRE                                         r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_18/C
  -------------------------------------------------------------------    -------------------
    SLICE_X96Y127        FDRE (Prop_AFF_SLICEM_C_Q)
                                                      0.077     5.235 r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_18/Q
                         net (fo=240, routed)         2.800     8.035    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/peripheral_aresetn[0]_repN_18_alias
    SLICE_X59Y146        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/dreg_32_dt_reg[2][23]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      5.000     5.000 r  
    PS8_X0Y0             PS8                          0.000     5.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     5.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     5.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=48236, routed)       1.931     7.113    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     7.743 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     7.958    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y133        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     7.982 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=4540, routed)        2.297    10.279    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/c_clk_i
    SLICE_X59Y146        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/dreg_32_dt_reg[2][23]/C
                         clock pessimism             -0.273    10.006    
                         clock uncertainty           -0.062     9.944    
    SLICE_X59Y146        FDCE (Recov_DFF_SLICEL_C_CLR)
                                                     -0.066     9.878    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/dreg_32_dt_reg[2][23]
  -------------------------------------------------------------------
                         required time                          9.878    
                         arrival time                          -8.035    
  -------------------------------------------------------------------
                         slack                                  1.843    

Slack (MET) :             1.989ns  (required time - arrival time)
  Source:                 d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_18/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/reg_D_reg[0][26]/CLR
                            (recovery check against rising-edge clock clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            5.000ns  (clk_out1_d_1_clk_core_0 rise@5.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        2.711ns  (logic 0.077ns (2.841%)  route 2.634ns (97.159%))
  Logic Levels:           0  
  Clock Path Skew:        -0.172ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.259ns = ( 10.259 - 5.000 ) 
    Source Clock Delay      (SCD):    5.158ns
    Clock Pessimism Removal (CPR):    -0.273ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.102ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.644ns (routing 1.461ns, distribution 1.183ns)
  Clock Net Delay (Destination): 2.277ns (routing 1.325ns, distribution 0.952ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=48236, routed)       2.142     2.368    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.241 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.486    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y133        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.514 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=4540, routed)        2.644     5.158    d_1_i/rst_core/U0/slowest_sync_clk
    SLICE_X96Y127        FDRE                                         r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_18/C
  -------------------------------------------------------------------    -------------------
    SLICE_X96Y127        FDRE (Prop_AFF_SLICEM_C_Q)
                                                      0.077     5.235 r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_18/Q
                         net (fo=240, routed)         2.634     7.869    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/peripheral_aresetn[0]_repN_18_alias
    SLICE_X60Y149        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/reg_D_reg[0][26]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      5.000     5.000 r  
    PS8_X0Y0             PS8                          0.000     5.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     5.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     5.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=48236, routed)       1.931     7.113    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     7.743 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     7.958    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y133        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     7.982 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=4540, routed)        2.277    10.259    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/c_clk_i
    SLICE_X60Y149        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/reg_D_reg[0][26]/C
                         clock pessimism             -0.273     9.986    
                         clock uncertainty           -0.062     9.924    
    SLICE_X60Y149        FDCE (Recov_DFF_SLICEM_C_CLR)
                                                     -0.066     9.858    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/reg_D_reg[0][26]
  -------------------------------------------------------------------
                         required time                          9.858    
                         arrival time                          -7.869    
  -------------------------------------------------------------------
                         slack                                  1.989    

Slack (MET) :             2.034ns  (required time - arrival time)
  Source:                 d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_18/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/dreg_32_dt_reg[3][28]/CLR
                            (recovery check against rising-edge clock clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            5.000ns  (clk_out1_d_1_clk_core_0 rise@5.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        2.685ns  (logic 0.077ns (2.868%)  route 2.608ns (97.132%))
  Logic Levels:           0  
  Clock Path Skew:        -0.153ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.278ns = ( 10.278 - 5.000 ) 
    Source Clock Delay      (SCD):    5.158ns
    Clock Pessimism Removal (CPR):    -0.273ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.102ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.644ns (routing 1.461ns, distribution 1.183ns)
  Clock Net Delay (Destination): 2.296ns (routing 1.325ns, distribution 0.971ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=48236, routed)       2.142     2.368    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.241 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.486    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y133        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.514 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=4540, routed)        2.644     5.158    d_1_i/rst_core/U0/slowest_sync_clk
    SLICE_X96Y127        FDRE                                         r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_18/C
  -------------------------------------------------------------------    -------------------
    SLICE_X96Y127        FDRE (Prop_AFF_SLICEM_C_Q)
                                                      0.077     5.235 r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_18/Q
                         net (fo=240, routed)         2.608     7.843    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/peripheral_aresetn[0]_repN_18_alias
    SLICE_X56Y150        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/dreg_32_dt_reg[3][28]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      5.000     5.000 r  
    PS8_X0Y0             PS8                          0.000     5.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     5.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     5.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=48236, routed)       1.931     7.113    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     7.743 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     7.958    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y133        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     7.982 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=4540, routed)        2.296    10.278    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/c_clk_i
    SLICE_X56Y150        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/dreg_32_dt_reg[3][28]/C
                         clock pessimism             -0.273    10.005    
                         clock uncertainty           -0.062     9.943    
    SLICE_X56Y150        FDCE (Recov_AFF_SLICEM_C_CLR)
                                                     -0.066     9.877    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/dreg_32_dt_reg[3][28]
  -------------------------------------------------------------------
                         required time                          9.877    
                         arrival time                          -7.843    
  -------------------------------------------------------------------
                         slack                                  2.034    

Slack (MET) :             2.056ns  (required time - arrival time)
  Source:                 d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_18/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/dreg_32_dt_reg[10][27]/CLR
                            (recovery check against rising-edge clock clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            5.000ns  (clk_out1_d_1_clk_core_0 rise@5.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        2.666ns  (logic 0.077ns (2.888%)  route 2.589ns (97.112%))
  Logic Levels:           0  
  Clock Path Skew:        -0.150ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.281ns = ( 10.281 - 5.000 ) 
    Source Clock Delay      (SCD):    5.158ns
    Clock Pessimism Removal (CPR):    -0.273ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.102ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.644ns (routing 1.461ns, distribution 1.183ns)
  Clock Net Delay (Destination): 2.299ns (routing 1.325ns, distribution 0.974ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=48236, routed)       2.142     2.368    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.241 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.486    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y133        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.514 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=4540, routed)        2.644     5.158    d_1_i/rst_core/U0/slowest_sync_clk
    SLICE_X96Y127        FDRE                                         r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_18/C
  -------------------------------------------------------------------    -------------------
    SLICE_X96Y127        FDRE (Prop_AFF_SLICEM_C_Q)
                                                      0.077     5.235 r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_18/Q
                         net (fo=240, routed)         2.589     7.824    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/peripheral_aresetn[0]_repN_18_alias
    SLICE_X55Y150        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/dreg_32_dt_reg[10][27]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      5.000     5.000 r  
    PS8_X0Y0             PS8                          0.000     5.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     5.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     5.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=48236, routed)       1.931     7.113    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     7.743 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     7.958    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y133        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     7.982 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=4540, routed)        2.299    10.281    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/c_clk_i
    SLICE_X55Y150        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/dreg_32_dt_reg[10][27]/C
                         clock pessimism             -0.273    10.008    
                         clock uncertainty           -0.062     9.946    
    SLICE_X55Y150        FDCE (Recov_EFF_SLICEL_C_CLR)
                                                     -0.066     9.880    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/dreg_32_dt_reg[10][27]
  -------------------------------------------------------------------
                         required time                          9.880    
                         arrival time                          -7.824    
  -------------------------------------------------------------------
                         slack                                  2.056    

Slack (MET) :             2.088ns  (required time - arrival time)
  Source:                 d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_18/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/dreg_32_dt_reg[15][16]/CLR
                            (recovery check against rising-edge clock clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            5.000ns  (clk_out1_d_1_clk_core_0 rise@5.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        2.647ns  (logic 0.077ns (2.909%)  route 2.570ns (97.091%))
  Logic Levels:           0  
  Clock Path Skew:        -0.137ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.294ns = ( 10.294 - 5.000 ) 
    Source Clock Delay      (SCD):    5.158ns
    Clock Pessimism Removal (CPR):    -0.273ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.102ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.644ns (routing 1.461ns, distribution 1.183ns)
  Clock Net Delay (Destination): 2.312ns (routing 1.325ns, distribution 0.987ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=48236, routed)       2.142     2.368    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.241 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.486    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y133        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.514 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=4540, routed)        2.644     5.158    d_1_i/rst_core/U0/slowest_sync_clk
    SLICE_X96Y127        FDRE                                         r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_18/C
  -------------------------------------------------------------------    -------------------
    SLICE_X96Y127        FDRE (Prop_AFF_SLICEM_C_Q)
                                                      0.077     5.235 r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_18/Q
                         net (fo=240, routed)         2.570     7.805    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/peripheral_aresetn[0]_repN_18_alias
    SLICE_X56Y139        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/dreg_32_dt_reg[15][16]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      5.000     5.000 r  
    PS8_X0Y0             PS8                          0.000     5.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     5.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     5.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=48236, routed)       1.931     7.113    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     7.743 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     7.958    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y133        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     7.982 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=4540, routed)        2.312    10.294    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/c_clk_i
    SLICE_X56Y139        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/dreg_32_dt_reg[15][16]/C
                         clock pessimism             -0.273    10.021    
                         clock uncertainty           -0.062     9.959    
    SLICE_X56Y139        FDCE (Recov_DFF_SLICEM_C_CLR)
                                                     -0.066     9.893    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/dreg_32_dt_reg[15][16]
  -------------------------------------------------------------------
                         required time                          9.893    
                         arrival time                          -7.805    
  -------------------------------------------------------------------
                         slack                                  2.088    

Slack (MET) :             2.088ns  (required time - arrival time)
  Source:                 d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_18/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/sreg_dt_reg[1][11]/CLR
                            (recovery check against rising-edge clock clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            5.000ns  (clk_out1_d_1_clk_core_0 rise@5.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        2.647ns  (logic 0.077ns (2.909%)  route 2.570ns (97.091%))
  Logic Levels:           0  
  Clock Path Skew:        -0.137ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.294ns = ( 10.294 - 5.000 ) 
    Source Clock Delay      (SCD):    5.158ns
    Clock Pessimism Removal (CPR):    -0.273ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.102ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.644ns (routing 1.461ns, distribution 1.183ns)
  Clock Net Delay (Destination): 2.312ns (routing 1.325ns, distribution 0.987ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=48236, routed)       2.142     2.368    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.241 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.486    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y133        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.514 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=4540, routed)        2.644     5.158    d_1_i/rst_core/U0/slowest_sync_clk
    SLICE_X96Y127        FDRE                                         r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_18/C
  -------------------------------------------------------------------    -------------------
    SLICE_X96Y127        FDRE (Prop_AFF_SLICEM_C_Q)
                                                      0.077     5.235 r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_18/Q
                         net (fo=240, routed)         2.570     7.805    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/peripheral_aresetn[0]_repN_18_alias
    SLICE_X56Y139        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/sreg_dt_reg[1][11]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      5.000     5.000 r  
    PS8_X0Y0             PS8                          0.000     5.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     5.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     5.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=48236, routed)       1.931     7.113    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     7.743 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     7.958    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y133        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     7.982 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=4540, routed)        2.312    10.294    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/c_clk_i
    SLICE_X56Y139        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/sreg_dt_reg[1][11]/C
                         clock pessimism             -0.273    10.021    
                         clock uncertainty           -0.062     9.959    
    SLICE_X56Y139        FDCE (Recov_DFF2_SLICEM_C_CLR)
                                                     -0.066     9.893    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/sreg_dt_reg[1][11]
  -------------------------------------------------------------------
                         required time                          9.893    
                         arrival time                          -7.805    
  -------------------------------------------------------------------
                         slack                                  2.088    

Slack (MET) :             2.088ns  (required time - arrival time)
  Source:                 d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_18/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/sreg_dt_reg[1][13]/CLR
                            (recovery check against rising-edge clock clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            5.000ns  (clk_out1_d_1_clk_core_0 rise@5.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        2.647ns  (logic 0.077ns (2.909%)  route 2.570ns (97.091%))
  Logic Levels:           0  
  Clock Path Skew:        -0.137ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.294ns = ( 10.294 - 5.000 ) 
    Source Clock Delay      (SCD):    5.158ns
    Clock Pessimism Removal (CPR):    -0.273ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.102ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.644ns (routing 1.461ns, distribution 1.183ns)
  Clock Net Delay (Destination): 2.312ns (routing 1.325ns, distribution 0.987ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=48236, routed)       2.142     2.368    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.241 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.486    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y133        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.514 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=4540, routed)        2.644     5.158    d_1_i/rst_core/U0/slowest_sync_clk
    SLICE_X96Y127        FDRE                                         r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_18/C
  -------------------------------------------------------------------    -------------------
    SLICE_X96Y127        FDRE (Prop_AFF_SLICEM_C_Q)
                                                      0.077     5.235 r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_18/Q
                         net (fo=240, routed)         2.570     7.805    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/peripheral_aresetn[0]_repN_18_alias
    SLICE_X56Y139        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/sreg_dt_reg[1][13]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      5.000     5.000 r  
    PS8_X0Y0             PS8                          0.000     5.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     5.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     5.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=48236, routed)       1.931     7.113    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     7.743 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     7.958    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y133        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     7.982 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=4540, routed)        2.312    10.294    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/c_clk_i
    SLICE_X56Y139        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/sreg_dt_reg[1][13]/C
                         clock pessimism             -0.273    10.021    
                         clock uncertainty           -0.062     9.959    
    SLICE_X56Y139        FDCE (Recov_CFF2_SLICEM_C_CLR)
                                                     -0.066     9.893    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/sreg_dt_reg[1][13]
  -------------------------------------------------------------------
                         required time                          9.893    
                         arrival time                          -7.805    
  -------------------------------------------------------------------
                         slack                                  2.088    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.111ns  (arrival time - required time)
  Source:                 d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/c_fifo_data_in_r_reg[119]/CLR
                            (removal check against rising-edge clock clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_core_0 rise@0.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        0.151ns  (logic 0.038ns (25.188%)  route 0.113ns (74.812%))
  Logic Levels:           0  
  Clock Path Skew:        0.060ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.914ns
    Source Clock Delay      (SCD):    3.066ns
    Clock Pessimism Removal (CPR):    -0.212ns
  Clock Net Delay (Source):      1.380ns (routing 0.804ns, distribution 0.576ns)
  Clock Net Delay (Destination): 1.566ns (routing 0.896ns, distribution 0.670ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=48236, routed)       1.173     1.293    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.523 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.669    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y133        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.686 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=4540, routed)        1.380     3.066    d_1_i/rst_core/U0/slowest_sync_clk
    SLICE_X69Y134        FDRE                                         r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/C
  -------------------------------------------------------------------    -------------------
    SLICE_X69Y134        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.038     3.104 r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/Q
                         net (fo=156, routed)         0.113     3.217    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/peripheral_aresetn[0]_repN_alias
    SLICE_X68Y134        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/c_fifo_data_in_r_reg[119]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=48236, routed)       1.311     1.458    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.163 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.329    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y133        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.348 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=4540, routed)        1.566     2.914    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/c_clk_i
    SLICE_X68Y134        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/c_fifo_data_in_r_reg[119]/C
                         clock pessimism              0.212     3.126    
    SLICE_X68Y134        FDCE (Remov_HFF_SLICEL_C_CLR)
                                                     -0.020     3.106    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/c_fifo_data_in_r_reg[119]
  -------------------------------------------------------------------
                         required time                         -3.106    
                         arrival time                           3.217    
  -------------------------------------------------------------------
                         slack                                  0.111    

Slack (MET) :             0.111ns  (arrival time - required time)
  Source:                 d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/c_fifo_data_in_r_reg[50]/CLR
                            (removal check against rising-edge clock clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_core_0 rise@0.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        0.151ns  (logic 0.038ns (25.188%)  route 0.113ns (74.812%))
  Logic Levels:           0  
  Clock Path Skew:        0.060ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.914ns
    Source Clock Delay      (SCD):    3.066ns
    Clock Pessimism Removal (CPR):    -0.212ns
  Clock Net Delay (Source):      1.380ns (routing 0.804ns, distribution 0.576ns)
  Clock Net Delay (Destination): 1.566ns (routing 0.896ns, distribution 0.670ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=48236, routed)       1.173     1.293    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.523 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.669    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y133        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.686 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=4540, routed)        1.380     3.066    d_1_i/rst_core/U0/slowest_sync_clk
    SLICE_X69Y134        FDRE                                         r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/C
  -------------------------------------------------------------------    -------------------
    SLICE_X69Y134        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.038     3.104 r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/Q
                         net (fo=156, routed)         0.113     3.217    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/peripheral_aresetn[0]_repN_alias
    SLICE_X68Y134        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/c_fifo_data_in_r_reg[50]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=48236, routed)       1.311     1.458    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.163 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.329    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y133        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.348 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=4540, routed)        1.566     2.914    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/c_clk_i
    SLICE_X68Y134        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/c_fifo_data_in_r_reg[50]/C
                         clock pessimism              0.212     3.126    
    SLICE_X68Y134        FDCE (Remov_GFF_SLICEL_C_CLR)
                                                     -0.020     3.106    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/c_fifo_data_in_r_reg[50]
  -------------------------------------------------------------------
                         required time                         -3.106    
                         arrival time                           3.217    
  -------------------------------------------------------------------
                         slack                                  0.111    

Slack (MET) :             0.120ns  (arrival time - required time)
  Source:                 d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_11/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/dreg_32_dt_reg[7][31]/CLR
                            (removal check against rising-edge clock clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_core_0 rise@0.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        0.146ns  (logic 0.039ns (26.755%)  route 0.107ns (73.245%))
  Logic Levels:           0  
  Clock Path Skew:        0.046ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.951ns
    Source Clock Delay      (SCD):    3.114ns
    Clock Pessimism Removal (CPR):    -0.208ns
  Clock Net Delay (Source):      1.428ns (routing 0.804ns, distribution 0.624ns)
  Clock Net Delay (Destination): 1.603ns (routing 0.896ns, distribution 0.707ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=48236, routed)       1.173     1.293    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.523 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.669    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y133        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.686 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=4540, routed)        1.428     3.114    d_1_i/rst_core/U0/slowest_sync_clk
    SLICE_X52Y147        FDRE                                         r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_11/C
  -------------------------------------------------------------------    -------------------
    SLICE_X52Y147        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.039     3.153 r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_11/Q
                         net (fo=154, routed)         0.107     3.259    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/peripheral_aresetn[0]_repN_11_alias
    SLICE_X53Y147        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/dreg_32_dt_reg[7][31]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=48236, routed)       1.311     1.458    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.163 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.329    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y133        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.348 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=4540, routed)        1.603     2.951    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/c_clk_i
    SLICE_X53Y147        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/dreg_32_dt_reg[7][31]/C
                         clock pessimism              0.208     3.159    
    SLICE_X53Y147        FDCE (Remov_HFF2_SLICEM_C_CLR)
                                                     -0.020     3.139    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/dreg_32_dt_reg[7][31]
  -------------------------------------------------------------------
                         required time                         -3.139    
                         arrival time                           3.259    
  -------------------------------------------------------------------
                         slack                                  0.120    

Slack (MET) :             0.120ns  (arrival time - required time)
  Source:                 d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_11/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/sreg_dt_reg[1][24]/CLR
                            (removal check against rising-edge clock clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_core_0 rise@0.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        0.146ns  (logic 0.039ns (26.755%)  route 0.107ns (73.245%))
  Logic Levels:           0  
  Clock Path Skew:        0.046ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.951ns
    Source Clock Delay      (SCD):    3.114ns
    Clock Pessimism Removal (CPR):    -0.208ns
  Clock Net Delay (Source):      1.428ns (routing 0.804ns, distribution 0.624ns)
  Clock Net Delay (Destination): 1.603ns (routing 0.896ns, distribution 0.707ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=48236, routed)       1.173     1.293    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.523 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.669    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y133        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.686 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=4540, routed)        1.428     3.114    d_1_i/rst_core/U0/slowest_sync_clk
    SLICE_X52Y147        FDRE                                         r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_11/C
  -------------------------------------------------------------------    -------------------
    SLICE_X52Y147        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.039     3.153 r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_11/Q
                         net (fo=154, routed)         0.107     3.259    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/peripheral_aresetn[0]_repN_11_alias
    SLICE_X53Y147        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/sreg_dt_reg[1][24]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=48236, routed)       1.311     1.458    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.163 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.329    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y133        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.348 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=4540, routed)        1.603     2.951    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/c_clk_i
    SLICE_X53Y147        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/sreg_dt_reg[1][24]/C
                         clock pessimism              0.208     3.159    
    SLICE_X53Y147        FDCE (Remov_HFF_SLICEM_C_CLR)
                                                     -0.020     3.139    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/sreg_dt_reg[1][24]
  -------------------------------------------------------------------
                         required time                         -3.139    
                         arrival time                           3.259    
  -------------------------------------------------------------------
                         slack                                  0.120    

Slack (MET) :             0.139ns  (arrival time - required time)
  Source:                 d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_8/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[13].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[4]/CLR
                            (removal check against rising-edge clock clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_core_0 rise@0.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        0.142ns  (logic 0.039ns (27.543%)  route 0.103ns (72.457%))
  Logic Levels:           0  
  Clock Path Skew:        0.022ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.043ns
    Source Clock Delay      (SCD):    3.188ns
    Clock Pessimism Removal (CPR):    -0.167ns
  Clock Net Delay (Source):      1.502ns (routing 0.804ns, distribution 0.698ns)
  Clock Net Delay (Destination): 1.695ns (routing 0.896ns, distribution 0.799ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=48236, routed)       1.173     1.293    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.523 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.669    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y133        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.686 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=4540, routed)        1.502     3.188    d_1_i/rst_core/U0/slowest_sync_clk
    SLICE_X58Y185        FDRE                                         r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_8/C
  -------------------------------------------------------------------    -------------------
    SLICE_X58Y185        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.039     3.227 r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_8/Q
                         net (fo=142, routed)         0.103     3.330    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[13].trig_fifo_inst/gcc_wr_ptr/peripheral_aresetn[0]_repN_8_alias
    SLICE_X58Y186        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[13].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[4]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=48236, routed)       1.311     1.458    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.163 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.329    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y133        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.348 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=4540, routed)        1.695     3.043    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[13].trig_fifo_inst/gcc_wr_ptr/c_clk_i
    SLICE_X58Y186        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[13].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[4]/C
                         clock pessimism              0.167     3.210    
    SLICE_X58Y186        FDCE (Remov_HFF_SLICEL_C_CLR)
                                                     -0.020     3.190    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[13].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[4]
  -------------------------------------------------------------------
                         required time                         -3.190    
                         arrival time                           3.330    
  -------------------------------------------------------------------
                         slack                                  0.139    

Slack (MET) :             0.139ns  (arrival time - required time)
  Source:                 d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_8/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[13].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[8]/CLR
                            (removal check against rising-edge clock clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_core_0 rise@0.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        0.142ns  (logic 0.039ns (27.543%)  route 0.103ns (72.457%))
  Logic Levels:           0  
  Clock Path Skew:        0.022ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.043ns
    Source Clock Delay      (SCD):    3.188ns
    Clock Pessimism Removal (CPR):    -0.167ns
  Clock Net Delay (Source):      1.502ns (routing 0.804ns, distribution 0.698ns)
  Clock Net Delay (Destination): 1.695ns (routing 0.896ns, distribution 0.799ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=48236, routed)       1.173     1.293    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.523 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.669    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y133        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.686 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=4540, routed)        1.502     3.188    d_1_i/rst_core/U0/slowest_sync_clk
    SLICE_X58Y185        FDRE                                         r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_8/C
  -------------------------------------------------------------------    -------------------
    SLICE_X58Y185        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.039     3.227 r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_8/Q
                         net (fo=142, routed)         0.103     3.330    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[13].trig_fifo_inst/gcc_wr_ptr/peripheral_aresetn[0]_repN_8_alias
    SLICE_X58Y186        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[13].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[8]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=48236, routed)       1.311     1.458    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.163 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.329    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y133        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.348 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=4540, routed)        1.695     3.043    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[13].trig_fifo_inst/gcc_wr_ptr/c_clk_i
    SLICE_X58Y186        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[13].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[8]/C
                         clock pessimism              0.167     3.210    
    SLICE_X58Y186        FDCE (Remov_GFF_SLICEL_C_CLR)
                                                     -0.020     3.190    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[13].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[8]
  -------------------------------------------------------------------
                         required time                         -3.190    
                         arrival time                           3.330    
  -------------------------------------------------------------------
                         slack                                  0.139    

Slack (MET) :             0.139ns  (arrival time - required time)
  Source:                 d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_8/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[13].trig_fifo_inst/gcc_wr_ptr/count_gray_r_reg[7]/CLR
                            (removal check against rising-edge clock clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_core_0 rise@0.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        0.142ns  (logic 0.039ns (27.543%)  route 0.103ns (72.457%))
  Logic Levels:           0  
  Clock Path Skew:        0.022ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.043ns
    Source Clock Delay      (SCD):    3.188ns
    Clock Pessimism Removal (CPR):    -0.167ns
  Clock Net Delay (Source):      1.502ns (routing 0.804ns, distribution 0.698ns)
  Clock Net Delay (Destination): 1.695ns (routing 0.896ns, distribution 0.799ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=48236, routed)       1.173     1.293    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.523 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.669    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y133        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.686 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=4540, routed)        1.502     3.188    d_1_i/rst_core/U0/slowest_sync_clk
    SLICE_X58Y185        FDRE                                         r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_8/C
  -------------------------------------------------------------------    -------------------
    SLICE_X58Y185        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.039     3.227 r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_8/Q
                         net (fo=142, routed)         0.103     3.330    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[13].trig_fifo_inst/gcc_wr_ptr/peripheral_aresetn[0]_repN_8_alias
    SLICE_X58Y186        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[13].trig_fifo_inst/gcc_wr_ptr/count_gray_r_reg[7]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=48236, routed)       1.311     1.458    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.163 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.329    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y133        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.348 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=4540, routed)        1.695     3.043    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[13].trig_fifo_inst/gcc_wr_ptr/c_clk_i
    SLICE_X58Y186        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[13].trig_fifo_inst/gcc_wr_ptr/count_gray_r_reg[7]/C
                         clock pessimism              0.167     3.210    
    SLICE_X58Y186        FDCE (Remov_FFF_SLICEL_C_CLR)
                                                     -0.020     3.190    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[13].trig_fifo_inst/gcc_wr_ptr/count_gray_r_reg[7]
  -------------------------------------------------------------------
                         required time                         -3.190    
                         arrival time                           3.330    
  -------------------------------------------------------------------
                         slack                                  0.139    

Slack (MET) :             0.139ns  (arrival time - required time)
  Source:                 d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_8/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[13].trig_fifo_inst/gcc_wr_ptr/count_gray_r_reg[8]/CLR
                            (removal check against rising-edge clock clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_core_0 rise@0.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        0.142ns  (logic 0.039ns (27.543%)  route 0.103ns (72.457%))
  Logic Levels:           0  
  Clock Path Skew:        0.022ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.043ns
    Source Clock Delay      (SCD):    3.188ns
    Clock Pessimism Removal (CPR):    -0.167ns
  Clock Net Delay (Source):      1.502ns (routing 0.804ns, distribution 0.698ns)
  Clock Net Delay (Destination): 1.695ns (routing 0.896ns, distribution 0.799ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=48236, routed)       1.173     1.293    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.523 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.669    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y133        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.686 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=4540, routed)        1.502     3.188    d_1_i/rst_core/U0/slowest_sync_clk
    SLICE_X58Y185        FDRE                                         r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_8/C
  -------------------------------------------------------------------    -------------------
    SLICE_X58Y185        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.039     3.227 r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_8/Q
                         net (fo=142, routed)         0.103     3.330    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[13].trig_fifo_inst/gcc_wr_ptr/peripheral_aresetn[0]_repN_8_alias
    SLICE_X58Y186        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[13].trig_fifo_inst/gcc_wr_ptr/count_gray_r_reg[8]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=48236, routed)       1.311     1.458    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.163 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.329    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y133        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.348 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=4540, routed)        1.695     3.043    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[13].trig_fifo_inst/gcc_wr_ptr/c_clk_i
    SLICE_X58Y186        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[13].trig_fifo_inst/gcc_wr_ptr/count_gray_r_reg[8]/C
                         clock pessimism              0.167     3.210    
    SLICE_X58Y186        FDCE (Remov_EFF_SLICEL_C_CLR)
                                                     -0.020     3.190    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[13].trig_fifo_inst/gcc_wr_ptr/count_gray_r_reg[8]
  -------------------------------------------------------------------
                         required time                         -3.190    
                         arrival time                           3.330    
  -------------------------------------------------------------------
                         slack                                  0.139    

Slack (MET) :             0.142ns  (arrival time - required time)
  Source:                 d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_12/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/wreg_32_dt_reg[5][29]/CLR
                            (removal check against rising-edge clock clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_core_0 rise@0.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        0.168ns  (logic 0.038ns (22.662%)  route 0.130ns (77.338%))
  Logic Levels:           0  
  Clock Path Skew:        0.046ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.972ns
    Source Clock Delay      (SCD):    3.134ns
    Clock Pessimism Removal (CPR):    -0.208ns
  Clock Net Delay (Source):      1.448ns (routing 0.804ns, distribution 0.644ns)
  Clock Net Delay (Destination): 1.624ns (routing 0.896ns, distribution 0.728ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=48236, routed)       1.173     1.293    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.523 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.669    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y133        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.686 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=4540, routed)        1.448     3.134    d_1_i/rst_core/U0/slowest_sync_clk
    SLICE_X48Y131        FDRE                                         r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_12/C
  -------------------------------------------------------------------    -------------------
    SLICE_X48Y131        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.038     3.172 r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_12/Q
                         net (fo=24, routed)          0.130     3.302    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/peripheral_aresetn[0]_repN_12_alias
    SLICE_X47Y129        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/wreg_32_dt_reg[5][29]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=48236, routed)       1.311     1.458    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.163 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.329    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y133        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.348 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=4540, routed)        1.624     2.972    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/c_clk_i
    SLICE_X47Y129        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/wreg_32_dt_reg[5][29]/C
                         clock pessimism              0.208     3.180    
    SLICE_X47Y129        FDCE (Remov_EFF_SLICEL_C_CLR)
                                                     -0.020     3.160    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/wreg_32_dt_reg[5][29]
  -------------------------------------------------------------------
                         required time                         -3.160    
                         arrival time                           3.302    
  -------------------------------------------------------------------
                         slack                                  0.142    

Slack (MET) :             0.144ns  (arrival time - required time)
  Source:                 d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_4/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/QPER_ARITH.ARITH/C_dt_reg[0]/CLR
                            (removal check against rising-edge clock clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_core_0 rise@0.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        0.146ns  (logic 0.038ns (25.973%)  route 0.108ns (74.027%))
  Logic Levels:           0  
  Clock Path Skew:        0.022ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.967ns
    Source Clock Delay      (SCD):    3.123ns
    Clock Pessimism Removal (CPR):    -0.177ns
  Clock Net Delay (Source):      1.437ns (routing 0.804ns, distribution 0.633ns)
  Clock Net Delay (Destination): 1.619ns (routing 0.896ns, distribution 0.723ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=48236, routed)       1.173     1.293    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.523 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.669    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y133        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.686 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=4540, routed)        1.437     3.123    d_1_i/rst_core/U0/slowest_sync_clk
    SLICE_X48Y146        FDRE                                         r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_4/C
  -------------------------------------------------------------------    -------------------
    SLICE_X48Y146        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.038     3.161 r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_4/Q
                         net (fo=227, routed)         0.108     3.269    d_1_i/qick_processor_0/inst/QPROC/QPER_ARITH.ARITH/peripheral_aresetn[0]_repN_4_alias
    SLICE_X49Y148        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/QPER_ARITH.ARITH/C_dt_reg[0]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=48236, routed)       1.311     1.458    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.163 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.329    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y133        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.348 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=4540, routed)        1.619     2.967    d_1_i/qick_processor_0/inst/QPROC/QPER_ARITH.ARITH/c_clk_i
    SLICE_X49Y148        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPER_ARITH.ARITH/C_dt_reg[0]/C
                         clock pessimism              0.177     3.144    
    SLICE_X49Y148        FDCE (Remov_EFF_SLICEL_C_CLR)
                                                     -0.020     3.124    d_1_i/qick_processor_0/inst/QPROC/QPER_ARITH.ARITH/C_dt_reg[0]
  -------------------------------------------------------------------
                         required time                         -3.124    
                         arrival time                           3.269    
  -------------------------------------------------------------------
                         slack                                  0.144    





---------------------------------------------------------------------------------------------------
Path Group:  **async_default**
From Clock:  clk_pl_0
  To Clock:  clk_pl_0

Setup :            0  Failing Endpoints,  Worst Slack        6.825ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.192ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             6.825ns  (required time - arrival time)
  Source:                 d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[1][10]/CLR
                            (recovery check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk_pl_0 rise@10.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        2.497ns  (logic 0.107ns (4.285%)  route 2.390ns (95.715%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        -0.482ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.010ns = ( 12.010 - 10.000 ) 
    Source Clock Delay      (SCD):    2.620ns
    Clock Pessimism Removal (CPR):    0.129ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.394ns (routing 0.662ns, distribution 1.732ns)
  Clock Net Delay (Destination): 1.828ns (routing 0.599ns, distribution 1.229ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       2.394     2.620    d_1_i/rst_100/U0/slowest_sync_clk
    SLICE_X102Y71        FDRE                                         r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X102Y71        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     2.699 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           1.019     3.718    d_1_i/rst_100/U0/peripheral_aresetn[0]_bufg_place
    BUFGCE_X0Y44         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.746 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_bufg_place/O
                         net (fo=13331, routed)       1.371     5.117    d_1_i/qick_processor_0/inst/QPROC/QMEM_CTRL_n_1
    SLICE_X42Y134        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[1][10]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                     10.000    10.000 r  
    PS8_X0Y0             PS8                          0.000    10.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157    10.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025    10.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.828    12.010    d_1_i/qick_processor_0/inst/QPROC/ps_clk_i
    SLICE_X42Y134        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[1][10]/C
                         clock pessimism              0.129    12.139    
                         clock uncertainty           -0.130    12.009    
    SLICE_X42Y134        FDCE (Recov_DFF_SLICEM_C_CLR)
                                                     -0.066    11.943    d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[1][10]
  -------------------------------------------------------------------
                         required time                         11.943    
                         arrival time                          -5.117    
  -------------------------------------------------------------------
                         slack                                  6.825    

Slack (MET) :             6.826ns  (required time - arrival time)
  Source:                 d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[1][19]/CLR
                            (recovery check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk_pl_0 rise@10.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        2.493ns  (logic 0.107ns (4.292%)  route 2.386ns (95.708%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        -0.485ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.007ns = ( 12.007 - 10.000 ) 
    Source Clock Delay      (SCD):    2.620ns
    Clock Pessimism Removal (CPR):    0.129ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.394ns (routing 0.662ns, distribution 1.732ns)
  Clock Net Delay (Destination): 1.825ns (routing 0.599ns, distribution 1.226ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       2.394     2.620    d_1_i/rst_100/U0/slowest_sync_clk
    SLICE_X102Y71        FDRE                                         r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X102Y71        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     2.699 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           1.019     3.718    d_1_i/rst_100/U0/peripheral_aresetn[0]_bufg_place
    BUFGCE_X0Y44         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.746 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_bufg_place/O
                         net (fo=13331, routed)       1.367     5.113    d_1_i/qick_processor_0/inst/QPROC/QMEM_CTRL_n_1
    SLICE_X42Y138        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[1][19]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                     10.000    10.000 r  
    PS8_X0Y0             PS8                          0.000    10.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157    10.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025    10.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.825    12.007    d_1_i/qick_processor_0/inst/QPROC/ps_clk_i
    SLICE_X42Y138        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[1][19]/C
                         clock pessimism              0.129    12.136    
                         clock uncertainty           -0.130    12.006    
    SLICE_X42Y138        FDCE (Recov_DFF_SLICEM_C_CLR)
                                                     -0.066    11.940    d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[1][19]
  -------------------------------------------------------------------
                         required time                         11.940    
                         arrival time                          -5.113    
  -------------------------------------------------------------------
                         slack                                  6.826    

Slack (MET) :             6.826ns  (required time - arrival time)
  Source:                 d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[0][6]/CLR
                            (recovery check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk_pl_0 rise@10.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        2.496ns  (logic 0.107ns (4.287%)  route 2.389ns (95.713%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        -0.482ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.010ns = ( 12.010 - 10.000 ) 
    Source Clock Delay      (SCD):    2.620ns
    Clock Pessimism Removal (CPR):    0.129ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.394ns (routing 0.662ns, distribution 1.732ns)
  Clock Net Delay (Destination): 1.828ns (routing 0.599ns, distribution 1.229ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       2.394     2.620    d_1_i/rst_100/U0/slowest_sync_clk
    SLICE_X102Y71        FDRE                                         r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X102Y71        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     2.699 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           1.019     3.718    d_1_i/rst_100/U0/peripheral_aresetn[0]_bufg_place
    BUFGCE_X0Y44         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.746 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_bufg_place/O
                         net (fo=13331, routed)       1.370     5.116    d_1_i/qick_processor_0/inst/QPROC/QMEM_CTRL_n_1
    SLICE_X42Y135        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[0][6]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                     10.000    10.000 r  
    PS8_X0Y0             PS8                          0.000    10.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157    10.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025    10.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.828    12.010    d_1_i/qick_processor_0/inst/QPROC/ps_clk_i
    SLICE_X42Y135        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[0][6]/C
                         clock pessimism              0.129    12.139    
                         clock uncertainty           -0.130    12.009    
    SLICE_X42Y135        FDCE (Recov_BFF_SLICEM_C_CLR)
                                                     -0.066    11.943    d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[0][6]
  -------------------------------------------------------------------
                         required time                         11.943    
                         arrival time                          -5.116    
  -------------------------------------------------------------------
                         slack                                  6.826    

Slack (MET) :             6.827ns  (required time - arrival time)
  Source:                 d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[1][18]/CLR
                            (recovery check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk_pl_0 rise@10.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        2.488ns  (logic 0.107ns (4.301%)  route 2.381ns (95.699%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        -0.490ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.002ns = ( 12.002 - 10.000 ) 
    Source Clock Delay      (SCD):    2.620ns
    Clock Pessimism Removal (CPR):    0.129ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.394ns (routing 0.662ns, distribution 1.732ns)
  Clock Net Delay (Destination): 1.820ns (routing 0.599ns, distribution 1.221ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       2.394     2.620    d_1_i/rst_100/U0/slowest_sync_clk
    SLICE_X102Y71        FDRE                                         r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X102Y71        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     2.699 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           1.019     3.718    d_1_i/rst_100/U0/peripheral_aresetn[0]_bufg_place
    BUFGCE_X0Y44         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.746 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_bufg_place/O
                         net (fo=13331, routed)       1.362     5.108    d_1_i/qick_processor_0/inst/QPROC/QMEM_CTRL_n_1
    SLICE_X41Y135        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[1][18]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                     10.000    10.000 r  
    PS8_X0Y0             PS8                          0.000    10.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157    10.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025    10.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.820    12.002    d_1_i/qick_processor_0/inst/QPROC/ps_clk_i
    SLICE_X41Y135        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[1][18]/C
                         clock pessimism              0.129    12.131    
                         clock uncertainty           -0.130    12.001    
    SLICE_X41Y135        FDCE (Recov_CFF_SLICEM_C_CLR)
                                                     -0.066    11.935    d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[1][18]
  -------------------------------------------------------------------
                         required time                         11.935    
                         arrival time                          -5.108    
  -------------------------------------------------------------------
                         slack                                  6.827    

Slack (MET) :             6.828ns  (required time - arrival time)
  Source:                 d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[1][24]/CLR
                            (recovery check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk_pl_0 rise@10.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        2.472ns  (logic 0.107ns (4.328%)  route 2.365ns (95.672%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        -0.505ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    1.987ns = ( 11.987 - 10.000 ) 
    Source Clock Delay      (SCD):    2.620ns
    Clock Pessimism Removal (CPR):    0.129ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.394ns (routing 0.662ns, distribution 1.732ns)
  Clock Net Delay (Destination): 1.805ns (routing 0.599ns, distribution 1.206ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       2.394     2.620    d_1_i/rst_100/U0/slowest_sync_clk
    SLICE_X102Y71        FDRE                                         r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X102Y71        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     2.699 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           1.019     3.718    d_1_i/rst_100/U0/peripheral_aresetn[0]_bufg_place
    BUFGCE_X0Y44         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.746 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_bufg_place/O
                         net (fo=13331, routed)       1.346     5.092    d_1_i/qick_processor_0/inst/QPROC/QMEM_CTRL_n_1
    SLICE_X41Y148        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[1][24]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                     10.000    10.000 r  
    PS8_X0Y0             PS8                          0.000    10.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157    10.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025    10.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.805    11.987    d_1_i/qick_processor_0/inst/QPROC/ps_clk_i
    SLICE_X41Y148        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[1][24]/C
                         clock pessimism              0.129    12.116    
                         clock uncertainty           -0.130    11.986    
    SLICE_X41Y148        FDCE (Recov_DFF_SLICEM_C_CLR)
                                                     -0.066    11.920    d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[1][24]
  -------------------------------------------------------------------
                         required time                         11.920    
                         arrival time                          -5.092    
  -------------------------------------------------------------------
                         slack                                  6.828    

Slack (MET) :             6.828ns  (required time - arrival time)
  Source:                 d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[1][27]/CLR
                            (recovery check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk_pl_0 rise@10.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        2.472ns  (logic 0.107ns (4.328%)  route 2.365ns (95.672%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        -0.505ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    1.987ns = ( 11.987 - 10.000 ) 
    Source Clock Delay      (SCD):    2.620ns
    Clock Pessimism Removal (CPR):    0.129ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.394ns (routing 0.662ns, distribution 1.732ns)
  Clock Net Delay (Destination): 1.805ns (routing 0.599ns, distribution 1.206ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       2.394     2.620    d_1_i/rst_100/U0/slowest_sync_clk
    SLICE_X102Y71        FDRE                                         r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X102Y71        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     2.699 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           1.019     3.718    d_1_i/rst_100/U0/peripheral_aresetn[0]_bufg_place
    BUFGCE_X0Y44         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.746 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_bufg_place/O
                         net (fo=13331, routed)       1.346     5.092    d_1_i/qick_processor_0/inst/QPROC/QMEM_CTRL_n_1
    SLICE_X41Y148        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[1][27]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                     10.000    10.000 r  
    PS8_X0Y0             PS8                          0.000    10.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157    10.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025    10.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.805    11.987    d_1_i/qick_processor_0/inst/QPROC/ps_clk_i
    SLICE_X41Y148        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[1][27]/C
                         clock pessimism              0.129    12.116    
                         clock uncertainty           -0.130    11.986    
    SLICE_X41Y148        FDCE (Recov_CFF_SLICEM_C_CLR)
                                                     -0.066    11.920    d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[1][27]
  -------------------------------------------------------------------
                         required time                         11.920    
                         arrival time                          -5.092    
  -------------------------------------------------------------------
                         slack                                  6.828    

Slack (MET) :             6.828ns  (required time - arrival time)
  Source:                 d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[1][6]/CLR
                            (recovery check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk_pl_0 rise@10.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        2.490ns  (logic 0.107ns (4.297%)  route 2.383ns (95.703%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        -0.486ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.006ns = ( 12.006 - 10.000 ) 
    Source Clock Delay      (SCD):    2.620ns
    Clock Pessimism Removal (CPR):    0.129ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.394ns (routing 0.662ns, distribution 1.732ns)
  Clock Net Delay (Destination): 1.824ns (routing 0.599ns, distribution 1.225ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       2.394     2.620    d_1_i/rst_100/U0/slowest_sync_clk
    SLICE_X102Y71        FDRE                                         r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X102Y71        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     2.699 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           1.019     3.718    d_1_i/rst_100/U0/peripheral_aresetn[0]_bufg_place
    BUFGCE_X0Y44         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.746 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_bufg_place/O
                         net (fo=13331, routed)       1.364     5.110    d_1_i/qick_processor_0/inst/QPROC/QMEM_CTRL_n_1
    SLICE_X42Y138        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[1][6]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                     10.000    10.000 r  
    PS8_X0Y0             PS8                          0.000    10.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157    10.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025    10.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.824    12.006    d_1_i/qick_processor_0/inst/QPROC/ps_clk_i
    SLICE_X42Y138        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[1][6]/C
                         clock pessimism              0.129    12.135    
                         clock uncertainty           -0.130    12.005    
    SLICE_X42Y138        FDCE (Recov_HFF_SLICEM_C_CLR)
                                                     -0.066    11.939    d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[1][6]
  -------------------------------------------------------------------
                         required time                         11.939    
                         arrival time                          -5.110    
  -------------------------------------------------------------------
                         slack                                  6.828    

Slack (MET) :             6.831ns  (required time - arrival time)
  Source:                 d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[1][25]/CLR
                            (recovery check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk_pl_0 rise@10.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        2.457ns  (logic 0.107ns (4.355%)  route 2.350ns (95.645%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        -0.516ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    1.975ns = ( 11.975 - 10.000 ) 
    Source Clock Delay      (SCD):    2.620ns
    Clock Pessimism Removal (CPR):    0.129ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.394ns (routing 0.662ns, distribution 1.732ns)
  Clock Net Delay (Destination): 1.793ns (routing 0.599ns, distribution 1.194ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       2.394     2.620    d_1_i/rst_100/U0/slowest_sync_clk
    SLICE_X102Y71        FDRE                                         r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X102Y71        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     2.699 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           1.019     3.718    d_1_i/rst_100/U0/peripheral_aresetn[0]_bufg_place
    BUFGCE_X0Y44         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.746 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_bufg_place/O
                         net (fo=13331, routed)       1.331     5.077    d_1_i/qick_processor_0/inst/QPROC/QMEM_CTRL_n_1
    SLICE_X41Y151        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[1][25]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                     10.000    10.000 r  
    PS8_X0Y0             PS8                          0.000    10.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157    10.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025    10.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.793    11.975    d_1_i/qick_processor_0/inst/QPROC/ps_clk_i
    SLICE_X41Y151        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[1][25]/C
                         clock pessimism              0.129    12.104    
                         clock uncertainty           -0.130    11.974    
    SLICE_X41Y151        FDCE (Recov_DFF_SLICEM_C_CLR)
                                                     -0.066    11.908    d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[1][25]
  -------------------------------------------------------------------
                         required time                         11.908    
                         arrival time                          -5.077    
  -------------------------------------------------------------------
                         slack                                  6.831    

Slack (MET) :             6.831ns  (required time - arrival time)
  Source:                 d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[1][26]/CLR
                            (recovery check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk_pl_0 rise@10.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        2.457ns  (logic 0.107ns (4.355%)  route 2.350ns (95.645%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        -0.516ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    1.975ns = ( 11.975 - 10.000 ) 
    Source Clock Delay      (SCD):    2.620ns
    Clock Pessimism Removal (CPR):    0.129ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.394ns (routing 0.662ns, distribution 1.732ns)
  Clock Net Delay (Destination): 1.793ns (routing 0.599ns, distribution 1.194ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       2.394     2.620    d_1_i/rst_100/U0/slowest_sync_clk
    SLICE_X102Y71        FDRE                                         r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X102Y71        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     2.699 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           1.019     3.718    d_1_i/rst_100/U0/peripheral_aresetn[0]_bufg_place
    BUFGCE_X0Y44         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.746 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_bufg_place/O
                         net (fo=13331, routed)       1.331     5.077    d_1_i/qick_processor_0/inst/QPROC/QMEM_CTRL_n_1
    SLICE_X41Y151        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[1][26]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                     10.000    10.000 r  
    PS8_X0Y0             PS8                          0.000    10.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157    10.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025    10.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.793    11.975    d_1_i/qick_processor_0/inst/QPROC/ps_clk_i
    SLICE_X41Y151        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[1][26]/C
                         clock pessimism              0.129    12.104    
                         clock uncertainty           -0.130    11.974    
    SLICE_X41Y151        FDCE (Recov_CFF_SLICEM_C_CLR)
                                                     -0.066    11.908    d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[1][26]
  -------------------------------------------------------------------
                         required time                         11.908    
                         arrival time                          -5.077    
  -------------------------------------------------------------------
                         slack                                  6.831    

Slack (MET) :             6.832ns  (required time - arrival time)
  Source:                 d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[1][0]/CLR
                            (recovery check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk_pl_0 rise@10.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        2.469ns  (logic 0.107ns (4.334%)  route 2.362ns (95.666%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        -0.504ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    1.988ns = ( 11.988 - 10.000 ) 
    Source Clock Delay      (SCD):    2.620ns
    Clock Pessimism Removal (CPR):    0.129ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.394ns (routing 0.662ns, distribution 1.732ns)
  Clock Net Delay (Destination): 1.806ns (routing 0.599ns, distribution 1.207ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       2.394     2.620    d_1_i/rst_100/U0/slowest_sync_clk
    SLICE_X102Y71        FDRE                                         r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X102Y71        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     2.699 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           1.019     3.718    d_1_i/rst_100/U0/peripheral_aresetn[0]_bufg_place
    BUFGCE_X0Y44         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.746 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_bufg_place/O
                         net (fo=13331, routed)       1.343     5.089    d_1_i/qick_processor_0/inst/QPROC/QMEM_CTRL_n_1
    SLICE_X40Y141        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[1][0]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                     10.000    10.000 r  
    PS8_X0Y0             PS8                          0.000    10.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157    10.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025    10.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.806    11.988    d_1_i/qick_processor_0/inst/QPROC/ps_clk_i
    SLICE_X40Y141        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[1][0]/C
                         clock pessimism              0.129    12.117    
                         clock uncertainty           -0.130    11.987    
    SLICE_X40Y141        FDCE (Recov_CFF2_SLICEL_C_CLR)
                                                     -0.066    11.921    d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[1][0]
  -------------------------------------------------------------------
                         required time                         11.921    
                         arrival time                          -5.089    
  -------------------------------------------------------------------
                         slack                                  6.832    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.192ns  (arrival time - required time)
  Source:                 d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[3]/CLR
                            (removal check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_pl_0 rise@0.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        0.228ns  (logic 0.074ns (32.417%)  route 0.154ns (67.583%))
  Logic Levels:           1  (LUT3=1)
  Clock Path Skew:        0.056ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.498ns
    Source Clock Delay      (SCD):    1.303ns
    Clock Pessimism Removal (CPR):    0.139ns
  Clock Net Delay (Source):      1.183ns (routing 0.359ns, distribution 0.824ns)
  Clock Net Delay (Destination): 1.351ns (routing 0.405ns, distribution 0.946ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.183     1.303    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/clk
    SLICE_X30Y29         FDRE                                         r  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X30Y29         FDRE (Prop_HFF_SLICEM_C_Q)
                                                      0.039     1.342 f  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[1]/Q
                         net (fo=2, routed)           0.028     1.370    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc[1]
    SLICE_X30Y29         LUT3 (Prop_F6LUT_SLICEM_I0_O)
                                                      0.035     1.405 f  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/gpregsm1.curr_fwft_state[1]_i_2/O
                         net (fo=32, routed)          0.126     1.531    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[4]_1
    SLICE_X29Y28         FDCE                                         f  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[3]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.351     1.498    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/clk
    SLICE_X29Y28         FDCE                                         r  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[3]/C
                         clock pessimism             -0.139     1.359    
    SLICE_X29Y28         FDCE (Remov_EFF_SLICEL_C_CLR)
                                                     -0.020     1.339    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[3]
  -------------------------------------------------------------------
                         required time                         -1.339    
                         arrival time                           1.531    
  -------------------------------------------------------------------
                         slack                                  0.192    

Slack (MET) :             0.192ns  (arrival time - required time)
  Source:                 d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[4]/CLR
                            (removal check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_pl_0 rise@0.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        0.228ns  (logic 0.074ns (32.417%)  route 0.154ns (67.583%))
  Logic Levels:           1  (LUT3=1)
  Clock Path Skew:        0.056ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.498ns
    Source Clock Delay      (SCD):    1.303ns
    Clock Pessimism Removal (CPR):    0.139ns
  Clock Net Delay (Source):      1.183ns (routing 0.359ns, distribution 0.824ns)
  Clock Net Delay (Destination): 1.351ns (routing 0.405ns, distribution 0.946ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.183     1.303    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/clk
    SLICE_X30Y29         FDRE                                         r  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X30Y29         FDRE (Prop_HFF_SLICEM_C_Q)
                                                      0.039     1.342 f  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[1]/Q
                         net (fo=2, routed)           0.028     1.370    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc[1]
    SLICE_X30Y29         LUT3 (Prop_F6LUT_SLICEM_I0_O)
                                                      0.035     1.405 f  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/gpregsm1.curr_fwft_state[1]_i_2/O
                         net (fo=32, routed)          0.126     1.531    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[4]_1
    SLICE_X29Y28         FDCE                                         f  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[4]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.351     1.498    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/clk
    SLICE_X29Y28         FDCE                                         r  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[4]/C
                         clock pessimism             -0.139     1.359    
    SLICE_X29Y28         FDCE (Remov_EFF2_SLICEL_C_CLR)
                                                     -0.020     1.339    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[4]
  -------------------------------------------------------------------
                         required time                         -1.339    
                         arrival time                           1.531    
  -------------------------------------------------------------------
                         slack                                  0.192    

Slack (MET) :             0.195ns  (arrival time - required time)
  Source:                 d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_reg[0]/PRE
                            (removal check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_pl_0 rise@0.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        0.235ns  (logic 0.074ns (31.453%)  route 0.161ns (68.547%))
  Logic Levels:           1  (LUT3=1)
  Clock Path Skew:        0.060ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.502ns
    Source Clock Delay      (SCD):    1.303ns
    Clock Pessimism Removal (CPR):    0.139ns
  Clock Net Delay (Source):      1.183ns (routing 0.359ns, distribution 0.824ns)
  Clock Net Delay (Destination): 1.355ns (routing 0.405ns, distribution 0.950ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.183     1.303    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/clk
    SLICE_X30Y29         FDRE                                         r  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X30Y29         FDRE (Prop_HFF_SLICEM_C_Q)
                                                      0.039     1.342 f  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[1]/Q
                         net (fo=2, routed)           0.028     1.370    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc[1]
    SLICE_X30Y29         LUT3 (Prop_F6LUT_SLICEM_I0_O)
                                                      0.035     1.405 f  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/gpregsm1.curr_fwft_state[1]_i_2/O
                         net (fo=32, routed)          0.133     1.538    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/AR[0]
    SLICE_X28Y28         FDPE                                         f  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_reg[0]/PRE
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.355     1.502    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/clk
    SLICE_X28Y28         FDPE                                         r  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_reg[0]/C
                         clock pessimism             -0.139     1.363    
    SLICE_X28Y28         FDPE (Remov_BFF2_SLICEM_C_PRE)
                                                     -0.020     1.343    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_reg[0]
  -------------------------------------------------------------------
                         required time                         -1.343    
                         arrival time                           1.538    
  -------------------------------------------------------------------
                         slack                                  0.195    

Slack (MET) :             0.195ns  (arrival time - required time)
  Source:                 d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_reg[2]/CLR
                            (removal check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_pl_0 rise@0.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        0.235ns  (logic 0.074ns (31.453%)  route 0.161ns (68.547%))
  Logic Levels:           1  (LUT3=1)
  Clock Path Skew:        0.060ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.502ns
    Source Clock Delay      (SCD):    1.303ns
    Clock Pessimism Removal (CPR):    0.139ns
  Clock Net Delay (Source):      1.183ns (routing 0.359ns, distribution 0.824ns)
  Clock Net Delay (Destination): 1.355ns (routing 0.405ns, distribution 0.950ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.183     1.303    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/clk
    SLICE_X30Y29         FDRE                                         r  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X30Y29         FDRE (Prop_HFF_SLICEM_C_Q)
                                                      0.039     1.342 f  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[1]/Q
                         net (fo=2, routed)           0.028     1.370    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc[1]
    SLICE_X30Y29         LUT3 (Prop_F6LUT_SLICEM_I0_O)
                                                      0.035     1.405 f  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/gpregsm1.curr_fwft_state[1]_i_2/O
                         net (fo=32, routed)          0.133     1.538    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/AR[0]
    SLICE_X28Y28         FDCE                                         f  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_reg[2]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.355     1.502    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/clk
    SLICE_X28Y28         FDCE                                         r  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_reg[2]/C
                         clock pessimism             -0.139     1.363    
    SLICE_X28Y28         FDCE (Remov_AFF2_SLICEM_C_CLR)
                                                     -0.020     1.343    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_reg[2]
  -------------------------------------------------------------------
                         required time                         -1.343    
                         arrival time                           1.538    
  -------------------------------------------------------------------
                         slack                                  0.195    

Slack (MET) :             0.195ns  (arrival time - required time)
  Source:                 d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_reg[3]/CLR
                            (removal check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_pl_0 rise@0.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        0.235ns  (logic 0.074ns (31.453%)  route 0.161ns (68.547%))
  Logic Levels:           1  (LUT3=1)
  Clock Path Skew:        0.060ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.502ns
    Source Clock Delay      (SCD):    1.303ns
    Clock Pessimism Removal (CPR):    0.139ns
  Clock Net Delay (Source):      1.183ns (routing 0.359ns, distribution 0.824ns)
  Clock Net Delay (Destination): 1.355ns (routing 0.405ns, distribution 0.950ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.183     1.303    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/clk
    SLICE_X30Y29         FDRE                                         r  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X30Y29         FDRE (Prop_HFF_SLICEM_C_Q)
                                                      0.039     1.342 f  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[1]/Q
                         net (fo=2, routed)           0.028     1.370    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc[1]
    SLICE_X30Y29         LUT3 (Prop_F6LUT_SLICEM_I0_O)
                                                      0.035     1.405 f  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/gpregsm1.curr_fwft_state[1]_i_2/O
                         net (fo=32, routed)          0.133     1.538    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/AR[0]
    SLICE_X28Y28         FDCE                                         f  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_reg[3]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.355     1.502    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/clk
    SLICE_X28Y28         FDCE                                         r  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_reg[3]/C
                         clock pessimism             -0.139     1.363    
    SLICE_X28Y28         FDCE (Remov_CFF_SLICEM_C_CLR)
                                                     -0.020     1.343    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_reg[3]
  -------------------------------------------------------------------
                         required time                         -1.343    
                         arrival time                           1.538    
  -------------------------------------------------------------------
                         slack                                  0.195    

Slack (MET) :             0.195ns  (arrival time - required time)
  Source:                 d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_reg[4]/CLR
                            (removal check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_pl_0 rise@0.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        0.235ns  (logic 0.074ns (31.453%)  route 0.161ns (68.547%))
  Logic Levels:           1  (LUT3=1)
  Clock Path Skew:        0.060ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.502ns
    Source Clock Delay      (SCD):    1.303ns
    Clock Pessimism Removal (CPR):    0.139ns
  Clock Net Delay (Source):      1.183ns (routing 0.359ns, distribution 0.824ns)
  Clock Net Delay (Destination): 1.355ns (routing 0.405ns, distribution 0.950ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.183     1.303    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/clk
    SLICE_X30Y29         FDRE                                         r  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X30Y29         FDRE (Prop_HFF_SLICEM_C_Q)
                                                      0.039     1.342 f  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[1]/Q
                         net (fo=2, routed)           0.028     1.370    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc[1]
    SLICE_X30Y29         LUT3 (Prop_F6LUT_SLICEM_I0_O)
                                                      0.035     1.405 f  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/gpregsm1.curr_fwft_state[1]_i_2/O
                         net (fo=32, routed)          0.133     1.538    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/AR[0]
    SLICE_X28Y28         FDCE                                         f  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_reg[4]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.355     1.502    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/clk
    SLICE_X28Y28         FDCE                                         r  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_reg[4]/C
                         clock pessimism             -0.139     1.363    
    SLICE_X28Y28         FDCE (Remov_CFF2_SLICEM_C_CLR)
                                                     -0.020     1.343    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_reg[4]
  -------------------------------------------------------------------
                         required time                         -1.343    
                         arrival time                           1.538    
  -------------------------------------------------------------------
                         slack                                  0.195    

Slack (MET) :             0.195ns  (arrival time - required time)
  Source:                 d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_reg[0]/CLR
                            (removal check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_pl_0 rise@0.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        0.234ns  (logic 0.074ns (31.587%)  route 0.160ns (68.413%))
  Logic Levels:           1  (LUT3=1)
  Clock Path Skew:        0.059ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.501ns
    Source Clock Delay      (SCD):    1.303ns
    Clock Pessimism Removal (CPR):    0.139ns
  Clock Net Delay (Source):      1.183ns (routing 0.359ns, distribution 0.824ns)
  Clock Net Delay (Destination): 1.354ns (routing 0.405ns, distribution 0.949ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.183     1.303    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/clk
    SLICE_X30Y29         FDRE                                         r  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X30Y29         FDRE (Prop_HFF_SLICEM_C_Q)
                                                      0.039     1.342 f  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[1]/Q
                         net (fo=2, routed)           0.028     1.370    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc[1]
    SLICE_X30Y29         LUT3 (Prop_F6LUT_SLICEM_I0_O)
                                                      0.035     1.405 f  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/gpregsm1.curr_fwft_state[1]_i_2/O
                         net (fo=32, routed)          0.132     1.537    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/AR[0]
    SLICE_X28Y28         FDCE                                         f  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_reg[0]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.354     1.501    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/clk
    SLICE_X28Y28         FDCE                                         r  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_reg[0]/C
                         clock pessimism             -0.139     1.362    
    SLICE_X28Y28         FDCE (Remov_EFF_SLICEM_C_CLR)
                                                     -0.020     1.342    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_reg[0]
  -------------------------------------------------------------------
                         required time                         -1.342    
                         arrival time                           1.537    
  -------------------------------------------------------------------
                         slack                                  0.195    

Slack (MET) :             0.195ns  (arrival time - required time)
  Source:                 d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_reg[2]/CLR
                            (removal check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_pl_0 rise@0.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        0.234ns  (logic 0.074ns (31.587%)  route 0.160ns (68.413%))
  Logic Levels:           1  (LUT3=1)
  Clock Path Skew:        0.059ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.501ns
    Source Clock Delay      (SCD):    1.303ns
    Clock Pessimism Removal (CPR):    0.139ns
  Clock Net Delay (Source):      1.183ns (routing 0.359ns, distribution 0.824ns)
  Clock Net Delay (Destination): 1.354ns (routing 0.405ns, distribution 0.949ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.183     1.303    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/clk
    SLICE_X30Y29         FDRE                                         r  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X30Y29         FDRE (Prop_HFF_SLICEM_C_Q)
                                                      0.039     1.342 f  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[1]/Q
                         net (fo=2, routed)           0.028     1.370    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc[1]
    SLICE_X30Y29         LUT3 (Prop_F6LUT_SLICEM_I0_O)
                                                      0.035     1.405 f  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/gpregsm1.curr_fwft_state[1]_i_2/O
                         net (fo=32, routed)          0.132     1.537    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/AR[0]
    SLICE_X28Y28         FDCE                                         f  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_reg[2]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.354     1.501    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/clk
    SLICE_X28Y28         FDCE                                         r  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_reg[2]/C
                         clock pessimism             -0.139     1.362    
    SLICE_X28Y28         FDCE (Remov_EFF2_SLICEM_C_CLR)
                                                     -0.020     1.342    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_reg[2]
  -------------------------------------------------------------------
                         required time                         -1.342    
                         arrival time                           1.537    
  -------------------------------------------------------------------
                         slack                                  0.195    

Slack (MET) :             0.195ns  (arrival time - required time)
  Source:                 d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_reg[1]/CLR
                            (removal check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_pl_0 rise@0.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        0.234ns  (logic 0.074ns (31.587%)  route 0.160ns (68.413%))
  Logic Levels:           1  (LUT3=1)
  Clock Path Skew:        0.059ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.501ns
    Source Clock Delay      (SCD):    1.303ns
    Clock Pessimism Removal (CPR):    0.139ns
  Clock Net Delay (Source):      1.183ns (routing 0.359ns, distribution 0.824ns)
  Clock Net Delay (Destination): 1.354ns (routing 0.405ns, distribution 0.949ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.183     1.303    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/clk
    SLICE_X30Y29         FDRE                                         r  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X30Y29         FDRE (Prop_HFF_SLICEM_C_Q)
                                                      0.039     1.342 f  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[1]/Q
                         net (fo=2, routed)           0.028     1.370    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc[1]
    SLICE_X30Y29         LUT3 (Prop_F6LUT_SLICEM_I0_O)
                                                      0.035     1.405 f  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/gpregsm1.curr_fwft_state[1]_i_2/O
                         net (fo=32, routed)          0.132     1.537    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/AR[0]
    SLICE_X28Y28         FDCE                                         f  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_reg[1]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.354     1.501    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/clk
    SLICE_X28Y28         FDCE                                         r  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_reg[1]/C
                         clock pessimism             -0.139     1.362    
    SLICE_X28Y28         FDCE (Remov_FFF_SLICEM_C_CLR)
                                                     -0.020     1.342    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_reg[1]
  -------------------------------------------------------------------
                         required time                         -1.342    
                         arrival time                           1.537    
  -------------------------------------------------------------------
                         slack                                  0.195    

Slack (MET) :             0.196ns  (arrival time - required time)
  Source:                 d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_reg/CLR
                            (removal check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_pl_0 rise@0.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        0.228ns  (logic 0.074ns (32.417%)  route 0.154ns (67.583%))
  Logic Levels:           1  (LUT3=1)
  Clock Path Skew:        0.052ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.494ns
    Source Clock Delay      (SCD):    1.303ns
    Clock Pessimism Removal (CPR):    0.139ns
  Clock Net Delay (Source):      1.183ns (routing 0.359ns, distribution 0.824ns)
  Clock Net Delay (Destination): 1.347ns (routing 0.405ns, distribution 0.942ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.183     1.303    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/clk
    SLICE_X30Y29         FDRE                                         r  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X30Y29         FDRE (Prop_HFF_SLICEM_C_Q)
                                                      0.039     1.342 f  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[1]/Q
                         net (fo=2, routed)           0.028     1.370    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc[1]
    SLICE_X30Y29         LUT3 (Prop_F6LUT_SLICEM_I0_O)
                                                      0.035     1.405 f  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/gpregsm1.curr_fwft_state[1]_i_2/O
                         net (fo=32, routed)          0.126     1.531    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/AR[0]
    SLICE_X29Y28         FDCE                                         f  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_reg/CLR
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.347     1.494    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/clk
    SLICE_X29Y28         FDCE                                         r  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_reg/C
                         clock pessimism             -0.139     1.355    
    SLICE_X29Y28         FDCE (Remov_AFF_SLICEL_C_CLR)
                                                     -0.020     1.335    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_reg
  -------------------------------------------------------------------
                         required time                         -1.335    
                         arrival time                           1.531    
  -------------------------------------------------------------------
                         slack                                  0.196    





---------------------------------------------------------------------------------------------------
Path Group:  **async_default**
From Clock:  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  To Clock:  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK

Setup :            0  Failing Endpoints,  Worst Slack       46.222ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.120ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             46.222ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/state_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[10]/CLR
                            (recovery check against rising-edge clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            50.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@50.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns)
  Data Path Delay:        3.514ns  (logic 0.212ns (6.034%)  route 3.302ns (93.966%))
  Logic Levels:           1  (LUT4=1)
  Clock Path Skew:        -0.163ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.257ns = ( 53.257 - 50.000 ) 
    Source Clock Delay      (SCD):    7.892ns
    Clock Pessimism Removal (CPR):    4.472ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.757ns (routing 0.515ns, distribution 1.242ns)
  Clock Net Delay (Destination): 1.549ns (routing 0.470ns, distribution 1.079ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.807     6.107    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y81         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     6.135 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.757     7.892    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_tck
    SLICE_X108Y70        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/state_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X108Y70        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     7.971 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/state_reg[1]/Q
                         net (fo=50, routed)          0.581     8.552    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/state[1]
    SLICE_X105Y72        LUT4 (Prop_D5LUT_SLICEL_I0_O)
                                                      0.133     8.685 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_sel[0]_INST_0/O
                         net (fo=11, routed)          2.720    11.406    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[6]_0
    SLICE_X105Y336       FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[10]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                     50.000    50.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    50.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465    50.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.219    51.684    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y81         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    51.708 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.549    53.257    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/m_bscan_tck[0]
    SLICE_X105Y336       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[10]/C
                         clock pessimism              4.472    57.729    
                         clock uncertainty           -0.035    57.693    
    SLICE_X105Y336       FDCE (Recov_EFF_SLICEL_C_CLR)
                                                     -0.066    57.627    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[10]
  -------------------------------------------------------------------
                         required time                         57.627    
                         arrival time                         -11.406    
  -------------------------------------------------------------------
                         slack                                 46.222    

Slack (MET) :             46.222ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/state_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[11]/CLR
                            (recovery check against rising-edge clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            50.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@50.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns)
  Data Path Delay:        3.514ns  (logic 0.212ns (6.034%)  route 3.302ns (93.966%))
  Logic Levels:           1  (LUT4=1)
  Clock Path Skew:        -0.163ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.257ns = ( 53.257 - 50.000 ) 
    Source Clock Delay      (SCD):    7.892ns
    Clock Pessimism Removal (CPR):    4.472ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.757ns (routing 0.515ns, distribution 1.242ns)
  Clock Net Delay (Destination): 1.549ns (routing 0.470ns, distribution 1.079ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.807     6.107    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y81         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     6.135 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.757     7.892    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_tck
    SLICE_X108Y70        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/state_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X108Y70        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     7.971 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/state_reg[1]/Q
                         net (fo=50, routed)          0.581     8.552    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/state[1]
    SLICE_X105Y72        LUT4 (Prop_D5LUT_SLICEL_I0_O)
                                                      0.133     8.685 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_sel[0]_INST_0/O
                         net (fo=11, routed)          2.720    11.406    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[6]_0
    SLICE_X105Y336       FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[11]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                     50.000    50.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    50.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465    50.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.219    51.684    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y81         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    51.708 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.549    53.257    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/m_bscan_tck[0]
    SLICE_X105Y336       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[11]/C
                         clock pessimism              4.472    57.729    
                         clock uncertainty           -0.035    57.693    
    SLICE_X105Y336       FDCE (Recov_EFF2_SLICEL_C_CLR)
                                                     -0.066    57.627    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[11]
  -------------------------------------------------------------------
                         required time                         57.627    
                         arrival time                         -11.406    
  -------------------------------------------------------------------
                         slack                                 46.222    

Slack (MET) :             46.222ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/state_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[12]/CLR
                            (recovery check against rising-edge clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            50.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@50.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns)
  Data Path Delay:        3.514ns  (logic 0.212ns (6.034%)  route 3.302ns (93.966%))
  Logic Levels:           1  (LUT4=1)
  Clock Path Skew:        -0.163ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.257ns = ( 53.257 - 50.000 ) 
    Source Clock Delay      (SCD):    7.892ns
    Clock Pessimism Removal (CPR):    4.472ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.757ns (routing 0.515ns, distribution 1.242ns)
  Clock Net Delay (Destination): 1.549ns (routing 0.470ns, distribution 1.079ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.807     6.107    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y81         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     6.135 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.757     7.892    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_tck
    SLICE_X108Y70        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/state_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X108Y70        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     7.971 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/state_reg[1]/Q
                         net (fo=50, routed)          0.581     8.552    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/state[1]
    SLICE_X105Y72        LUT4 (Prop_D5LUT_SLICEL_I0_O)
                                                      0.133     8.685 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_sel[0]_INST_0/O
                         net (fo=11, routed)          2.720    11.406    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[6]_0
    SLICE_X105Y336       FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[12]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                     50.000    50.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    50.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465    50.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.219    51.684    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y81         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    51.708 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.549    53.257    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/m_bscan_tck[0]
    SLICE_X105Y336       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[12]/C
                         clock pessimism              4.472    57.729    
                         clock uncertainty           -0.035    57.693    
    SLICE_X105Y336       FDCE (Recov_FFF_SLICEL_C_CLR)
                                                     -0.066    57.627    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[12]
  -------------------------------------------------------------------
                         required time                         57.627    
                         arrival time                         -11.406    
  -------------------------------------------------------------------
                         slack                                 46.222    

Slack (MET) :             46.222ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/state_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[13]/CLR
                            (recovery check against rising-edge clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            50.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@50.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns)
  Data Path Delay:        3.514ns  (logic 0.212ns (6.034%)  route 3.302ns (93.966%))
  Logic Levels:           1  (LUT4=1)
  Clock Path Skew:        -0.163ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.257ns = ( 53.257 - 50.000 ) 
    Source Clock Delay      (SCD):    7.892ns
    Clock Pessimism Removal (CPR):    4.472ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.757ns (routing 0.515ns, distribution 1.242ns)
  Clock Net Delay (Destination): 1.549ns (routing 0.470ns, distribution 1.079ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.807     6.107    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y81         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     6.135 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.757     7.892    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_tck
    SLICE_X108Y70        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/state_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X108Y70        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     7.971 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/state_reg[1]/Q
                         net (fo=50, routed)          0.581     8.552    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/state[1]
    SLICE_X105Y72        LUT4 (Prop_D5LUT_SLICEL_I0_O)
                                                      0.133     8.685 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_sel[0]_INST_0/O
                         net (fo=11, routed)          2.720    11.406    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[6]_0
    SLICE_X105Y336       FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[13]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                     50.000    50.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    50.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465    50.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.219    51.684    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y81         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    51.708 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.549    53.257    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/m_bscan_tck[0]
    SLICE_X105Y336       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[13]/C
                         clock pessimism              4.472    57.729    
                         clock uncertainty           -0.035    57.693    
    SLICE_X105Y336       FDCE (Recov_FFF2_SLICEL_C_CLR)
                                                     -0.066    57.627    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[13]
  -------------------------------------------------------------------
                         required time                         57.627    
                         arrival time                         -11.406    
  -------------------------------------------------------------------
                         slack                                 46.222    

Slack (MET) :             46.222ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/state_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[6]/CLR
                            (recovery check against rising-edge clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            50.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@50.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns)
  Data Path Delay:        3.514ns  (logic 0.212ns (6.034%)  route 3.302ns (93.966%))
  Logic Levels:           1  (LUT4=1)
  Clock Path Skew:        -0.163ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.257ns = ( 53.257 - 50.000 ) 
    Source Clock Delay      (SCD):    7.892ns
    Clock Pessimism Removal (CPR):    4.472ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.757ns (routing 0.515ns, distribution 1.242ns)
  Clock Net Delay (Destination): 1.549ns (routing 0.470ns, distribution 1.079ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.807     6.107    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y81         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     6.135 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.757     7.892    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_tck
    SLICE_X108Y70        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/state_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X108Y70        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     7.971 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/state_reg[1]/Q
                         net (fo=50, routed)          0.581     8.552    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/state[1]
    SLICE_X105Y72        LUT4 (Prop_D5LUT_SLICEL_I0_O)
                                                      0.133     8.685 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_sel[0]_INST_0/O
                         net (fo=11, routed)          2.720    11.406    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[6]_0
    SLICE_X105Y336       FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[6]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                     50.000    50.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    50.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465    50.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.219    51.684    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y81         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    51.708 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.549    53.257    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/m_bscan_tck[0]
    SLICE_X105Y336       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[6]/C
                         clock pessimism              4.472    57.729    
                         clock uncertainty           -0.035    57.693    
    SLICE_X105Y336       FDCE (Recov_GFF_SLICEL_C_CLR)
                                                     -0.066    57.627    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[6]
  -------------------------------------------------------------------
                         required time                         57.627    
                         arrival time                         -11.406    
  -------------------------------------------------------------------
                         slack                                 46.222    

Slack (MET) :             46.222ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/state_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[7]/CLR
                            (recovery check against rising-edge clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            50.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@50.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns)
  Data Path Delay:        3.514ns  (logic 0.212ns (6.034%)  route 3.302ns (93.966%))
  Logic Levels:           1  (LUT4=1)
  Clock Path Skew:        -0.163ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.257ns = ( 53.257 - 50.000 ) 
    Source Clock Delay      (SCD):    7.892ns
    Clock Pessimism Removal (CPR):    4.472ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.757ns (routing 0.515ns, distribution 1.242ns)
  Clock Net Delay (Destination): 1.549ns (routing 0.470ns, distribution 1.079ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.807     6.107    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y81         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     6.135 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.757     7.892    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_tck
    SLICE_X108Y70        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/state_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X108Y70        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     7.971 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/state_reg[1]/Q
                         net (fo=50, routed)          0.581     8.552    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/state[1]
    SLICE_X105Y72        LUT4 (Prop_D5LUT_SLICEL_I0_O)
                                                      0.133     8.685 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_sel[0]_INST_0/O
                         net (fo=11, routed)          2.720    11.406    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[6]_0
    SLICE_X105Y336       FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[7]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                     50.000    50.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    50.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465    50.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.219    51.684    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y81         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    51.708 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.549    53.257    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/m_bscan_tck[0]
    SLICE_X105Y336       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[7]/C
                         clock pessimism              4.472    57.729    
                         clock uncertainty           -0.035    57.693    
    SLICE_X105Y336       FDCE (Recov_GFF2_SLICEL_C_CLR)
                                                     -0.066    57.627    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[7]
  -------------------------------------------------------------------
                         required time                         57.627    
                         arrival time                         -11.406    
  -------------------------------------------------------------------
                         slack                                 46.222    

Slack (MET) :             46.222ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/state_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[8]/CLR
                            (recovery check against rising-edge clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            50.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@50.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns)
  Data Path Delay:        3.514ns  (logic 0.212ns (6.034%)  route 3.302ns (93.966%))
  Logic Levels:           1  (LUT4=1)
  Clock Path Skew:        -0.163ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.257ns = ( 53.257 - 50.000 ) 
    Source Clock Delay      (SCD):    7.892ns
    Clock Pessimism Removal (CPR):    4.472ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.757ns (routing 0.515ns, distribution 1.242ns)
  Clock Net Delay (Destination): 1.549ns (routing 0.470ns, distribution 1.079ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.807     6.107    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y81         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     6.135 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.757     7.892    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_tck
    SLICE_X108Y70        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/state_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X108Y70        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     7.971 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/state_reg[1]/Q
                         net (fo=50, routed)          0.581     8.552    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/state[1]
    SLICE_X105Y72        LUT4 (Prop_D5LUT_SLICEL_I0_O)
                                                      0.133     8.685 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_sel[0]_INST_0/O
                         net (fo=11, routed)          2.720    11.406    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[6]_0
    SLICE_X105Y336       FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[8]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                     50.000    50.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    50.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465    50.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.219    51.684    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y81         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    51.708 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.549    53.257    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/m_bscan_tck[0]
    SLICE_X105Y336       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[8]/C
                         clock pessimism              4.472    57.729    
                         clock uncertainty           -0.035    57.693    
    SLICE_X105Y336       FDCE (Recov_HFF_SLICEL_C_CLR)
                                                     -0.066    57.627    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[8]
  -------------------------------------------------------------------
                         required time                         57.627    
                         arrival time                         -11.406    
  -------------------------------------------------------------------
                         slack                                 46.222    

Slack (MET) :             46.222ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/state_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[9]/CLR
                            (recovery check against rising-edge clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            50.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@50.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns)
  Data Path Delay:        3.514ns  (logic 0.212ns (6.034%)  route 3.302ns (93.966%))
  Logic Levels:           1  (LUT4=1)
  Clock Path Skew:        -0.163ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.257ns = ( 53.257 - 50.000 ) 
    Source Clock Delay      (SCD):    7.892ns
    Clock Pessimism Removal (CPR):    4.472ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.757ns (routing 0.515ns, distribution 1.242ns)
  Clock Net Delay (Destination): 1.549ns (routing 0.470ns, distribution 1.079ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.807     6.107    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y81         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     6.135 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.757     7.892    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_tck
    SLICE_X108Y70        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/state_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X108Y70        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     7.971 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/state_reg[1]/Q
                         net (fo=50, routed)          0.581     8.552    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/state[1]
    SLICE_X105Y72        LUT4 (Prop_D5LUT_SLICEL_I0_O)
                                                      0.133     8.685 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_sel[0]_INST_0/O
                         net (fo=11, routed)          2.720    11.406    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[6]_0
    SLICE_X105Y336       FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[9]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                     50.000    50.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    50.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465    50.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.219    51.684    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y81         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    51.708 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.549    53.257    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/m_bscan_tck[0]
    SLICE_X105Y336       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[9]/C
                         clock pessimism              4.472    57.729    
                         clock uncertainty           -0.035    57.693    
    SLICE_X105Y336       FDCE (Recov_HFF2_SLICEL_C_CLR)
                                                     -0.066    57.627    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[9]
  -------------------------------------------------------------------
                         required time                         57.627    
                         arrival time                         -11.406    
  -------------------------------------------------------------------
                         slack                                 46.222    

Slack (MET) :             46.316ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/state_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[14]/CLR
                            (recovery check against rising-edge clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            50.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@50.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns)
  Data Path Delay:        3.420ns  (logic 0.212ns (6.200%)  route 3.208ns (93.800%))
  Logic Levels:           1  (LUT4=1)
  Clock Path Skew:        -0.163ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.257ns = ( 53.257 - 50.000 ) 
    Source Clock Delay      (SCD):    7.892ns
    Clock Pessimism Removal (CPR):    4.472ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.757ns (routing 0.515ns, distribution 1.242ns)
  Clock Net Delay (Destination): 1.549ns (routing 0.470ns, distribution 1.079ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.807     6.107    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y81         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     6.135 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.757     7.892    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_tck
    SLICE_X108Y70        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/state_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X108Y70        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     7.971 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/state_reg[1]/Q
                         net (fo=50, routed)          0.581     8.552    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/state[1]
    SLICE_X105Y72        LUT4 (Prop_D5LUT_SLICEL_I0_O)
                                                      0.133     8.685 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_sel[0]_INST_0/O
                         net (fo=11, routed)          2.626    11.312    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[6]_0
    SLICE_X104Y333       FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[14]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                     50.000    50.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    50.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465    50.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.219    51.684    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y81         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    51.708 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.549    53.257    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/m_bscan_tck[0]
    SLICE_X104Y333       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[14]/C
                         clock pessimism              4.472    57.729    
                         clock uncertainty           -0.035    57.693    
    SLICE_X104Y333       FDCE (Recov_EFF_SLICEM_C_CLR)
                                                     -0.066    57.627    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[14]
  -------------------------------------------------------------------
                         required time                         57.627    
                         arrival time                         -11.312    
  -------------------------------------------------------------------
                         slack                                 46.316    

Slack (MET) :             46.316ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/state_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[15]/CLR
                            (recovery check against rising-edge clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            50.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@50.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns)
  Data Path Delay:        3.420ns  (logic 0.212ns (6.200%)  route 3.208ns (93.800%))
  Logic Levels:           1  (LUT4=1)
  Clock Path Skew:        -0.163ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.257ns = ( 53.257 - 50.000 ) 
    Source Clock Delay      (SCD):    7.892ns
    Clock Pessimism Removal (CPR):    4.472ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.757ns (routing 0.515ns, distribution 1.242ns)
  Clock Net Delay (Destination): 1.549ns (routing 0.470ns, distribution 1.079ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.807     6.107    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y81         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     6.135 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.757     7.892    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_tck
    SLICE_X108Y70        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/state_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X108Y70        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     7.971 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/state_reg[1]/Q
                         net (fo=50, routed)          0.581     8.552    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/state[1]
    SLICE_X105Y72        LUT4 (Prop_D5LUT_SLICEL_I0_O)
                                                      0.133     8.685 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_sel[0]_INST_0/O
                         net (fo=11, routed)          2.626    11.312    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[6]_0
    SLICE_X104Y333       FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[15]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                     50.000    50.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    50.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465    50.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.219    51.684    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y81         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    51.708 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.549    53.257    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/m_bscan_tck[0]
    SLICE_X104Y333       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[15]/C
                         clock pessimism              4.472    57.729    
                         clock uncertainty           -0.035    57.693    
    SLICE_X104Y333       FDCE (Recov_EFF2_SLICEM_C_CLR)
                                                     -0.066    57.627    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[15]
  -------------------------------------------------------------------
                         required time                         57.627    
                         arrival time                         -11.312    
  -------------------------------------------------------------------
                         slack                                 46.316    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.120ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]/C
                            (rising edge-triggered cell FDPE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_reg[0]/PRE
                            (removal check against rising-edge clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns)
  Data Path Delay:        0.149ns  (logic 0.039ns (26.242%)  route 0.110ns (73.758%))
  Logic Levels:           0  
  Clock Path Skew:        0.049ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    6.699ns
    Source Clock Delay      (SCD):    2.422ns
    Clock Pessimism Removal (CPR):    4.229ns
  Clock Net Delay (Source):      0.986ns (routing 0.283ns, distribution 0.703ns)
  Clock Net Delay (Destination): 1.116ns (routing 0.313ns, distribution 0.803ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.954     1.419    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y81         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.436 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         0.986     2.422    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_clk
    SLICE_X103Y373       FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X103Y373       FDPE (Prop_EFF2_SLICEM_C_Q)
                                                      0.039     2.461 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]/Q
                         net (fo=12, routed)          0.110     2.570    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_reg[0]_0[0]
    SLICE_X102Y373       FDPE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_reg[0]/PRE
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.264     5.564    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y81         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     5.583 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.116     6.699    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/wr_clk
    SLICE_X102Y373       FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_reg[0]/C
                         clock pessimism             -4.229     2.470    
    SLICE_X102Y373       FDPE (Remov_EFF_SLICEL_C_PRE)
                                                     -0.020     2.450    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_reg[0]
  -------------------------------------------------------------------
                         required time                         -2.450    
                         arrival time                           2.570    
  -------------------------------------------------------------------
                         slack                                  0.120    

Slack (MET) :             0.120ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]/C
                            (rising edge-triggered cell FDPE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_reg[1]/CLR
                            (removal check against rising-edge clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns)
  Data Path Delay:        0.149ns  (logic 0.039ns (26.242%)  route 0.110ns (73.758%))
  Logic Levels:           0  
  Clock Path Skew:        0.049ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    6.699ns
    Source Clock Delay      (SCD):    2.422ns
    Clock Pessimism Removal (CPR):    4.229ns
  Clock Net Delay (Source):      0.986ns (routing 0.283ns, distribution 0.703ns)
  Clock Net Delay (Destination): 1.116ns (routing 0.313ns, distribution 0.803ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.954     1.419    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y81         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.436 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         0.986     2.422    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_clk
    SLICE_X103Y373       FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X103Y373       FDPE (Prop_EFF2_SLICEM_C_Q)
                                                      0.039     2.461 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]/Q
                         net (fo=12, routed)          0.110     2.570    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_reg[0]_0[0]
    SLICE_X102Y373       FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_reg[1]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.264     5.564    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y81         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     5.583 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.116     6.699    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/wr_clk
    SLICE_X102Y373       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_reg[1]/C
                         clock pessimism             -4.229     2.470    
    SLICE_X102Y373       FDCE (Remov_EFF2_SLICEL_C_CLR)
                                                     -0.020     2.450    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_reg[1]
  -------------------------------------------------------------------
                         required time                         -2.450    
                         arrival time                           2.570    
  -------------------------------------------------------------------
                         slack                                  0.120    

Slack (MET) :             0.123ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/wrdata_rst_reg/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rst_wr_reg1_reg/PRE
                            (removal check against rising-edge clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns)
  Data Path Delay:        0.200ns  (logic 0.037ns (18.512%)  route 0.163ns (81.488%))
  Logic Levels:           0  
  Clock Path Skew:        0.097ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    6.696ns
    Source Clock Delay      (SCD):    2.403ns
    Clock Pessimism Removal (CPR):    4.196ns
  Clock Net Delay (Source):      0.967ns (routing 0.283ns, distribution 0.684ns)
  Clock Net Delay (Destination): 1.113ns (routing 0.313ns, distribution 0.800ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.954     1.419    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y81         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.436 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         0.967     2.403    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/m_bscan_tck[0]
    SLICE_X104Y358       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/wrdata_rst_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X104Y358       FDRE (Prop_FFF_SLICEM_C_Q)
                                                      0.037     2.440 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/wrdata_rst_reg/Q
                         net (fo=20, routed)          0.163     2.603    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/rst
    SLICE_X104Y374       FDPE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rst_wr_reg1_reg/PRE
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.264     5.564    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y81         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     5.583 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.113     6.696    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_clk
    SLICE_X104Y374       FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rst_wr_reg1_reg/C
                         clock pessimism             -4.196     2.500    
    SLICE_X104Y374       FDPE (Remov_HFF2_SLICEM_C_PRE)
                                                     -0.020     2.480    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rst_wr_reg1_reg
  -------------------------------------------------------------------
                         required time                         -2.480    
                         arrival time                           2.603    
  -------------------------------------------------------------------
                         slack                                  0.123    

Slack (MET) :             0.123ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/wrdata_rst_reg/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rst_wr_reg2_reg/PRE
                            (removal check against rising-edge clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns)
  Data Path Delay:        0.200ns  (logic 0.037ns (18.512%)  route 0.163ns (81.488%))
  Logic Levels:           0  
  Clock Path Skew:        0.097ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    6.696ns
    Source Clock Delay      (SCD):    2.403ns
    Clock Pessimism Removal (CPR):    4.196ns
  Clock Net Delay (Source):      0.967ns (routing 0.283ns, distribution 0.684ns)
  Clock Net Delay (Destination): 1.113ns (routing 0.313ns, distribution 0.800ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.954     1.419    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y81         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.436 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         0.967     2.403    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/m_bscan_tck[0]
    SLICE_X104Y358       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/wrdata_rst_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X104Y358       FDRE (Prop_FFF_SLICEM_C_Q)
                                                      0.037     2.440 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/wrdata_rst_reg/Q
                         net (fo=20, routed)          0.163     2.603    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/rst
    SLICE_X104Y374       FDPE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rst_wr_reg2_reg/PRE
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.264     5.564    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y81         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     5.583 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.113     6.696    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_clk
    SLICE_X104Y374       FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rst_wr_reg2_reg/C
                         clock pessimism             -4.196     2.500    
    SLICE_X104Y374       FDPE (Remov_EFF2_SLICEM_C_PRE)
                                                     -0.020     2.480    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rst_wr_reg2_reg
  -------------------------------------------------------------------
                         required time                         -2.480    
                         arrival time                           2.603    
  -------------------------------------------------------------------
                         slack                                  0.123    

Slack (MET) :             0.124ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]/C
                            (rising edge-triggered cell FDPE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_reg[1]/PRE
                            (removal check against rising-edge clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns)
  Data Path Delay:        0.149ns  (logic 0.039ns (26.242%)  route 0.110ns (73.758%))
  Logic Levels:           0  
  Clock Path Skew:        0.045ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    6.695ns
    Source Clock Delay      (SCD):    2.422ns
    Clock Pessimism Removal (CPR):    4.229ns
  Clock Net Delay (Source):      0.986ns (routing 0.283ns, distribution 0.703ns)
  Clock Net Delay (Destination): 1.112ns (routing 0.313ns, distribution 0.799ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.954     1.419    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y81         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.436 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         0.986     2.422    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_clk
    SLICE_X103Y373       FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X103Y373       FDPE (Prop_EFF2_SLICEM_C_Q)
                                                      0.039     2.461 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]/Q
                         net (fo=12, routed)          0.110     2.570    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_reg[0]_0[0]
    SLICE_X102Y373       FDPE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_reg[1]/PRE
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.264     5.564    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y81         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     5.583 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.112     6.695    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/wr_clk
    SLICE_X102Y373       FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_reg[1]/C
                         clock pessimism             -4.229     2.466    
    SLICE_X102Y373       FDPE (Remov_DFF2_SLICEL_C_PRE)
                                                     -0.020     2.446    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_reg[1]
  -------------------------------------------------------------------
                         required time                         -2.446    
                         arrival time                           2.570    
  -------------------------------------------------------------------
                         slack                                  0.124    

Slack (MET) :             0.127ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]/C
                            (rising edge-triggered cell FDPE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_reg[3]/CLR
                            (removal check against rising-edge clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns)
  Data Path Delay:        0.121ns  (logic 0.039ns (32.134%)  route 0.082ns (67.866%))
  Logic Levels:           0  
  Clock Path Skew:        0.015ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    6.700ns
    Source Clock Delay      (SCD):    2.422ns
    Clock Pessimism Removal (CPR):    4.264ns
  Clock Net Delay (Source):      0.986ns (routing 0.283ns, distribution 0.703ns)
  Clock Net Delay (Destination): 1.117ns (routing 0.313ns, distribution 0.804ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.954     1.419    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y81         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.436 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         0.986     2.422    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_clk
    SLICE_X103Y373       FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X103Y373       FDPE (Prop_EFF2_SLICEM_C_Q)
                                                      0.039     2.461 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]/Q
                         net (fo=12, routed)          0.082     2.543    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_reg[0]_0[0]
    SLICE_X103Y373       FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_reg[3]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.264     5.564    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y81         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     5.583 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.117     6.700    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/wr_clk
    SLICE_X103Y373       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_reg[3]/C
                         clock pessimism             -4.264     2.436    
    SLICE_X103Y373       FDCE (Remov_AFF_SLICEM_C_CLR)
                                                     -0.020     2.416    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_reg[3]
  -------------------------------------------------------------------
                         required time                         -2.416    
                         arrival time                           2.543    
  -------------------------------------------------------------------
                         slack                                  0.127    

Slack (MET) :             0.127ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]/C
                            (rising edge-triggered cell FDPE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_reg[2]/CLR
                            (removal check against rising-edge clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns)
  Data Path Delay:        0.121ns  (logic 0.039ns (32.134%)  route 0.082ns (67.866%))
  Logic Levels:           0  
  Clock Path Skew:        0.015ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    6.700ns
    Source Clock Delay      (SCD):    2.422ns
    Clock Pessimism Removal (CPR):    4.264ns
  Clock Net Delay (Source):      0.986ns (routing 0.283ns, distribution 0.703ns)
  Clock Net Delay (Destination): 1.117ns (routing 0.313ns, distribution 0.804ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.954     1.419    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y81         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.436 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         0.986     2.422    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_clk
    SLICE_X103Y373       FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X103Y373       FDPE (Prop_EFF2_SLICEM_C_Q)
                                                      0.039     2.461 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]/Q
                         net (fo=12, routed)          0.082     2.543    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_reg[0]_0[0]
    SLICE_X103Y373       FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_reg[2]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.264     5.564    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y81         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     5.583 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.117     6.700    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/wr_clk
    SLICE_X103Y373       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_reg[2]/C
                         clock pessimism             -4.264     2.436    
    SLICE_X103Y373       FDCE (Remov_DFF_SLICEM_C_CLR)
                                                     -0.020     2.416    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_reg[2]
  -------------------------------------------------------------------
                         required time                         -2.416    
                         arrival time                           2.543    
  -------------------------------------------------------------------
                         slack                                  0.127    

Slack (MET) :             0.127ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]/C
                            (rising edge-triggered cell FDPE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_reg[3]/CLR
                            (removal check against rising-edge clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns)
  Data Path Delay:        0.121ns  (logic 0.039ns (32.134%)  route 0.082ns (67.866%))
  Logic Levels:           0  
  Clock Path Skew:        0.015ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    6.700ns
    Source Clock Delay      (SCD):    2.422ns
    Clock Pessimism Removal (CPR):    4.264ns
  Clock Net Delay (Source):      0.986ns (routing 0.283ns, distribution 0.703ns)
  Clock Net Delay (Destination): 1.117ns (routing 0.313ns, distribution 0.804ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.954     1.419    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y81         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.436 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         0.986     2.422    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_clk
    SLICE_X103Y373       FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X103Y373       FDPE (Prop_EFF2_SLICEM_C_Q)
                                                      0.039     2.461 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]/Q
                         net (fo=12, routed)          0.082     2.543    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_reg[0]_0[0]
    SLICE_X103Y373       FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_reg[3]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.264     5.564    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y81         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     5.583 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.117     6.700    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/wr_clk
    SLICE_X103Y373       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_reg[3]/C
                         clock pessimism             -4.264     2.436    
    SLICE_X103Y373       FDCE (Remov_DFF2_SLICEM_C_CLR)
                                                     -0.020     2.416    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_reg[3]
  -------------------------------------------------------------------
                         required time                         -2.416    
                         arrival time                           2.543    
  -------------------------------------------------------------------
                         slack                                  0.127    

Slack (MET) :             0.127ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]/C
                            (rising edge-triggered cell FDPE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/empty_fwft_fb_i_reg/PRE
                            (removal check against rising-edge clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns)
  Data Path Delay:        0.165ns  (logic 0.037ns (22.377%)  route 0.128ns (77.623%))
  Logic Levels:           0  
  Clock Path Skew:        0.059ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    6.685ns
    Source Clock Delay      (SCD):    2.402ns
    Clock Pessimism Removal (CPR):    4.224ns
  Clock Net Delay (Source):      0.966ns (routing 0.283ns, distribution 0.683ns)
  Clock Net Delay (Destination): 1.102ns (routing 0.313ns, distribution 0.789ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.954     1.419    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y81         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.436 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         0.966     2.402    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_clk
    SLICE_X104Y353       FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X104Y353       FDPE (Prop_FFF_SLICEM_C_Q)
                                                      0.037     2.439 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]/Q
                         net (fo=18, routed)          0.128     2.567    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/out[1]
    SLICE_X102Y351       FDPE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/empty_fwft_fb_i_reg/PRE
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.264     5.564    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y81         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     5.583 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.102     6.685    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/rd_clk
    SLICE_X102Y351       FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/empty_fwft_fb_i_reg/C
                         clock pessimism             -4.224     2.461    
    SLICE_X102Y351       FDPE (Remov_EFF_SLICEL_C_PRE)
                                                     -0.020     2.441    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/empty_fwft_fb_i_reg
  -------------------------------------------------------------------
                         required time                         -2.441    
                         arrival time                           2.567    
  -------------------------------------------------------------------
                         slack                                  0.127    

Slack (MET) :             0.129ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rst_wr_reg2_reg/C
                            (rising edge-triggered cell FDPE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_asreg_reg/PRE
                            (removal check against rising-edge clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns)
  Data Path Delay:        0.138ns  (logic 0.039ns (28.261%)  route 0.099ns (71.739%))
  Logic Levels:           0  
  Clock Path Skew:        0.029ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    6.705ns
    Source Clock Delay      (SCD):    2.419ns
    Clock Pessimism Removal (CPR):    4.258ns
  Clock Net Delay (Source):      0.983ns (routing 0.283ns, distribution 0.700ns)
  Clock Net Delay (Destination): 1.122ns (routing 0.313ns, distribution 0.809ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.954     1.419    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y81         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.436 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         0.983     2.419    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_clk
    SLICE_X104Y374       FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rst_wr_reg2_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X104Y374       FDPE (Prop_EFF2_SLICEM_C_Q)
                                                      0.039     2.458 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rst_wr_reg2_reg/Q
                         net (fo=1, routed)           0.099     2.557    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.rst_wr_reg2
    SLICE_X104Y373       FDPE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_asreg_reg/PRE
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.264     5.564    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y81         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     5.583 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.122     6.705    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_clk
    SLICE_X104Y373       FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_asreg_reg/C
                         clock pessimism             -4.258     2.448    
    SLICE_X104Y373       FDPE (Remov_DFF2_SLICEM_C_PRE)
                                                     -0.020     2.428    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_asreg_reg
  -------------------------------------------------------------------
                         required time                         -2.428    
                         arrival time                           2.557    
  -------------------------------------------------------------------
                         slack                                  0.129    





---------------------------------------------------------------------------------------------------
Path Group:  **async_default**
From Clock:  mmcm_clkout5
  To Clock:  mmcm_clkout5

Setup :            0  Failing Endpoints,  Worst Slack       10.521ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.114ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             10.521ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[12]/CLR
                            (recovery check against rising-edge clock mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            12.002ns  (mmcm_clkout5 rise@12.002ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        1.291ns  (logic 0.076ns (5.887%)  route 1.215ns (94.113%))
  Logic Levels:           0  
  Clock Path Skew:        -0.049ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.492ns = ( 16.494 - 12.002 ) 
    Source Clock Delay      (SCD):    4.246ns
    Clock Pessimism Removal (CPR):    -0.295ns
  Clock Uncertainty:      0.076ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.499ns (routing 0.632ns, distribution 0.867ns)
  Clock Net Delay (Destination): 1.352ns (routing 0.575ns, distribution 0.777ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.524     2.610    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     2.483 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.236     2.719    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y115        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.747 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.499     4.246    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/clk
    SLICE_X103Y341       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X103Y341       FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     4.322 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/Q
                         net (fo=176, routed)         1.215     5.537    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/out[0]
    SLICE_X104Y352       FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[12]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                     12.002    12.002 r  
    J19                                               0.000    12.002 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079    12.081    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475    12.556 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040    12.596    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000    12.596 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297    12.893    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    12.917 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.364    14.281    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630    14.911 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.207    15.118    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y115        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    15.142 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.352    16.494    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/clk
    SLICE_X104Y352       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[12]/C
                         clock pessimism             -0.295    16.200    
                         clock uncertainty           -0.076    16.124    
    SLICE_X104Y352       FDCE (Recov_HFF_SLICEM_C_CLR)
                                                     -0.066    16.058    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[12]
  -------------------------------------------------------------------
                         required time                         16.058    
                         arrival time                          -5.537    
  -------------------------------------------------------------------
                         slack                                 10.521    

Slack (MET) :             10.521ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[13]/CLR
                            (recovery check against rising-edge clock mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            12.002ns  (mmcm_clkout5 rise@12.002ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        1.291ns  (logic 0.076ns (5.887%)  route 1.215ns (94.113%))
  Logic Levels:           0  
  Clock Path Skew:        -0.049ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.492ns = ( 16.494 - 12.002 ) 
    Source Clock Delay      (SCD):    4.246ns
    Clock Pessimism Removal (CPR):    -0.295ns
  Clock Uncertainty:      0.076ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.499ns (routing 0.632ns, distribution 0.867ns)
  Clock Net Delay (Destination): 1.352ns (routing 0.575ns, distribution 0.777ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.524     2.610    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     2.483 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.236     2.719    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y115        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.747 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.499     4.246    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/clk
    SLICE_X103Y341       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X103Y341       FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     4.322 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/Q
                         net (fo=176, routed)         1.215     5.537    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/out[0]
    SLICE_X104Y352       FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[13]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                     12.002    12.002 r  
    J19                                               0.000    12.002 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079    12.081    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475    12.556 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040    12.596    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000    12.596 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297    12.893    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    12.917 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.364    14.281    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630    14.911 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.207    15.118    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y115        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    15.142 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.352    16.494    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/clk
    SLICE_X104Y352       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[13]/C
                         clock pessimism             -0.295    16.200    
                         clock uncertainty           -0.076    16.124    
    SLICE_X104Y352       FDCE (Recov_HFF2_SLICEM_C_CLR)
                                                     -0.066    16.058    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[13]
  -------------------------------------------------------------------
                         required time                         16.058    
                         arrival time                          -5.537    
  -------------------------------------------------------------------
                         slack                                 10.521    

Slack (MET) :             10.521ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[18]/CLR
                            (recovery check against rising-edge clock mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            12.002ns  (mmcm_clkout5 rise@12.002ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        1.291ns  (logic 0.076ns (5.887%)  route 1.215ns (94.113%))
  Logic Levels:           0  
  Clock Path Skew:        -0.049ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.492ns = ( 16.494 - 12.002 ) 
    Source Clock Delay      (SCD):    4.246ns
    Clock Pessimism Removal (CPR):    -0.295ns
  Clock Uncertainty:      0.076ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.499ns (routing 0.632ns, distribution 0.867ns)
  Clock Net Delay (Destination): 1.352ns (routing 0.575ns, distribution 0.777ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.524     2.610    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     2.483 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.236     2.719    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y115        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.747 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.499     4.246    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/clk
    SLICE_X103Y341       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X103Y341       FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     4.322 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/Q
                         net (fo=176, routed)         1.215     5.537    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/out[0]
    SLICE_X104Y352       FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[18]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                     12.002    12.002 r  
    J19                                               0.000    12.002 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079    12.081    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475    12.556 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040    12.596    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000    12.596 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297    12.893    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    12.917 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.364    14.281    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630    14.911 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.207    15.118    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y115        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    15.142 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.352    16.494    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/clk
    SLICE_X104Y352       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[18]/C
                         clock pessimism             -0.295    16.200    
                         clock uncertainty           -0.076    16.124    
    SLICE_X104Y352       FDCE (Recov_EFF_SLICEM_C_CLR)
                                                     -0.066    16.058    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[18]
  -------------------------------------------------------------------
                         required time                         16.058    
                         arrival time                          -5.537    
  -------------------------------------------------------------------
                         slack                                 10.521    

Slack (MET) :             10.521ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[6]/CLR
                            (recovery check against rising-edge clock mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            12.002ns  (mmcm_clkout5 rise@12.002ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        1.291ns  (logic 0.076ns (5.887%)  route 1.215ns (94.113%))
  Logic Levels:           0  
  Clock Path Skew:        -0.049ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.492ns = ( 16.494 - 12.002 ) 
    Source Clock Delay      (SCD):    4.246ns
    Clock Pessimism Removal (CPR):    -0.295ns
  Clock Uncertainty:      0.076ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.499ns (routing 0.632ns, distribution 0.867ns)
  Clock Net Delay (Destination): 1.352ns (routing 0.575ns, distribution 0.777ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.524     2.610    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     2.483 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.236     2.719    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y115        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.747 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.499     4.246    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/clk
    SLICE_X103Y341       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X103Y341       FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     4.322 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/Q
                         net (fo=176, routed)         1.215     5.537    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/out[0]
    SLICE_X104Y352       FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[6]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                     12.002    12.002 r  
    J19                                               0.000    12.002 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079    12.081    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475    12.556 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040    12.596    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000    12.596 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297    12.893    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    12.917 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.364    14.281    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630    14.911 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.207    15.118    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y115        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    15.142 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.352    16.494    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/clk
    SLICE_X104Y352       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[6]/C
                         clock pessimism             -0.295    16.200    
                         clock uncertainty           -0.076    16.124    
    SLICE_X104Y352       FDCE (Recov_GFF_SLICEM_C_CLR)
                                                     -0.066    16.058    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[6]
  -------------------------------------------------------------------
                         required time                         16.058    
                         arrival time                          -5.537    
  -------------------------------------------------------------------
                         slack                                 10.521    

Slack (MET) :             10.521ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[7]/CLR
                            (recovery check against rising-edge clock mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            12.002ns  (mmcm_clkout5 rise@12.002ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        1.291ns  (logic 0.076ns (5.887%)  route 1.215ns (94.113%))
  Logic Levels:           0  
  Clock Path Skew:        -0.049ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.492ns = ( 16.494 - 12.002 ) 
    Source Clock Delay      (SCD):    4.246ns
    Clock Pessimism Removal (CPR):    -0.295ns
  Clock Uncertainty:      0.076ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.499ns (routing 0.632ns, distribution 0.867ns)
  Clock Net Delay (Destination): 1.352ns (routing 0.575ns, distribution 0.777ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.524     2.610    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     2.483 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.236     2.719    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y115        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.747 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.499     4.246    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/clk
    SLICE_X103Y341       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X103Y341       FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     4.322 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/Q
                         net (fo=176, routed)         1.215     5.537    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/out[0]
    SLICE_X104Y352       FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[7]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                     12.002    12.002 r  
    J19                                               0.000    12.002 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079    12.081    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475    12.556 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040    12.596    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000    12.596 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297    12.893    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    12.917 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.364    14.281    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630    14.911 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.207    15.118    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y115        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    15.142 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.352    16.494    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/clk
    SLICE_X104Y352       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[7]/C
                         clock pessimism             -0.295    16.200    
                         clock uncertainty           -0.076    16.124    
    SLICE_X104Y352       FDCE (Recov_GFF2_SLICEM_C_CLR)
                                                     -0.066    16.058    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[7]
  -------------------------------------------------------------------
                         required time                         16.058    
                         arrival time                          -5.537    
  -------------------------------------------------------------------
                         slack                                 10.521    

Slack (MET) :             10.521ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[8]/CLR
                            (recovery check against rising-edge clock mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            12.002ns  (mmcm_clkout5 rise@12.002ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        1.291ns  (logic 0.076ns (5.887%)  route 1.215ns (94.113%))
  Logic Levels:           0  
  Clock Path Skew:        -0.049ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.492ns = ( 16.494 - 12.002 ) 
    Source Clock Delay      (SCD):    4.246ns
    Clock Pessimism Removal (CPR):    -0.295ns
  Clock Uncertainty:      0.076ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.499ns (routing 0.632ns, distribution 0.867ns)
  Clock Net Delay (Destination): 1.352ns (routing 0.575ns, distribution 0.777ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.524     2.610    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     2.483 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.236     2.719    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y115        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.747 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.499     4.246    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/clk
    SLICE_X103Y341       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X103Y341       FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     4.322 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/Q
                         net (fo=176, routed)         1.215     5.537    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/out[0]
    SLICE_X104Y352       FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[8]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                     12.002    12.002 r  
    J19                                               0.000    12.002 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079    12.081    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475    12.556 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040    12.596    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000    12.596 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297    12.893    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    12.917 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.364    14.281    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630    14.911 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.207    15.118    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y115        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    15.142 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.352    16.494    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/clk
    SLICE_X104Y352       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[8]/C
                         clock pessimism             -0.295    16.200    
                         clock uncertainty           -0.076    16.124    
    SLICE_X104Y352       FDCE (Recov_FFF_SLICEM_C_CLR)
                                                     -0.066    16.058    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[8]
  -------------------------------------------------------------------
                         required time                         16.058    
                         arrival time                          -5.537    
  -------------------------------------------------------------------
                         slack                                 10.521    

Slack (MET) :             10.530ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[14]/CLR
                            (recovery check against rising-edge clock mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            12.002ns  (mmcm_clkout5 rise@12.002ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        1.279ns  (logic 0.076ns (5.943%)  route 1.203ns (94.057%))
  Logic Levels:           0  
  Clock Path Skew:        -0.052ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.489ns = ( 16.491 - 12.002 ) 
    Source Clock Delay      (SCD):    4.246ns
    Clock Pessimism Removal (CPR):    -0.295ns
  Clock Uncertainty:      0.076ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.499ns (routing 0.632ns, distribution 0.867ns)
  Clock Net Delay (Destination): 1.349ns (routing 0.575ns, distribution 0.774ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.524     2.610    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     2.483 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.236     2.719    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y115        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.747 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.499     4.246    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/clk
    SLICE_X103Y341       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X103Y341       FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     4.322 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/Q
                         net (fo=176, routed)         1.203     5.525    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/out[0]
    SLICE_X105Y352       FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[14]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                     12.002    12.002 r  
    J19                                               0.000    12.002 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079    12.081    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475    12.556 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040    12.596    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000    12.596 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297    12.893    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    12.917 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.364    14.281    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630    14.911 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.207    15.118    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y115        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    15.142 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.349    16.491    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/clk
    SLICE_X105Y352       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[14]/C
                         clock pessimism             -0.295    16.197    
                         clock uncertainty           -0.076    16.121    
    SLICE_X105Y352       FDCE (Recov_DFF_SLICEL_C_CLR)
                                                     -0.066    16.055    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[14]
  -------------------------------------------------------------------
                         required time                         16.055    
                         arrival time                          -5.525    
  -------------------------------------------------------------------
                         slack                                 10.530    

Slack (MET) :             10.533ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[10]/CLR
                            (recovery check against rising-edge clock mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            12.002ns  (mmcm_clkout5 rise@12.002ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        1.278ns  (logic 0.076ns (5.947%)  route 1.202ns (94.053%))
  Logic Levels:           0  
  Clock Path Skew:        -0.050ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.491ns = ( 16.493 - 12.002 ) 
    Source Clock Delay      (SCD):    4.246ns
    Clock Pessimism Removal (CPR):    -0.295ns
  Clock Uncertainty:      0.076ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.499ns (routing 0.632ns, distribution 0.867ns)
  Clock Net Delay (Destination): 1.351ns (routing 0.575ns, distribution 0.776ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.524     2.610    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     2.483 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.236     2.719    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y115        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.747 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.499     4.246    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/clk
    SLICE_X103Y341       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X103Y341       FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     4.322 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/Q
                         net (fo=176, routed)         1.202     5.524    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/out[0]
    SLICE_X105Y352       FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[10]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                     12.002    12.002 r  
    J19                                               0.000    12.002 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079    12.081    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475    12.556 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040    12.596    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000    12.596 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297    12.893    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    12.917 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.364    14.281    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630    14.911 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.207    15.118    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y115        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    15.142 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.351    16.493    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/clk
    SLICE_X105Y352       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[10]/C
                         clock pessimism             -0.295    16.199    
                         clock uncertainty           -0.076    16.123    
    SLICE_X105Y352       FDCE (Recov_HFF2_SLICEL_C_CLR)
                                                     -0.066    16.057    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[10]
  -------------------------------------------------------------------
                         required time                         16.057    
                         arrival time                          -5.524    
  -------------------------------------------------------------------
                         slack                                 10.533    

Slack (MET) :             10.743ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[15]/CLR
                            (recovery check against rising-edge clock mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            12.002ns  (mmcm_clkout5 rise@12.002ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        1.066ns  (logic 0.076ns (7.130%)  route 0.990ns (92.870%))
  Logic Levels:           0  
  Clock Path Skew:        -0.052ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.488ns = ( 16.491 - 12.002 ) 
    Source Clock Delay      (SCD):    4.246ns
    Clock Pessimism Removal (CPR):    -0.295ns
  Clock Uncertainty:      0.076ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.499ns (routing 0.632ns, distribution 0.867ns)
  Clock Net Delay (Destination): 1.348ns (routing 0.575ns, distribution 0.773ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.524     2.610    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     2.483 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.236     2.719    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y115        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.747 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.499     4.246    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/clk
    SLICE_X103Y341       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X103Y341       FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     4.322 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/Q
                         net (fo=176, routed)         0.990     5.312    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/out[0]
    SLICE_X104Y353       FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[15]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                     12.002    12.002 r  
    J19                                               0.000    12.002 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079    12.081    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475    12.556 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040    12.596    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000    12.596 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297    12.893    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    12.917 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.364    14.281    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630    14.911 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.207    15.118    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y115        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    15.142 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.348    16.491    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/clk
    SLICE_X104Y353       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[15]/C
                         clock pessimism             -0.295    16.196    
                         clock uncertainty           -0.076    16.120    
    SLICE_X104Y353       FDCE (Recov_DFF2_SLICEM_C_CLR)
                                                     -0.066    16.054    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[15]
  -------------------------------------------------------------------
                         required time                         16.054    
                         arrival time                          -5.312    
  -------------------------------------------------------------------
                         slack                                 10.743    

Slack (MET) :             10.743ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/clr_abort_rd_reg/CLR
                            (recovery check against rising-edge clock mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            12.002ns  (mmcm_clkout5 rise@12.002ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        1.066ns  (logic 0.076ns (7.130%)  route 0.990ns (92.870%))
  Logic Levels:           0  
  Clock Path Skew:        -0.052ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.488ns = ( 16.491 - 12.002 ) 
    Source Clock Delay      (SCD):    4.246ns
    Clock Pessimism Removal (CPR):    -0.295ns
  Clock Uncertainty:      0.076ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.499ns (routing 0.632ns, distribution 0.867ns)
  Clock Net Delay (Destination): 1.348ns (routing 0.575ns, distribution 0.773ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.524     2.610    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     2.483 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.236     2.719    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y115        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.747 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.499     4.246    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/clk
    SLICE_X103Y341       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X103Y341       FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     4.322 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/Q
                         net (fo=176, routed)         0.990     5.312    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/out[0]
    SLICE_X104Y353       FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/clr_abort_rd_reg/CLR
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                     12.002    12.002 r  
    J19                                               0.000    12.002 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079    12.081    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475    12.556 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040    12.596    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000    12.596 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297    12.893    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    12.917 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.364    14.281    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630    14.911 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.207    15.118    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y115        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    15.142 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.348    16.491    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/clk
    SLICE_X104Y353       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/clr_abort_rd_reg/C
                         clock pessimism             -0.295    16.196    
                         clock uncertainty           -0.076    16.120    
    SLICE_X104Y353       FDCE (Recov_BFF_SLICEM_C_CLR)
                                                     -0.066    16.054    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/clr_abort_rd_reg
  -------------------------------------------------------------------
                         required time                         16.054    
                         arrival time                          -5.312    
  -------------------------------------------------------------------
                         slack                                 10.743    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.114ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]/C
                            (rising edge-triggered cell FDPE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i_reg/PRE
                            (removal check against rising-edge clock mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (mmcm_clkout5 rise@0.000ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        0.110ns  (logic 0.040ns (36.469%)  route 0.070ns (63.531%))
  Logic Levels:           0  
  Clock Path Skew:        0.016ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.599ns
    Source Clock Delay      (SCD):    2.711ns
    Clock Pessimism Removal (CPR):    -0.127ns
  Clock Net Delay (Source):      0.868ns (routing 0.347ns, distribution 0.521ns)
  Clock Net Delay (Destination): 0.989ns (routing 0.388ns, distribution 0.601ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.839     1.456    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     1.686 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.140     1.826    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y115        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.843 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.868     2.711    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_clk
    SLICE_X105Y371       FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X105Y371       FDPE (Prop_AFF2_SLICEL_C_Q)
                                                      0.040     2.751 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]/Q
                         net (fo=10, routed)          0.070     2.820    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/AR[0]
    SLICE_X105Y371       FDPE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i_reg/PRE
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.940     1.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     1.432 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.159     1.591    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y115        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.610 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.989     2.599    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/rd_clk
    SLICE_X105Y371       FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i_reg/C
                         clock pessimism              0.127     2.726    
    SLICE_X105Y371       FDPE (Remov_HFF2_SLICEL_C_PRE)
                                                     -0.020     2.706    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i_reg
  -------------------------------------------------------------------
                         required time                         -2.706    
                         arrival time                           2.820    
  -------------------------------------------------------------------
                         slack                                  0.114    

Slack (MET) :             0.114ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]/C
                            (rising edge-triggered cell FDPE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i_reg/PRE
                            (removal check against rising-edge clock mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (mmcm_clkout5 rise@0.000ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        0.110ns  (logic 0.040ns (36.469%)  route 0.070ns (63.531%))
  Logic Levels:           0  
  Clock Path Skew:        0.016ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.599ns
    Source Clock Delay      (SCD):    2.711ns
    Clock Pessimism Removal (CPR):    -0.127ns
  Clock Net Delay (Source):      0.868ns (routing 0.347ns, distribution 0.521ns)
  Clock Net Delay (Destination): 0.989ns (routing 0.388ns, distribution 0.601ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.839     1.456    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     1.686 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.140     1.826    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y115        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.843 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.868     2.711    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_clk
    SLICE_X105Y371       FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X105Y371       FDPE (Prop_AFF2_SLICEL_C_Q)
                                                      0.040     2.751 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]/Q
                         net (fo=10, routed)          0.070     2.820    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/AR[0]
    SLICE_X105Y371       FDPE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i_reg/PRE
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.940     1.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     1.432 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.159     1.591    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y115        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.610 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.989     2.599    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/rd_clk
    SLICE_X105Y371       FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i_reg/C
                         clock pessimism              0.127     2.726    
    SLICE_X105Y371       FDPE (Remov_GFF2_SLICEL_C_PRE)
                                                     -0.020     2.706    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i_reg
  -------------------------------------------------------------------
                         required time                         -2.706    
                         arrival time                           2.820    
  -------------------------------------------------------------------
                         slack                                  0.114    

Slack (MET) :             0.114ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]/C
                            (rising edge-triggered cell FDPE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_reg[0]/PRE
                            (removal check against rising-edge clock mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (mmcm_clkout5 rise@0.000ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        0.110ns  (logic 0.040ns (36.469%)  route 0.070ns (63.531%))
  Logic Levels:           0  
  Clock Path Skew:        0.016ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.599ns
    Source Clock Delay      (SCD):    2.711ns
    Clock Pessimism Removal (CPR):    -0.127ns
  Clock Net Delay (Source):      0.868ns (routing 0.347ns, distribution 0.521ns)
  Clock Net Delay (Destination): 0.989ns (routing 0.388ns, distribution 0.601ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.839     1.456    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     1.686 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.140     1.826    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y115        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.843 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.868     2.711    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_clk
    SLICE_X105Y371       FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X105Y371       FDPE (Prop_AFF2_SLICEL_C_Q)
                                                      0.040     2.751 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]/Q
                         net (fo=10, routed)          0.070     2.820    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/AR[0]
    SLICE_X105Y371       FDPE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_reg[0]/PRE
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.940     1.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     1.432 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.159     1.591    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y115        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.610 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.989     2.599    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/rd_clk
    SLICE_X105Y371       FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_reg[0]/C
                         clock pessimism              0.127     2.726    
    SLICE_X105Y371       FDPE (Remov_HFF_SLICEL_C_PRE)
                                                     -0.020     2.706    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_reg[0]
  -------------------------------------------------------------------
                         required time                         -2.706    
                         arrival time                           2.820    
  -------------------------------------------------------------------
                         slack                                  0.114    

Slack (MET) :             0.114ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]/C
                            (rising edge-triggered cell FDPE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_reg[2]/CLR
                            (removal check against rising-edge clock mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (mmcm_clkout5 rise@0.000ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        0.110ns  (logic 0.040ns (36.469%)  route 0.070ns (63.531%))
  Logic Levels:           0  
  Clock Path Skew:        0.016ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.599ns
    Source Clock Delay      (SCD):    2.711ns
    Clock Pessimism Removal (CPR):    -0.127ns
  Clock Net Delay (Source):      0.868ns (routing 0.347ns, distribution 0.521ns)
  Clock Net Delay (Destination): 0.989ns (routing 0.388ns, distribution 0.601ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.839     1.456    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     1.686 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.140     1.826    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y115        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.843 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.868     2.711    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_clk
    SLICE_X105Y371       FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X105Y371       FDPE (Prop_AFF2_SLICEL_C_Q)
                                                      0.040     2.751 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]/Q
                         net (fo=10, routed)          0.070     2.820    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/AR[0]
    SLICE_X105Y371       FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_reg[2]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.940     1.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     1.432 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.159     1.591    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y115        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.610 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.989     2.599    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/rd_clk
    SLICE_X105Y371       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_reg[2]/C
                         clock pessimism              0.127     2.726    
    SLICE_X105Y371       FDCE (Remov_GFF_SLICEL_C_CLR)
                                                     -0.020     2.706    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_reg[2]
  -------------------------------------------------------------------
                         required time                         -2.706    
                         arrival time                           2.820    
  -------------------------------------------------------------------
                         slack                                  0.114    

Slack (MET) :             0.119ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]/C
                            (rising edge-triggered cell FDPE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_reg[1]/CLR
                            (removal check against rising-edge clock mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (mmcm_clkout5 rise@0.000ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        0.113ns  (logic 0.040ns (35.278%)  route 0.073ns (64.722%))
  Logic Levels:           0  
  Clock Path Skew:        0.014ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.568ns
    Source Clock Delay      (SCD):    2.686ns
    Clock Pessimism Removal (CPR):    -0.131ns
  Clock Net Delay (Source):      0.843ns (routing 0.347ns, distribution 0.496ns)
  Clock Net Delay (Destination): 0.959ns (routing 0.388ns, distribution 0.571ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.839     1.456    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     1.686 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.140     1.826    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y115        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.843 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.843     2.686    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_clk
    SLICE_X101Y345       FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X101Y345       FDPE (Prop_EFF2_SLICEL_C_Q)
                                                      0.040     2.726 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]/Q
                         net (fo=12, routed)          0.073     2.799    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_reg[0]_0[0]
    SLICE_X102Y345       FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_reg[1]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.940     1.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     1.432 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.159     1.591    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y115        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.610 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.959     2.568    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/wr_clk
    SLICE_X102Y345       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_reg[1]/C
                         clock pessimism              0.131     2.700    
    SLICE_X102Y345       FDCE (Remov_EFF_SLICEL_C_CLR)
                                                     -0.020     2.680    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_reg[1]
  -------------------------------------------------------------------
                         required time                         -2.680    
                         arrival time                           2.799    
  -------------------------------------------------------------------
                         slack                                  0.119    

Slack (MET) :             0.119ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]/C
                            (rising edge-triggered cell FDPE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_reg[2]/CLR
                            (removal check against rising-edge clock mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (mmcm_clkout5 rise@0.000ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        0.113ns  (logic 0.040ns (35.278%)  route 0.073ns (64.722%))
  Logic Levels:           0  
  Clock Path Skew:        0.014ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.568ns
    Source Clock Delay      (SCD):    2.686ns
    Clock Pessimism Removal (CPR):    -0.131ns
  Clock Net Delay (Source):      0.843ns (routing 0.347ns, distribution 0.496ns)
  Clock Net Delay (Destination): 0.959ns (routing 0.388ns, distribution 0.571ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.839     1.456    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     1.686 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.140     1.826    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y115        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.843 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.843     2.686    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_clk
    SLICE_X101Y345       FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X101Y345       FDPE (Prop_EFF2_SLICEL_C_Q)
                                                      0.040     2.726 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]/Q
                         net (fo=12, routed)          0.073     2.799    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_reg[0]_0[0]
    SLICE_X102Y345       FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_reg[2]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.940     1.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     1.432 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.159     1.591    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y115        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.610 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.959     2.568    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/wr_clk
    SLICE_X102Y345       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_reg[2]/C
                         clock pessimism              0.131     2.700    
    SLICE_X102Y345       FDCE (Remov_EFF2_SLICEL_C_CLR)
                                                     -0.020     2.680    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_reg[2]
  -------------------------------------------------------------------
                         required time                         -2.680    
                         arrival time                           2.799    
  -------------------------------------------------------------------
                         slack                                  0.119    

Slack (MET) :             0.119ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]/C
                            (rising edge-triggered cell FDPE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_reg[3]/CLR
                            (removal check against rising-edge clock mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (mmcm_clkout5 rise@0.000ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        0.113ns  (logic 0.040ns (35.278%)  route 0.073ns (64.722%))
  Logic Levels:           0  
  Clock Path Skew:        0.014ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.568ns
    Source Clock Delay      (SCD):    2.686ns
    Clock Pessimism Removal (CPR):    -0.131ns
  Clock Net Delay (Source):      0.843ns (routing 0.347ns, distribution 0.496ns)
  Clock Net Delay (Destination): 0.959ns (routing 0.388ns, distribution 0.571ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.839     1.456    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     1.686 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.140     1.826    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y115        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.843 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.843     2.686    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_clk
    SLICE_X101Y345       FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X101Y345       FDPE (Prop_EFF2_SLICEL_C_Q)
                                                      0.040     2.726 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]/Q
                         net (fo=12, routed)          0.073     2.799    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_reg[0]_0[0]
    SLICE_X102Y345       FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_reg[3]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.940     1.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     1.432 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.159     1.591    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y115        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.610 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.959     2.568    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/wr_clk
    SLICE_X102Y345       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_reg[3]/C
                         clock pessimism              0.131     2.700    
    SLICE_X102Y345       FDCE (Remov_FFF_SLICEL_C_CLR)
                                                     -0.020     2.680    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_reg[3]
  -------------------------------------------------------------------
                         required time                         -2.680    
                         arrival time                           2.799    
  -------------------------------------------------------------------
                         slack                                  0.119    

Slack (MET) :             0.119ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]/C
                            (rising edge-triggered cell FDPE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_reg[1]/CLR
                            (removal check against rising-edge clock mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (mmcm_clkout5 rise@0.000ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        0.113ns  (logic 0.040ns (35.278%)  route 0.073ns (64.722%))
  Logic Levels:           0  
  Clock Path Skew:        0.014ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.568ns
    Source Clock Delay      (SCD):    2.686ns
    Clock Pessimism Removal (CPR):    -0.131ns
  Clock Net Delay (Source):      0.843ns (routing 0.347ns, distribution 0.496ns)
  Clock Net Delay (Destination): 0.959ns (routing 0.388ns, distribution 0.571ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.839     1.456    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     1.686 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.140     1.826    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y115        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.843 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.843     2.686    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_clk
    SLICE_X101Y345       FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X101Y345       FDPE (Prop_EFF2_SLICEL_C_Q)
                                                      0.040     2.726 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]/Q
                         net (fo=12, routed)          0.073     2.799    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_reg[0]_0[0]
    SLICE_X102Y345       FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_reg[1]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.940     1.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     1.432 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.159     1.591    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y115        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.610 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.959     2.568    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/wr_clk
    SLICE_X102Y345       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_reg[1]/C
                         clock pessimism              0.131     2.700    
    SLICE_X102Y345       FDCE (Remov_FFF2_SLICEL_C_CLR)
                                                     -0.020     2.680    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_reg[1]
  -------------------------------------------------------------------
                         required time                         -2.680    
                         arrival time                           2.799    
  -------------------------------------------------------------------
                         slack                                  0.119    

Slack (MET) :             0.119ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]/C
                            (rising edge-triggered cell FDPE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_reg[2]/CLR
                            (removal check against rising-edge clock mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (mmcm_clkout5 rise@0.000ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        0.113ns  (logic 0.040ns (35.278%)  route 0.073ns (64.722%))
  Logic Levels:           0  
  Clock Path Skew:        0.014ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.568ns
    Source Clock Delay      (SCD):    2.686ns
    Clock Pessimism Removal (CPR):    -0.131ns
  Clock Net Delay (Source):      0.843ns (routing 0.347ns, distribution 0.496ns)
  Clock Net Delay (Destination): 0.959ns (routing 0.388ns, distribution 0.571ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.839     1.456    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     1.686 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.140     1.826    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y115        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.843 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.843     2.686    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_clk
    SLICE_X101Y345       FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X101Y345       FDPE (Prop_EFF2_SLICEL_C_Q)
                                                      0.040     2.726 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]/Q
                         net (fo=12, routed)          0.073     2.799    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_reg[0]_0[0]
    SLICE_X102Y345       FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_reg[2]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.940     1.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     1.432 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.159     1.591    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y115        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.610 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.959     2.568    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/wr_clk
    SLICE_X102Y345       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_reg[2]/C
                         clock pessimism              0.131     2.700    
    SLICE_X102Y345       FDCE (Remov_GFF_SLICEL_C_CLR)
                                                     -0.020     2.680    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_reg[2]
  -------------------------------------------------------------------
                         required time                         -2.680    
                         arrival time                           2.799    
  -------------------------------------------------------------------
                         slack                                  0.119    

Slack (MET) :             0.119ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]/C
                            (rising edge-triggered cell FDPE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_reg[3]/CLR
                            (removal check against rising-edge clock mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (mmcm_clkout5 rise@0.000ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        0.113ns  (logic 0.040ns (35.278%)  route 0.073ns (64.722%))
  Logic Levels:           0  
  Clock Path Skew:        0.014ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.568ns
    Source Clock Delay      (SCD):    2.686ns
    Clock Pessimism Removal (CPR):    -0.131ns
  Clock Net Delay (Source):      0.843ns (routing 0.347ns, distribution 0.496ns)
  Clock Net Delay (Destination): 0.959ns (routing 0.388ns, distribution 0.571ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.839     1.456    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     1.686 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.140     1.826    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y115        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.843 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.843     2.686    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_clk
    SLICE_X101Y345       FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X101Y345       FDPE (Prop_EFF2_SLICEL_C_Q)
                                                      0.040     2.726 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]/Q
                         net (fo=12, routed)          0.073     2.799    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_reg[0]_0[0]
    SLICE_X102Y345       FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_reg[3]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.940     1.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     1.432 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.159     1.591    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y115        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.610 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.959     2.568    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/wr_clk
    SLICE_X102Y345       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_reg[3]/C
                         clock pessimism              0.131     2.700    
    SLICE_X102Y345       FDCE (Remov_GFF2_SLICEL_C_CLR)
                                                     -0.020     2.680    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_reg[3]
  -------------------------------------------------------------------
                         required time                         -2.680    
                         arrival time                           2.799    
  -------------------------------------------------------------------
                         slack                                  0.119    





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  RFDAC0_CLK
  To Clock:  

Max Delay             8 Endpoints
Min Delay             8 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[2]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            PMOD0_2_LS
                            (output port)
  Path Group:             (none)
  Path Type:              Max at Slow Process Corner
  Data Path Delay:        3.955ns  (logic 0.945ns (23.889%)  route 3.010ns (76.111%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.856ns (routing 1.460ns, distribution 1.396ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y100       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89456, routed)       2.856     3.529    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
    SLICE_X54Y177        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X54Y177        FDCE (Prop_HFF_SLICEM_C_Q)
                                                      0.079     3.608 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[2]/Q
                         net (fo=2, routed)           3.010     6.618    PMOD0_2_LS_OBUF
    H16                  OBUF (Prop_OUTBUF_HPIOB_S_I_O)
                                                      0.866     7.484 r  PMOD0_2_LS_OBUF_inst/O
                         net (fo=0)                   0.000     7.484    PMOD0_2_LS
    H16                                                               r  PMOD0_2_LS (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[4]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            PMOD0_4_LS
                            (output port)
  Path Group:             (none)
  Path Type:              Max at Slow Process Corner
  Data Path Delay:        3.518ns  (logic 0.948ns (26.935%)  route 2.570ns (73.065%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.943ns (routing 1.460ns, distribution 1.483ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y100       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89456, routed)       2.943     3.616    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
    SLICE_X69Y170        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X69Y170        FDCE (Prop_DFF_SLICEM_C_Q)
                                                      0.078     3.694 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[4]/Q
                         net (fo=2, routed)           2.570     6.264    PMOD0_4_LS_OBUF
    J16                  OBUF (Prop_OUTBUF_HPIOB_S_I_O)
                                                      0.870     7.134 r  PMOD0_4_LS_OBUF_inst/O
                         net (fo=0)                   0.000     7.134    PMOD0_4_LS
    J16                                                               r  PMOD0_4_LS (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[3]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            PMOD0_3_LS
                            (output port)
  Path Group:             (none)
  Path Type:              Max at Slow Process Corner
  Data Path Delay:        3.637ns  (logic 0.943ns (25.925%)  route 2.694ns (74.075%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.821ns (routing 1.460ns, distribution 1.361ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y100       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89456, routed)       2.821     3.494    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
    SLICE_X56Y220        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X56Y220        FDCE (Prop_DFF_SLICEM_C_Q)
                                                      0.078     3.572 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[3]/Q
                         net (fo=2, routed)           2.694     6.266    PMOD0_3_LS_OBUF
    H17                  OBUF (Prop_OUTBUF_HPIOB_M_I_O)
                                                      0.865     7.131 r  PMOD0_3_LS_OBUF_inst/O
                         net (fo=0)                   0.000     7.131    PMOD0_3_LS
    H17                                                               r  PMOD0_3_LS (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[0]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            PMOD0_0_LS
                            (output port)
  Path Group:             (none)
  Path Type:              Max at Slow Process Corner
  Data Path Delay:        3.485ns  (logic 0.927ns (26.614%)  route 2.557ns (73.386%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.953ns (routing 1.460ns, distribution 1.493ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y100       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89456, routed)       2.953     3.626    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
    SLICE_X68Y239        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X68Y239        FDCE (Prop_HFF2_SLICEL_C_Q)
                                                      0.080     3.706 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[0]/Q
                         net (fo=2, routed)           2.557     6.263    PMOD0_0_LS_OBUF
    C17                  OBUF (Prop_OUTBUF_HPIOB_M_I_O)
                                                      0.847     7.111 r  PMOD0_0_LS_OBUF_inst/O
                         net (fo=0)                   0.000     7.111    PMOD0_0_LS
    C17                                                               r  PMOD0_0_LS (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[1]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            PMOD0_1_LS
                            (output port)
  Path Group:             (none)
  Path Type:              Max at Slow Process Corner
  Data Path Delay:        3.286ns  (logic 0.937ns (28.517%)  route 2.349ns (71.483%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.937ns (routing 1.460ns, distribution 1.477ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y100       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89456, routed)       2.937     3.610    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
    SLICE_X69Y229        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X69Y229        FDCE (Prop_CFF_SLICEM_C_Q)
                                                      0.078     3.688 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[1]/Q
                         net (fo=2, routed)           2.349     6.038    PMOD0_1_LS_OBUF
    M18                  OBUF (Prop_OUTBUF_HPIOB_SNGL_I_O)
                                                      0.859     6.897 r  PMOD0_1_LS_OBUF_inst/O
                         net (fo=0)                   0.000     6.897    PMOD0_1_LS
    M18                                                               r  PMOD0_1_LS (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[5]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            PMOD0_5_LS
                            (output port)
  Path Group:             (none)
  Path Type:              Max at Slow Process Corner
  Data Path Delay:        3.009ns  (logic 0.948ns (31.500%)  route 2.061ns (68.500%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.932ns (routing 1.460ns, distribution 1.472ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y100       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89456, routed)       2.932     3.605    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
    SLICE_X74Y225        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[5]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X74Y225        FDCE (Prop_DFF_SLICEL_C_Q)
                                                      0.079     3.684 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[5]/Q
                         net (fo=2, routed)           2.061     5.745    PMOD0_5_LS_OBUF
    K16                  OBUF (Prop_OUTBUF_HPIOB_M_I_O)
                                                      0.869     6.614 r  PMOD0_5_LS_OBUF_inst/O
                         net (fo=0)                   0.000     6.614    PMOD0_5_LS
    K16                                                               r  PMOD0_5_LS (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[6]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            PMOD0_6_LS
                            (output port)
  Path Group:             (none)
  Path Type:              Max at Slow Process Corner
  Data Path Delay:        2.976ns  (logic 0.938ns (31.532%)  route 2.037ns (68.468%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.933ns (routing 1.460ns, distribution 1.473ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y100       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89456, routed)       2.933     3.606    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
    SLICE_X71Y230        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[6]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X71Y230        FDCE (Prop_DFF_SLICEL_C_Q)
                                                      0.079     3.685 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[6]/Q
                         net (fo=2, routed)           2.037     5.723    PMOD0_6_LS_OBUF
    H15                  OBUF (Prop_OUTBUF_HPIOB_S_I_O)
                                                      0.859     6.582 r  PMOD0_6_LS_OBUF_inst/O
                         net (fo=0)                   0.000     6.582    PMOD0_6_LS
    H15                                                               r  PMOD0_6_LS (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[7]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            PMOD0_7_LS
                            (output port)
  Path Group:             (none)
  Path Type:              Max at Slow Process Corner
  Data Path Delay:        2.899ns  (logic 0.938ns (32.356%)  route 1.961ns (67.644%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.937ns (routing 1.460ns, distribution 1.477ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y100       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89456, routed)       2.937     3.610    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
    SLICE_X74Y235        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[7]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X74Y235        FDCE (Prop_DFF_SLICEL_C_Q)
                                                      0.079     3.689 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[7]/Q
                         net (fo=2, routed)           1.961     5.650    PMOD0_7_LS_OBUF
    J15                  OBUF (Prop_OUTBUF_HPIOB_M_I_O)
                                                      0.859     6.509 r  PMOD0_7_LS_OBUF_inst/O
                         net (fo=0)                   0.000     6.509    PMOD0_7_LS
    J15                                                               r  PMOD0_7_LS (OUT)
  -------------------------------------------------------------------    -------------------





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[7]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            PMOD0_7_LS
                            (output port)
  Path Group:             (none)
  Path Type:              Min at Fast Process Corner
  Data Path Delay:        1.416ns  (logic 0.472ns (33.313%)  route 0.944ns (66.687%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.601ns (routing 0.786ns, distribution 0.815ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y100       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89456, routed)       1.601     1.950    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
    SLICE_X74Y235        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[7]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X74Y235        FDCE (Prop_DFF_SLICEL_C_Q)
                                                      0.039     1.989 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[7]/Q
                         net (fo=2, routed)           0.944     2.933    PMOD0_7_LS_OBUF
    J15                  OBUF (Prop_OUTBUF_HPIOB_M_I_O)
                                                      0.433     3.366 r  PMOD0_7_LS_OBUF_inst/O
                         net (fo=0)                   0.000     3.366    PMOD0_7_LS
    J15                                                               r  PMOD0_7_LS (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[6]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            PMOD0_6_LS
                            (output port)
  Path Group:             (none)
  Path Type:              Min at Fast Process Corner
  Data Path Delay:        1.443ns  (logic 0.472ns (32.696%)  route 0.971ns (67.304%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.596ns (routing 0.786ns, distribution 0.810ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y100       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89456, routed)       1.596     1.945    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
    SLICE_X71Y230        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[6]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X71Y230        FDCE (Prop_DFF_SLICEL_C_Q)
                                                      0.039     1.984 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[6]/Q
                         net (fo=2, routed)           0.971     2.955    PMOD0_6_LS_OBUF
    H15                  OBUF (Prop_OUTBUF_HPIOB_S_I_O)
                                                      0.433     3.387 r  PMOD0_6_LS_OBUF_inst/O
                         net (fo=0)                   0.000     3.387    PMOD0_6_LS
    H15                                                               r  PMOD0_6_LS (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[5]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            PMOD0_5_LS
                            (output port)
  Path Group:             (none)
  Path Type:              Min at Fast Process Corner
  Data Path Delay:        1.468ns  (logic 0.481ns (32.776%)  route 0.987ns (67.224%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.598ns (routing 0.786ns, distribution 0.812ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y100       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89456, routed)       1.598     1.947    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
    SLICE_X74Y225        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[5]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X74Y225        FDCE (Prop_DFF_SLICEL_C_Q)
                                                      0.039     1.986 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[5]/Q
                         net (fo=2, routed)           0.987     2.973    PMOD0_5_LS_OBUF
    K16                  OBUF (Prop_OUTBUF_HPIOB_M_I_O)
                                                      0.442     3.415 r  PMOD0_5_LS_OBUF_inst/O
                         net (fo=0)                   0.000     3.415    PMOD0_5_LS
    K16                                                               r  PMOD0_5_LS (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[1]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            PMOD0_1_LS
                            (output port)
  Path Group:             (none)
  Path Type:              Min at Fast Process Corner
  Data Path Delay:        1.597ns  (logic 0.471ns (29.477%)  route 1.126ns (70.523%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.599ns (routing 0.786ns, distribution 0.813ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y100       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89456, routed)       1.599     1.948    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
    SLICE_X69Y229        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X69Y229        FDCE (Prop_CFF_SLICEM_C_Q)
                                                      0.038     1.986 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[1]/Q
                         net (fo=2, routed)           1.126     3.112    PMOD0_1_LS_OBUF
    M18                  OBUF (Prop_OUTBUF_HPIOB_SNGL_I_O)
                                                      0.433     3.544 r  PMOD0_1_LS_OBUF_inst/O
                         net (fo=0)                   0.000     3.544    PMOD0_1_LS
    M18                                                               r  PMOD0_1_LS (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[0]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            PMOD0_0_LS
                            (output port)
  Path Group:             (none)
  Path Type:              Min at Fast Process Corner
  Data Path Delay:        1.697ns  (logic 0.460ns (27.116%)  route 1.237ns (72.884%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.601ns (routing 0.786ns, distribution 0.815ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y100       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89456, routed)       1.601     1.950    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
    SLICE_X68Y239        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X68Y239        FDCE (Prop_HFF2_SLICEL_C_Q)
                                                      0.039     1.989 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[0]/Q
                         net (fo=2, routed)           1.237     3.225    PMOD0_0_LS_OBUF
    C17                  OBUF (Prop_OUTBUF_HPIOB_M_I_O)
                                                      0.421     3.646 r  PMOD0_0_LS_OBUF_inst/O
                         net (fo=0)                   0.000     3.646    PMOD0_0_LS
    C17                                                               r  PMOD0_0_LS (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[4]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            PMOD0_4_LS
                            (output port)
  Path Group:             (none)
  Path Type:              Min at Fast Process Corner
  Data Path Delay:        1.727ns  (logic 0.482ns (27.905%)  route 1.245ns (72.095%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.606ns (routing 0.786ns, distribution 0.820ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y100       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89456, routed)       1.606     1.955    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
    SLICE_X69Y170        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X69Y170        FDCE (Prop_DFF_SLICEM_C_Q)
                                                      0.039     1.994 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[4]/Q
                         net (fo=2, routed)           1.245     3.239    PMOD0_4_LS_OBUF
    J16                  OBUF (Prop_OUTBUF_HPIOB_S_I_O)
                                                      0.443     3.682 r  PMOD0_4_LS_OBUF_inst/O
                         net (fo=0)                   0.000     3.682    PMOD0_4_LS
    J16                                                               r  PMOD0_4_LS (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[3]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            PMOD0_3_LS
                            (output port)
  Path Group:             (none)
  Path Type:              Min at Fast Process Corner
  Data Path Delay:        1.797ns  (logic 0.477ns (26.558%)  route 1.320ns (73.442%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.538ns (routing 0.786ns, distribution 0.752ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y100       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89456, routed)       1.538     1.887    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
    SLICE_X56Y220        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X56Y220        FDCE (Prop_DFF_SLICEM_C_Q)
                                                      0.039     1.926 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[3]/Q
                         net (fo=2, routed)           1.320     3.246    PMOD0_3_LS_OBUF
    H17                  OBUF (Prop_OUTBUF_HPIOB_M_I_O)
                                                      0.438     3.684 r  PMOD0_3_LS_OBUF_inst/O
                         net (fo=0)                   0.000     3.684    PMOD0_3_LS
    H17                                                               r  PMOD0_3_LS (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[2]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            PMOD0_2_LS
                            (output port)
  Path Group:             (none)
  Path Type:              Min at Fast Process Corner
  Data Path Delay:        1.954ns  (logic 0.478ns (24.472%)  route 1.476ns (75.528%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.556ns (routing 0.786ns, distribution 0.770ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y100       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89456, routed)       1.556     1.905    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
    SLICE_X54Y177        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X54Y177        FDCE (Prop_HFF_SLICEM_C_Q)
                                                      0.039     1.944 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[2]/Q
                         net (fo=2, routed)           1.476     3.420    PMOD0_2_LS_OBUF
    H16                  OBUF (Prop_OUTBUF_HPIOB_S_I_O)
                                                      0.439     3.859 r  PMOD0_2_LS_OBUF_inst/O
                         net (fo=0)                   0.000     3.859    PMOD0_2_LS
    H16                                                               r  PMOD0_2_LS (OUT)
  -------------------------------------------------------------------    -------------------





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  
  To Clock:  RFADC0_CLK

Max Delay             1 Endpoint
Min Delay             1 Endpoint
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/EMIOGPIOO[95]
                            (internal pin)
  Destination:            d_1_i/rst_adc0/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
                            (rising edge-triggered cell FDRE clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.454ns  (logic 0.069ns (1.998%)  route 3.385ns (98.002%))
  Logic Levels:           1  (LUT1=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.584ns (routing 1.251ns, distribution 1.333ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    PS8_X0Y0             PS8                          0.000     0.000 f  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/EMIOGPIOO[95]
                         net (fo=5, routed)           3.138     3.138    d_1_i/rst_adc0/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/ext_reset_in
    SLICE_X102Y63        LUT1 (Prop_A5LUT_SLICEL_I0_O)
                                                      0.069     3.207 r  d_1_i/rst_adc0/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1/O
                         net (fo=1, routed)           0.247     3.454    d_1_i/rst_adc0/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/exr_d1
    SLICE_X103Y63        FDRE                                         r  d_1_i/rst_adc0/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
    X4Y4 (CLOCK_ROOT)    net (fo=35, routed)          2.584     2.970    d_1_i/rst_adc0/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/slowest_sync_clk
    SLICE_X103Y63        FDRE                                         r  d_1_i/rst_adc0/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/EMIOGPIOO[95]
                            (internal pin)
  Destination:            d_1_i/rst_adc0/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
                            (rising edge-triggered cell FDRE clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.673ns  (logic 0.020ns (1.195%)  route 1.653ns (98.805%))
  Logic Levels:           1  (LUT1=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.794ns (routing 0.844ns, distribution 0.950ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    PS8_X0Y0             PS8                          0.000     0.000 f  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/EMIOGPIOO[95]
                         net (fo=5, routed)           1.552     1.552    d_1_i/rst_adc0/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/ext_reset_in
    SLICE_X102Y63        LUT1 (Prop_A5LUT_SLICEL_I0_O)
                                                      0.020     1.572 r  d_1_i/rst_adc0/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1/O
                         net (fo=1, routed)           0.101     1.673    d_1_i/rst_adc0/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/exr_d1
    SLICE_X103Y63        FDRE                                         r  d_1_i/rst_adc0/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
    X4Y4 (CLOCK_ROOT)    net (fo=35, routed)          1.794     2.146    d_1_i/rst_adc0/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/slowest_sync_clk
    SLICE_X103Y63        FDRE                                         r  d_1_i/rst_adc0/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  
  To Clock:  RFDAC0_CLK

Max Delay             1 Endpoint
Min Delay             1 Endpoint
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/EMIOGPIOO[95]
                            (internal pin)
  Destination:            d_1_i/rst_dac0/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.401ns  (logic 0.097ns (2.852%)  route 3.304ns (97.148%))
  Logic Levels:           1  (LUT1=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.857ns (routing 1.327ns, distribution 1.530ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    PS8_X0Y0             PS8                          0.000     0.000 f  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/EMIOGPIOO[95]
                         net (fo=5, routed)           3.051     3.051    d_1_i/rst_dac0/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/ext_reset_in
    SLICE_X101Y70        LUT1 (Prop_G6LUT_SLICEL_I0_O)
                                                      0.097     3.148 r  d_1_i/rst_dac0/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1/O
                         net (fo=1, routed)           0.253     3.401    d_1_i/rst_dac0/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/exr_d1
    SLICE_X101Y70        FDRE                                         r  d_1_i/rst_dac0/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y100       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89456, routed)       2.857     3.378    d_1_i/rst_dac0/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/slowest_sync_clk
    SLICE_X101Y70        FDRE                                         r  d_1_i/rst_dac0/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/EMIOGPIOO[95]
                            (internal pin)
  Destination:            d_1_i/rst_dac0/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.652ns  (logic 0.040ns (2.421%)  route 1.612ns (97.579%))
  Logic Levels:           1  (LUT1=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.953ns (routing 0.877ns, distribution 1.076ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    PS8_X0Y0             PS8                          0.000     0.000 f  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/EMIOGPIOO[95]
                         net (fo=5, routed)           1.507     1.507    d_1_i/rst_dac0/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/ext_reset_in
    SLICE_X101Y70        LUT1 (Prop_G6LUT_SLICEL_I0_O)
                                                      0.040     1.547 r  d_1_i/rst_dac0/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1/O
                         net (fo=1, routed)           0.105     1.652    d_1_i/rst_dac0/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/exr_d1
    SLICE_X101Y70        FDRE                                         r  d_1_i/rst_dac0/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y100       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89456, routed)       1.953     2.401    d_1_i/rst_dac0/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/slowest_sync_clk
    SLICE_X101Y70        FDRE                                         r  d_1_i/rst_dac0/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  RFDAC0_CLK
  To Clock:  RFDAC0_CLK

Max Delay         29858 Endpoints
Min Delay         29858 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_replica_9/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        5.973ns  (logic 0.156ns (2.612%)  route 5.817ns (97.388%))
  Logic Levels:           2  (BUFGCE=1 LUT1=1)
  Clock Path Skew:        -0.438ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.337ns
    Source Clock Delay      (SCD):    3.774ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      3.101ns (routing 1.460ns, distribution 1.641ns)
  Clock Net Delay (Destination): 2.816ns (routing 1.327ns, distribution 1.489ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y100       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89456, routed)       3.101     3.774    d_1_i/rst_dac0/U0/slowest_sync_clk
    SLICE_X86Y270        FDRE                                         r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X86Y270        FDRE (Prop_AFF_SLICEM_C_Q)
                                                      0.077     3.851 r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           0.590     4.441    d_1_i/rst_dac0/U0/peripheral_aresetn[0]
    BUFGCE_X0Y101        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     4.469 r  d_1_i/rst_dac0/U0/peripheral_aresetn[0]_BUFG_inst/O
                         net (fo=29042, routed)       1.169     5.638    d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/aresetn
    SLICE_X91Y212        LUT1 (Prop_E6LUT_SLICEL_I0_O)
                                                      0.051     5.689 r  d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_xlnx_opt/O
                         net (fo=18, routed)          4.058     9.747    d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_xlnx_opt_1
    SLICE_X81Y362        FDRE                                         r  d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_replica_9/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y100       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89456, routed)       2.816     3.337    d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/aclk
    SLICE_X81Y362        FDRE                                         r  d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_replica_9/C

Slack:                    inf
  Source:                 d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_replica_11/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        5.748ns  (logic 0.156ns (2.714%)  route 5.592ns (97.286%))
  Logic Levels:           2  (BUFGCE=1 LUT1=1)
  Clock Path Skew:        -0.441ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.334ns
    Source Clock Delay      (SCD):    3.774ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      3.101ns (routing 1.460ns, distribution 1.641ns)
  Clock Net Delay (Destination): 2.813ns (routing 1.327ns, distribution 1.486ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y100       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89456, routed)       3.101     3.774    d_1_i/rst_dac0/U0/slowest_sync_clk
    SLICE_X86Y270        FDRE                                         r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X86Y270        FDRE (Prop_AFF_SLICEM_C_Q)
                                                      0.077     3.851 r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           0.590     4.441    d_1_i/rst_dac0/U0/peripheral_aresetn[0]
    BUFGCE_X0Y101        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     4.469 r  d_1_i/rst_dac0/U0/peripheral_aresetn[0]_BUFG_inst/O
                         net (fo=29042, routed)       1.169     5.638    d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/aresetn
    SLICE_X91Y212        LUT1 (Prop_E6LUT_SLICEL_I0_O)
                                                      0.051     5.689 r  d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_xlnx_opt/O
                         net (fo=18, routed)          3.833     9.522    d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_xlnx_opt_1
    SLICE_X80Y329        FDRE                                         r  d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_replica_11/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y100       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89456, routed)       2.813     3.334    d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/aclk
    SLICE_X80Y329        FDRE                                         r  d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_replica_11/C

Slack:                    inf
  Source:                 d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_replica_13/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        5.646ns  (logic 0.156ns (2.763%)  route 5.490ns (97.237%))
  Logic Levels:           2  (BUFGCE=1 LUT1=1)
  Clock Path Skew:        -0.446ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.328ns
    Source Clock Delay      (SCD):    3.774ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      3.101ns (routing 1.460ns, distribution 1.641ns)
  Clock Net Delay (Destination): 2.807ns (routing 1.327ns, distribution 1.480ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y100       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89456, routed)       3.101     3.774    d_1_i/rst_dac0/U0/slowest_sync_clk
    SLICE_X86Y270        FDRE                                         r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X86Y270        FDRE (Prop_AFF_SLICEM_C_Q)
                                                      0.077     3.851 r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           0.590     4.441    d_1_i/rst_dac0/U0/peripheral_aresetn[0]
    BUFGCE_X0Y101        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     4.469 r  d_1_i/rst_dac0/U0/peripheral_aresetn[0]_BUFG_inst/O
                         net (fo=29042, routed)       1.169     5.638    d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/aresetn
    SLICE_X91Y212        LUT1 (Prop_E6LUT_SLICEL_I0_O)
                                                      0.051     5.689 r  d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_xlnx_opt/O
                         net (fo=18, routed)          3.731     9.420    d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_xlnx_opt_1
    SLICE_X91Y337        FDRE                                         r  d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_replica_13/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y100       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89456, routed)       2.807     3.328    d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/aclk
    SLICE_X91Y337        FDRE                                         r  d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_replica_13/C

Slack:                    inf
  Source:                 d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_replica_10/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        4.806ns  (logic 0.156ns (3.246%)  route 4.650ns (96.754%))
  Logic Levels:           2  (BUFGCE=1 LUT1=1)
  Clock Path Skew:        -0.480ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.294ns
    Source Clock Delay      (SCD):    3.774ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      3.101ns (routing 1.460ns, distribution 1.641ns)
  Clock Net Delay (Destination): 2.773ns (routing 1.327ns, distribution 1.446ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y100       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89456, routed)       3.101     3.774    d_1_i/rst_dac0/U0/slowest_sync_clk
    SLICE_X86Y270        FDRE                                         r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X86Y270        FDRE (Prop_AFF_SLICEM_C_Q)
                                                      0.077     3.851 r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           0.590     4.441    d_1_i/rst_dac0/U0/peripheral_aresetn[0]
    BUFGCE_X0Y101        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     4.469 r  d_1_i/rst_dac0/U0/peripheral_aresetn[0]_BUFG_inst/O
                         net (fo=29042, routed)       1.169     5.638    d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/aresetn
    SLICE_X91Y212        LUT1 (Prop_E6LUT_SLICEL_I0_O)
                                                      0.051     5.689 r  d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_xlnx_opt/O
                         net (fo=18, routed)          2.891     8.580    d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_xlnx_opt_1
    SLICE_X82Y280        FDRE                                         r  d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_replica_10/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y100       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89456, routed)       2.773     3.294    d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/aclk
    SLICE_X82Y280        FDRE                                         r  d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_replica_10/C

Slack:                    inf
  Source:                 d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_replica_8/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        4.746ns  (logic 0.156ns (3.287%)  route 4.590ns (96.713%))
  Logic Levels:           2  (BUFGCE=1 LUT1=1)
  Clock Path Skew:        -0.470ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.305ns
    Source Clock Delay      (SCD):    3.774ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      3.101ns (routing 1.460ns, distribution 1.641ns)
  Clock Net Delay (Destination): 2.784ns (routing 1.327ns, distribution 1.457ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y100       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89456, routed)       3.101     3.774    d_1_i/rst_dac0/U0/slowest_sync_clk
    SLICE_X86Y270        FDRE                                         r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X86Y270        FDRE (Prop_AFF_SLICEM_C_Q)
                                                      0.077     3.851 r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           0.590     4.441    d_1_i/rst_dac0/U0/peripheral_aresetn[0]
    BUFGCE_X0Y101        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     4.469 r  d_1_i/rst_dac0/U0/peripheral_aresetn[0]_BUFG_inst/O
                         net (fo=29042, routed)       1.169     5.638    d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/aresetn
    SLICE_X91Y212        LUT1 (Prop_E6LUT_SLICEL_I0_O)
                                                      0.051     5.689 r  d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_xlnx_opt/O
                         net (fo=18, routed)          2.831     8.520    d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_xlnx_opt_1
    SLICE_X86Y122        FDRE                                         r  d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_replica_8/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y100       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89456, routed)       2.784     3.305    d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/aclk
    SLICE_X86Y122        FDRE                                         r  d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_replica_8/C

Slack:                    inf
  Source:                 d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_replica_15/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        4.452ns  (logic 0.156ns (3.504%)  route 4.296ns (96.496%))
  Logic Levels:           2  (BUFGCE=1 LUT1=1)
  Clock Path Skew:        -0.399ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.376ns
    Source Clock Delay      (SCD):    3.774ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      3.101ns (routing 1.460ns, distribution 1.641ns)
  Clock Net Delay (Destination): 2.855ns (routing 1.327ns, distribution 1.528ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y100       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89456, routed)       3.101     3.774    d_1_i/rst_dac0/U0/slowest_sync_clk
    SLICE_X86Y270        FDRE                                         r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X86Y270        FDRE (Prop_AFF_SLICEM_C_Q)
                                                      0.077     3.851 r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           0.590     4.441    d_1_i/rst_dac0/U0/peripheral_aresetn[0]
    BUFGCE_X0Y101        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     4.469 r  d_1_i/rst_dac0/U0/peripheral_aresetn[0]_BUFG_inst/O
                         net (fo=29042, routed)       1.169     5.638    d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/aresetn
    SLICE_X91Y212        LUT1 (Prop_E6LUT_SLICEL_I0_O)
                                                      0.051     5.689 r  d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_xlnx_opt/O
                         net (fo=18, routed)          2.537     8.226    d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_xlnx_opt_1
    SLICE_X100Y274       FDRE                                         r  d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_replica_15/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y100       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89456, routed)       2.855     3.376    d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/aclk
    SLICE_X100Y274       FDRE                                         r  d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_replica_15/C

Slack:                    inf
  Source:                 d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_replica_12/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        4.357ns  (logic 0.156ns (3.580%)  route 4.201ns (96.420%))
  Logic Levels:           2  (BUFGCE=1 LUT1=1)
  Clock Path Skew:        -0.456ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.318ns
    Source Clock Delay      (SCD):    3.774ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      3.101ns (routing 1.460ns, distribution 1.641ns)
  Clock Net Delay (Destination): 2.797ns (routing 1.327ns, distribution 1.470ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y100       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89456, routed)       3.101     3.774    d_1_i/rst_dac0/U0/slowest_sync_clk
    SLICE_X86Y270        FDRE                                         r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X86Y270        FDRE (Prop_AFF_SLICEM_C_Q)
                                                      0.077     3.851 r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           0.590     4.441    d_1_i/rst_dac0/U0/peripheral_aresetn[0]
    BUFGCE_X0Y101        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     4.469 r  d_1_i/rst_dac0/U0/peripheral_aresetn[0]_BUFG_inst/O
                         net (fo=29042, routed)       1.169     5.638    d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/aresetn
    SLICE_X91Y212        LUT1 (Prop_E6LUT_SLICEL_I0_O)
                                                      0.051     5.689 r  d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_xlnx_opt/O
                         net (fo=18, routed)          2.442     8.132    d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_xlnx_opt_1
    SLICE_X96Y267        FDRE                                         r  d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_replica_12/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y100       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89456, routed)       2.797     3.318    d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/aclk
    SLICE_X96Y267        FDRE                                         r  d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_replica_12/C

Slack:                    inf
  Source:                 d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        4.117ns  (logic 0.156ns (3.789%)  route 3.961ns (96.211%))
  Logic Levels:           2  (BUFGCE=1 LUT1=1)
  Clock Path Skew:        -0.376ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.399ns
    Source Clock Delay      (SCD):    3.774ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      3.101ns (routing 1.460ns, distribution 1.641ns)
  Clock Net Delay (Destination): 2.878ns (routing 1.327ns, distribution 1.551ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y100       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89456, routed)       3.101     3.774    d_1_i/rst_dac0/U0/slowest_sync_clk
    SLICE_X86Y270        FDRE                                         r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X86Y270        FDRE (Prop_AFF_SLICEM_C_Q)
                                                      0.077     3.851 r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           0.590     4.441    d_1_i/rst_dac0/U0/peripheral_aresetn[0]
    BUFGCE_X0Y101        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     4.469 r  d_1_i/rst_dac0/U0/peripheral_aresetn[0]_BUFG_inst/O
                         net (fo=29042, routed)       1.169     5.638    d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/aresetn
    SLICE_X91Y212        LUT1 (Prop_E6LUT_SLICEL_I0_O)
                                                      0.051     5.689 r  d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_xlnx_opt/O
                         net (fo=18, routed)          2.202     7.891    d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_xlnx_opt_1
    SLICE_X103Y253       FDRE                                         r  d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y100       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89456, routed)       2.878     3.399    d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/aclk
    SLICE_X103Y253       FDRE                                         r  d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg/C

Slack:                    inf
  Source:                 d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_replica_16/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.837ns  (logic 0.156ns (4.065%)  route 3.681ns (95.935%))
  Logic Levels:           2  (BUFGCE=1 LUT1=1)
  Clock Path Skew:        -0.437ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.338ns
    Source Clock Delay      (SCD):    3.774ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      3.101ns (routing 1.460ns, distribution 1.641ns)
  Clock Net Delay (Destination): 2.817ns (routing 1.327ns, distribution 1.490ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y100       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89456, routed)       3.101     3.774    d_1_i/rst_dac0/U0/slowest_sync_clk
    SLICE_X86Y270        FDRE                                         r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X86Y270        FDRE (Prop_AFF_SLICEM_C_Q)
                                                      0.077     3.851 r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           0.590     4.441    d_1_i/rst_dac0/U0/peripheral_aresetn[0]
    BUFGCE_X0Y101        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     4.469 r  d_1_i/rst_dac0/U0/peripheral_aresetn[0]_BUFG_inst/O
                         net (fo=29042, routed)       1.169     5.638    d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/aresetn
    SLICE_X91Y212        LUT1 (Prop_E6LUT_SLICEL_I0_O)
                                                      0.051     5.689 r  d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_xlnx_opt/O
                         net (fo=18, routed)          1.922     7.612    d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_xlnx_opt_1
    SLICE_X98Y221        FDRE                                         r  d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_replica_16/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y100       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89456, routed)       2.817     3.338    d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/aclk
    SLICE_X98Y221        FDRE                                         r  d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_replica_16/C

Slack:                    inf
  Source:                 d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_replica_3/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.676ns  (logic 0.156ns (4.243%)  route 3.520ns (95.757%))
  Logic Levels:           2  (BUFGCE=1 LUT1=1)
  Clock Path Skew:        -0.433ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.342ns
    Source Clock Delay      (SCD):    3.774ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      3.101ns (routing 1.460ns, distribution 1.641ns)
  Clock Net Delay (Destination): 2.821ns (routing 1.327ns, distribution 1.494ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y100       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89456, routed)       3.101     3.774    d_1_i/rst_dac0/U0/slowest_sync_clk
    SLICE_X86Y270        FDRE                                         r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X86Y270        FDRE (Prop_AFF_SLICEM_C_Q)
                                                      0.077     3.851 r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           0.590     4.441    d_1_i/rst_dac0/U0/peripheral_aresetn[0]
    BUFGCE_X0Y101        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     4.469 r  d_1_i/rst_dac0/U0/peripheral_aresetn[0]_BUFG_inst/O
                         net (fo=29042, routed)       1.169     5.638    d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/aresetn
    SLICE_X91Y212        LUT1 (Prop_E6LUT_SLICEL_I0_O)
                                                      0.051     5.689 r  d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_xlnx_opt/O
                         net (fo=18, routed)          1.761     7.451    d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_xlnx_opt_1
    SLICE_X97Y223        FDRE                                         r  d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_replica_3/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y100       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89456, routed)       2.821     3.342    d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/aclk
    SLICE_X97Y223        FDRE                                         r  d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_replica_3/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/axis_signal_gen_v6_1/inst/signal_gen_top_i/signal_gen_i/GEN_dds[8].prodg_y_full_real_r_reg[8]/DSP_M_DATA_INST/RSTM
                            (rising edge-triggered cell DSP_M_DATA clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.937ns  (logic 0.055ns (5.870%)  route 0.882ns (94.130%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        0.312ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.350ns
    Source Clock Delay      (SCD):    2.038ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.689ns (routing 0.786ns, distribution 0.903ns)
  Clock Net Delay (Destination): 1.902ns (routing 0.877ns, distribution 1.025ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y100       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89456, routed)       1.689     2.038    d_1_i/rst_dac0/U0/slowest_sync_clk
    SLICE_X86Y270        FDRE                                         r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X86Y270        FDRE (Prop_AFF_SLICEM_C_Q)
                                                      0.038     2.076 f  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           0.314     2.390    d_1_i/rst_dac0/U0/peripheral_aresetn[0]
    BUFGCE_X0Y101        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.407 f  d_1_i/rst_dac0/U0/peripheral_aresetn[0]_BUFG_inst/O
                         net (fo=29042, routed)       0.568     2.975    d_1_i/axis_signal_gen_v6_1/inst/signal_gen_top_i/signal_gen_i/GEN_dds[8].prodg_y_full_real_r_reg[8]/RSTM
    DSP48E2_X15Y108      DSP_M_DATA                                   r  d_1_i/axis_signal_gen_v6_1/inst/signal_gen_top_i/signal_gen_i/GEN_dds[8].prodg_y_full_real_r_reg[8]/DSP_M_DATA_INST/RSTM  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y100       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89456, routed)       1.902     2.350    d_1_i/axis_signal_gen_v6_1/inst/signal_gen_top_i/signal_gen_i/GEN_dds[8].prodg_y_full_real_r_reg[8]/CLK
    DSP48E2_X15Y108      DSP_M_DATA                                   r  d_1_i/axis_signal_gen_v6_1/inst/signal_gen_top_i/signal_gen_i/GEN_dds[8].prodg_y_full_real_r_reg[8]/DSP_M_DATA_INST/CLK

Slack:                    inf
  Source:                 d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/axis_signal_gen_v6_1/inst/signal_gen_top_i/signal_gen_i/GEN_dds[14].prodg_y_full_real_r_reg[14]/DSP_M_DATA_INST/RSTM
                            (rising edge-triggered cell DSP_M_DATA clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.938ns  (logic 0.055ns (5.864%)  route 0.883ns (94.136%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        0.335ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.373ns
    Source Clock Delay      (SCD):    2.038ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.689ns (routing 0.786ns, distribution 0.903ns)
  Clock Net Delay (Destination): 1.925ns (routing 0.877ns, distribution 1.048ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y100       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89456, routed)       1.689     2.038    d_1_i/rst_dac0/U0/slowest_sync_clk
    SLICE_X86Y270        FDRE                                         r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X86Y270        FDRE (Prop_AFF_SLICEM_C_Q)
                                                      0.038     2.076 f  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           0.314     2.390    d_1_i/rst_dac0/U0/peripheral_aresetn[0]
    BUFGCE_X0Y101        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.407 f  d_1_i/rst_dac0/U0/peripheral_aresetn[0]_BUFG_inst/O
                         net (fo=29042, routed)       0.569     2.976    d_1_i/axis_signal_gen_v6_1/inst/signal_gen_top_i/signal_gen_i/GEN_dds[14].prodg_y_full_real_r_reg[14]/RSTM
    DSP48E2_X15Y107      DSP_M_DATA                                   r  d_1_i/axis_signal_gen_v6_1/inst/signal_gen_top_i/signal_gen_i/GEN_dds[14].prodg_y_full_real_r_reg[14]/DSP_M_DATA_INST/RSTM  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y100       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89456, routed)       1.925     2.373    d_1_i/axis_signal_gen_v6_1/inst/signal_gen_top_i/signal_gen_i/GEN_dds[14].prodg_y_full_real_r_reg[14]/CLK
    DSP48E2_X15Y107      DSP_M_DATA                                   r  d_1_i/axis_signal_gen_v6_1/inst/signal_gen_top_i/signal_gen_i/GEN_dds[14].prodg_y_full_real_r_reg[14]/DSP_M_DATA_INST/CLK

Slack:                    inf
  Source:                 d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/axis_signal_gen_v6_1/inst/signal_gen_top_i/signal_gen_i/GEN_dds[5].prodg_y_full_real_r_reg[5]/DSP_M_DATA_INST/RSTM
                            (rising edge-triggered cell DSP_M_DATA clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.938ns  (logic 0.055ns (5.864%)  route 0.883ns (94.136%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        0.314ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.352ns
    Source Clock Delay      (SCD):    2.038ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.689ns (routing 0.786ns, distribution 0.903ns)
  Clock Net Delay (Destination): 1.904ns (routing 0.877ns, distribution 1.027ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y100       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89456, routed)       1.689     2.038    d_1_i/rst_dac0/U0/slowest_sync_clk
    SLICE_X86Y270        FDRE                                         r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X86Y270        FDRE (Prop_AFF_SLICEM_C_Q)
                                                      0.038     2.076 f  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           0.314     2.390    d_1_i/rst_dac0/U0/peripheral_aresetn[0]
    BUFGCE_X0Y101        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.407 f  d_1_i/rst_dac0/U0/peripheral_aresetn[0]_BUFG_inst/O
                         net (fo=29042, routed)       0.569     2.976    d_1_i/axis_signal_gen_v6_1/inst/signal_gen_top_i/signal_gen_i/GEN_dds[5].prodg_y_full_real_r_reg[5]/RSTM
    DSP48E2_X15Y109      DSP_M_DATA                                   r  d_1_i/axis_signal_gen_v6_1/inst/signal_gen_top_i/signal_gen_i/GEN_dds[5].prodg_y_full_real_r_reg[5]/DSP_M_DATA_INST/RSTM  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y100       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89456, routed)       1.904     2.352    d_1_i/axis_signal_gen_v6_1/inst/signal_gen_top_i/signal_gen_i/GEN_dds[5].prodg_y_full_real_r_reg[5]/CLK
    DSP48E2_X15Y109      DSP_M_DATA                                   r  d_1_i/axis_signal_gen_v6_1/inst/signal_gen_top_i/signal_gen_i/GEN_dds[5].prodg_y_full_real_r_reg[5]/DSP_M_DATA_INST/CLK

Slack:                    inf
  Source:                 d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/axis_signal_gen_v6_1/inst/signal_gen_top_i/signal_gen_i/src_latency_reg_i/GEN_reg[15].shift_r_reg[15][0]_rep/R
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.939ns  (logic 0.055ns (5.857%)  route 0.884ns (94.143%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        0.292ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.329ns
    Source Clock Delay      (SCD):    2.038ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.689ns (routing 0.786ns, distribution 0.903ns)
  Clock Net Delay (Destination): 1.881ns (routing 0.877ns, distribution 1.004ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y100       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89456, routed)       1.689     2.038    d_1_i/rst_dac0/U0/slowest_sync_clk
    SLICE_X86Y270        FDRE                                         r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X86Y270        FDRE (Prop_AFF_SLICEM_C_Q)
                                                      0.038     2.076 f  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           0.314     2.390    d_1_i/rst_dac0/U0/peripheral_aresetn[0]
    BUFGCE_X0Y101        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.407 f  d_1_i/rst_dac0/U0/peripheral_aresetn[0]_BUFG_inst/O
                         net (fo=29042, routed)       0.570     2.977    d_1_i/axis_signal_gen_v6_1/inst/signal_gen_top_i/signal_gen_i/src_latency_reg_i/SR[0]
    SLICE_X81Y265        FDRE                                         r  d_1_i/axis_signal_gen_v6_1/inst/signal_gen_top_i/signal_gen_i/src_latency_reg_i/GEN_reg[15].shift_r_reg[15][0]_rep/R  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y100       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89456, routed)       1.881     2.329    d_1_i/axis_signal_gen_v6_1/inst/signal_gen_top_i/signal_gen_i/src_latency_reg_i/aclk
    SLICE_X81Y265        FDRE                                         r  d_1_i/axis_signal_gen_v6_1/inst/signal_gen_top_i/signal_gen_i/src_latency_reg_i/GEN_reg[15].shift_r_reg[15][0]_rep/C

Slack:                    inf
  Source:                 d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/axis_signal_gen_v6_1/inst/signal_gen_top_i/signal_gen_i/GEN_dds[1].prodg_y_full_real_r_reg[1]/DSP_M_DATA_INST/RSTM
                            (rising edge-triggered cell DSP_M_DATA clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.940ns  (logic 0.055ns (5.851%)  route 0.885ns (94.149%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        0.316ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.354ns
    Source Clock Delay      (SCD):    2.038ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.689ns (routing 0.786ns, distribution 0.903ns)
  Clock Net Delay (Destination): 1.906ns (routing 0.877ns, distribution 1.029ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y100       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89456, routed)       1.689     2.038    d_1_i/rst_dac0/U0/slowest_sync_clk
    SLICE_X86Y270        FDRE                                         r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X86Y270        FDRE (Prop_AFF_SLICEM_C_Q)
                                                      0.038     2.076 f  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           0.314     2.390    d_1_i/rst_dac0/U0/peripheral_aresetn[0]
    BUFGCE_X0Y101        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.407 f  d_1_i/rst_dac0/U0/peripheral_aresetn[0]_BUFG_inst/O
                         net (fo=29042, routed)       0.571     2.978    d_1_i/axis_signal_gen_v6_1/inst/signal_gen_top_i/signal_gen_i/GEN_dds[1].prodg_y_full_real_r_reg[1]/RSTM
    DSP48E2_X15Y110      DSP_M_DATA                                   r  d_1_i/axis_signal_gen_v6_1/inst/signal_gen_top_i/signal_gen_i/GEN_dds[1].prodg_y_full_real_r_reg[1]/DSP_M_DATA_INST/RSTM  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y100       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89456, routed)       1.906     2.354    d_1_i/axis_signal_gen_v6_1/inst/signal_gen_top_i/signal_gen_i/GEN_dds[1].prodg_y_full_real_r_reg[1]/CLK
    DSP48E2_X15Y110      DSP_M_DATA                                   r  d_1_i/axis_signal_gen_v6_1/inst/signal_gen_top_i/signal_gen_i/GEN_dds[1].prodg_y_full_real_r_reg[1]/DSP_M_DATA_INST/CLK

Slack:                    inf
  Source:                 d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/axis_signal_gen_v6_1/inst/signal_gen_top_i/signal_gen_i/GEN_dds[8].prodg_y_full_real_r_reg[8]/DSP_A_B_DATA_INST/RSTA
                            (rising edge-triggered cell DSP_A_B_DATA clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.940ns  (logic 0.055ns (5.851%)  route 0.885ns (94.149%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        0.312ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.350ns
    Source Clock Delay      (SCD):    2.038ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.689ns (routing 0.786ns, distribution 0.903ns)
  Clock Net Delay (Destination): 1.902ns (routing 0.877ns, distribution 1.025ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y100       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89456, routed)       1.689     2.038    d_1_i/rst_dac0/U0/slowest_sync_clk
    SLICE_X86Y270        FDRE                                         r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X86Y270        FDRE (Prop_AFF_SLICEM_C_Q)
                                                      0.038     2.076 f  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           0.314     2.390    d_1_i/rst_dac0/U0/peripheral_aresetn[0]
    BUFGCE_X0Y101        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.407 f  d_1_i/rst_dac0/U0/peripheral_aresetn[0]_BUFG_inst/O
                         net (fo=29042, routed)       0.571     2.978    d_1_i/axis_signal_gen_v6_1/inst/signal_gen_top_i/signal_gen_i/GEN_dds[8].prodg_y_full_real_r_reg[8]/RSTA
    DSP48E2_X15Y108      DSP_A_B_DATA                                 r  d_1_i/axis_signal_gen_v6_1/inst/signal_gen_top_i/signal_gen_i/GEN_dds[8].prodg_y_full_real_r_reg[8]/DSP_A_B_DATA_INST/RSTA  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y100       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89456, routed)       1.902     2.350    d_1_i/axis_signal_gen_v6_1/inst/signal_gen_top_i/signal_gen_i/GEN_dds[8].prodg_y_full_real_r_reg[8]/CLK
    DSP48E2_X15Y108      DSP_A_B_DATA                                 r  d_1_i/axis_signal_gen_v6_1/inst/signal_gen_top_i/signal_gen_i/GEN_dds[8].prodg_y_full_real_r_reg[8]/DSP_A_B_DATA_INST/CLK

Slack:                    inf
  Source:                 d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/axis_signal_gen_v6_1/inst/signal_gen_top_i/signal_gen_i/GEN_dds[8].prodg_y_full_real_r_reg[8]/DSP_A_B_DATA_INST/RSTB
                            (rising edge-triggered cell DSP_A_B_DATA clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.940ns  (logic 0.055ns (5.851%)  route 0.885ns (94.149%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        0.312ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.350ns
    Source Clock Delay      (SCD):    2.038ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.689ns (routing 0.786ns, distribution 0.903ns)
  Clock Net Delay (Destination): 1.902ns (routing 0.877ns, distribution 1.025ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y100       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89456, routed)       1.689     2.038    d_1_i/rst_dac0/U0/slowest_sync_clk
    SLICE_X86Y270        FDRE                                         r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X86Y270        FDRE (Prop_AFF_SLICEM_C_Q)
                                                      0.038     2.076 f  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           0.314     2.390    d_1_i/rst_dac0/U0/peripheral_aresetn[0]
    BUFGCE_X0Y101        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.407 f  d_1_i/rst_dac0/U0/peripheral_aresetn[0]_BUFG_inst/O
                         net (fo=29042, routed)       0.571     2.978    d_1_i/axis_signal_gen_v6_1/inst/signal_gen_top_i/signal_gen_i/GEN_dds[8].prodg_y_full_real_r_reg[8]/RSTB
    DSP48E2_X15Y108      DSP_A_B_DATA                                 r  d_1_i/axis_signal_gen_v6_1/inst/signal_gen_top_i/signal_gen_i/GEN_dds[8].prodg_y_full_real_r_reg[8]/DSP_A_B_DATA_INST/RSTB  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y100       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89456, routed)       1.902     2.350    d_1_i/axis_signal_gen_v6_1/inst/signal_gen_top_i/signal_gen_i/GEN_dds[8].prodg_y_full_real_r_reg[8]/CLK
    DSP48E2_X15Y108      DSP_A_B_DATA                                 r  d_1_i/axis_signal_gen_v6_1/inst/signal_gen_top_i/signal_gen_i/GEN_dds[8].prodg_y_full_real_r_reg[8]/DSP_A_B_DATA_INST/CLK

Slack:                    inf
  Source:                 d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/axis_signal_gen_v6_1/inst/signal_gen_top_i/signal_gen_i/GEN_dds[13].prodg_y_full_real_r_reg[13]/DSP_M_DATA_INST/RSTM
                            (rising edge-triggered cell DSP_M_DATA clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.941ns  (logic 0.055ns (5.845%)  route 0.886ns (94.155%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        0.324ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.362ns
    Source Clock Delay      (SCD):    2.038ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.689ns (routing 0.786ns, distribution 0.903ns)
  Clock Net Delay (Destination): 1.914ns (routing 0.877ns, distribution 1.037ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y100       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89456, routed)       1.689     2.038    d_1_i/rst_dac0/U0/slowest_sync_clk
    SLICE_X86Y270        FDRE                                         r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X86Y270        FDRE (Prop_AFF_SLICEM_C_Q)
                                                      0.038     2.076 f  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           0.314     2.390    d_1_i/rst_dac0/U0/peripheral_aresetn[0]
    BUFGCE_X0Y101        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.407 f  d_1_i/rst_dac0/U0/peripheral_aresetn[0]_BUFG_inst/O
                         net (fo=29042, routed)       0.572     2.979    d_1_i/axis_signal_gen_v6_1/inst/signal_gen_top_i/signal_gen_i/GEN_dds[13].prodg_y_full_real_r_reg[13]/RSTM
    DSP48E2_X15Y106      DSP_M_DATA                                   r  d_1_i/axis_signal_gen_v6_1/inst/signal_gen_top_i/signal_gen_i/GEN_dds[13].prodg_y_full_real_r_reg[13]/DSP_M_DATA_INST/RSTM  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y100       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89456, routed)       1.914     2.362    d_1_i/axis_signal_gen_v6_1/inst/signal_gen_top_i/signal_gen_i/GEN_dds[13].prodg_y_full_real_r_reg[13]/CLK
    DSP48E2_X15Y106      DSP_M_DATA                                   r  d_1_i/axis_signal_gen_v6_1/inst/signal_gen_top_i/signal_gen_i/GEN_dds[13].prodg_y_full_real_r_reg[13]/DSP_M_DATA_INST/CLK

Slack:                    inf
  Source:                 d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/axis_signal_gen_v6_1/inst/signal_gen_top_i/signal_gen_i/GEN_dds[5].prodg_y_full_real_r_reg[5]/DSP_A_B_DATA_INST/RSTB
                            (rising edge-triggered cell DSP_A_B_DATA clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.941ns  (logic 0.055ns (5.845%)  route 0.886ns (94.155%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        0.314ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.352ns
    Source Clock Delay      (SCD):    2.038ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.689ns (routing 0.786ns, distribution 0.903ns)
  Clock Net Delay (Destination): 1.904ns (routing 0.877ns, distribution 1.027ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y100       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89456, routed)       1.689     2.038    d_1_i/rst_dac0/U0/slowest_sync_clk
    SLICE_X86Y270        FDRE                                         r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X86Y270        FDRE (Prop_AFF_SLICEM_C_Q)
                                                      0.038     2.076 f  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           0.314     2.390    d_1_i/rst_dac0/U0/peripheral_aresetn[0]
    BUFGCE_X0Y101        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.407 f  d_1_i/rst_dac0/U0/peripheral_aresetn[0]_BUFG_inst/O
                         net (fo=29042, routed)       0.572     2.979    d_1_i/axis_signal_gen_v6_1/inst/signal_gen_top_i/signal_gen_i/GEN_dds[5].prodg_y_full_real_r_reg[5]/RSTB
    DSP48E2_X15Y109      DSP_A_B_DATA                                 r  d_1_i/axis_signal_gen_v6_1/inst/signal_gen_top_i/signal_gen_i/GEN_dds[5].prodg_y_full_real_r_reg[5]/DSP_A_B_DATA_INST/RSTB  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y100       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89456, routed)       1.904     2.352    d_1_i/axis_signal_gen_v6_1/inst/signal_gen_top_i/signal_gen_i/GEN_dds[5].prodg_y_full_real_r_reg[5]/CLK
    DSP48E2_X15Y109      DSP_A_B_DATA                                 r  d_1_i/axis_signal_gen_v6_1/inst/signal_gen_top_i/signal_gen_i/GEN_dds[5].prodg_y_full_real_r_reg[5]/DSP_A_B_DATA_INST/CLK

Slack:                    inf
  Source:                 d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/axis_signal_gen_v6_1/inst/signal_gen_top_i/signal_gen_i/GEN_dds[14].prodg_y_full_real_r_reg[14]/DSP_A_B_DATA_INST/RSTB
                            (rising edge-triggered cell DSP_A_B_DATA clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.942ns  (logic 0.055ns (5.839%)  route 0.887ns (94.161%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        0.335ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.373ns
    Source Clock Delay      (SCD):    2.038ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.689ns (routing 0.786ns, distribution 0.903ns)
  Clock Net Delay (Destination): 1.925ns (routing 0.877ns, distribution 1.048ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y100       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89456, routed)       1.689     2.038    d_1_i/rst_dac0/U0/slowest_sync_clk
    SLICE_X86Y270        FDRE                                         r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X86Y270        FDRE (Prop_AFF_SLICEM_C_Q)
                                                      0.038     2.076 f  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           0.314     2.390    d_1_i/rst_dac0/U0/peripheral_aresetn[0]
    BUFGCE_X0Y101        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.407 f  d_1_i/rst_dac0/U0/peripheral_aresetn[0]_BUFG_inst/O
                         net (fo=29042, routed)       0.573     2.980    d_1_i/axis_signal_gen_v6_1/inst/signal_gen_top_i/signal_gen_i/GEN_dds[14].prodg_y_full_real_r_reg[14]/RSTB
    DSP48E2_X15Y107      DSP_A_B_DATA                                 r  d_1_i/axis_signal_gen_v6_1/inst/signal_gen_top_i/signal_gen_i/GEN_dds[14].prodg_y_full_real_r_reg[14]/DSP_A_B_DATA_INST/RSTB  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y100       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89456, routed)       1.925     2.373    d_1_i/axis_signal_gen_v6_1/inst/signal_gen_top_i/signal_gen_i/GEN_dds[14].prodg_y_full_real_r_reg[14]/CLK
    DSP48E2_X15Y107      DSP_A_B_DATA                                 r  d_1_i/axis_signal_gen_v6_1/inst/signal_gen_top_i/signal_gen_i/GEN_dds[14].prodg_y_full_real_r_reg[14]/DSP_A_B_DATA_INST/CLK





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  clk_out1_d_1_clk_adc0_x2_0
  To Clock:  RFDAC0_CLK

Max Delay             4 Endpoints
Min Delay             4 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_reg[0]_rep/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/data_int_reg_reg[0][0]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.465ns  (logic 0.168ns (11.470%)  route 1.297ns (88.530%))
  Logic Levels:           1  (LUT2=1)
  Clock Path Skew:        -3.129ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.304ns
    Source Clock Delay      (SCD):    6.433ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.128ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.073ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      3.103ns (routing 1.545ns, distribution 1.558ns)
  Clock Net Delay (Destination): 2.783ns (routing 1.327ns, distribution 1.456ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.657     3.184    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     3.057 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     3.302    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.330 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86296, routed)       3.103     6.433    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/m_axis_aclk
    SLICE_X91Y114        FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_reg[0]_rep/C
  -------------------------------------------------------------------    -------------------
    SLICE_X91Y114        FDRE (Prop_HFF_SLICEL_C_Q)
                                                      0.079     6.512 r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_reg[0]_rep/Q
                         net (fo=139, routed)         0.754     7.266    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/data_int_reg_reg[0][0]_0[0]
    SLICE_X95Y99         LUT2 (Prop_D6LUT_SLICEL_I0_O)
                                                      0.089     7.355 r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/data_int_reg[0][0]_i_1__0/O
                         net (fo=4, routed)           0.543     7.898    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/D[0]
    SLICE_X91Y99         FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/data_int_reg_reg[0][0]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y100       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89456, routed)       2.783     3.304    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/s_axis_aclk
    SLICE_X91Y99         FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/data_int_reg_reg[0][0]/C

Slack:                    inf
  Source:                 d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/data_int_reg_reg[0][1]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.816ns  (logic 0.212ns (25.976%)  route 0.604ns (74.024%))
  Logic Levels:           1  (LUT2=1)
  Clock Path Skew:        -3.132ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.305ns
    Source Clock Delay      (SCD):    6.437ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.128ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.073ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      3.107ns (routing 1.545ns, distribution 1.562ns)
  Clock Net Delay (Destination): 2.784ns (routing 1.327ns, distribution 1.457ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.657     3.184    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     3.057 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     3.302    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.330 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86296, routed)       3.107     6.437    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/m_axis_aclk
    SLICE_X91Y102        FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X91Y102        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     6.516 r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_reg[1]/Q
                         net (fo=204, routed)         0.419     6.935    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/data_int_reg_reg[0][3]_0[0]
    SLICE_X95Y99         LUT2 (Prop_D5LUT_SLICEL_I0_O)
                                                      0.133     7.068 r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/data_int_reg[0][1]_i_1__0/O
                         net (fo=1, routed)           0.185     7.253    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/rptr_g[1]
    SLICE_X95Y98         FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/data_int_reg_reg[0][1]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y100       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89456, routed)       2.784     3.305    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/s_axis_aclk
    SLICE_X95Y98         FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/data_int_reg_reg[0][1]/C

Slack:                    inf
  Source:                 d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/data_int_reg_reg[0][2]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.654ns  (logic 0.146ns (22.322%)  route 0.508ns (77.678%))
  Logic Levels:           1  (LUT2=1)
  Clock Path Skew:        -3.136ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.308ns
    Source Clock Delay      (SCD):    6.444ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.128ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.073ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      3.114ns (routing 1.545ns, distribution 1.569ns)
  Clock Net Delay (Destination): 2.787ns (routing 1.327ns, distribution 1.460ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.657     3.184    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     3.057 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     3.302    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.330 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86296, routed)       3.114     6.444    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/m_axis_aclk
    SLICE_X94Y102        FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X94Y102        FDRE (Prop_DFF2_SLICEM_C_Q)
                                                      0.080     6.524 r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_reg[3]/Q
                         net (fo=205, routed)         0.490     7.014    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/data_int_reg_reg[0][3]_0[2]
    SLICE_X94Y96         LUT2 (Prop_H5LUT_SLICEM_I1_O)
                                                      0.066     7.080 r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/data_int_reg[0][2]_i_1__0/O
                         net (fo=1, routed)           0.018     7.098    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/rptr_g[2]
    SLICE_X94Y96         FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/data_int_reg_reg[0][2]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y100       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89456, routed)       2.787     3.308    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/s_axis_aclk
    SLICE_X94Y96         FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/data_int_reg_reg[0][2]/C

Slack:                    inf
  Source:                 d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/data_int_reg_reg[0][3]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.553ns  (logic 0.080ns (14.479%)  route 0.473ns (85.521%))
  Logic Levels:           0  
  Clock Path Skew:        -3.139ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.305ns
    Source Clock Delay      (SCD):    6.444ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.128ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.073ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      3.114ns (routing 1.545ns, distribution 1.569ns)
  Clock Net Delay (Destination): 2.784ns (routing 1.327ns, distribution 1.457ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.657     3.184    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     3.057 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     3.302    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.330 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86296, routed)       3.114     6.444    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/m_axis_aclk
    SLICE_X94Y102        FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X94Y102        FDRE (Prop_DFF2_SLICEM_C_Q)
                                                      0.080     6.524 r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_reg[3]/Q
                         net (fo=205, routed)         0.473     6.997    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/data_int_reg_reg[0][3]_0[2]
    SLICE_X95Y98         FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/data_int_reg_reg[0][3]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y100       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89456, routed)       2.784     3.305    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/s_axis_aclk
    SLICE_X95Y98         FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/data_int_reg_reg[0][3]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/data_int_reg_reg[0][2]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.211ns  (logic 0.079ns (37.389%)  route 0.132ns (62.611%))
  Logic Levels:           1  (LUT2=1)
  Clock Path Skew:        -1.459ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.354ns
    Source Clock Delay      (SCD):    3.813ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.128ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.073ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      1.706ns (routing 0.846ns, distribution 0.860ns)
  Clock Net Delay (Destination): 1.906ns (routing 0.877ns, distribution 1.029ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.451     1.714    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.944 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     2.090    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.107 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86296, routed)       1.706     3.813    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/m_axis_aclk
    SLICE_X94Y102        FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X94Y102        FDRE (Prop_BFF2_SLICEM_C_Q)
                                                      0.040     3.853 r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_reg[2]/Q
                         net (fo=207, routed)         0.126     3.979    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/data_int_reg_reg[0][3]_0[1]
    SLICE_X94Y96         LUT2 (Prop_H5LUT_SLICEM_I0_O)
                                                      0.039     4.018 r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/data_int_reg[0][2]_i_1__0/O
                         net (fo=1, routed)           0.006     4.024    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/rptr_g[2]
    SLICE_X94Y96         FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/data_int_reg_reg[0][2]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y100       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89456, routed)       1.906     2.354    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/s_axis_aclk
    SLICE_X94Y96         FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/data_int_reg_reg[0][2]/C

Slack:                    inf
  Source:                 d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/data_int_reg_reg[0][1]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.247ns  (logic 0.060ns (24.244%)  route 0.187ns (75.756%))
  Logic Levels:           1  (LUT2=1)
  Clock Path Skew:        -1.465ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.348ns
    Source Clock Delay      (SCD):    3.813ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.128ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.073ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      1.706ns (routing 0.846ns, distribution 0.860ns)
  Clock Net Delay (Destination): 1.900ns (routing 0.877ns, distribution 1.023ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.451     1.714    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.944 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     2.090    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.107 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86296, routed)       1.706     3.813    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/m_axis_aclk
    SLICE_X94Y102        FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X94Y102        FDRE (Prop_BFF2_SLICEM_C_Q)
                                                      0.040     3.853 r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_reg[2]/Q
                         net (fo=207, routed)         0.109     3.962    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/data_int_reg_reg[0][3]_0[1]
    SLICE_X95Y99         LUT2 (Prop_D5LUT_SLICEL_I1_O)
                                                      0.020     3.982 r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/data_int_reg[0][1]_i_1__0/O
                         net (fo=1, routed)           0.078     4.060    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/rptr_g[1]
    SLICE_X95Y98         FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/data_int_reg_reg[0][1]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y100       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89456, routed)       1.900     2.348    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/s_axis_aclk
    SLICE_X95Y98         FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/data_int_reg_reg[0][1]/C

Slack:                    inf
  Source:                 d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/data_int_reg_reg[0][3]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.256ns  (logic 0.041ns (16.002%)  route 0.215ns (83.998%))
  Logic Levels:           0  
  Clock Path Skew:        -1.465ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.348ns
    Source Clock Delay      (SCD):    3.813ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.128ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.073ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      1.706ns (routing 0.846ns, distribution 0.860ns)
  Clock Net Delay (Destination): 1.900ns (routing 0.877ns, distribution 1.023ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.451     1.714    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.944 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     2.090    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.107 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86296, routed)       1.706     3.813    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/m_axis_aclk
    SLICE_X94Y102        FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X94Y102        FDRE (Prop_DFF2_SLICEM_C_Q)
                                                      0.041     3.854 r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_reg[3]/Q
                         net (fo=205, routed)         0.215     4.069    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/data_int_reg_reg[0][3]_0[2]
    SLICE_X95Y98         FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/data_int_reg_reg[0][3]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y100       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89456, routed)       1.900     2.348    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/s_axis_aclk
    SLICE_X95Y98         FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/data_int_reg_reg[0][3]/C

Slack:                    inf
  Source:                 d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/data_int_reg_reg[0][0]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.556ns  (logic 0.089ns (15.998%)  route 0.467ns (84.002%))
  Logic Levels:           1  (LUT2=1)
  Clock Path Skew:        -1.460ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.350ns
    Source Clock Delay      (SCD):    3.810ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.128ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.073ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      1.703ns (routing 0.846ns, distribution 0.857ns)
  Clock Net Delay (Destination): 1.902ns (routing 0.877ns, distribution 1.025ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.451     1.714    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.944 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     2.090    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.107 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86296, routed)       1.703     3.810    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/m_axis_aclk
    SLICE_X91Y102        FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X91Y102        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.039     3.849 r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_reg[1]/Q
                         net (fo=204, routed)         0.215     4.063    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/data_int_reg_reg[0][3]_0[0]
    SLICE_X95Y99         LUT2 (Prop_D6LUT_SLICEL_I1_O)
                                                      0.050     4.113 r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/data_int_reg[0][0]_i_1__0/O
                         net (fo=4, routed)           0.253     4.366    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/D[0]
    SLICE_X91Y99         FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/data_int_reg_reg[0][0]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y100       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89456, routed)       1.902     2.350    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/s_axis_aclk
    SLICE_X91Y99         FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/data_int_reg_reg[0][0]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  clk_out1_d_1_clk_core_0
  To Clock:  RFDAC0_CLK

Max Delay           822 Endpoints
Min Delay           822 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[11].trig_fifo_inst/rd_gptr_r_reg[8]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/sync_ctrl_ps_t/data_cdc_reg[4]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        5.671ns  (logic 0.637ns (11.232%)  route 5.034ns (88.768%))
  Logic Levels:           6  (LUT4=1 LUT5=3 LUT6=2)
  Clock Path Skew:        -1.803ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.296ns
    Source Clock Delay      (SCD):    5.099ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      2.585ns (routing 1.461ns, distribution 1.124ns)
  Clock Net Delay (Destination): 2.775ns (routing 1.327ns, distribution 1.448ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=48236, routed)       2.142     2.368    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.241 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.486    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y133        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.514 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=4540, routed)        2.585     5.099    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[11].trig_fifo_inst/c_clk_i
    SLICE_X56Y207        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[11].trig_fifo_inst/rd_gptr_r_reg[8]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X56Y207        FDRE (Prop_AFF2_SLICEM_C_Q)
                                                      0.080     5.179 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[11].trig_fifo_inst/rd_gptr_r_reg[8]/Q
                         net (fo=1, routed)           0.149     5.328    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[11].trig_fifo_inst/gcc_wr_ptr/RAM_reg_0[8]
    SLICE_X55Y206        LUT6 (Prop_H6LUT_SLICEL_I3_O)
                                                      0.124     5.452 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[11].trig_fifo_inst/gcc_wr_ptr/RAM_reg_i_3__10/O
                         net (fo=3, routed)           0.478     5.930    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[11].trig_fifo_inst/gcc_wr_ptr/RAM_reg_i_3__10_n_0
    SLICE_X61Y201        LUT5 (Prop_H6LUT_SLICEM_I1_O)
                                                      0.090     6.020 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[11].trig_fifo_inst/gcc_wr_ptr/reg_A[0][31]_i_39/O
                         net (fo=3, routed)           0.638     6.658    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[11].trig_fifo_inst/gcc_wr_ptr/c_fifo_trig_full[0]
    SLICE_X66Y181        LUT4 (Prop_H6LUT_SLICEM_I0_O)
                                                      0.039     6.697 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[11].trig_fifo_inst/gcc_wr_ptr/reg_A[0][31]_i_18/O
                         net (fo=1, routed)           0.399     7.096    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[3].wave_fifo_inst/gcc_wr_ptr/c_fifo_wave_push_r_reg[0]_1
    SLICE_X70Y161        LUT5 (Prop_E6LUT_SLICEM_I3_O)
                                                      0.091     7.187 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[3].wave_fifo_inst/gcc_wr_ptr/reg_A[0][31]_i_4/O
                         net (fo=8, routed)           0.527     7.714    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[8].wave_fifo_inst/gcc_wr_ptr/c_fifo_wave_push_r_reg[0]_2
    SLICE_X71Y174        LUT5 (Prop_C6LUT_SLICEL_I3_O)
                                                      0.123     7.837 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[8].wave_fifo_inst/gcc_wr_ptr/reg_A[0][31]_i_1/O
                         net (fo=1, routed)           1.182     9.019    d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/core_en
    SLICE_X37Y157        LUT6 (Prop_H6LUT_SLICEM_I5_O)
                                                      0.090     9.109 r  d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/data_cdc[4]_i_1/O
                         net (fo=1, routed)           1.661    10.770    d_1_i/qick_processor_0/inst/QPROC/sync_ctrl_ps_t/data_cdc_reg[6]_0[4]
    SLICE_X83Y167        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/sync_ctrl_ps_t/data_cdc_reg[4]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y100       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89456, routed)       2.775     3.296    d_1_i/qick_processor_0/inst/QPROC/sync_ctrl_ps_t/t_clk_i
    SLICE_X83Y167        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/sync_ctrl_ps_t/data_cdc_reg[4]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/gcc_wr_ptr/count_gray_r_reg[4]/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/sync_ctrl_ps_t/data_cdc_reg[3]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        4.866ns  (logic 0.575ns (11.817%)  route 4.291ns (88.183%))
  Logic Levels:           7  (LUT3=2 LUT5=3 LUT6=2)
  Clock Path Skew:        -1.867ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.296ns
    Source Clock Delay      (SCD):    5.163ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      2.649ns (routing 1.461ns, distribution 1.188ns)
  Clock Net Delay (Destination): 2.775ns (routing 1.327ns, distribution 1.448ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=48236, routed)       2.142     2.368    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.241 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.486    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y133        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.514 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=4540, routed)        2.649     5.163    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/gcc_wr_ptr/c_clk_i
    SLICE_X91Y235        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/gcc_wr_ptr/count_gray_r_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X91Y235        FDCE (Prop_AFF2_SLICEL_C_Q)
                                                      0.081     5.244 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/gcc_wr_ptr/count_gray_r_reg[4]/Q
                         net (fo=8, routed)           0.788     6.032    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/gcc_wr_ptr/wr_gptr_p1[4]
    SLICE_X80Y235        LUT6 (Prop_A6LUT_SLICEL_I2_O)
                                                      0.149     6.181 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/gcc_wr_ptr/count_gray_r[8]_i_3__40/O
                         net (fo=3, routed)           0.787     6.968    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/gcc_wr_ptr/count_gray_r[8]_i_3__40_n_0
    SLICE_X71Y174        LUT5 (Prop_B6LUT_SLICEL_I0_O)
                                                      0.148     7.116 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/gcc_wr_ptr/reg_A[0][31]_i_13/O
                         net (fo=2, routed)           0.045     7.161    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[8].wave_fifo_inst/gcc_wr_ptr/c_fifo_wave_push_r_reg[0][2]
    SLICE_X71Y174        LUT5 (Prop_A6LUT_SLICEL_I3_O)
                                                      0.050     7.211 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[8].wave_fifo_inst/gcc_wr_ptr/reg_A[0][31]_i_3/O
                         net (fo=10, routed)          0.414     7.625    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[8].wave_fifo_inst/gcc_wr_ptr/clr_fifo_req_reg
    SLICE_X62Y156        LUT5 (Prop_B6LUT_SLICEL_I2_O)
                                                      0.036     7.661 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[8].wave_fifo_inst/gcc_wr_ptr/reg_A[0][31]_i_1_replica_2/O
                         net (fo=474, routed)         0.407     8.068    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/FSM_sequential_core_st_reg[0]_repN_2_alias
    SLICE_X56Y157        LUT6 (Prop_H6LUT_SLICEM_I4_O)
                                                      0.039     8.107 f  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/data_cdc[4]_i_3/O
                         net (fo=4, routed)           0.375     8.482    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/x1_ctrl_reg[usr_ctrl][5]_1
    SLICE_X47Y157        LUT3 (Prop_F6LUT_SLICEL_I0_O)
                                                      0.035     8.517 f  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/data_cdc[3]_i_2/O
                         net (fo=33, routed)          0.100     8.617    d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/data_cdc_reg[3]
    SLICE_X46Y157        LUT3 (Prop_G6LUT_SLICEM_I2_O)
                                                      0.037     8.654 r  d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/data_cdc[3]_i_1/O
                         net (fo=33, routed)          1.375    10.029    d_1_i/qick_processor_0/inst/QPROC/sync_ctrl_ps_t/data_cdc_reg[6]_0[3]
    SLICE_X83Y167        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/sync_ctrl_ps_t/data_cdc_reg[3]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y100       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89456, routed)       2.775     3.296    d_1_i/qick_processor_0/inst/QPROC/sync_ctrl_ps_t/t_clk_i
    SLICE_X83Y167        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/sync_ctrl_ps_t/data_cdc_reg[3]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/tproc_ctrl_r_reg[10]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/sync_ctrl_ps_t/data_cdc_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.408ns  (logic 0.228ns (9.468%)  route 2.180ns (90.532%))
  Logic Levels:           1  (LUT4=1)
  Clock Path Skew:        -1.914ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.291ns
    Source Clock Delay      (SCD):    5.205ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      2.691ns (routing 1.461ns, distribution 1.230ns)
  Clock Net Delay (Destination): 2.770ns (routing 1.327ns, distribution 1.443ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=48236, routed)       2.142     2.368    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.241 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.486    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y133        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.514 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=4540, routed)        2.691     5.205    d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/c_clk_i
    SLICE_X30Y150        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/tproc_ctrl_r_reg[10]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X30Y150        FDRE (Prop_EFF2_SLICEM_C_Q)
                                                      0.079     5.284 r  d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/tproc_ctrl_r_reg[10]/Q
                         net (fo=3, routed)           0.223     5.507    d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/tproc_ctrl_r[10]
    SLICE_X32Y151        LUT4 (Prop_G6LUT_SLICEL_I1_O)
                                                      0.149     5.656 r  d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/data_cdc[0]_i_1/O
                         net (fo=1, routed)           1.957     7.613    d_1_i/qick_processor_0/inst/QPROC/sync_ctrl_ps_t/data_cdc_reg[6]_0[0]
    SLICE_X84Y167        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/sync_ctrl_ps_t/data_cdc_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y100       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89456, routed)       2.770     3.291    d_1_i/qick_processor_0/inst/QPROC/sync_ctrl_ps_t/t_clk_i
    SLICE_X84Y167        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/sync_ctrl_ps_t/data_cdc_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/tproc_ctrl_r_reg[8]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/sync_ctrl_ps_t/data_cdc_reg[1]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.369ns  (logic 0.230ns (9.709%)  route 2.139ns (90.291%))
  Logic Levels:           1  (LUT4=1)
  Clock Path Skew:        -1.926ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.291ns
    Source Clock Delay      (SCD):    5.217ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      2.703ns (routing 1.461ns, distribution 1.242ns)
  Clock Net Delay (Destination): 2.770ns (routing 1.327ns, distribution 1.443ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=48236, routed)       2.142     2.368    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.241 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.486    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y133        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.514 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=4540, routed)        2.703     5.217    d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/c_clk_i
    SLICE_X29Y158        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/tproc_ctrl_r_reg[8]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X29Y158        FDRE (Prop_FFF2_SLICEL_C_Q)
                                                      0.081     5.298 r  d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/tproc_ctrl_r_reg[8]/Q
                         net (fo=3, routed)           0.172     5.470    d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/tproc_ctrl_r[8]
    SLICE_X29Y158        LUT4 (Prop_G6LUT_SLICEL_I3_O)
                                                      0.149     5.619 r  d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/data_cdc[1]_i_1__0/O
                         net (fo=1, routed)           1.967     7.586    d_1_i/qick_processor_0/inst/QPROC/sync_ctrl_ps_t/data_cdc_reg[6]_0[1]
    SLICE_X84Y167        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/sync_ctrl_ps_t/data_cdc_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y100       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89456, routed)       2.770     3.291    d_1_i/qick_processor_0/inst/QPROC/sync_ctrl_ps_t/t_clk_i
    SLICE_X84Y167        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/sync_ctrl_ps_t/data_cdc_reg[1]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/clr_fifo_ack_reg/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/gcc_rd_ptr/count_gray_r_reg[0]/CE
                            (rising edge-triggered cell FDPE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.347ns  (logic 0.351ns (14.953%)  route 1.996ns (85.047%))
  Logic Levels:           3  (LUT3=1 LUT5=1 LUT6=1)
  Clock Path Skew:        -1.656ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.391ns
    Source Clock Delay      (SCD):    5.047ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      2.533ns (routing 1.461ns, distribution 1.072ns)
  Clock Net Delay (Destination): 2.870ns (routing 1.327ns, distribution 1.543ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=48236, routed)       2.142     2.368    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.241 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.486    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y133        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.514 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=4540, routed)        2.533     5.047    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/c_clk_i
    SLICE_X80Y234        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/clr_fifo_ack_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X80Y234        FDCE (Prop_GFF_SLICEL_C_Q)
                                                      0.079     5.126 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/clr_fifo_ack_reg/Q
                         net (fo=4, routed)           0.995     6.121    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/clr_fifo_ack_reg_n_0
    SLICE_X97Y233        LUT3 (Prop_C5LUT_SLICEM_I1_O)
                                                      0.137     6.258 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/t_fifo_wave_empty_inferred_i_1/O
                         net (fo=1, routed)           0.242     6.500    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].ADDSUB_MACRO_inst/wave_pop_r_reg[11][0]
    SLICE_X97Y226        LUT6 (Prop_G6LUT_SLICEM_I0_O)
                                                      0.037     6.537 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].ADDSUB_MACRO_inst/wave_pop_r[11]_i_1/O
                         net (fo=2, routed)           0.337     6.874    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/gcc_rd_ptr/D[0]
    SLICE_X97Y253        LUT5 (Prop_F6LUT_SLICEM_I4_O)
                                                      0.098     6.972 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/gcc_rd_ptr/count_gray_r[8]_i_1__52/O
                         net (fo=18, routed)          0.422     7.394    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/gcc_rd_ptr/count_bin_2r
    SLICE_X97Y259        FDPE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/gcc_rd_ptr/count_gray_r_reg[0]/CE
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y100       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89456, routed)       2.870     3.391    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/gcc_rd_ptr/t_clk_i
    SLICE_X97Y259        FDPE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/gcc_rd_ptr/count_gray_r_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/clr_fifo_ack_reg/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/gcc_rd_ptr/count_gray_r_reg[1]/CE
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.347ns  (logic 0.351ns (14.953%)  route 1.996ns (85.047%))
  Logic Levels:           3  (LUT3=1 LUT5=1 LUT6=1)
  Clock Path Skew:        -1.656ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.391ns
    Source Clock Delay      (SCD):    5.047ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      2.533ns (routing 1.461ns, distribution 1.072ns)
  Clock Net Delay (Destination): 2.870ns (routing 1.327ns, distribution 1.543ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=48236, routed)       2.142     2.368    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.241 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.486    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y133        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.514 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=4540, routed)        2.533     5.047    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/c_clk_i
    SLICE_X80Y234        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/clr_fifo_ack_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X80Y234        FDCE (Prop_GFF_SLICEL_C_Q)
                                                      0.079     5.126 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/clr_fifo_ack_reg/Q
                         net (fo=4, routed)           0.995     6.121    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/clr_fifo_ack_reg_n_0
    SLICE_X97Y233        LUT3 (Prop_C5LUT_SLICEM_I1_O)
                                                      0.137     6.258 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/t_fifo_wave_empty_inferred_i_1/O
                         net (fo=1, routed)           0.242     6.500    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].ADDSUB_MACRO_inst/wave_pop_r_reg[11][0]
    SLICE_X97Y226        LUT6 (Prop_G6LUT_SLICEM_I0_O)
                                                      0.037     6.537 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].ADDSUB_MACRO_inst/wave_pop_r[11]_i_1/O
                         net (fo=2, routed)           0.337     6.874    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/gcc_rd_ptr/D[0]
    SLICE_X97Y253        LUT5 (Prop_F6LUT_SLICEM_I4_O)
                                                      0.098     6.972 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/gcc_rd_ptr/count_gray_r[8]_i_1__52/O
                         net (fo=18, routed)          0.422     7.394    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/gcc_rd_ptr/count_bin_2r
    SLICE_X97Y259        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/gcc_rd_ptr/count_gray_r_reg[1]/CE
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y100       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89456, routed)       2.870     3.391    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/gcc_rd_ptr/t_clk_i
    SLICE_X97Y259        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/gcc_rd_ptr/count_gray_r_reg[1]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/clr_fifo_ack_reg/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/gcc_rd_ptr/count_gray_r_reg[3]/CE
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.347ns  (logic 0.351ns (14.953%)  route 1.996ns (85.047%))
  Logic Levels:           3  (LUT3=1 LUT5=1 LUT6=1)
  Clock Path Skew:        -1.656ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.391ns
    Source Clock Delay      (SCD):    5.047ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      2.533ns (routing 1.461ns, distribution 1.072ns)
  Clock Net Delay (Destination): 2.870ns (routing 1.327ns, distribution 1.543ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=48236, routed)       2.142     2.368    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.241 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.486    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y133        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.514 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=4540, routed)        2.533     5.047    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/c_clk_i
    SLICE_X80Y234        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/clr_fifo_ack_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X80Y234        FDCE (Prop_GFF_SLICEL_C_Q)
                                                      0.079     5.126 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/clr_fifo_ack_reg/Q
                         net (fo=4, routed)           0.995     6.121    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/clr_fifo_ack_reg_n_0
    SLICE_X97Y233        LUT3 (Prop_C5LUT_SLICEM_I1_O)
                                                      0.137     6.258 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/t_fifo_wave_empty_inferred_i_1/O
                         net (fo=1, routed)           0.242     6.500    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].ADDSUB_MACRO_inst/wave_pop_r_reg[11][0]
    SLICE_X97Y226        LUT6 (Prop_G6LUT_SLICEM_I0_O)
                                                      0.037     6.537 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].ADDSUB_MACRO_inst/wave_pop_r[11]_i_1/O
                         net (fo=2, routed)           0.337     6.874    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/gcc_rd_ptr/D[0]
    SLICE_X97Y253        LUT5 (Prop_F6LUT_SLICEM_I4_O)
                                                      0.098     6.972 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/gcc_rd_ptr/count_gray_r[8]_i_1__52/O
                         net (fo=18, routed)          0.422     7.394    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/gcc_rd_ptr/count_bin_2r
    SLICE_X97Y259        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/gcc_rd_ptr/count_gray_r_reg[3]/CE
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y100       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89456, routed)       2.870     3.391    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/gcc_rd_ptr/t_clk_i
    SLICE_X97Y259        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/gcc_rd_ptr/count_gray_r_reg[3]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/clr_fifo_ack_reg/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/gcc_rd_ptr/count_gray_r_reg[4]/CE
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.347ns  (logic 0.351ns (14.953%)  route 1.996ns (85.047%))
  Logic Levels:           3  (LUT3=1 LUT5=1 LUT6=1)
  Clock Path Skew:        -1.656ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.391ns
    Source Clock Delay      (SCD):    5.047ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      2.533ns (routing 1.461ns, distribution 1.072ns)
  Clock Net Delay (Destination): 2.870ns (routing 1.327ns, distribution 1.543ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=48236, routed)       2.142     2.368    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.241 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.486    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y133        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.514 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=4540, routed)        2.533     5.047    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/c_clk_i
    SLICE_X80Y234        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/clr_fifo_ack_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X80Y234        FDCE (Prop_GFF_SLICEL_C_Q)
                                                      0.079     5.126 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/clr_fifo_ack_reg/Q
                         net (fo=4, routed)           0.995     6.121    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/clr_fifo_ack_reg_n_0
    SLICE_X97Y233        LUT3 (Prop_C5LUT_SLICEM_I1_O)
                                                      0.137     6.258 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/t_fifo_wave_empty_inferred_i_1/O
                         net (fo=1, routed)           0.242     6.500    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].ADDSUB_MACRO_inst/wave_pop_r_reg[11][0]
    SLICE_X97Y226        LUT6 (Prop_G6LUT_SLICEM_I0_O)
                                                      0.037     6.537 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].ADDSUB_MACRO_inst/wave_pop_r[11]_i_1/O
                         net (fo=2, routed)           0.337     6.874    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/gcc_rd_ptr/D[0]
    SLICE_X97Y253        LUT5 (Prop_F6LUT_SLICEM_I4_O)
                                                      0.098     6.972 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/gcc_rd_ptr/count_gray_r[8]_i_1__52/O
                         net (fo=18, routed)          0.422     7.394    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/gcc_rd_ptr/count_bin_2r
    SLICE_X97Y259        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/gcc_rd_ptr/count_gray_r_reg[4]/CE
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y100       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89456, routed)       2.870     3.391    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/gcc_rd_ptr/t_clk_i
    SLICE_X97Y259        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/gcc_rd_ptr/count_gray_r_reg[4]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/tproc_ctrl_r_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/sync_ctrl_ps_t/data_cdc_reg[2]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.116ns  (logic 0.178ns (8.413%)  route 1.938ns (91.587%))
  Logic Levels:           1  (LUT6=1)
  Clock Path Skew:        -1.929ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.289ns
    Source Clock Delay      (SCD):    5.218ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      2.704ns (routing 1.461ns, distribution 1.243ns)
  Clock Net Delay (Destination): 2.768ns (routing 1.327ns, distribution 1.441ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=48236, routed)       2.142     2.368    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.241 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.486    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y133        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.514 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=4540, routed)        2.704     5.218    d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/c_clk_i
    SLICE_X30Y159        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/tproc_ctrl_r_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X30Y159        FDRE (Prop_GFF2_SLICEM_C_Q)
                                                      0.079     5.297 r  d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/tproc_ctrl_r_reg[3]/Q
                         net (fo=3, routed)           0.271     5.568    d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/tproc_ctrl_r[3]
    SLICE_X29Y158        LUT6 (Prop_D6LUT_SLICEL_I2_O)
                                                      0.099     5.667 r  d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/data_cdc[2]_i_1/O
                         net (fo=1, routed)           1.667     7.334    d_1_i/qick_processor_0/inst/QPROC/sync_ctrl_ps_t/data_cdc_reg[6]_0[2]
    SLICE_X84Y167        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/sync_ctrl_ps_t/data_cdc_reg[2]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y100       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89456, routed)       2.768     3.289    d_1_i/qick_processor_0/inst/QPROC/sync_ctrl_ps_t/t_clk_i
    SLICE_X84Y167        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/sync_ctrl_ps_t/data_cdc_reg[2]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/tproc_ctrl_r_reg[6]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/sync_ctrl_ps_t/data_cdc_reg[5]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.108ns  (logic 0.133ns (6.308%)  route 1.975ns (93.692%))
  Logic Levels:           1  (LUT2=1)
  Clock Path Skew:        -1.931ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.289ns
    Source Clock Delay      (SCD):    5.220ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      2.706ns (routing 1.461ns, distribution 1.245ns)
  Clock Net Delay (Destination): 2.768ns (routing 1.327ns, distribution 1.441ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=48236, routed)       2.142     2.368    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.241 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.486    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y133        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.514 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=4540, routed)        2.706     5.220    d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/c_clk_i
    SLICE_X30Y159        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/tproc_ctrl_r_reg[6]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X30Y159        FDRE (Prop_BFF2_SLICEM_C_Q)
                                                      0.080     5.300 r  d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/tproc_ctrl_r_reg[6]/Q
                         net (fo=2, routed)           0.155     5.455    d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/tproc_ctrl_r[6]
    SLICE_X31Y160        LUT2 (Prop_H6LUT_SLICEM_I0_O)
                                                      0.053     5.508 r  d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/data_cdc[3]_i_1__0/O
                         net (fo=2, routed)           1.820     7.328    d_1_i/qick_processor_0/inst/QPROC/sync_ctrl_ps_t/data_cdc_reg[6]_0[5]
    SLICE_X84Y167        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/sync_ctrl_ps_t/data_cdc_reg[5]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y100       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89456, routed)       2.768     3.289    d_1_i/qick_processor_0/inst/QPROC/sync_ctrl_ps_t/t_clk_i
    SLICE_X84Y167        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/sync_ctrl_ps_t/data_cdc_reg[5]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[1]/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/wr_gptr_cdc_reg[1]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.095ns  (logic 0.039ns (41.190%)  route 0.056ns (58.810%))
  Logic Levels:           0  
  Clock Path Skew:        -0.819ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.248ns
    Source Clock Delay      (SCD):    3.067ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.381ns (routing 0.804ns, distribution 0.577ns)
  Clock Net Delay (Destination): 1.800ns (routing 0.877ns, distribution 0.923ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=48236, routed)       1.173     1.293    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.523 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.669    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y133        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.686 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=4540, routed)        1.381     3.067    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_wr_ptr/c_clk_i
    SLICE_X73Y142        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X73Y142        FDCE (Prop_HFF_SLICEL_C_Q)
                                                      0.039     3.106 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[1]/Q
                         net (fo=2, routed)           0.056     3.162    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/wr_gptr[1]
    SLICE_X73Y142        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/wr_gptr_cdc_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y100       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89456, routed)       1.800     2.248    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/t_clk_i
    SLICE_X73Y142        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/wr_gptr_cdc_reg[1]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[2]/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/wr_gptr_cdc_reg[2]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.097ns  (logic 0.039ns (40.023%)  route 0.058ns (59.977%))
  Logic Levels:           0  
  Clock Path Skew:        -0.812ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.255ns
    Source Clock Delay      (SCD):    3.067ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.381ns (routing 0.804ns, distribution 0.577ns)
  Clock Net Delay (Destination): 1.807ns (routing 0.877ns, distribution 0.930ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=48236, routed)       1.173     1.293    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.523 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.669    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y133        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.686 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=4540, routed)        1.381     3.067    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_wr_ptr/c_clk_i
    SLICE_X73Y142        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X73Y142        FDCE (Prop_GFF_SLICEL_C_Q)
                                                      0.039     3.106 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[2]/Q
                         net (fo=2, routed)           0.058     3.164    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/wr_gptr[2]
    SLICE_X73Y143        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/wr_gptr_cdc_reg[2]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y100       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89456, routed)       1.807     2.255    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/t_clk_i
    SLICE_X73Y143        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/wr_gptr_cdc_reg[2]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/clr_fifo_req_reg/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_rd_ptr/clear_cdc_reg/D
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.099ns  (logic 0.040ns (40.207%)  route 0.059ns (59.793%))
  Logic Levels:           0  
  Clock Path Skew:        -0.812ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.255ns
    Source Clock Delay      (SCD):    3.067ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.381ns (routing 0.804ns, distribution 0.577ns)
  Clock Net Delay (Destination): 1.807ns (routing 0.877ns, distribution 0.930ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=48236, routed)       1.173     1.293    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.523 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.669    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y133        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.686 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=4540, routed)        1.381     3.067    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/c_clk_i
    SLICE_X70Y141        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/clr_fifo_req_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X70Y141        FDCE (Prop_FFF2_SLICEM_C_Q)
                                                      0.040     3.107 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/clr_fifo_req_reg/Q
                         net (fo=5, routed)           0.059     3.167    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_rd_ptr/clr_fifo_req
    SLICE_X71Y140        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_rd_ptr/clear_cdc_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y100       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89456, routed)       1.807     2.255    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_rd_ptr/t_clk_i
    SLICE_X71Y140        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_rd_ptr/clear_cdc_reg/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[5]/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/wr_gptr_cdc_reg[5]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.105ns  (logic 0.039ns (37.255%)  route 0.066ns (62.745%))
  Logic Levels:           0  
  Clock Path Skew:        -0.804ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.262ns
    Source Clock Delay      (SCD):    3.066ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.380ns (routing 0.804ns, distribution 0.576ns)
  Clock Net Delay (Destination): 1.814ns (routing 0.877ns, distribution 0.937ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=48236, routed)       1.173     1.293    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.523 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.669    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y133        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.686 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=4540, routed)        1.380     3.066    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_wr_ptr/c_clk_i
    SLICE_X72Y142        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[5]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X72Y142        FDCE (Prop_HFF_SLICEM_C_Q)
                                                      0.039     3.105 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[5]/Q
                         net (fo=2, routed)           0.066     3.171    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/wr_gptr[5]
    SLICE_X72Y143        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/wr_gptr_cdc_reg[5]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y100       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89456, routed)       1.814     2.262    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/t_clk_i
    SLICE_X72Y143        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/wr_gptr_cdc_reg[5]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[8].wave_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[0]/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[8].wave_fifo_inst/wr_gptr_cdc_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.077ns  (logic 0.039ns (50.859%)  route 0.038ns (49.141%))
  Logic Levels:           0  
  Clock Path Skew:        -0.752ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.356ns
    Source Clock Delay      (SCD):    3.109ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.423ns (routing 0.804ns, distribution 0.619ns)
  Clock Net Delay (Destination): 1.908ns (routing 0.877ns, distribution 1.031ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=48236, routed)       1.173     1.293    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.523 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.669    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y133        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.686 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=4540, routed)        1.423     3.109    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[8].wave_fifo_inst/gcc_wr_ptr/c_clk_i
    SLICE_X85Y117        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[8].wave_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X85Y117        FDCE (Prop_CFF_SLICEL_C_Q)
                                                      0.039     3.148 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[8].wave_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[0]/Q
                         net (fo=4, routed)           0.038     3.185    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[8].wave_fifo_inst/wr_gptr[0]
    SLICE_X85Y116        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[8].wave_fifo_inst/wr_gptr_cdc_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y100       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89456, routed)       1.908     2.356    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[8].wave_fifo_inst/t_clk_i
    SLICE_X85Y116        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[8].wave_fifo_inst/wr_gptr_cdc_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/QPER_TIME_READ.sync_ab_en_inst/a_pulse_req_reg/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/QPER_TIME_READ.sync_ab_en_inst/pulse_req_cdc_reg/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.141ns  (logic 0.039ns (27.660%)  route 0.102ns (72.340%))
  Logic Levels:           0  
  Clock Path Skew:        -0.798ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.247ns
    Source Clock Delay      (SCD):    3.045ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.359ns (routing 0.804ns, distribution 0.555ns)
  Clock Net Delay (Destination): 1.799ns (routing 0.877ns, distribution 0.922ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=48236, routed)       1.173     1.293    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.523 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.669    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y133        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.686 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=4540, routed)        1.359     3.045    d_1_i/qick_processor_0/inst/QPROC/QPER_TIME_READ.sync_ab_en_inst/c_clk_i
    SLICE_X62Y115        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPER_TIME_READ.sync_ab_en_inst/a_pulse_req_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X62Y115        FDCE (Prop_HFF2_SLICEL_C_Q)
                                                      0.039     3.084 r  d_1_i/qick_processor_0/inst/QPROC/QPER_TIME_READ.sync_ab_en_inst/a_pulse_req_reg/Q
                         net (fo=2, routed)           0.102     3.186    d_1_i/qick_processor_0/inst/QPROC/QPER_TIME_READ.sync_ab_en_inst/a_pulse_req
    SLICE_X62Y115        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPER_TIME_READ.sync_ab_en_inst/pulse_req_cdc_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y100       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89456, routed)       1.799     2.247    d_1_i/qick_processor_0/inst/QPROC/QPER_TIME_READ.sync_ab_en_inst/t_clk_i
    SLICE_X62Y115        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPER_TIME_READ.sync_ab_en_inst/pulse_req_cdc_reg/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[6]/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/wr_gptr_cdc_reg[6]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.126ns  (logic 0.039ns (31.030%)  route 0.087ns (68.970%))
  Logic Levels:           0  
  Clock Path Skew:        -0.795ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.266ns
    Source Clock Delay      (SCD):    3.062ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.376ns (routing 0.804ns, distribution 0.572ns)
  Clock Net Delay (Destination): 1.818ns (routing 0.877ns, distribution 0.941ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=48236, routed)       1.173     1.293    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.523 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.669    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y133        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.686 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=4540, routed)        1.376     3.062    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_wr_ptr/c_clk_i
    SLICE_X74Y141        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[6]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X74Y141        FDCE (Prop_DFF_SLICEL_C_Q)
                                                      0.039     3.101 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[6]/Q
                         net (fo=2, routed)           0.087     3.187    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/wr_gptr[6]
    SLICE_X75Y141        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/wr_gptr_cdc_reg[6]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y100       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89456, routed)       1.818     2.266    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/t_clk_i
    SLICE_X75Y141        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/wr_gptr_cdc_reg[6]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[5].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[7]/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[5].trig_fifo_inst/wr_gptr_cdc_reg[7]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.100ns  (logic 0.039ns (39.124%)  route 0.061ns (60.876%))
  Logic Levels:           0  
  Clock Path Skew:        -0.857ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.232ns
    Source Clock Delay      (SCD):    3.089ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.403ns (routing 0.804ns, distribution 0.599ns)
  Clock Net Delay (Destination): 1.784ns (routing 0.877ns, distribution 0.907ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=48236, routed)       1.173     1.293    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.523 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.669    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y133        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.686 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=4540, routed)        1.403     3.089    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[5].trig_fifo_inst/gcc_wr_ptr/c_clk_i
    SLICE_X70Y195        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[5].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[7]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X70Y195        FDCE (Prop_DFF_SLICEM_C_Q)
                                                      0.039     3.128 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[5].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[7]/Q
                         net (fo=2, routed)           0.061     3.189    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[5].trig_fifo_inst/wr_gptr[7]
    SLICE_X71Y195        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[5].trig_fifo_inst/wr_gptr_cdc_reg[7]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y100       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89456, routed)       1.784     2.232    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[5].trig_fifo_inst/t_clk_i
    SLICE_X71Y195        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[5].trig_fifo_inst/wr_gptr_cdc_reg[7]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[7]/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/wr_gptr_cdc_reg[7]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.129ns  (logic 0.039ns (30.307%)  route 0.090ns (69.693%))
  Logic Levels:           0  
  Clock Path Skew:        -0.795ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.266ns
    Source Clock Delay      (SCD):    3.062ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.376ns (routing 0.804ns, distribution 0.572ns)
  Clock Net Delay (Destination): 1.818ns (routing 0.877ns, distribution 0.941ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=48236, routed)       1.173     1.293    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.523 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.669    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y133        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.686 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=4540, routed)        1.376     3.062    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_wr_ptr/c_clk_i
    SLICE_X74Y141        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[7]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X74Y141        FDCE (Prop_CFF_SLICEL_C_Q)
                                                      0.039     3.101 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[7]/Q
                         net (fo=2, routed)           0.090     3.190    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/wr_gptr[7]
    SLICE_X75Y141        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/wr_gptr_cdc_reg[7]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y100       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89456, routed)       1.818     2.266    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/t_clk_i
    SLICE_X75Y141        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/wr_gptr_cdc_reg[7]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[4].trig_fifo_inst/clr_fifo_req_reg/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[4].trig_fifo_inst/gcc_rd_ptr/clear_cdc_reg/D
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.123ns  (logic 0.039ns (31.789%)  route 0.084ns (68.211%))
  Logic Levels:           0  
  Clock Path Skew:        -0.806ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.263ns
    Source Clock Delay      (SCD):    3.069ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.383ns (routing 0.804ns, distribution 0.579ns)
  Clock Net Delay (Destination): 1.815ns (routing 0.877ns, distribution 0.938ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=48236, routed)       1.173     1.293    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.523 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.669    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y133        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.686 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=4540, routed)        1.383     3.069    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[4].trig_fifo_inst/c_clk_i
    SLICE_X74Y175        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[4].trig_fifo_inst/clr_fifo_req_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X74Y175        FDCE (Prop_HFF2_SLICEL_C_Q)
                                                      0.039     3.108 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[4].trig_fifo_inst/clr_fifo_req_reg/Q
                         net (fo=5, routed)           0.084     3.191    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[4].trig_fifo_inst/gcc_rd_ptr/clr_fifo_req
    SLICE_X74Y174        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[4].trig_fifo_inst/gcc_rd_ptr/clear_cdc_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y100       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89456, routed)       1.815     2.263    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[4].trig_fifo_inst/gcc_rd_ptr/t_clk_i
    SLICE_X74Y174        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[4].trig_fifo_inst/gcc_rd_ptr/clear_cdc_reg/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  clk_pl_0
  To Clock:  RFDAC0_CLK

Max Delay             2 Endpoints
Min Delay             2 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/dac1_done_i_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac1_done_i/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.295ns  (logic 0.078ns (6.023%)  route 1.217ns (93.977%))
  Logic Levels:           0  
  Clock Path Skew:        0.724ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.400ns
    Source Clock Delay      (SCD):    2.676ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.450ns (routing 0.662ns, distribution 1.788ns)
  Clock Net Delay (Destination): 2.879ns (routing 1.327ns, distribution 1.552ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       2.450     2.676    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/s_axi_aclk
    SLICE_X113Y130       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/dac1_done_i_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X113Y130       FDRE (Prop_DFF_SLICEM_C_Q)
                                                      0.078     2.754 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/dac1_done_i_reg/Q
                         net (fo=1, routed)           1.217     3.971    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac1_done_i/src_in
    SLICE_X117Y238       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac1_done_i/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y100       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89456, routed)       2.879     3.400    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac1_done_i/dest_clk
    SLICE_X117Y238       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac1_done_i/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/dac0_done_i_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac0_done_i/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.353ns  (logic 0.079ns (5.839%)  route 1.274ns (94.161%))
  Logic Levels:           0  
  Clock Path Skew:        0.799ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.394ns
    Source Clock Delay      (SCD):    2.594ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.368ns (routing 0.662ns, distribution 1.706ns)
  Clock Net Delay (Destination): 2.873ns (routing 1.327ns, distribution 1.546ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       2.368     2.594    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/s_axi_aclk
    SLICE_X105Y142       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/dac0_done_i_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X105Y142       FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     2.673 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/dac0_done_i_reg/Q
                         net (fo=1, routed)           1.274     3.947    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac0_done_i/src_in
    SLICE_X117Y223       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac0_done_i/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y100       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89456, routed)       2.873     3.394    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac0_done_i/dest_clk
    SLICE_X117Y223       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac0_done_i/syncstages_ff_reg[0]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/dac1_done_i_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac1_done_i/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.638ns  (logic 0.039ns (6.113%)  route 0.599ns (93.887%))
  Logic Levels:           0  
  Clock Path Skew:        0.945ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.402ns
    Source Clock Delay      (SCD):    1.458ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.338ns (routing 0.359ns, distribution 0.979ns)
  Clock Net Delay (Destination): 1.954ns (routing 0.877ns, distribution 1.077ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.338     1.458    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/s_axi_aclk
    SLICE_X113Y130       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/dac1_done_i_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X113Y130       FDRE (Prop_DFF_SLICEM_C_Q)
                                                      0.039     1.497 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/dac1_done_i_reg/Q
                         net (fo=1, routed)           0.599     2.096    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac1_done_i/src_in
    SLICE_X117Y238       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac1_done_i/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y100       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89456, routed)       1.954     2.402    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac1_done_i/dest_clk
    SLICE_X117Y238       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac1_done_i/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/dac0_done_i_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac0_done_i/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.679ns  (logic 0.039ns (5.744%)  route 0.640ns (94.256%))
  Logic Levels:           0  
  Clock Path Skew:        0.978ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.398ns
    Source Clock Delay      (SCD):    1.421ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.301ns (routing 0.359ns, distribution 0.942ns)
  Clock Net Delay (Destination): 1.950ns (routing 0.877ns, distribution 1.073ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.301     1.421    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/s_axi_aclk
    SLICE_X105Y142       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/dac0_done_i_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X105Y142       FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.039     1.460 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/dac0_done_i_reg/Q
                         net (fo=1, routed)           0.640     2.100    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac0_done_i/src_in
    SLICE_X117Y223       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac0_done_i/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y100       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89456, routed)       1.950     2.398    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac0_done_i/dest_clk
    SLICE_X117Y223       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac0_done_i/syncstages_ff_reg[0]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  
  To Clock:  clk_out1_d_1_clk_adc0_x2_0

Max Delay             1 Endpoint
Min Delay             1 Endpoint
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/EMIOGPIOO[95]
                            (internal pin)
  Destination:            d_1_i/rst_adc0_x2/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.399ns  (logic 0.089ns (2.618%)  route 3.310ns (97.382%))
  Logic Levels:           1  (LUT1=1)
  Clock Uncertainty:      0.122ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.073ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Destination): 2.833ns (routing 1.400ns, distribution 1.433ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    PS8_X0Y0             PS8                          0.000     0.000 f  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/EMIOGPIOO[95]
                         net (fo=5, routed)           2.997     2.997    d_1_i/rst_adc0_x2/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/ext_reset_in
    SLICE_X101Y66        LUT1 (Prop_D6LUT_SLICEL_I0_O)
                                                      0.089     3.086 r  d_1_i/rst_adc0_x2/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1/O
                         net (fo=1, routed)           0.313     3.399    d_1_i/rst_adc0_x2/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/exr_d1
    SLICE_X104Y66        FDRE                                         r  d_1_i/rst_adc0_x2/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.389     2.775    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     3.405 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.216     3.621    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.645 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86296, routed)       2.833     6.478    d_1_i/rst_adc0_x2/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/slowest_sync_clk
    SLICE_X104Y66        FDRE                                         r  d_1_i/rst_adc0_x2/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/EMIOGPIOO[95]
                            (internal pin)
  Destination:            d_1_i/rst_adc0_x2/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.628ns  (logic 0.035ns (2.149%)  route 1.593ns (97.851%))
  Logic Levels:           1  (LUT1=1)
  Clock Uncertainty:      0.122ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.073ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Destination): 1.959ns (routing 0.950ns, distribution 1.009ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    PS8_X0Y0             PS8                          0.000     0.000 f  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/EMIOGPIOO[95]
                         net (fo=5, routed)           1.481     1.481    d_1_i/rst_adc0_x2/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/ext_reset_in
    SLICE_X101Y66        LUT1 (Prop_D6LUT_SLICEL_I0_O)
                                                      0.035     1.516 r  d_1_i/rst_adc0_x2/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1/O
                         net (fo=1, routed)           0.112     1.628    d_1_i/rst_adc0_x2/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/exr_d1
    SLICE_X104Y66        FDRE                                         r  d_1_i/rst_adc0_x2/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.624     1.976    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.681 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.847    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.866 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86296, routed)       1.959     3.825    d_1_i/rst_adc0_x2/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/slowest_sync_clk
    SLICE_X104Y66        FDRE                                         r  d_1_i/rst_adc0_x2/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  RFDAC0_CLK
  To Clock:  clk_out1_d_1_clk_adc0_x2_0

Max Delay           349 Endpoints
Min Delay           349 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[8]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/trigger_resync_i/data_int_reg_reg[0]/D
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.994ns  (logic 0.079ns (7.945%)  route 0.915ns (92.055%))
  Logic Levels:           0  
  Clock Path Skew:        2.755ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    6.239ns
    Source Clock Delay      (SCD):    3.484ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.128ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.073ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      2.811ns (routing 1.460ns, distribution 1.351ns)
  Clock Net Delay (Destination): 2.594ns (routing 1.400ns, distribution 1.194ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y100       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89456, routed)       2.811     3.484    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
    SLICE_X52Y199        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[8]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X52Y199        FDCE (Prop_DFF_SLICEL_C_Q)
                                                      0.079     3.563 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[8]/Q
                         net (fo=2, routed)           0.915     4.478    d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/trigger_resync_i/trigger
    SLICE_X70Y148        FDCE                                         r  d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/trigger_resync_i/data_int_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.389     2.775    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     3.405 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.216     3.621    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.645 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86296, routed)       2.594     6.239    d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/trigger_resync_i/s00_axis_aclk
    SLICE_X70Y148        FDCE                                         r  d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/trigger_resync_i/data_int_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[11]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/trigger_resync_i/data_int_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.744ns  (logic 0.079ns (10.614%)  route 0.665ns (89.386%))
  Logic Levels:           0  
  Clock Path Skew:        2.702ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    6.250ns
    Source Clock Delay      (SCD):    3.548ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.128ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.073ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      2.875ns (routing 1.460ns, distribution 1.415ns)
  Clock Net Delay (Destination): 2.605ns (routing 1.400ns, distribution 1.205ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y100       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89456, routed)       2.875     3.548    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
    SLICE_X64Y217        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[11]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X64Y217        FDCE (Prop_CFF_SLICEL_C_Q)
                                                      0.079     3.627 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[11]/Q
                         net (fo=2, routed)           0.665     4.292    d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/trigger_resync_i/trigger
    SLICE_X74Y190        FDRE                                         r  d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/trigger_resync_i/data_int_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.389     2.775    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     3.405 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.216     3.621    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.645 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86296, routed)       2.605     6.250    d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/trigger_resync_i/s_axis_aclk
    SLICE_X74Y190        FDRE                                         r  d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/trigger_resync_i/data_int_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[10]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/trigger_resync_i/data_int_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.730ns  (logic 0.079ns (10.821%)  route 0.651ns (89.179%))
  Logic Levels:           0  
  Clock Path Skew:        2.814ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    6.337ns
    Source Clock Delay      (SCD):    3.523ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.128ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.073ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      2.850ns (routing 1.460ns, distribution 1.390ns)
  Clock Net Delay (Destination): 2.692ns (routing 1.400ns, distribution 1.292ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y100       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89456, routed)       2.850     3.523    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
    SLICE_X52Y168        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[10]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X52Y168        FDCE (Prop_HFF_SLICEL_C_Q)
                                                      0.079     3.602 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[10]/Q
                         net (fo=2, routed)           0.651     4.253    d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/trigger_resync_i/trigger
    SLICE_X54Y129        FDRE                                         r  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/trigger_resync_i/data_int_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.389     2.775    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     3.405 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.216     3.621    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.645 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86296, routed)       2.692     6.337    d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/trigger_resync_i/s_axis_aclk
    SLICE_X54Y129        FDRE                                         r  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/trigger_resync_i/data_int_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[13]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/axis_avg_buffer_3/inst/avg_buffer_i/trigger_resync_i/data_int_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.594ns  (logic 0.079ns (13.293%)  route 0.515ns (86.707%))
  Logic Levels:           0  
  Clock Path Skew:        2.656ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    6.258ns
    Source Clock Delay      (SCD):    3.602ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.128ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.073ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      2.929ns (routing 1.460ns, distribution 1.469ns)
  Clock Net Delay (Destination): 2.613ns (routing 1.400ns, distribution 1.213ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y100       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89456, routed)       2.929     3.602    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
    SLICE_X65Y183        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[13]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X65Y183        FDCE (Prop_DFF_SLICEL_C_Q)
                                                      0.079     3.681 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[13]/Q
                         net (fo=2, routed)           0.515     4.196    d_1_i/axis_avg_buffer_3/inst/avg_buffer_i/trigger_resync_i/trigger
    SLICE_X70Y176        FDRE                                         r  d_1_i/axis_avg_buffer_3/inst/avg_buffer_i/trigger_resync_i/data_int_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.389     2.775    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     3.405 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.216     3.621    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.645 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86296, routed)       2.613     6.258    d_1_i/axis_avg_buffer_3/inst/avg_buffer_i/trigger_resync_i/s_axis_aclk
    SLICE_X70Y176        FDRE                                         r  d_1_i/axis_avg_buffer_3/inst/avg_buffer_i/trigger_resync_i/data_int_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[12]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/trigger_resync_i/data_int_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.594ns  (logic 0.079ns (13.299%)  route 0.515ns (86.701%))
  Logic Levels:           0  
  Clock Path Skew:        2.821ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    6.333ns
    Source Clock Delay      (SCD):    3.512ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.128ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.073ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      2.839ns (routing 1.460ns, distribution 1.379ns)
  Clock Net Delay (Destination): 2.688ns (routing 1.400ns, distribution 1.288ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y100       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89456, routed)       2.839     3.512    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
    SLICE_X55Y164        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[12]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X55Y164        FDCE (Prop_HFF_SLICEL_C_Q)
                                                      0.079     3.591 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[12]/Q
                         net (fo=2, routed)           0.515     4.106    d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/trigger_resync_i/trigger
    SLICE_X55Y129        FDRE                                         r  d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/trigger_resync_i/data_int_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.389     2.775    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     3.405 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.216     3.621    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.645 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86296, routed)       2.688     6.333    d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/trigger_resync_i/s_axis_aclk
    SLICE_X55Y129        FDRE                                         r  d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/trigger_resync_i/data_int_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/wptr_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/wptr_g_i/data_int_reg_reg[0][2]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.698ns  (logic 0.180ns (10.600%)  route 1.518ns (89.400%))
  Logic Levels:           1  (LUT2=1)
  Clock Path Skew:        2.640ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    6.411ns
    Source Clock Delay      (SCD):    3.771ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.128ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.073ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      3.098ns (routing 1.460ns, distribution 1.638ns)
  Clock Net Delay (Destination): 2.766ns (routing 1.400ns, distribution 1.366ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y100       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89456, routed)       3.098     3.771    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/s_axis_aclk
    SLICE_X91Y99         FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/wptr_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X91Y99         FDRE (Prop_GFF2_SLICEL_C_Q)
                                                      0.081     3.852 r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/wptr_reg[3]/Q
                         net (fo=556, routed)         1.467     5.319    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/wptr_g_i/data_int_reg_reg[0][3]_0[3]
    SLICE_X92Y114        LUT2 (Prop_H6LUT_SLICEL_I1_O)
                                                      0.099     5.418 r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/wptr_g_i/data_int_reg[0][2]_i_1/O
                         net (fo=1, routed)           0.051     5.469    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/wptr_g_i/wptr_g[2]
    SLICE_X92Y114        FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/wptr_g_i/data_int_reg_reg[0][2]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.389     2.775    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     3.405 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.216     3.621    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.645 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86296, routed)       2.766     6.411    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/wptr_g_i/m_axis_aclk
    SLICE_X92Y114        FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/wptr_g_i/data_int_reg_reg[0][2]/C

Slack:                    inf
  Source:                 d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/wptr_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/wptr_g_i/data_int_reg_reg[0][3]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.675ns  (logic 0.081ns (4.835%)  route 1.594ns (95.165%))
  Logic Levels:           0  
  Clock Path Skew:        2.640ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    6.411ns
    Source Clock Delay      (SCD):    3.771ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.128ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.073ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      3.098ns (routing 1.460ns, distribution 1.638ns)
  Clock Net Delay (Destination): 2.766ns (routing 1.400ns, distribution 1.366ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y100       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89456, routed)       3.098     3.771    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/s_axis_aclk
    SLICE_X91Y99         FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/wptr_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X91Y99         FDRE (Prop_GFF2_SLICEL_C_Q)
                                                      0.081     3.852 r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/wptr_reg[3]/Q
                         net (fo=556, routed)         1.594     5.446    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/wptr_g_i/data_int_reg_reg[0][3]_0[3]
    SLICE_X92Y114        FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/wptr_g_i/data_int_reg_reg[0][3]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.389     2.775    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     3.405 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.216     3.621    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.645 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86296, routed)       2.766     6.411    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/wptr_g_i/m_axis_aclk
    SLICE_X92Y114        FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/wptr_g_i/data_int_reg_reg[0][3]/C

Slack:                    inf
  Source:                 d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/wptr_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/wptr_g_i/data_int_reg_reg[0][0]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.659ns  (logic 0.241ns (14.529%)  route 1.418ns (85.471%))
  Logic Levels:           1  (LUT2=1)
  Clock Path Skew:        2.634ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    6.403ns
    Source Clock Delay      (SCD):    3.769ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.128ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.073ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      3.096ns (routing 1.460ns, distribution 1.636ns)
  Clock Net Delay (Destination): 2.758ns (routing 1.400ns, distribution 1.358ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y100       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89456, routed)       3.096     3.769    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/s_axis_aclk
    SLICE_X95Y98         FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/wptr_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X95Y98         FDRE (Prop_BFF2_SLICEL_C_Q)
                                                      0.080     3.849 r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/wptr_reg[0]/Q
                         net (fo=557, routed)         1.141     4.990    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/wptr_g_i/data_int_reg_reg[0][3]_0[0]
    SLICE_X89Y106        LUT2 (Prop_H5LUT_SLICEM_I0_O)
                                                      0.161     5.151 r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/wptr_g_i/data_int_reg[0][0]_i_1/O
                         net (fo=2, routed)           0.277     5.428    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/wptr_g_i/wptr_reg[0][0]
    SLICE_X89Y106        FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/wptr_g_i/data_int_reg_reg[0][0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.389     2.775    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     3.405 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.216     3.621    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.645 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86296, routed)       2.758     6.403    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/wptr_g_i/m_axis_aclk
    SLICE_X89Y106        FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/wptr_g_i/data_int_reg_reg[0][0]/C

Slack:                    inf
  Source:                 d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/wptr_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/wptr_g_i/data_int_reg_reg[0][1]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.171ns  (logic 0.204ns (17.426%)  route 0.967ns (82.574%))
  Logic Levels:           1  (LUT2=1)
  Clock Path Skew:        2.626ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    6.403ns
    Source Clock Delay      (SCD):    3.777ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.128ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.073ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      3.104ns (routing 1.460ns, distribution 1.644ns)
  Clock Net Delay (Destination): 2.758ns (routing 1.400ns, distribution 1.358ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y100       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89456, routed)       3.104     3.777    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/s_axis_aclk
    SLICE_X95Y100        FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/wptr_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X95Y100        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     3.856 r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/wptr_reg[1]/Q
                         net (fo=557, routed)         0.911     4.767    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/wptr_g_i/data_int_reg_reg[0][3]_0[1]
    SLICE_X89Y106        LUT2 (Prop_H6LUT_SLICEM_I0_O)
                                                      0.125     4.892 r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/wptr_g_i/data_int_reg[0][1]_i_1/O
                         net (fo=1, routed)           0.056     4.948    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/wptr_g_i/wptr_g[1]
    SLICE_X89Y106        FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/wptr_g_i/data_int_reg_reg[0][1]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.389     2.775    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     3.405 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.216     3.621    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.645 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86296, routed)       2.758     6.403    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/wptr_g_i/m_axis_aclk
    SLICE_X89Y106        FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/wptr_g_i/data_int_reg_reg[0][1]/C

Slack:                    inf
  Source:                 d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/RAM_reg_0_15_336_349/RAMA_D1/CLK
                            (rising edge-triggered cell RAMD32 clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/dob_reg[337]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.914ns  (logic 0.305ns (33.370%)  route 0.609ns (66.630%))
  Logic Levels:           0  
  Clock Path Skew:        2.598ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    6.407ns
    Source Clock Delay      (SCD):    3.808ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.128ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.073ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      3.135ns (routing 1.460ns, distribution 1.675ns)
  Clock Net Delay (Destination): 2.762ns (routing 1.400ns, distribution 1.362ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y100       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89456, routed)       3.135     3.808    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/RAM_reg_0_15_336_349/WCLK
    SLICE_X90Y134        RAMD32                                       r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/RAM_reg_0_15_336_349/RAMA_D1/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X90Y134        RAMD32 (Prop_A6LUT_SLICEM_CLK_O)
                                                      0.305     4.113 r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/RAM_reg_0_15_336_349/RAMA_D1/O
                         net (fo=1, routed)           0.609     4.722    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/dob0[337]
    SLICE_X95Y107        FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/dob_reg[337]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.389     2.775    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     3.405 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.216     3.621    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.645 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86296, routed)       2.762     6.407    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/m_axis_aclk
    SLICE_X95Y107        FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/dob_reg[337]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[12]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/trigger_resync_i/data_int_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.296ns  (logic 0.039ns (13.190%)  route 0.257ns (86.810%))
  Logic Levels:           0  
  Clock Path Skew:        1.824ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.723ns
    Source Clock Delay      (SCD):    1.899ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.128ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.073ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      1.550ns (routing 0.786ns, distribution 0.764ns)
  Clock Net Delay (Destination): 1.857ns (routing 0.950ns, distribution 0.907ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y100       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89456, routed)       1.550     1.899    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
    SLICE_X55Y164        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[12]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X55Y164        FDCE (Prop_HFF_SLICEL_C_Q)
                                                      0.039     1.938 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[12]/Q
                         net (fo=2, routed)           0.257     2.195    d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/trigger_resync_i/trigger
    SLICE_X55Y129        FDRE                                         r  d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/trigger_resync_i/data_int_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.624     1.976    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.681 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.847    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.866 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86296, routed)       1.857     3.723    d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/trigger_resync_i/s_axis_aclk
    SLICE_X55Y129        FDRE                                         r  d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/trigger_resync_i/data_int_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[13]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/axis_avg_buffer_3/inst/avg_buffer_i/trigger_resync_i/data_int_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.282ns  (logic 0.039ns (13.825%)  route 0.243ns (86.175%))
  Logic Levels:           0  
  Clock Path Skew:        1.730ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.671ns
    Source Clock Delay      (SCD):    1.941ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.128ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.073ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      1.592ns (routing 0.786ns, distribution 0.806ns)
  Clock Net Delay (Destination): 1.805ns (routing 0.950ns, distribution 0.855ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y100       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89456, routed)       1.592     1.941    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
    SLICE_X65Y183        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[13]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X65Y183        FDCE (Prop_DFF_SLICEL_C_Q)
                                                      0.039     1.980 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[13]/Q
                         net (fo=2, routed)           0.243     2.223    d_1_i/axis_avg_buffer_3/inst/avg_buffer_i/trigger_resync_i/trigger
    SLICE_X70Y176        FDRE                                         r  d_1_i/axis_avg_buffer_3/inst/avg_buffer_i/trigger_resync_i/data_int_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.624     1.976    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.681 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.847    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.866 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86296, routed)       1.805     3.671    d_1_i/axis_avg_buffer_3/inst/avg_buffer_i/trigger_resync_i/s_axis_aclk
    SLICE_X70Y176        FDRE                                         r  d_1_i/axis_avg_buffer_3/inst/avg_buffer_i/trigger_resync_i/data_int_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[10]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/trigger_resync_i/data_int_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.343ns  (logic 0.039ns (11.381%)  route 0.304ns (88.619%))
  Logic Levels:           0  
  Clock Path Skew:        1.824ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.726ns
    Source Clock Delay      (SCD):    1.903ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.128ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.073ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      1.554ns (routing 0.786ns, distribution 0.768ns)
  Clock Net Delay (Destination): 1.860ns (routing 0.950ns, distribution 0.910ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y100       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89456, routed)       1.554     1.903    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
    SLICE_X52Y168        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[10]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X52Y168        FDCE (Prop_HFF_SLICEL_C_Q)
                                                      0.039     1.942 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[10]/Q
                         net (fo=2, routed)           0.304     2.245    d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/trigger_resync_i/trigger
    SLICE_X54Y129        FDRE                                         r  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/trigger_resync_i/data_int_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.624     1.976    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.681 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.847    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.866 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86296, routed)       1.860     3.726    d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/trigger_resync_i/s_axis_aclk
    SLICE_X54Y129        FDRE                                         r  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/trigger_resync_i/data_int_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[11]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/trigger_resync_i/data_int_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.366ns  (logic 0.039ns (10.653%)  route 0.327ns (89.347%))
  Logic Levels:           0  
  Clock Path Skew:        1.739ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.656ns
    Source Clock Delay      (SCD):    1.917ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.128ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.073ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      1.568ns (routing 0.786ns, distribution 0.782ns)
  Clock Net Delay (Destination): 1.790ns (routing 0.950ns, distribution 0.840ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y100       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89456, routed)       1.568     1.917    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
    SLICE_X64Y217        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[11]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X64Y217        FDCE (Prop_CFF_SLICEL_C_Q)
                                                      0.039     1.956 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[11]/Q
                         net (fo=2, routed)           0.327     2.283    d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/trigger_resync_i/trigger
    SLICE_X74Y190        FDRE                                         r  d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/trigger_resync_i/data_int_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.624     1.976    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.681 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.847    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.866 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86296, routed)       1.790     3.656    d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/trigger_resync_i/s_axis_aclk
    SLICE_X74Y190        FDRE                                         r  d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/trigger_resync_i/data_int_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[8]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/trigger_resync_i/data_int_reg_reg[0]/D
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.490ns  (logic 0.039ns (7.958%)  route 0.451ns (92.042%))
  Logic Levels:           0  
  Clock Path Skew:        1.779ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.660ns
    Source Clock Delay      (SCD):    1.881ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.128ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.073ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      1.532ns (routing 0.786ns, distribution 0.746ns)
  Clock Net Delay (Destination): 1.794ns (routing 0.950ns, distribution 0.844ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y100       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89456, routed)       1.532     1.881    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
    SLICE_X52Y199        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[8]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X52Y199        FDCE (Prop_DFF_SLICEL_C_Q)
                                                      0.039     1.920 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[8]/Q
                         net (fo=2, routed)           0.451     2.371    d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/trigger_resync_i/trigger
    SLICE_X70Y148        FDCE                                         r  d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/trigger_resync_i/data_int_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.624     1.976    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.681 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.847    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.866 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86296, routed)       1.794     3.660    d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/trigger_resync_i/s00_axis_aclk
    SLICE_X70Y148        FDCE                                         r  d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/trigger_resync_i/data_int_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/RAM_reg_0_15_518_531/RAMC_D1/CLK
                            (rising edge-triggered cell RAMD32 clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/dob_reg[523]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.148ns  (logic 0.110ns (74.324%)  route 0.038ns (25.676%))
  Logic Levels:           0  
  Clock Path Skew:        1.705ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.762ns
    Source Clock Delay      (SCD):    2.058ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.128ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.073ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      1.709ns (routing 0.786ns, distribution 0.923ns)
  Clock Net Delay (Destination): 1.896ns (routing 0.950ns, distribution 0.946ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y100       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89456, routed)       1.709     2.058    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/RAM_reg_0_15_518_531/WCLK
    SLICE_X87Y134        RAMD32                                       r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/RAM_reg_0_15_518_531/RAMC_D1/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X87Y134        RAMD32 (Prop_C6LUT_SLICEM_CLK_O)
                                                      0.110     2.168 r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/RAM_reg_0_15_518_531/RAMC_D1/O
                         net (fo=1, routed)           0.038     2.206    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/dob0[523]
    SLICE_X87Y133        FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/dob_reg[523]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.624     1.976    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.681 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.847    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.866 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86296, routed)       1.896     3.762    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/m_axis_aclk
    SLICE_X87Y133        FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/dob_reg[523]/C

Slack:                    inf
  Source:                 d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/RAM_reg_0_15_546_559/RAMC_D1/CLK
                            (rising edge-triggered cell RAMD32 clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/dob_reg[551]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.163ns  (logic 0.110ns (67.485%)  route 0.053ns (32.515%))
  Logic Levels:           0  
  Clock Path Skew:        1.702ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.756ns
    Source Clock Delay      (SCD):    2.054ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.128ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.073ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      1.705ns (routing 0.786ns, distribution 0.919ns)
  Clock Net Delay (Destination): 1.890ns (routing 0.950ns, distribution 0.940ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y100       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89456, routed)       1.705     2.054    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/RAM_reg_0_15_546_559/WCLK
    SLICE_X90Y137        RAMD32                                       r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/RAM_reg_0_15_546_559/RAMC_D1/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X90Y137        RAMD32 (Prop_C6LUT_SLICEM_CLK_O)
                                                      0.110     2.164 r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/RAM_reg_0_15_546_559/RAMC_D1/O
                         net (fo=1, routed)           0.053     2.217    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/dob0[551]
    SLICE_X91Y137        FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/dob_reg[551]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.624     1.976    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.681 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.847    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.866 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86296, routed)       1.890     3.756    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/m_axis_aclk
    SLICE_X91Y137        FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/dob_reg[551]/C

Slack:                    inf
  Source:                 d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/RAM_reg_0_15_546_559/RAME_D1/CLK
                            (rising edge-triggered cell RAMD32 clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/dob_reg[555]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.164ns  (logic 0.108ns (65.854%)  route 0.056ns (34.146%))
  Logic Levels:           0  
  Clock Path Skew:        1.702ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.756ns
    Source Clock Delay      (SCD):    2.054ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.128ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.073ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      1.705ns (routing 0.786ns, distribution 0.919ns)
  Clock Net Delay (Destination): 1.890ns (routing 0.950ns, distribution 0.940ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y100       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89456, routed)       1.705     2.054    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/RAM_reg_0_15_546_559/WCLK
    SLICE_X90Y137        RAMD32                                       r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/RAM_reg_0_15_546_559/RAME_D1/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X90Y137        RAMD32 (Prop_E6LUT_SLICEM_CLK_O)
                                                      0.108     2.162 r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/RAM_reg_0_15_546_559/RAME_D1/O
                         net (fo=1, routed)           0.056     2.218    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/dob0[555]
    SLICE_X91Y137        FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/dob_reg[555]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.624     1.976    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.681 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.847    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.866 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86296, routed)       1.890     3.756    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/m_axis_aclk
    SLICE_X91Y137        FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/dob_reg[555]/C

Slack:                    inf
  Source:                 d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/RAM_reg_0_15_504_517/RAMF_D1/CLK
                            (rising edge-triggered cell RAMD32 clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/dob_reg[515]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.172ns  (logic 0.111ns (64.535%)  route 0.061ns (35.465%))
  Logic Levels:           0  
  Clock Path Skew:        1.705ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.761ns
    Source Clock Delay      (SCD):    2.056ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.128ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.073ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      1.707ns (routing 0.786ns, distribution 0.921ns)
  Clock Net Delay (Destination): 1.895ns (routing 0.950ns, distribution 0.945ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y100       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89456, routed)       1.707     2.056    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/RAM_reg_0_15_504_517/WCLK
    SLICE_X90Y133        RAMD32                                       r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/RAM_reg_0_15_504_517/RAMF_D1/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X90Y133        RAMD32 (Prop_F6LUT_SLICEM_CLK_O)
                                                      0.111     2.167 r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/RAM_reg_0_15_504_517/RAMF_D1/O
                         net (fo=1, routed)           0.061     2.228    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/dob0[515]
    SLICE_X91Y133        FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/dob_reg[515]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.624     1.976    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.681 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.847    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.866 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86296, routed)       1.895     3.761    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/m_axis_aclk
    SLICE_X91Y133        FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/dob_reg[515]/C

Slack:                    inf
  Source:                 d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/RAM_reg_0_15_546_559/RAMF_D1/CLK
                            (rising edge-triggered cell RAMD32 clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/dob_reg[557]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.184ns  (logic 0.111ns (60.326%)  route 0.073ns (39.674%))
  Logic Levels:           0  
  Clock Path Skew:        1.702ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.756ns
    Source Clock Delay      (SCD):    2.054ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.128ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.073ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      1.705ns (routing 0.786ns, distribution 0.919ns)
  Clock Net Delay (Destination): 1.890ns (routing 0.950ns, distribution 0.940ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y100       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89456, routed)       1.705     2.054    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/RAM_reg_0_15_546_559/WCLK
    SLICE_X90Y137        RAMD32                                       r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/RAM_reg_0_15_546_559/RAMF_D1/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X90Y137        RAMD32 (Prop_F6LUT_SLICEM_CLK_O)
                                                      0.111     2.165 r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/RAM_reg_0_15_546_559/RAMF_D1/O
                         net (fo=1, routed)           0.073     2.238    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/dob0[557]
    SLICE_X91Y137        FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/dob_reg[557]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.624     1.976    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.681 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.847    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.866 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86296, routed)       1.890     3.756    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/m_axis_aclk
    SLICE_X91Y137        FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/dob_reg[557]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  clk_pl_0
  To Clock:  clk_out1_d_1_clk_adc0_x2_0

Max Delay           810 Endpoints
Min Delay           810 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/adc0_done_i_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_adc0_done_i/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.661ns  (logic 0.079ns (11.952%)  route 0.582ns (88.048%))
  Logic Levels:           0  
  Clock Path Skew:        3.865ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    6.515ns
    Source Clock Delay      (SCD):    2.650ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.243ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.323ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      2.424ns (routing 0.662ns, distribution 1.762ns)
  Clock Net Delay (Destination): 2.870ns (routing 1.400ns, distribution 1.470ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       2.424     2.650    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/s_axi_aclk
    SLICE_X108Y99        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/adc0_done_i_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X108Y99        FDRE (Prop_HFF_SLICEL_C_Q)
                                                      0.079     2.729 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/adc0_done_i_reg/Q
                         net (fo=1, routed)           0.582     3.311    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_adc0_done_i/src_in
    SLICE_X108Y62        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_adc0_done_i/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.389     2.775    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     3.405 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.216     3.621    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.645 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86296, routed)       2.870     6.515    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_adc0_done_i/dest_clk
    SLICE_X108Y62        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_adc0_done_i/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/adc2_done_i_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_adc2_done_i/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.645ns  (logic 0.079ns (12.248%)  route 0.566ns (87.752%))
  Logic Levels:           0  
  Clock Path Skew:        3.882ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    6.509ns
    Source Clock Delay      (SCD):    2.627ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.243ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.323ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      2.401ns (routing 0.662ns, distribution 1.739ns)
  Clock Net Delay (Destination): 2.864ns (routing 1.400ns, distribution 1.464ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       2.401     2.627    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/s_axi_aclk
    SLICE_X108Y124       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/adc2_done_i_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X108Y124       FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.079     2.706 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/adc2_done_i_reg/Q
                         net (fo=1, routed)           0.566     3.272    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_adc2_done_i/src_in
    SLICE_X117Y139       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_adc2_done_i/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.389     2.775    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     3.405 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.216     3.621    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.645 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86296, routed)       2.864     6.509    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_adc2_done_i/dest_clk
    SLICE_X117Y139       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_adc2_done_i/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_sendd_ff_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.521ns  (logic 0.080ns (15.354%)  route 0.441ns (84.646%))
  Logic Levels:           0  
  Clock Path Skew:        3.875ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    6.417ns
    Source Clock Delay      (SCD):    2.542ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.243ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.323ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      2.316ns (routing 0.662ns, distribution 1.654ns)
  Clock Net Delay (Destination): 2.772ns (routing 1.400ns, distribution 1.372ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       2.316     2.542    d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_clk
    SLICE_X85Y71         FDRE                                         r  d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_sendd_ff_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X85Y71         FDRE (Prop_HFF2_SLICEL_C_Q)
                                                      0.080     2.622 r  d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_sendd_ff_reg/Q
                         net (fo=2, routed)           0.441     3.063    d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/src_in
    SLICE_X87Y69         FDRE                                         r  d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.389     2.775    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     3.405 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.216     3.621    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.645 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86296, routed)       2.772     6.417    d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/dest_clk
    SLICE_X87Y69         FDRE                                         r  d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_sendd_ff_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.576ns  (logic 0.079ns (13.706%)  route 0.497ns (86.294%))
  Logic Levels:           0  
  Clock Path Skew:        4.035ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    6.296ns
    Source Clock Delay      (SCD):    2.261ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.243ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.323ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      2.035ns (routing 0.662ns, distribution 1.373ns)
  Clock Net Delay (Destination): 2.651ns (routing 1.400ns, distribution 1.251ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       2.035     2.261    d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_clk
    SLICE_X57Y182        FDRE                                         r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_sendd_ff_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X57Y182        FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.079     2.340 r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_sendd_ff_reg/Q
                         net (fo=2, routed)           0.497     2.837    d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/src_in
    SLICE_X55Y206        FDRE                                         r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.389     2.775    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     3.405 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.216     3.621    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.645 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86296, routed)       2.651     6.296    d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/dest_clk
    SLICE_X55Y206        FDRE                                         r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axis_avg_buffer_2/inst/axi_slv_i/slv_reg1_reg[10]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/avg_top_i/avg_i/addr_r_reg[10]_replica/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.648ns  (logic 0.215ns (8.119%)  route 2.433ns (91.881%))
  Logic Levels:           1  (LUT4=1)
  Clock Path Skew:        3.979ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    6.410ns
    Source Clock Delay      (SCD):    2.431ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.243ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.323ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      2.205ns (routing 0.662ns, distribution 1.543ns)
  Clock Net Delay (Destination): 2.765ns (routing 1.400ns, distribution 1.365ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       2.205     2.431    d_1_i/axis_avg_buffer_2/inst/axi_slv_i/s_axi_aclk
    SLICE_X80Y101        FDRE                                         r  d_1_i/axis_avg_buffer_2/inst/axi_slv_i/slv_reg1_reg[10]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X80Y101        FDRE (Prop_HFF2_SLICEL_C_Q)
                                                      0.080     2.511 r  d_1_i/axis_avg_buffer_2/inst/axi_slv_i/slv_reg1_reg[10]/Q
                         net (fo=2, routed)           1.647     4.158    d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/avg_top_i/avg_i/addr_r_reg[13]_15[10]
    SLICE_X79Y67         LUT4 (Prop_H5LUT_SLICEM_I0_O)
                                                      0.135     4.293 r  d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/avg_top_i/avg_i/addr_r[10]_i_1/O
                         net (fo=7, routed)           0.786     5.079    d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/avg_top_i/avg_i/p_0_in[10]
    SLICE_X83Y54         FDRE                                         r  d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/avg_top_i/avg_i/addr_r_reg[10]_replica/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.389     2.775    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     3.405 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.216     3.621    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.645 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86296, routed)       2.765     6.410    d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/avg_top_i/avg_i/s_axis_aclk
    SLICE_X83Y54         FDRE                                         r  d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/avg_top_i/avg_i/addr_r_reg[10]_replica/C

Slack:                    inf
  Source:                 d_1_i/axis_avg_buffer_1/inst/axi_slv_i/slv_reg7_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/buffer_top_i/buffer_i/addr_r_reg[1]_replica/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.682ns  (logic 0.240ns (8.949%)  route 2.442ns (91.051%))
  Logic Levels:           1  (LUT4=1)
  Clock Path Skew:        3.859ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    6.244ns
    Source Clock Delay      (SCD):    2.385ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.243ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.323ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      2.159ns (routing 0.662ns, distribution 1.497ns)
  Clock Net Delay (Destination): 2.599ns (routing 1.400ns, distribution 1.199ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       2.159     2.385    d_1_i/axis_avg_buffer_1/inst/axi_slv_i/s_axi_aclk
    SLICE_X80Y151        FDRE                                         r  d_1_i/axis_avg_buffer_1/inst/axi_slv_i/slv_reg7_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X80Y151        FDRE (Prop_EFF2_SLICEL_C_Q)
                                                      0.081     2.466 r  d_1_i/axis_avg_buffer_1/inst/axi_slv_i/slv_reg7_reg[1]/Q
                         net (fo=2, routed)           1.561     4.027    d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/buffer_top_i/buffer_i/addr_r_reg[11]_1[1]
    SLICE_X82Y191        LUT4 (Prop_C5LUT_SLICEM_I0_O)
                                                      0.159     4.186 r  d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/buffer_top_i/buffer_i/addr_r[1]_i_1__0/O
                         net (fo=3, routed)           0.881     5.067    d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/buffer_top_i/buffer_i/p_0_in__2[1]
    SLICE_X80Y214        FDRE                                         r  d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/buffer_top_i/buffer_i/addr_r_reg[1]_replica/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.389     2.775    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     3.405 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.216     3.621    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.645 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86296, routed)       2.599     6.244    d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/buffer_top_i/buffer_i/s_axis_aclk
    SLICE_X80Y214        FDRE                                         r  d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/buffer_top_i/buffer_i/addr_r_reg[1]_replica/C

Slack:                    inf
  Source:                 d_1_i/axis_avg_buffer_2/inst/axi_slv_i/slv_reg1_reg[10]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/avg_top_i/avg_i/addr_r_reg[10]_replica_1/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.503ns  (logic 0.215ns (8.588%)  route 2.288ns (91.412%))
  Logic Levels:           1  (LUT4=1)
  Clock Path Skew:        3.862ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    6.293ns
    Source Clock Delay      (SCD):    2.431ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.243ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.323ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      2.205ns (routing 0.662ns, distribution 1.543ns)
  Clock Net Delay (Destination): 2.648ns (routing 1.400ns, distribution 1.248ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       2.205     2.431    d_1_i/axis_avg_buffer_2/inst/axi_slv_i/s_axi_aclk
    SLICE_X80Y101        FDRE                                         r  d_1_i/axis_avg_buffer_2/inst/axi_slv_i/slv_reg1_reg[10]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X80Y101        FDRE (Prop_HFF2_SLICEL_C_Q)
                                                      0.080     2.511 r  d_1_i/axis_avg_buffer_2/inst/axi_slv_i/slv_reg1_reg[10]/Q
                         net (fo=2, routed)           1.647     4.158    d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/avg_top_i/avg_i/addr_r_reg[13]_15[10]
    SLICE_X79Y67         LUT4 (Prop_H5LUT_SLICEM_I0_O)
                                                      0.135     4.293 r  d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/avg_top_i/avg_i/addr_r[10]_i_1/O
                         net (fo=7, routed)           0.642     4.935    d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/avg_top_i/avg_i/p_0_in[10]
    SLICE_X74Y54         FDRE                                         r  d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/avg_top_i/avg_i/addr_r_reg[10]_replica_1/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.389     2.775    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     3.405 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.216     3.621    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.645 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86296, routed)       2.648     6.293    d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/avg_top_i/avg_i/s_axis_aclk
    SLICE_X74Y54         FDRE                                         r  d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/avg_top_i/avg_i/addr_r_reg[10]_replica_1/C

Slack:                    inf
  Source:                 d_1_i/axis_avg_buffer_2/inst/axi_slv_i/slv_reg1_reg[10]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/avg_top_i/avg_i/addr_r_reg[10]_replica_4/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.399ns  (logic 0.215ns (8.961%)  route 2.184ns (91.039%))
  Logic Levels:           1  (LUT4=1)
  Clock Path Skew:        3.862ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    6.293ns
    Source Clock Delay      (SCD):    2.431ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.243ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.323ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      2.205ns (routing 0.662ns, distribution 1.543ns)
  Clock Net Delay (Destination): 2.648ns (routing 1.400ns, distribution 1.248ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       2.205     2.431    d_1_i/axis_avg_buffer_2/inst/axi_slv_i/s_axi_aclk
    SLICE_X80Y101        FDRE                                         r  d_1_i/axis_avg_buffer_2/inst/axi_slv_i/slv_reg1_reg[10]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X80Y101        FDRE (Prop_HFF2_SLICEL_C_Q)
                                                      0.080     2.511 r  d_1_i/axis_avg_buffer_2/inst/axi_slv_i/slv_reg1_reg[10]/Q
                         net (fo=2, routed)           1.647     4.158    d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/avg_top_i/avg_i/addr_r_reg[13]_15[10]
    SLICE_X79Y67         LUT4 (Prop_H5LUT_SLICEM_I0_O)
                                                      0.135     4.293 r  d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/avg_top_i/avg_i/addr_r[10]_i_1/O
                         net (fo=7, routed)           0.538     4.831    d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/avg_top_i/avg_i/p_0_in[10]
    SLICE_X74Y59         FDRE                                         r  d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/avg_top_i/avg_i/addr_r_reg[10]_replica_4/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.389     2.775    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     3.405 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.216     3.621    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.645 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86296, routed)       2.648     6.293    d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/avg_top_i/avg_i/s_axis_aclk
    SLICE_X74Y59         FDRE                                         r  d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/avg_top_i/avg_i/addr_r_reg[10]_replica_4/C

Slack:                    inf
  Source:                 d_1_i/axis_avg_buffer_1/inst/axi_slv_i/slv_reg7_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/buffer_top_i/buffer_i/addr_r_reg[1]_replica_1/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.435ns  (logic 0.240ns (9.857%)  route 2.195ns (90.143%))
  Logic Levels:           1  (LUT4=1)
  Clock Path Skew:        3.883ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    6.268ns
    Source Clock Delay      (SCD):    2.385ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.243ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.323ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      2.159ns (routing 0.662ns, distribution 1.497ns)
  Clock Net Delay (Destination): 2.623ns (routing 1.400ns, distribution 1.223ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       2.159     2.385    d_1_i/axis_avg_buffer_1/inst/axi_slv_i/s_axi_aclk
    SLICE_X80Y151        FDRE                                         r  d_1_i/axis_avg_buffer_1/inst/axi_slv_i/slv_reg7_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X80Y151        FDRE (Prop_EFF2_SLICEL_C_Q)
                                                      0.081     2.466 r  d_1_i/axis_avg_buffer_1/inst/axi_slv_i/slv_reg7_reg[1]/Q
                         net (fo=2, routed)           1.561     4.027    d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/buffer_top_i/buffer_i/addr_r_reg[11]_1[1]
    SLICE_X82Y191        LUT4 (Prop_C5LUT_SLICEM_I0_O)
                                                      0.159     4.186 r  d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/buffer_top_i/buffer_i/addr_r[1]_i_1__0/O
                         net (fo=3, routed)           0.634     4.820    d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/buffer_top_i/buffer_i/p_0_in__2[1]
    SLICE_X80Y198        FDRE                                         r  d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/buffer_top_i/buffer_i/addr_r_reg[1]_replica_1/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.389     2.775    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     3.405 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.216     3.621    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.645 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86296, routed)       2.623     6.268    d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/buffer_top_i/buffer_i/s_axis_aclk
    SLICE_X80Y198        FDRE                                         r  d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/buffer_top_i/buffer_i/addr_r_reg[1]_replica_1/C

Slack:                    inf
  Source:                 d_1_i/axis_avg_buffer_2/inst/axi_slv_i/slv_reg1_reg[12]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/avg_top_i/avg_i/addr_r_reg[12]_replica/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.372ns  (logic 0.216ns (9.106%)  route 2.156ns (90.894%))
  Logic Levels:           1  (LUT5=1)
  Clock Path Skew:        3.967ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    6.398ns
    Source Clock Delay      (SCD):    2.431ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.243ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.323ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      2.205ns (routing 0.662ns, distribution 1.543ns)
  Clock Net Delay (Destination): 2.753ns (routing 1.400ns, distribution 1.353ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       2.205     2.431    d_1_i/axis_avg_buffer_2/inst/axi_slv_i/s_axi_aclk
    SLICE_X80Y101        FDRE                                         r  d_1_i/axis_avg_buffer_2/inst/axi_slv_i/slv_reg1_reg[12]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X80Y101        FDRE (Prop_GFF2_SLICEL_C_Q)
                                                      0.081     2.512 r  d_1_i/axis_avg_buffer_2/inst/axi_slv_i/slv_reg1_reg[12]/Q
                         net (fo=2, routed)           1.322     3.835    d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/avg_top_i/avg_i/addr_r_reg[13]_15[12]
    SLICE_X79Y57         LUT5 (Prop_H5LUT_SLICEM_I0_O)
                                                      0.135     3.970 r  d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/avg_top_i/avg_i/addr_r[12]_i_1/O
                         net (fo=5, routed)           0.834     4.803    d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/avg_top_i/avg_i/p_0_in[12]
    SLICE_X83Y65         FDRE                                         r  d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/avg_top_i/avg_i/addr_r_reg[12]_replica/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.389     2.775    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     3.405 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.216     3.621    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.645 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86296, routed)       2.753     6.398    d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/avg_top_i/avg_i/s_axis_aclk
    SLICE_X83Y65         FDRE                                         r  d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/avg_top_i/avg_i/addr_r_reg[12]_replica/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_hsdata_ff_reg[1]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.179ns  (logic 0.040ns (22.346%)  route 0.139ns (77.654%))
  Logic Levels:           0  
  Clock Path Skew:        2.463ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.688ns
    Source Clock Delay      (SCD):    1.225ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.243ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.323ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      1.105ns (routing 0.359ns, distribution 0.746ns)
  Clock Net Delay (Destination): 1.822ns (routing 0.950ns, distribution 0.872ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.105     1.225    d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_clk
    SLICE_X55Y207        FDRE                                         r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X55Y207        FDRE (Prop_AFF2_SLICEL_C_Q)
                                                      0.040     1.265 r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff_reg[1]/Q
                         net (fo=1, routed)           0.139     1.404    d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff[1]
    SLICE_X55Y208        FDRE                                         r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_hsdata_ff_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.624     1.976    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.681 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.847    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.866 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86296, routed)       1.822     3.688    d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_clk
    SLICE_X55Y208        FDRE                                         r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_hsdata_ff_reg[1]/C

Slack:                    inf
  Source:                 d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_hsdata_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.184ns  (logic 0.039ns (21.196%)  route 0.145ns (78.804%))
  Logic Levels:           0  
  Clock Path Skew:        2.463ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.688ns
    Source Clock Delay      (SCD):    1.225ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.243ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.323ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      1.105ns (routing 0.359ns, distribution 0.746ns)
  Clock Net Delay (Destination): 1.822ns (routing 0.950ns, distribution 0.872ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.105     1.225    d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_clk
    SLICE_X55Y207        FDRE                                         r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X55Y207        FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.039     1.264 r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff_reg[0]/Q
                         net (fo=1, routed)           0.145     1.409    d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff[0]
    SLICE_X55Y208        FDRE                                         r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_hsdata_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.624     1.976    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.681 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.847    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.866 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86296, routed)       1.822     3.688    d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_clk
    SLICE_X55Y208        FDRE                                         r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_hsdata_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_hsdata_ff_reg[2]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.207ns  (logic 0.039ns (18.841%)  route 0.168ns (81.159%))
  Logic Levels:           0  
  Clock Path Skew:        2.466ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.691ns
    Source Clock Delay      (SCD):    1.225ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.243ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.323ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      1.105ns (routing 0.359ns, distribution 0.746ns)
  Clock Net Delay (Destination): 1.825ns (routing 0.950ns, distribution 0.875ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.105     1.225    d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_clk
    SLICE_X55Y207        FDRE                                         r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X55Y207        FDRE (Prop_BFF_SLICEL_C_Q)
                                                      0.039     1.264 r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff_reg[2]/Q
                         net (fo=1, routed)           0.168     1.432    d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff[2]
    SLICE_X56Y214        FDRE                                         r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_hsdata_ff_reg[2]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.624     1.976    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.681 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.847    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.866 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86296, routed)       1.825     3.691    d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_clk
    SLICE_X56Y214        FDRE                                         r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_hsdata_ff_reg[2]/C

Slack:                    inf
  Source:                 d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_hsdata_ff_reg[3]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.220ns  (logic 0.040ns (18.182%)  route 0.180ns (81.818%))
  Logic Levels:           0  
  Clock Path Skew:        2.466ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.691ns
    Source Clock Delay      (SCD):    1.225ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.243ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.323ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      1.105ns (routing 0.359ns, distribution 0.746ns)
  Clock Net Delay (Destination): 1.825ns (routing 0.950ns, distribution 0.875ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.105     1.225    d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_clk
    SLICE_X55Y207        FDRE                                         r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X55Y207        FDRE (Prop_BFF2_SLICEL_C_Q)
                                                      0.040     1.265 r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff_reg[3]/Q
                         net (fo=1, routed)           0.180     1.445    d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff[3]
    SLICE_X56Y214        FDRE                                         r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_hsdata_ff_reg[3]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.624     1.976    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.681 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.847    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.866 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86296, routed)       1.825     3.691    d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_clk
    SLICE_X56Y214        FDRE                                         r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_hsdata_ff_reg[3]/C

Slack:                    inf
  Source:                 d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff_reg[4]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_hsdata_ff_reg[4]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.260ns  (logic 0.039ns (15.000%)  route 0.221ns (85.000%))
  Logic Levels:           0  
  Clock Path Skew:        2.466ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.691ns
    Source Clock Delay      (SCD):    1.225ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.243ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.323ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      1.105ns (routing 0.359ns, distribution 0.746ns)
  Clock Net Delay (Destination): 1.825ns (routing 0.950ns, distribution 0.875ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.105     1.225    d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_clk
    SLICE_X55Y207        FDRE                                         r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X55Y207        FDRE (Prop_CFF_SLICEL_C_Q)
                                                      0.039     1.264 r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff_reg[4]/Q
                         net (fo=1, routed)           0.221     1.485    d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff[4]
    SLICE_X56Y214        FDRE                                         r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_hsdata_ff_reg[4]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.624     1.976    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.681 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.847    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.866 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86296, routed)       1.825     3.691    d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_clk
    SLICE_X56Y214        FDRE                                         r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_hsdata_ff_reg[4]/C

Slack:                    inf
  Source:                 d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_sendd_ff_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.266ns  (logic 0.039ns (14.652%)  route 0.227ns (85.348%))
  Logic Levels:           0  
  Clock Path Skew:        2.456ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.690ns
    Source Clock Delay      (SCD):    1.234ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.243ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.323ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      1.114ns (routing 0.359ns, distribution 0.755ns)
  Clock Net Delay (Destination): 1.824ns (routing 0.950ns, distribution 0.874ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.114     1.234    d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_clk
    SLICE_X57Y182        FDRE                                         r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_sendd_ff_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X57Y182        FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.039     1.273 r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_sendd_ff_reg/Q
                         net (fo=2, routed)           0.227     1.500    d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/src_in
    SLICE_X55Y206        FDRE                                         r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.624     1.976    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.681 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.847    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.866 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86296, routed)       1.824     3.690    d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/dest_clk
    SLICE_X55Y206        FDRE                                         r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_hsdata_ff_reg[1]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.136ns  (logic 0.039ns (28.676%)  route 0.097ns (71.324%))
  Logic Levels:           0  
  Clock Path Skew:        2.380ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.770ns
    Source Clock Delay      (SCD):    1.390ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.243ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.323ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      1.270ns (routing 0.359ns, distribution 0.911ns)
  Clock Net Delay (Destination): 1.904ns (routing 0.950ns, distribution 0.954ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.270     1.390    d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_clk
    SLICE_X86Y73         FDRE                                         r  d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X86Y73         FDRE (Prop_GFF2_SLICEM_C_Q)
                                                      0.039     1.429 r  d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff_reg[1]/Q
                         net (fo=1, routed)           0.097     1.526    d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff[1]
    SLICE_X86Y73         FDRE                                         r  d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_hsdata_ff_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.624     1.976    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.681 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.847    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.866 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86296, routed)       1.904     3.770    d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_clk
    SLICE_X86Y73         FDRE                                         r  d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_hsdata_ff_reg[1]/C

Slack:                    inf
  Source:                 d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff_reg[4]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_hsdata_ff_reg[4]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.163ns  (logic 0.039ns (23.926%)  route 0.124ns (76.074%))
  Logic Levels:           0  
  Clock Path Skew:        2.396ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.787ns
    Source Clock Delay      (SCD):    1.391ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.243ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.323ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      1.271ns (routing 0.359ns, distribution 0.912ns)
  Clock Net Delay (Destination): 1.921ns (routing 0.950ns, distribution 0.971ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.271     1.391    d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_clk
    SLICE_X86Y71         FDRE                                         r  d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X86Y71         FDRE (Prop_HFF2_SLICEM_C_Q)
                                                      0.039     1.430 r  d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff_reg[4]/Q
                         net (fo=1, routed)           0.124     1.554    d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff[4]
    SLICE_X87Y68         FDRE                                         r  d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_hsdata_ff_reg[4]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.624     1.976    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.681 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.847    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.866 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86296, routed)       1.921     3.787    d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_clk
    SLICE_X87Y68         FDRE                                         r  d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_hsdata_ff_reg[4]/C

Slack:                    inf
  Source:                 d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_hsdata_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.173ns  (logic 0.039ns (22.543%)  route 0.134ns (77.457%))
  Logic Levels:           0  
  Clock Path Skew:        2.380ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.770ns
    Source Clock Delay      (SCD):    1.390ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.243ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.323ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      1.270ns (routing 0.359ns, distribution 0.911ns)
  Clock Net Delay (Destination): 1.904ns (routing 0.950ns, distribution 0.954ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.270     1.390    d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_clk
    SLICE_X86Y73         FDRE                                         r  d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X86Y73         FDRE (Prop_HFF2_SLICEM_C_Q)
                                                      0.039     1.429 r  d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff_reg[0]/Q
                         net (fo=1, routed)           0.134     1.563    d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff[0]
    SLICE_X86Y73         FDRE                                         r  d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_hsdata_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.624     1.976    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.681 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.847    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.866 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86296, routed)       1.904     3.770    d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_clk
    SLICE_X86Y73         FDRE                                         r  d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_hsdata_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_hsdata_ff_reg[2]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.190ns  (logic 0.040ns (21.053%)  route 0.150ns (78.947%))
  Logic Levels:           0  
  Clock Path Skew:        2.380ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.770ns
    Source Clock Delay      (SCD):    1.390ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.243ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.323ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      1.270ns (routing 0.359ns, distribution 0.911ns)
  Clock Net Delay (Destination): 1.904ns (routing 0.950ns, distribution 0.954ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.270     1.390    d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_clk
    SLICE_X86Y73         FDRE                                         r  d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X86Y73         FDRE (Prop_FFF2_SLICEM_C_Q)
                                                      0.040     1.430 r  d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff_reg[2]/Q
                         net (fo=1, routed)           0.150     1.580    d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff[2]
    SLICE_X86Y73         FDRE                                         r  d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_hsdata_ff_reg[2]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.624     1.976    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.681 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.847    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.866 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86296, routed)       1.904     3.770    d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_clk
    SLICE_X86Y73         FDRE                                         r  d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_hsdata_ff_reg[2]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  mmcm_clkout0
  To Clock:  clk_out1_d_1_clk_adc0_x2_0

Max Delay             7 Endpoints
Min Delay             7 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/rst_ddr4/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.866ns  (logic 0.180ns (20.784%)  route 0.686ns (79.216%))
  Logic Levels:           1  (LUT1=1)
  Clock Path Skew:        1.372ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    6.262ns
    Source Clock Delay      (SCD):    4.890ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.220ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.176ns
    Phase Error              (PE):    0.125ns
  Clock Net Delay (Source):      2.135ns (routing 0.696ns, distribution 1.439ns)
  Clock Net Delay (Destination): 2.617ns (routing 1.400ns, distribution 1.217ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.524     2.610    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.483 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.244     2.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.755 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       2.135     4.890    d_1_i/rst_ddr4/U0/slowest_sync_clk
    SLICE_X47Y183        FDRE                                         r  d_1_i/rst_ddr4/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X47Y183        FDRE (Prop_DFF2_SLICEL_C_Q)
                                                      0.081     4.971 f  d_1_i/rst_ddr4/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=2, routed)           0.637     5.608    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/m_axis_aresetn
    SLICE_X65Y173        LUT1 (Prop_H6LUT_SLICEL_I0_O)
                                                      0.099     5.707 r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst_i_1/O
                         net (fo=1, routed)           0.049     5.756    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst/src_rst
    SLICE_X65Y173        FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.389     2.775    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     3.405 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.216     3.621    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.645 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86296, routed)       2.617     6.262    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst/dest_clk
    SLICE_X65Y173        FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.308ns  (logic 0.079ns (25.649%)  route 0.229ns (74.351%))
  Logic Levels:           0  
  Clock Path Skew:        1.460ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    6.395ns
    Source Clock Delay      (SCD):    4.935ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.220ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.176ns
    Phase Error              (PE):    0.125ns
  Clock Net Delay (Source):      2.180ns (routing 0.696ns, distribution 1.484ns)
  Clock Net Delay (Destination): 2.750ns (routing 1.400ns, distribution 1.350ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.524     2.610    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.483 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.244     2.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.755 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       2.180     4.935    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/rd_clk
    SLICE_X48Y241        FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X48Y241        FDRE (Prop_GFF2_SLICEM_C_Q)
                                                      0.079     5.014 r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg/Q
                         net (fo=1, routed)           0.229     5.243    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/src_rst
    SLICE_X48Y242        FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.389     2.775    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     3.405 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.216     3.621    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.645 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86296, routed)       2.750     6.395    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/dest_clk
    SLICE_X48Y242        FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.408ns  (logic 0.080ns (19.608%)  route 0.328ns (80.392%))
  Logic Levels:           0  
  Clock Path Skew:        1.474ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    6.388ns
    Source Clock Delay      (SCD):    4.914ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.220ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.176ns
    Phase Error              (PE):    0.125ns
  Clock Net Delay (Source):      2.159ns (routing 0.696ns, distribution 1.463ns)
  Clock Net Delay (Destination): 2.743ns (routing 1.400ns, distribution 1.343ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.524     2.610    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.483 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.244     2.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.755 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       2.159     4.914    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_clk
    SLICE_X45Y261        FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X45Y261        FDRE (Prop_DFF2_SLICEM_C_Q)
                                                      0.080     4.994 r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[1]/Q
                         net (fo=1, routed)           0.328     5.322    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/async_path[1]
    SLICE_X45Y261        FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.389     2.775    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     3.405 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.216     3.621    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.645 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86296, routed)       2.743     6.388    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_clk
    SLICE_X45Y261        FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/C

Slack:                    inf
  Source:                 d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[4]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][4]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.354ns  (logic 0.079ns (22.316%)  route 0.275ns (77.684%))
  Logic Levels:           0  
  Clock Path Skew:        1.451ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    6.382ns
    Source Clock Delay      (SCD):    4.931ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.220ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.176ns
    Phase Error              (PE):    0.125ns
  Clock Net Delay (Source):      2.176ns (routing 0.696ns, distribution 1.480ns)
  Clock Net Delay (Destination): 2.737ns (routing 1.400ns, distribution 1.337ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.524     2.610    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.483 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.244     2.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.755 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       2.176     4.931    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_clk
    SLICE_X46Y267        FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X46Y267        FDRE (Prop_HFF_SLICEM_C_Q)
                                                      0.079     5.010 r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[4]/Q
                         net (fo=1, routed)           0.275     5.285    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/async_path[4]
    SLICE_X46Y266        FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][4]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.389     2.775    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     3.405 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.216     3.621    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.645 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86296, routed)       2.737     6.382    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_clk
    SLICE_X46Y266        FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][4]/C

Slack:                    inf
  Source:                 d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.353ns  (logic 0.078ns (22.096%)  route 0.275ns (77.904%))
  Logic Levels:           0  
  Clock Path Skew:        1.474ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    6.388ns
    Source Clock Delay      (SCD):    4.914ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.220ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.176ns
    Phase Error              (PE):    0.125ns
  Clock Net Delay (Source):      2.159ns (routing 0.696ns, distribution 1.463ns)
  Clock Net Delay (Destination): 2.743ns (routing 1.400ns, distribution 1.343ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.524     2.610    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.483 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.244     2.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.755 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       2.159     4.914    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_clk
    SLICE_X45Y261        FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X45Y261        FDRE (Prop_DFF_SLICEM_C_Q)
                                                      0.078     4.992 r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[0]/Q
                         net (fo=1, routed)           0.275     5.267    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/async_path[0]
    SLICE_X45Y261        FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.389     2.775    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     3.405 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.216     3.621    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.645 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86296, routed)       2.743     6.388    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_clk
    SLICE_X45Y261        FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/C

Slack:                    inf
  Source:                 d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.339ns  (logic 0.077ns (22.714%)  route 0.262ns (77.286%))
  Logic Levels:           0  
  Clock Path Skew:        1.476ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    6.390ns
    Source Clock Delay      (SCD):    4.914ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.220ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.176ns
    Phase Error              (PE):    0.125ns
  Clock Net Delay (Source):      2.159ns (routing 0.696ns, distribution 1.463ns)
  Clock Net Delay (Destination): 2.745ns (routing 1.400ns, distribution 1.345ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.524     2.610    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.483 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.244     2.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.755 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       2.159     4.914    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_clk
    SLICE_X45Y261        FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X45Y261        FDRE (Prop_CFF2_SLICEM_C_Q)
                                                      0.077     4.991 r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[3]/Q
                         net (fo=1, routed)           0.262     5.253    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/async_path[3]
    SLICE_X44Y261        FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.389     2.775    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     3.405 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.216     3.621    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.645 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86296, routed)       2.745     6.390    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_clk
    SLICE_X44Y261        FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/C

Slack:                    inf
  Source:                 d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.336ns  (logic 0.078ns (23.214%)  route 0.258ns (76.786%))
  Logic Levels:           0  
  Clock Path Skew:        1.476ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    6.390ns
    Source Clock Delay      (SCD):    4.914ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.220ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.176ns
    Phase Error              (PE):    0.125ns
  Clock Net Delay (Source):      2.159ns (routing 0.696ns, distribution 1.463ns)
  Clock Net Delay (Destination): 2.745ns (routing 1.400ns, distribution 1.345ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.524     2.610    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.483 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.244     2.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.755 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       2.159     4.914    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_clk
    SLICE_X45Y261        FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X45Y261        FDRE (Prop_CFF_SLICEM_C_Q)
                                                      0.078     4.992 r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[2]/Q
                         net (fo=1, routed)           0.258     5.250    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/async_path[2]
    SLICE_X44Y261        FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.389     2.775    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     3.405 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.216     3.621    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.645 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86296, routed)       2.745     6.390    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_clk
    SLICE_X44Y261        FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.127ns  (logic 0.039ns (30.709%)  route 0.088ns (69.291%))
  Logic Levels:           0  
  Clock Path Skew:        0.709ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.755ns
    Source Clock Delay      (SCD):    3.046ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.220ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.176ns
    Phase Error              (PE):    0.125ns
  Clock Net Delay (Source):      1.198ns (routing 0.384ns, distribution 0.814ns)
  Clock Net Delay (Destination): 1.889ns (routing 0.950ns, distribution 0.939ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.839     1.456    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.686 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.145     1.831    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.848 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.198     3.046    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/rd_clk
    SLICE_X48Y241        FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X48Y241        FDRE (Prop_GFF2_SLICEM_C_Q)
                                                      0.039     3.085 r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg/Q
                         net (fo=1, routed)           0.088     3.173    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/src_rst
    SLICE_X48Y242        FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.624     1.976    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.681 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.847    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.866 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86296, routed)       1.889     3.755    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/dest_clk
    SLICE_X48Y242        FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.144ns  (logic 0.038ns (26.389%)  route 0.106ns (73.611%))
  Logic Levels:           0  
  Clock Path Skew:        0.709ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.749ns
    Source Clock Delay      (SCD):    3.040ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.220ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.176ns
    Phase Error              (PE):    0.125ns
  Clock Net Delay (Source):      1.192ns (routing 0.384ns, distribution 0.808ns)
  Clock Net Delay (Destination): 1.883ns (routing 0.950ns, distribution 0.933ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.839     1.456    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.686 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.145     1.831    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.848 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.192     3.040    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_clk
    SLICE_X45Y261        FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X45Y261        FDRE (Prop_CFF_SLICEM_C_Q)
                                                      0.038     3.078 r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[2]/Q
                         net (fo=1, routed)           0.106     3.184    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/async_path[2]
    SLICE_X44Y261        FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.624     1.976    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.681 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.847    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.866 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86296, routed)       1.883     3.749    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_clk
    SLICE_X44Y261        FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/C

Slack:                    inf
  Source:                 d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.148ns  (logic 0.039ns (26.351%)  route 0.109ns (73.649%))
  Logic Levels:           0  
  Clock Path Skew:        0.709ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.749ns
    Source Clock Delay      (SCD):    3.040ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.220ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.176ns
    Phase Error              (PE):    0.125ns
  Clock Net Delay (Source):      1.192ns (routing 0.384ns, distribution 0.808ns)
  Clock Net Delay (Destination): 1.883ns (routing 0.950ns, distribution 0.933ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.839     1.456    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.686 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.145     1.831    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.848 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.192     3.040    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_clk
    SLICE_X45Y261        FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X45Y261        FDRE (Prop_CFF2_SLICEM_C_Q)
                                                      0.039     3.079 r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[3]/Q
                         net (fo=1, routed)           0.109     3.188    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/async_path[3]
    SLICE_X44Y261        FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.624     1.976    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.681 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.847    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.866 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86296, routed)       1.883     3.749    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_clk
    SLICE_X44Y261        FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/C

Slack:                    inf
  Source:                 d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.154ns  (logic 0.039ns (25.325%)  route 0.115ns (74.675%))
  Logic Levels:           0  
  Clock Path Skew:        0.709ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.749ns
    Source Clock Delay      (SCD):    3.040ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.220ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.176ns
    Phase Error              (PE):    0.125ns
  Clock Net Delay (Source):      1.192ns (routing 0.384ns, distribution 0.808ns)
  Clock Net Delay (Destination): 1.883ns (routing 0.950ns, distribution 0.933ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.839     1.456    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.686 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.145     1.831    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.848 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.192     3.040    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_clk
    SLICE_X45Y261        FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X45Y261        FDRE (Prop_DFF_SLICEM_C_Q)
                                                      0.039     3.079 r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[0]/Q
                         net (fo=1, routed)           0.115     3.194    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/async_path[0]
    SLICE_X45Y261        FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.624     1.976    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.681 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.847    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.866 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86296, routed)       1.883     3.749    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_clk
    SLICE_X45Y261        FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/C

Slack:                    inf
  Source:                 d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[4]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][4]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.162ns  (logic 0.039ns (24.074%)  route 0.123ns (75.926%))
  Logic Levels:           0  
  Clock Path Skew:        0.705ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.747ns
    Source Clock Delay      (SCD):    3.043ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.220ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.176ns
    Phase Error              (PE):    0.125ns
  Clock Net Delay (Source):      1.195ns (routing 0.384ns, distribution 0.811ns)
  Clock Net Delay (Destination): 1.881ns (routing 0.950ns, distribution 0.931ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.839     1.456    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.686 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.145     1.831    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.848 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.195     3.043    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_clk
    SLICE_X46Y267        FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X46Y267        FDRE (Prop_HFF_SLICEM_C_Q)
                                                      0.039     3.082 r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[4]/Q
                         net (fo=1, routed)           0.123     3.205    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/async_path[4]
    SLICE_X46Y266        FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][4]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.624     1.976    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.681 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.847    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.866 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86296, routed)       1.881     3.747    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_clk
    SLICE_X46Y266        FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][4]/C

Slack:                    inf
  Source:                 d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.180ns  (logic 0.041ns (22.778%)  route 0.139ns (77.222%))
  Logic Levels:           0  
  Clock Path Skew:        0.709ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.749ns
    Source Clock Delay      (SCD):    3.040ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.220ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.176ns
    Phase Error              (PE):    0.125ns
  Clock Net Delay (Source):      1.192ns (routing 0.384ns, distribution 0.808ns)
  Clock Net Delay (Destination): 1.883ns (routing 0.950ns, distribution 0.933ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.839     1.456    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.686 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.145     1.831    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.848 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.192     3.040    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_clk
    SLICE_X45Y261        FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X45Y261        FDRE (Prop_DFF2_SLICEM_C_Q)
                                                      0.041     3.081 r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[1]/Q
                         net (fo=1, routed)           0.139     3.220    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/async_path[1]
    SLICE_X45Y261        FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.624     1.976    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.681 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.847    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.866 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86296, routed)       1.883     3.749    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_clk
    SLICE_X45Y261        FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/C

Slack:                    inf
  Source:                 d_1_i/rst_ddr4/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.428ns  (logic 0.082ns (19.173%)  route 0.346ns (80.827%))
  Logic Levels:           1  (LUT1=1)
  Clock Path Skew:        0.653ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.676ns
    Source Clock Delay      (SCD):    3.023ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.220ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.176ns
    Phase Error              (PE):    0.125ns
  Clock Net Delay (Source):      1.175ns (routing 0.384ns, distribution 0.791ns)
  Clock Net Delay (Destination): 1.810ns (routing 0.950ns, distribution 0.860ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.839     1.456    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.686 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.145     1.831    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.848 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.175     3.023    d_1_i/rst_ddr4/U0/slowest_sync_clk
    SLICE_X47Y183        FDRE                                         r  d_1_i/rst_ddr4/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X47Y183        FDRE (Prop_DFF2_SLICEL_C_Q)
                                                      0.041     3.064 f  d_1_i/rst_ddr4/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=2, routed)           0.331     3.395    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/m_axis_aresetn
    SLICE_X65Y173        LUT1 (Prop_H6LUT_SLICEL_I0_O)
                                                      0.041     3.436 r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst_i_1/O
                         net (fo=1, routed)           0.015     3.451    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst/src_rst
    SLICE_X65Y173        FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.624     1.976    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.681 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.847    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.866 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86296, routed)       1.810     3.676    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst/dest_clk
    SLICE_X65Y173        FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst/syncstages_ff_reg[0]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  
  To Clock:  clk_out1_d_1_clk_core_0

Max Delay             1 Endpoint
Min Delay             1 Endpoint
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/EMIOGPIOO[95]
                            (internal pin)
  Destination:            d_1_i/rst_core/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.318ns  (logic 0.096ns (2.893%)  route 3.222ns (97.107%))
  Logic Levels:           1  (LUT1=1)
  Clock Uncertainty:      0.143ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Destination): 2.369ns (routing 1.325ns, distribution 1.044ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    PS8_X0Y0             PS8                          0.000     0.000 f  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/EMIOGPIOO[95]
                         net (fo=5, routed)           2.997     2.997    d_1_i/rst_core/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/ext_reset_in
    SLICE_X101Y66        LUT1 (Prop_D5LUT_SLICEL_I0_O)
                                                      0.096     3.093 r  d_1_i/rst_core/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1/O
                         net (fo=1, routed)           0.225     3.318    d_1_i/rst_core/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/exr_d1
    SLICE_X101Y67        FDRE                                         r  d_1_i/rst_core/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=48236, routed)       1.931     2.113    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.743 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.958    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y133        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.982 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=4540, routed)        2.369     5.351    d_1_i/rst_core/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/slowest_sync_clk
    SLICE_X101Y67        FDRE                                         r  d_1_i/rst_core/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/EMIOGPIOO[95]
                            (internal pin)
  Destination:            d_1_i/rst_core/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.605ns  (logic 0.033ns (2.055%)  route 1.572ns (97.945%))
  Logic Levels:           1  (LUT1=1)
  Clock Uncertainty:      0.143ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Destination): 1.643ns (routing 0.896ns, distribution 0.747ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    PS8_X0Y0             PS8                          0.000     0.000 f  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/EMIOGPIOO[95]
                         net (fo=5, routed)           1.481     1.481    d_1_i/rst_core/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/ext_reset_in
    SLICE_X101Y66        LUT1 (Prop_D5LUT_SLICEL_I0_O)
                                                      0.033     1.514 r  d_1_i/rst_core/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1/O
                         net (fo=1, routed)           0.091     1.605    d_1_i/rst_core/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/exr_d1
    SLICE_X101Y67        FDRE                                         r  d_1_i/rst_core/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=48236, routed)       1.311     1.458    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.163 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.329    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y133        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.348 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=4540, routed)        1.643     2.991    d_1_i/rst_core/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/slowest_sync_clk
    SLICE_X101Y67        FDRE                                         r  d_1_i/rst_core/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  RFDAC0_CLK
  To Clock:  clk_out1_d_1_clk_core_0

Max Delay           303 Endpoints
Min Delay           303 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[2]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/rd_gptr_cdc_reg[2]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.475ns  (logic 0.078ns (5.288%)  route 1.397ns (94.712%))
  Logic Levels:           0  
  Clock Path Skew:        1.362ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.242ns
    Source Clock Delay      (SCD):    3.880ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      3.207ns (routing 1.460ns, distribution 1.747ns)
  Clock Net Delay (Destination): 2.260ns (routing 1.325ns, distribution 0.935ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y100       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89456, routed)       3.207     3.880    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/gcc_rd_ptr/t_clk_i
    SLICE_X97Y254        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X97Y254        FDCE (Prop_CFF_SLICEM_C_Q)
                                                      0.078     3.958 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[2]/Q
                         net (fo=5, routed)           1.397     5.355    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/rd_gptr[2]
    SLICE_X80Y235        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/rd_gptr_cdc_reg[2]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=48236, routed)       1.931     2.113    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.743 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.958    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y133        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.982 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=4540, routed)        2.260     5.242    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/c_clk_i
    SLICE_X80Y235        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/rd_gptr_cdc_reg[2]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[0]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/rd_gptr_cdc_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.314ns  (logic 0.080ns (6.088%)  route 1.234ns (93.912%))
  Logic Levels:           0  
  Clock Path Skew:        1.386ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.241ns
    Source Clock Delay      (SCD):    3.855ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      3.182ns (routing 1.460ns, distribution 1.722ns)
  Clock Net Delay (Destination): 2.259ns (routing 1.325ns, distribution 0.934ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y100       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89456, routed)       3.182     3.855    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/gcc_rd_ptr/t_clk_i
    SLICE_X97Y256        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X97Y256        FDCE (Prop_DFF2_SLICEM_C_Q)
                                                      0.080     3.935 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[0]/Q
                         net (fo=5, routed)           1.234     5.169    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/rd_gptr[0]
    SLICE_X80Y233        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/rd_gptr_cdc_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=48236, routed)       1.931     2.113    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.743 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.958    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y133        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.982 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=4540, routed)        2.259     5.241    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/c_clk_i
    SLICE_X80Y233        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/rd_gptr_cdc_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[1]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/rd_gptr_cdc_reg[1]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.206ns  (logic 0.078ns (6.467%)  route 1.128ns (93.533%))
  Logic Levels:           0  
  Clock Path Skew:        1.361ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.241ns
    Source Clock Delay      (SCD):    3.880ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      3.207ns (routing 1.460ns, distribution 1.747ns)
  Clock Net Delay (Destination): 2.259ns (routing 1.325ns, distribution 0.934ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y100       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89456, routed)       3.207     3.880    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/gcc_rd_ptr/t_clk_i
    SLICE_X97Y254        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X97Y254        FDCE (Prop_DFF_SLICEM_C_Q)
                                                      0.078     3.958 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[1]/Q
                         net (fo=5, routed)           1.128     5.086    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/rd_gptr[1]
    SLICE_X80Y233        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/rd_gptr_cdc_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=48236, routed)       1.931     2.113    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.743 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.958    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y133        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.982 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=4540, routed)        2.259     5.241    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/c_clk_i
    SLICE_X80Y233        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/rd_gptr_cdc_reg[1]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[3].wave_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[0]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[3].wave_fifo_inst/rd_gptr_cdc_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.439ns  (logic 0.081ns (5.630%)  route 1.358ns (94.370%))
  Logic Levels:           0  
  Clock Path Skew:        1.674ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.296ns
    Source Clock Delay      (SCD):    3.622ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      2.949ns (routing 1.460ns, distribution 1.489ns)
  Clock Net Delay (Destination): 2.314ns (routing 1.325ns, distribution 0.989ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y100       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89456, routed)       2.949     3.622    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[3].wave_fifo_inst/gcc_rd_ptr/t_clk_i
    SLICE_X80Y151        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[3].wave_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X80Y151        FDCE (Prop_DFF2_SLICEL_C_Q)
                                                      0.081     3.703 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[3].wave_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[0]/Q
                         net (fo=5, routed)           1.358     5.061    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[3].wave_fifo_inst/rd_gptr[0]
    SLICE_X84Y153        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[3].wave_fifo_inst/rd_gptr_cdc_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=48236, routed)       1.931     2.113    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.743 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.958    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y133        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.982 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=4540, routed)        2.314     5.296    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[3].wave_fifo_inst/c_clk_i
    SLICE_X84Y153        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[3].wave_fifo_inst/rd_gptr_cdc_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/gcc_rd_ptr/clear_r_reg/C
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/clr_fifo_ack_reg/D
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.201ns  (logic 0.229ns (19.060%)  route 0.972ns (80.940%))
  Logic Levels:           1  (LUT3=1)
  Clock Path Skew:        1.420ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.244ns
    Source Clock Delay      (SCD):    3.824ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      3.151ns (routing 1.460ns, distribution 1.691ns)
  Clock Net Delay (Destination): 2.262ns (routing 1.325ns, distribution 0.937ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y100       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89456, routed)       3.151     3.824    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/gcc_rd_ptr/t_clk_i
    SLICE_X99Y235        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/gcc_rd_ptr/clear_r_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X99Y235        FDCE (Prop_AFF2_SLICEM_C_Q)
                                                      0.080     3.904 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/gcc_rd_ptr/clear_r_reg/Q
                         net (fo=20, routed)          0.924     4.829    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/clr_rd
    SLICE_X80Y234        LUT3 (Prop_G6LUT_SLICEL_I0_O)
                                                      0.149     4.978 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/clr_fifo_ack_i_1/O
                         net (fo=1, routed)           0.048     5.026    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/clr_fifo_ack_i_1_n_0
    SLICE_X80Y234        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/clr_fifo_ack_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=48236, routed)       1.931     2.113    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.743 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.958    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y133        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.982 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=4540, routed)        2.262     5.244    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/c_clk_i
    SLICE_X80Y234        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/clr_fifo_ack_reg/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[10].wave_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[4]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[10].wave_fifo_inst/rd_gptr_cdc_reg[4]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.167ns  (logic 0.079ns (6.771%)  route 1.088ns (93.229%))
  Logic Levels:           0  
  Clock Path Skew:        1.536ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.344ns
    Source Clock Delay      (SCD):    3.808ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      3.135ns (routing 1.460ns, distribution 1.675ns)
  Clock Net Delay (Destination): 2.362ns (routing 1.325ns, distribution 1.037ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y100       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89456, routed)       3.135     3.808    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[10].wave_fifo_inst/gcc_rd_ptr/t_clk_i
    SLICE_X95Y110        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[10].wave_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X95Y110        FDCE (Prop_HFF_SLICEL_C_Q)
                                                      0.079     3.887 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[10].wave_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[4]/Q
                         net (fo=5, routed)           1.088     4.974    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[10].wave_fifo_inst/rd_gptr[4]
    SLICE_X90Y131        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[10].wave_fifo_inst/rd_gptr_cdc_reg[4]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=48236, routed)       1.931     2.113    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.743 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.958    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y133        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.982 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=4540, routed)        2.362     5.344    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[10].wave_fifo_inst/c_clk_i
    SLICE_X90Y131        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[10].wave_fifo_inst/rd_gptr_cdc_reg[4]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[4].wave_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[4]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[4].wave_fifo_inst/rd_gptr_cdc_reg[4]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.345ns  (logic 0.078ns (5.799%)  route 1.267ns (94.201%))
  Logic Levels:           0  
  Clock Path Skew:        1.702ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.220ns
    Source Clock Delay      (SCD):    3.518ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      2.845ns (routing 1.460ns, distribution 1.385ns)
  Clock Net Delay (Destination): 2.238ns (routing 1.325ns, distribution 0.913ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y100       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89456, routed)       2.845     3.518    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[4].wave_fifo_inst/gcc_rd_ptr/t_clk_i
    SLICE_X53Y178        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[4].wave_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X53Y178        FDCE (Prop_CFF_SLICEM_C_Q)
                                                      0.078     3.596 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[4].wave_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[4]/Q
                         net (fo=5, routed)           1.267     4.863    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[4].wave_fifo_inst/rd_gptr[4]
    SLICE_X63Y170        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[4].wave_fifo_inst/rd_gptr_cdc_reg[4]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=48236, routed)       1.931     2.113    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.743 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.958    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y133        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.982 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=4540, routed)        2.238     5.220    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[4].wave_fifo_inst/c_clk_i
    SLICE_X63Y170        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[4].wave_fifo_inst/rd_gptr_cdc_reg[4]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[4]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/rd_gptr_cdc_reg[4]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.941ns  (logic 0.078ns (8.285%)  route 0.863ns (91.715%))
  Logic Levels:           0  
  Clock Path Skew:        1.478ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.333ns
    Source Clock Delay      (SCD):    3.855ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      3.182ns (routing 1.460ns, distribution 1.722ns)
  Clock Net Delay (Destination): 2.351ns (routing 1.325ns, distribution 1.026ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y100       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89456, routed)       3.182     3.855    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/gcc_rd_ptr/t_clk_i
    SLICE_X97Y256        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X97Y256        FDCE (Prop_CFF_SLICEM_C_Q)
                                                      0.078     3.933 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[4]/Q
                         net (fo=5, routed)           0.863     4.796    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/rd_gptr[4]
    SLICE_X84Y233        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/rd_gptr_cdc_reg[4]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=48236, routed)       1.931     2.113    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.743 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.958    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y133        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.982 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=4540, routed)        2.351     5.333    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/c_clk_i
    SLICE_X84Y233        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[11].wave_fifo_inst/rd_gptr_cdc_reg[4]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[10].wave_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[6]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[10].wave_fifo_inst/rd_gptr_cdc_reg[6]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.976ns  (logic 0.079ns (8.097%)  route 0.897ns (91.903%))
  Logic Levels:           0  
  Clock Path Skew:        1.532ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.340ns
    Source Clock Delay      (SCD):    3.808ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      3.135ns (routing 1.460ns, distribution 1.675ns)
  Clock Net Delay (Destination): 2.358ns (routing 1.325ns, distribution 1.033ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y100       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89456, routed)       3.135     3.808    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[10].wave_fifo_inst/gcc_rd_ptr/t_clk_i
    SLICE_X95Y110        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[10].wave_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[6]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X95Y110        FDCE (Prop_GFF_SLICEL_C_Q)
                                                      0.079     3.887 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[10].wave_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[6]/Q
                         net (fo=5, routed)           0.897     4.783    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[10].wave_fifo_inst/rd_gptr[6]
    SLICE_X91Y131        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[10].wave_fifo_inst/rd_gptr_cdc_reg[6]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=48236, routed)       1.931     2.113    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.743 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.958    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y133        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.982 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=4540, routed)        2.358     5.340    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[10].wave_fifo_inst/c_clk_i
    SLICE_X91Y131        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[10].wave_fifo_inst/rd_gptr_cdc_reg[6]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[10].wave_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[8]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[10].wave_fifo_inst/rd_gptr_cdc_reg[8]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.977ns  (logic 0.079ns (8.085%)  route 0.898ns (91.915%))
  Logic Levels:           0  
  Clock Path Skew:        1.568ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.346ns
    Source Clock Delay      (SCD):    3.778ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      3.105ns (routing 1.460ns, distribution 1.645ns)
  Clock Net Delay (Destination): 2.364ns (routing 1.325ns, distribution 1.039ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y100       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89456, routed)       3.105     3.778    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[10].wave_fifo_inst/gcc_rd_ptr/t_clk_i
    SLICE_X92Y110        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[10].wave_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[8]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X92Y110        FDCE (Prop_DFF_SLICEL_C_Q)
                                                      0.079     3.857 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[10].wave_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[8]/Q
                         net (fo=5, routed)           0.898     4.755    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[10].wave_fifo_inst/rd_gptr[8]
    SLICE_X91Y132        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[10].wave_fifo_inst/rd_gptr_cdc_reg[8]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=48236, routed)       1.931     2.113    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.743 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.958    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y133        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.982 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=4540, routed)        2.364     5.346    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[10].wave_fifo_inst/c_clk_i
    SLICE_X91Y132        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[10].wave_fifo_inst/rd_gptr_cdc_reg[8]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[10].trig_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[2]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[10].trig_fifo_inst/rd_gptr_cdc_reg[2]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.099ns  (logic 0.039ns (39.218%)  route 0.060ns (60.782%))
  Logic Levels:           0  
  Clock Path Skew:        1.057ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.962ns
    Source Clock Delay      (SCD):    1.905ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.556ns (routing 0.786ns, distribution 0.770ns)
  Clock Net Delay (Destination): 1.614ns (routing 0.896ns, distribution 0.718ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y100       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89456, routed)       1.556     1.905    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[10].trig_fifo_inst/gcc_rd_ptr/t_clk_i
    SLICE_X49Y172        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[10].trig_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X49Y172        FDCE (Prop_DFF_SLICEL_C_Q)
                                                      0.039     1.944 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[10].trig_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[2]/Q
                         net (fo=3, routed)           0.060     2.004    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[10].trig_fifo_inst/rd_gptr[2]
    SLICE_X49Y171        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[10].trig_fifo_inst/rd_gptr_cdc_reg[2]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=48236, routed)       1.311     1.458    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.163 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.329    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y133        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.348 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=4540, routed)        1.614     2.962    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[10].trig_fifo_inst/c_clk_i
    SLICE_X49Y171        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[10].trig_fifo_inst/rd_gptr_cdc_reg[2]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/QPER_TIME_READ.t_time_abs_cdc_reg[20]/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/QPER_TIME_READ.c_time_abs_r_reg[20]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.100ns  (logic 0.039ns (39.000%)  route 0.061ns (61.000%))
  Logic Levels:           0  
  Clock Path Skew:        1.049ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.954ns
    Source Clock Delay      (SCD):    1.905ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.556ns (routing 0.786ns, distribution 0.770ns)
  Clock Net Delay (Destination): 1.606ns (routing 0.896ns, distribution 0.710ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y100       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89456, routed)       1.556     1.905    d_1_i/qick_processor_0/inst/QPROC/t_clk_i
    SLICE_X56Y129        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPER_TIME_READ.t_time_abs_cdc_reg[20]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X56Y129        FDRE (Prop_EFF2_SLICEM_C_Q)
                                                      0.039     1.944 r  d_1_i/qick_processor_0/inst/QPROC/QPER_TIME_READ.t_time_abs_cdc_reg[20]/Q
                         net (fo=1, routed)           0.061     2.005    d_1_i/qick_processor_0/inst/QPROC/t_time_abs_cdc[20]
    SLICE_X55Y129        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPER_TIME_READ.c_time_abs_r_reg[20]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=48236, routed)       1.311     1.458    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.163 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.329    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y133        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.348 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=4540, routed)        1.606     2.954    d_1_i/qick_processor_0/inst/QPROC/c_clk_i
    SLICE_X55Y129        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPER_TIME_READ.c_time_abs_r_reg[20]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/QPER_TIME_READ.t_time_abs_cdc_reg[12]/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/QPER_TIME_READ.c_time_abs_r_reg[12]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.104ns  (logic 0.039ns (37.500%)  route 0.065ns (62.500%))
  Logic Levels:           0  
  Clock Path Skew:        1.055ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.957ns
    Source Clock Delay      (SCD):    1.903ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.554ns (routing 0.786ns, distribution 0.768ns)
  Clock Net Delay (Destination): 1.609ns (routing 0.896ns, distribution 0.713ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y100       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89456, routed)       1.554     1.903    d_1_i/qick_processor_0/inst/QPROC/t_clk_i
    SLICE_X55Y131        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPER_TIME_READ.t_time_abs_cdc_reg[12]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X55Y131        FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.039     1.942 r  d_1_i/qick_processor_0/inst/QPROC/QPER_TIME_READ.t_time_abs_cdc_reg[12]/Q
                         net (fo=1, routed)           0.065     2.007    d_1_i/qick_processor_0/inst/QPROC/t_time_abs_cdc[12]
    SLICE_X55Y131        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPER_TIME_READ.c_time_abs_r_reg[12]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=48236, routed)       1.311     1.458    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.163 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.329    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y133        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.348 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=4540, routed)        1.609     2.957    d_1_i/qick_processor_0/inst/QPROC/c_clk_i
    SLICE_X55Y131        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPER_TIME_READ.c_time_abs_r_reg[12]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[6]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/rd_gptr_cdc_reg[6]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.124ns  (logic 0.039ns (31.485%)  route 0.085ns (68.515%))
  Logic Levels:           0  
  Clock Path Skew:        1.068ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.961ns
    Source Clock Delay      (SCD):    1.893ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.544ns (routing 0.786ns, distribution 0.758ns)
  Clock Net Delay (Destination): 1.613ns (routing 0.896ns, distribution 0.717ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y100       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89456, routed)       1.544     1.893    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/gcc_rd_ptr/t_clk_i
    SLICE_X58Y199        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[6]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X58Y199        FDCE (Prop_HFF_SLICEL_C_Q)
                                                      0.039     1.932 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[6]/Q
                         net (fo=3, routed)           0.085     2.017    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/rd_gptr[6]
    SLICE_X59Y199        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/rd_gptr_cdc_reg[6]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=48236, routed)       1.311     1.458    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.163 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.329    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y133        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.348 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=4540, routed)        1.613     2.961    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/c_clk_i
    SLICE_X59Y199        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/rd_gptr_cdc_reg[6]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[1]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/rd_gptr_cdc_reg[1]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.110ns  (logic 0.039ns (35.557%)  route 0.071ns (64.443%))
  Logic Levels:           0  
  Clock Path Skew:        1.070ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.978ns
    Source Clock Delay      (SCD):    1.908ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.559ns (routing 0.786ns, distribution 0.773ns)
  Clock Net Delay (Destination): 1.630ns (routing 0.896ns, distribution 0.734ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y100       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89456, routed)       1.559     1.908    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/gcc_rd_ptr/t_clk_i
    SLICE_X52Y201        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X52Y201        FDCE (Prop_DFF_SLICEL_C_Q)
                                                      0.039     1.947 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[1]/Q
                         net (fo=3, routed)           0.071     2.018    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/rd_gptr[1]
    SLICE_X53Y201        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/rd_gptr_cdc_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=48236, routed)       1.311     1.458    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.163 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.329    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y133        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.348 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=4540, routed)        1.630     2.978    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/c_clk_i
    SLICE_X53Y201        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/rd_gptr_cdc_reg[1]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/QPER_TIME_READ.t_time_abs_cdc_reg[11]/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/QPER_TIME_READ.c_time_abs_r_reg[11]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.118ns  (logic 0.040ns (33.898%)  route 0.078ns (66.102%))
  Logic Levels:           0  
  Clock Path Skew:        1.055ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.955ns
    Source Clock Delay      (SCD):    1.900ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.551ns (routing 0.786ns, distribution 0.765ns)
  Clock Net Delay (Destination): 1.607ns (routing 0.896ns, distribution 0.711ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y100       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89456, routed)       1.551     1.900    d_1_i/qick_processor_0/inst/QPROC/t_clk_i
    SLICE_X55Y123        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPER_TIME_READ.t_time_abs_cdc_reg[11]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X55Y123        FDRE (Prop_AFF2_SLICEL_C_Q)
                                                      0.040     1.940 r  d_1_i/qick_processor_0/inst/QPROC/QPER_TIME_READ.t_time_abs_cdc_reg[11]/Q
                         net (fo=1, routed)           0.078     2.018    d_1_i/qick_processor_0/inst/QPROC/t_time_abs_cdc[11]
    SLICE_X55Y123        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPER_TIME_READ.c_time_abs_r_reg[11]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=48236, routed)       1.311     1.458    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.163 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.329    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y133        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.348 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=4540, routed)        1.607     2.955    d_1_i/qick_processor_0/inst/QPROC/c_clk_i
    SLICE_X55Y123        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPER_TIME_READ.c_time_abs_r_reg[11]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/QPER_TIME_READ.t_time_abs_cdc_reg[15]/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/QPER_TIME_READ.c_time_abs_r_reg[15]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.112ns  (logic 0.038ns (33.929%)  route 0.074ns (66.071%))
  Logic Levels:           0  
  Clock Path Skew:        1.048ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.954ns
    Source Clock Delay      (SCD):    1.906ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.557ns (routing 0.786ns, distribution 0.771ns)
  Clock Net Delay (Destination): 1.606ns (routing 0.896ns, distribution 0.710ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y100       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89456, routed)       1.557     1.906    d_1_i/qick_processor_0/inst/QPROC/t_clk_i
    SLICE_X54Y124        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPER_TIME_READ.t_time_abs_cdc_reg[15]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X54Y124        FDRE (Prop_AFF_SLICEM_C_Q)
                                                      0.038     1.944 r  d_1_i/qick_processor_0/inst/QPROC/QPER_TIME_READ.t_time_abs_cdc_reg[15]/Q
                         net (fo=1, routed)           0.074     2.018    d_1_i/qick_processor_0/inst/QPROC/t_time_abs_cdc[15]
    SLICE_X54Y124        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPER_TIME_READ.c_time_abs_r_reg[15]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=48236, routed)       1.311     1.458    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.163 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.329    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y133        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.348 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=4540, routed)        1.606     2.954    d_1_i/qick_processor_0/inst/QPROC/c_clk_i
    SLICE_X54Y124        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPER_TIME_READ.c_time_abs_r_reg[15]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/QPER_TIME_READ.t_time_abs_cdc_reg[18]/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/QPER_TIME_READ.c_time_abs_r_reg[18]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.112ns  (logic 0.038ns (33.929%)  route 0.074ns (66.071%))
  Logic Levels:           0  
  Clock Path Skew:        1.048ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.956ns
    Source Clock Delay      (SCD):    1.909ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.560ns (routing 0.786ns, distribution 0.774ns)
  Clock Net Delay (Destination): 1.608ns (routing 0.896ns, distribution 0.712ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y100       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89456, routed)       1.560     1.909    d_1_i/qick_processor_0/inst/QPROC/t_clk_i
    SLICE_X54Y131        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPER_TIME_READ.t_time_abs_cdc_reg[18]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X54Y131        FDRE (Prop_AFF_SLICEM_C_Q)
                                                      0.038     1.947 r  d_1_i/qick_processor_0/inst/QPROC/QPER_TIME_READ.t_time_abs_cdc_reg[18]/Q
                         net (fo=1, routed)           0.074     2.021    d_1_i/qick_processor_0/inst/QPROC/t_time_abs_cdc[18]
    SLICE_X54Y131        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPER_TIME_READ.c_time_abs_r_reg[18]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=48236, routed)       1.311     1.458    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.163 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.329    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y133        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.348 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=4540, routed)        1.608     2.956    d_1_i/qick_processor_0/inst/QPROC/c_clk_i
    SLICE_X54Y131        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPER_TIME_READ.c_time_abs_r_reg[18]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/QPER_TIME_READ.t_time_abs_cdc_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/QPER_TIME_READ.c_time_abs_r_reg[2]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.118ns  (logic 0.040ns (33.898%)  route 0.078ns (66.102%))
  Logic Levels:           0  
  Clock Path Skew:        1.055ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.957ns
    Source Clock Delay      (SCD):    1.903ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.554ns (routing 0.786ns, distribution 0.768ns)
  Clock Net Delay (Destination): 1.609ns (routing 0.896ns, distribution 0.713ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y100       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89456, routed)       1.554     1.903    d_1_i/qick_processor_0/inst/QPROC/t_clk_i
    SLICE_X55Y131        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPER_TIME_READ.t_time_abs_cdc_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X55Y131        FDRE (Prop_AFF2_SLICEL_C_Q)
                                                      0.040     1.943 r  d_1_i/qick_processor_0/inst/QPROC/QPER_TIME_READ.t_time_abs_cdc_reg[2]/Q
                         net (fo=1, routed)           0.078     2.021    d_1_i/qick_processor_0/inst/QPROC/t_time_abs_cdc[2]
    SLICE_X55Y131        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPER_TIME_READ.c_time_abs_r_reg[2]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=48236, routed)       1.311     1.458    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.163 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.329    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y133        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.348 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=4540, routed)        1.609     2.957    d_1_i/qick_processor_0/inst/QPROC/c_clk_i
    SLICE_X55Y131        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPER_TIME_READ.c_time_abs_r_reg[2]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[13].trig_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[6]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[13].trig_fifo_inst/rd_gptr_cdc_reg[6]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.100ns  (logic 0.039ns (39.182%)  route 0.061ns (60.818%))
  Logic Levels:           0  
  Clock Path Skew:        1.048ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.969ns
    Source Clock Delay      (SCD):    1.922ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.573ns (routing 0.786ns, distribution 0.787ns)
  Clock Net Delay (Destination): 1.621ns (routing 0.896ns, distribution 0.725ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y100       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89456, routed)       1.573     1.922    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[13].trig_fifo_inst/gcc_rd_ptr/t_clk_i
    SLICE_X58Y188        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[13].trig_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[6]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X58Y188        FDCE (Prop_FFF_SLICEL_C_Q)
                                                      0.039     1.961 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[13].trig_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[6]/Q
                         net (fo=3, routed)           0.061     2.021    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[13].trig_fifo_inst/rd_gptr[6]
    SLICE_X58Y187        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[13].trig_fifo_inst/rd_gptr_cdc_reg[6]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=48236, routed)       1.311     1.458    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.163 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.329    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y133        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.348 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=4540, routed)        1.621     2.969    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[13].trig_fifo_inst/c_clk_i
    SLICE_X58Y187        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[13].trig_fifo_inst/rd_gptr_cdc_reg[6]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  clk_pl_0
  To Clock:  clk_out1_d_1_clk_core_0

Max Delay           494 Endpoints
Min Delay           494 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_42_55/RAMD/CLK
                            (rising edge-triggered cell RAMD32 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[48]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.592ns  (logic 0.287ns (18.028%)  route 1.305ns (81.972%))
  Logic Levels:           0  
  Clock Path Skew:        2.715ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.273ns
    Source Clock Delay      (SCD):    2.558ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.153ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.111ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      2.332ns (routing 0.662ns, distribution 1.670ns)
  Clock Net Delay (Destination): 2.291ns (routing 1.325ns, distribution 0.966ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       2.332     2.558    d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_42_55/WCLK
    SLICE_X82Y63         RAMD32                                       r  d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_42_55/RAMD/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X82Y63         RAMD32 (Prop_D5LUT_SLICEM_CLK_O)
                                                      0.287     2.845 r  d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_42_55/RAMD/O
                         net (fo=1, routed)           1.305     4.150    d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0[48]
    SLICE_X81Y63         FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[48]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=48236, routed)       1.931     2.113    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.743 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.958    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y133        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.982 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=4540, routed)        2.291     5.273    d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X81Y63         FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[48]/C

Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_42_55/RAMG_D1/CLK
                            (rising edge-triggered cell RAMD32 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[55]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.293ns  (logic 0.295ns (22.815%)  route 0.998ns (77.185%))
  Logic Levels:           0  
  Clock Path Skew:        2.713ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.271ns
    Source Clock Delay      (SCD):    2.558ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.153ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.111ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      2.332ns (routing 0.662ns, distribution 1.670ns)
  Clock Net Delay (Destination): 2.289ns (routing 1.325ns, distribution 0.964ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       2.332     2.558    d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_42_55/WCLK
    SLICE_X82Y63         RAMD32                                       r  d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_42_55/RAMG_D1/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X82Y63         RAMD32 (Prop_G6LUT_SLICEM_CLK_O)
                                                      0.295     2.853 r  d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_42_55/RAMG_D1/O
                         net (fo=1, routed)           0.998     3.851    d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0[55]
    SLICE_X81Y63         FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[55]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=48236, routed)       1.931     2.113    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.743 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.958    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y133        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.982 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=4540, routed)        2.289     5.271    d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X81Y63         FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[55]/C

Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_42_55/RAME/CLK
                            (rising edge-triggered cell RAMD32 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[50]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.058ns  (logic 0.288ns (27.221%)  route 0.770ns (72.779%))
  Logic Levels:           0  
  Clock Path Skew:        2.710ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.268ns
    Source Clock Delay      (SCD):    2.558ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.153ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.111ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      2.332ns (routing 0.662ns, distribution 1.670ns)
  Clock Net Delay (Destination): 2.286ns (routing 1.325ns, distribution 0.961ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       2.332     2.558    d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_42_55/WCLK
    SLICE_X82Y63         RAMD32                                       r  d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_42_55/RAME/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X82Y63         RAMD32 (Prop_E5LUT_SLICEM_CLK_O)
                                                      0.288     2.846 r  d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_42_55/RAME/O
                         net (fo=1, routed)           0.770     3.616    d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0[50]
    SLICE_X81Y64         FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[50]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=48236, routed)       1.931     2.113    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.743 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.958    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y133        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.982 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=4540, routed)        2.286     5.268    d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X81Y64         FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[50]/C

Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41/RAMA_D1/CLK
                            (rising edge-triggered cell RAMD32 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[29]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.986ns  (logic 0.305ns (30.933%)  route 0.681ns (69.067%))
  Logic Levels:           0  
  Clock Path Skew:        2.715ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.273ns
    Source Clock Delay      (SCD):    2.558ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.153ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.111ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      2.332ns (routing 0.662ns, distribution 1.670ns)
  Clock Net Delay (Destination): 2.291ns (routing 1.325ns, distribution 0.966ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       2.332     2.558    d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41/WCLK
    SLICE_X82Y61         RAMD32                                       r  d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41/RAMA_D1/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X82Y61         RAMD32 (Prop_A6LUT_SLICEM_CLK_O)
                                                      0.305     2.863 r  d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41/RAMA_D1/O
                         net (fo=1, routed)           0.681     3.544    d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0[29]
    SLICE_X81Y63         FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[29]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=48236, routed)       1.931     2.113    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.743 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.958    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y133        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.982 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=4540, routed)        2.291     5.273    d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X81Y63         FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[29]/C

Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_56_63/RAMA_D1/CLK
                            (rising edge-triggered cell RAMD32 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[57]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.885ns  (logic 0.305ns (34.463%)  route 0.580ns (65.537%))
  Logic Levels:           0  
  Clock Path Skew:        2.729ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.287ns
    Source Clock Delay      (SCD):    2.558ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.153ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.111ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      2.332ns (routing 0.662ns, distribution 1.670ns)
  Clock Net Delay (Destination): 2.305ns (routing 1.325ns, distribution 0.980ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       2.332     2.558    d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_56_63/WCLK
    SLICE_X82Y62         RAMD32                                       r  d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_56_63/RAMA_D1/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X82Y62         RAMD32 (Prop_A6LUT_SLICEM_CLK_O)
                                                      0.305     2.863 r  d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_56_63/RAMA_D1/O
                         net (fo=1, routed)           0.580     3.443    d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0[57]
    SLICE_X83Y64         FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[57]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=48236, routed)       1.931     2.113    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.743 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.958    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y133        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.982 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=4540, routed)        2.305     5.287    d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X83Y64         FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[57]/C

Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41/RAMF_D1/CLK
                            (rising edge-triggered cell RAMD32 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[39]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.846ns  (logic 0.304ns (35.934%)  route 0.542ns (64.066%))
  Logic Levels:           0  
  Clock Path Skew:        2.730ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.288ns
    Source Clock Delay      (SCD):    2.558ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.153ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.111ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      2.332ns (routing 0.662ns, distribution 1.670ns)
  Clock Net Delay (Destination): 2.306ns (routing 1.325ns, distribution 0.981ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       2.332     2.558    d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41/WCLK
    SLICE_X82Y61         RAMD32                                       r  d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41/RAMF_D1/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X82Y61         RAMD32 (Prop_F6LUT_SLICEM_CLK_O)
                                                      0.304     2.862 r  d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41/RAMF_D1/O
                         net (fo=1, routed)           0.542     3.404    d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0[39]
    SLICE_X83Y64         FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[39]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=48236, routed)       1.931     2.113    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.743 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.958    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y133        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.982 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=4540, routed)        2.306     5.288    d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X83Y64         FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[39]/C

Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41/RAMF/CLK
                            (rising edge-triggered cell RAMD32 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[38]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.833ns  (logic 0.295ns (35.414%)  route 0.538ns (64.586%))
  Logic Levels:           0  
  Clock Path Skew:        2.730ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.288ns
    Source Clock Delay      (SCD):    2.558ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.153ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.111ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      2.332ns (routing 0.662ns, distribution 1.670ns)
  Clock Net Delay (Destination): 2.306ns (routing 1.325ns, distribution 0.981ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       2.332     2.558    d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41/WCLK
    SLICE_X82Y61         RAMD32                                       r  d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41/RAMF/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X82Y61         RAMD32 (Prop_F5LUT_SLICEM_CLK_O)
                                                      0.295     2.853 r  d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41/RAMF/O
                         net (fo=1, routed)           0.538     3.391    d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0[38]
    SLICE_X83Y64         FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[38]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=48236, routed)       1.931     2.113    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.743 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.958    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y133        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.982 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=4540, routed)        2.306     5.288    d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X83Y64         FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[38]/C

Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13/RAMD/CLK
                            (rising edge-triggered cell RAMD32 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[6]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.825ns  (logic 0.287ns (34.788%)  route 0.538ns (65.212%))
  Logic Levels:           0  
  Clock Path Skew:        2.724ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.287ns
    Source Clock Delay      (SCD):    2.563ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.153ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.111ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      2.337ns (routing 0.662ns, distribution 1.675ns)
  Clock Net Delay (Destination): 2.305ns (routing 1.325ns, distribution 0.980ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       2.337     2.563    d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13/WCLK
    SLICE_X83Y61         RAMD32                                       r  d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13/RAMD/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X83Y61         RAMD32 (Prop_D5LUT_SLICEM_CLK_O)
                                                      0.287     2.850 r  d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13/RAMD/O
                         net (fo=1, routed)           0.538     3.388    d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0[6]
    SLICE_X83Y64         FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[6]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=48236, routed)       1.931     2.113    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.743 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.958    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y133        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.982 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=4540, routed)        2.305     5.287    d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X83Y64         FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[6]/C

Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13/RAMD_D1/CLK
                            (rising edge-triggered cell RAMD32 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[7]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.798ns  (logic 0.301ns (37.719%)  route 0.497ns (62.281%))
  Logic Levels:           0  
  Clock Path Skew:        2.724ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.287ns
    Source Clock Delay      (SCD):    2.563ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.153ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.111ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      2.337ns (routing 0.662ns, distribution 1.675ns)
  Clock Net Delay (Destination): 2.305ns (routing 1.325ns, distribution 0.980ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       2.337     2.563    d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13/WCLK
    SLICE_X83Y61         RAMD32                                       r  d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13/RAMD_D1/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X83Y61         RAMD32 (Prop_D6LUT_SLICEM_CLK_O)
                                                      0.301     2.864 r  d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13/RAMD_D1/O
                         net (fo=1, routed)           0.497     3.361    d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0[7]
    SLICE_X83Y64         FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[7]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=48236, routed)       1.931     2.113    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.743 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.958    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y133        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.982 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=4540, routed)        2.305     5.287    d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X83Y64         FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[7]/C

Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41/RAMB/CLK
                            (rising edge-triggered cell RAMD32 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[30]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.011ns  (logic 0.292ns (28.882%)  route 0.719ns (71.118%))
  Logic Levels:           0  
  Clock Path Skew:        2.993ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.333ns
    Source Clock Delay      (SCD):    2.340ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.153ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.111ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      2.114ns (routing 0.662ns, distribution 1.452ns)
  Clock Net Delay (Destination): 2.351ns (routing 1.325ns, distribution 1.026ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       2.114     2.340    d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41/WCLK
    SLICE_X37Y164        RAMD32                                       r  d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41/RAMB/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X37Y164        RAMD32 (Prop_B5LUT_SLICEM_CLK_O)
                                                      0.292     2.632 r  d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41/RAMB/O
                         net (fo=1, routed)           0.719     3.351    d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0[30]
    SLICE_X38Y163        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[30]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=48236, routed)       1.931     2.113    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.743 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.958    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y133        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.982 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=4540, routed)        2.351     5.333    d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X38Y163        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[30]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_wr_rst_ic_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.091ns  (logic 0.039ns (42.941%)  route 0.052ns (57.059%))
  Logic Levels:           0  
  Clock Path Skew:        1.745ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.980ns
    Source Clock Delay      (SCD):    1.235ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.153ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.111ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.115ns (routing 0.359ns, distribution 0.756ns)
  Clock Net Delay (Destination): 1.632ns (routing 0.896ns, distribution 0.736ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.115     1.235    d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/wr_clk
    SLICE_X38Y173        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_wr_rst_ic_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X38Y173        FDRE (Prop_FFF_SLICEL_C_Q)
                                                      0.039     1.274 r  d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_wr_rst_ic_reg/Q
                         net (fo=2, routed)           0.052     1.326    d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst/src_rst
    SLICE_X38Y173        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=48236, routed)       1.311     1.458    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.163 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.329    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y133        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.348 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=4540, routed)        1.632     2.980    d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst/dest_clk
    SLICE_X38Y173        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.096ns  (logic 0.039ns (40.625%)  route 0.057ns (59.375%))
  Logic Levels:           0  
  Clock Path Skew:        1.645ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.913ns
    Source Clock Delay      (SCD):    1.268ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.153ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.111ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.148ns (routing 0.359ns, distribution 0.789ns)
  Clock Net Delay (Destination): 1.565ns (routing 0.896ns, distribution 0.669ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.148     1.268    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_clk
    SLICE_X57Y103        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X57Y103        FDRE (Prop_HFF2_SLICEL_C_Q)
                                                      0.039     1.307 r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[3]/Q
                         net (fo=1, routed)           0.057     1.364    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/async_path[3]
    SLICE_X57Y102        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=48236, routed)       1.311     1.458    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.163 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.329    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y133        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.348 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=4540, routed)        1.565     2.913    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_clk
    SLICE_X57Y102        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/C

Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.112ns  (logic 0.039ns (34.821%)  route 0.073ns (65.179%))
  Logic Levels:           0  
  Clock Path Skew:        1.741ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.012ns
    Source Clock Delay      (SCD):    1.271ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.153ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.111ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.151ns (routing 0.359ns, distribution 0.792ns)
  Clock Net Delay (Destination): 1.664ns (routing 0.896ns, distribution 0.768ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.151     1.271    d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_clk
    SLICE_X34Y166        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X34Y166        FDRE (Prop_GFF_SLICEM_C_Q)
                                                      0.039     1.310 r  d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[2]/Q
                         net (fo=1, routed)           0.073     1.383    d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/async_path[2]
    SLICE_X35Y166        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=48236, routed)       1.311     1.458    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.163 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.329    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y133        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.348 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=4540, routed)        1.664     3.012    d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_clk
    SLICE_X35Y166        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/C

Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[4]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][4]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.127ns  (logic 0.039ns (30.709%)  route 0.088ns (69.291%))
  Logic Levels:           0  
  Clock Path Skew:        1.746ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.014ns
    Source Clock Delay      (SCD):    1.268ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.153ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.111ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.148ns (routing 0.359ns, distribution 0.789ns)
  Clock Net Delay (Destination): 1.666ns (routing 0.896ns, distribution 0.770ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.148     1.268    d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_clk
    SLICE_X33Y164        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X33Y164        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.039     1.307 r  d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[4]/Q
                         net (fo=1, routed)           0.088     1.395    d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/async_path[4]
    SLICE_X34Y164        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][4]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=48236, routed)       1.311     1.458    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.163 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.329    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y133        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.348 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=4540, routed)        1.666     3.014    d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_clk
    SLICE_X34Y164        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][4]/C

Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.126ns  (logic 0.039ns (30.952%)  route 0.087ns (69.048%))
  Logic Levels:           0  
  Clock Path Skew:        1.740ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.011ns
    Source Clock Delay      (SCD):    1.271ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.153ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.111ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.151ns (routing 0.359ns, distribution 0.792ns)
  Clock Net Delay (Destination): 1.663ns (routing 0.896ns, distribution 0.767ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.151     1.271    d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_clk
    SLICE_X34Y166        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X34Y166        FDRE (Prop_HFF2_SLICEM_C_Q)
                                                      0.039     1.310 r  d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[1]/Q
                         net (fo=1, routed)           0.087     1.397    d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/async_path[1]
    SLICE_X33Y164        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=48236, routed)       1.311     1.458    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.163 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.329    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y133        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.348 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=4540, routed)        1.663     3.011    d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_clk
    SLICE_X33Y164        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/C

Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.098ns  (logic 0.038ns (38.775%)  route 0.060ns (61.224%))
  Logic Levels:           0  
  Clock Path Skew:        1.606ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.906ns
    Source Clock Delay      (SCD):    1.300ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.153ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.111ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.180ns (routing 0.359ns, distribution 0.821ns)
  Clock Net Delay (Destination): 1.558ns (routing 0.896ns, distribution 0.662ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.180     1.300    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_clk
    SLICE_X66Y121        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X66Y121        FDRE (Prop_CFF_SLICEM_C_Q)
                                                      0.038     1.338 r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[2]/Q
                         net (fo=1, routed)           0.060     1.398    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/async_path[2]
    SLICE_X65Y120        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=48236, routed)       1.311     1.458    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.163 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.329    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y133        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.348 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=4540, routed)        1.558     2.906    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_clk
    SLICE_X65Y120        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/C

Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.138ns  (logic 0.041ns (29.710%)  route 0.097ns (70.290%))
  Logic Levels:           0  
  Clock Path Skew:        1.644ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.909ns
    Source Clock Delay      (SCD):    1.265ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.153ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.111ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.145ns (routing 0.359ns, distribution 0.786ns)
  Clock Net Delay (Destination): 1.561ns (routing 0.896ns, distribution 0.665ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.145     1.265    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_clk
    SLICE_X59Y100        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X59Y100        FDRE (Prop_DFF2_SLICEL_C_Q)
                                                      0.041     1.306 r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[1]/Q
                         net (fo=1, routed)           0.097     1.403    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/async_path[1]
    SLICE_X58Y99         FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=48236, routed)       1.311     1.458    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.163 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.329    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y133        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.348 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=4540, routed)        1.561     2.909    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_clk
    SLICE_X58Y99         FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/C

Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_42_55/RAMG_D1/CLK
                            (rising edge-triggered cell RAMD32 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[55]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.157ns  (logic 0.105ns (66.879%)  route 0.052ns (33.121%))
  Logic Levels:           0  
  Clock Path Skew:        1.724ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.977ns
    Source Clock Delay      (SCD):    1.253ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.153ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.111ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.133ns (routing 0.359ns, distribution 0.774ns)
  Clock Net Delay (Destination): 1.629ns (routing 0.896ns, distribution 0.733ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.133     1.253    d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_42_55/WCLK
    SLICE_X39Y166        RAMD32                                       r  d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_42_55/RAMG_D1/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X39Y166        RAMD32 (Prop_G6LUT_SLICEM_CLK_O)
                                                      0.105     1.358 r  d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_42_55/RAMG_D1/O
                         net (fo=1, routed)           0.052     1.410    d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0[55]
    SLICE_X40Y166        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[55]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=48236, routed)       1.311     1.458    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.163 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.329    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y133        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.348 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=4540, routed)        1.629     2.977    d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X40Y166        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[55]/C

Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.148ns  (logic 0.039ns (26.351%)  route 0.109ns (73.649%))
  Logic Levels:           0  
  Clock Path Skew:        1.740ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.011ns
    Source Clock Delay      (SCD):    1.271ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.153ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.111ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.151ns (routing 0.359ns, distribution 0.792ns)
  Clock Net Delay (Destination): 1.663ns (routing 0.896ns, distribution 0.767ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.151     1.271    d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_clk
    SLICE_X34Y166        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X34Y166        FDRE (Prop_GFF2_SLICEM_C_Q)
                                                      0.039     1.310 r  d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[3]/Q
                         net (fo=1, routed)           0.109     1.419    d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/async_path[3]
    SLICE_X33Y164        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=48236, routed)       1.311     1.458    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.163 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.329    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y133        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.348 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=4540, routed)        1.663     3.011    d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_clk
    SLICE_X33Y164        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/C

Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.154ns  (logic 0.039ns (25.325%)  route 0.115ns (74.675%))
  Logic Levels:           0  
  Clock Path Skew:        1.652ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.919ns
    Source Clock Delay      (SCD):    1.268ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.153ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.111ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.148ns (routing 0.359ns, distribution 0.789ns)
  Clock Net Delay (Destination): 1.571ns (routing 0.896ns, distribution 0.675ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.148     1.268    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_clk
    SLICE_X57Y103        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X57Y103        FDRE (Prop_HFF_SLICEL_C_Q)
                                                      0.039     1.307 r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[2]/Q
                         net (fo=1, routed)           0.115     1.422    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/async_path[2]
    SLICE_X58Y103        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=48236, routed)       1.311     1.458    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.163 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.329    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y133        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.348 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=4540, routed)        1.571     2.919    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_clk
    SLICE_X58Y103        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  
  To Clock:  clk_pl_0

Max Delay           107 Endpoints
Min Delay           107 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/EMIOGPIOO[95]
                            (internal pin)
  Destination:            d_1_i/rst_100/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.473ns  (logic 0.050ns (1.440%)  route 3.423ns (98.560%))
  Logic Levels:           1  (LUT1=1)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.141ns (routing 0.599ns, distribution 1.542ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    PS8_X0Y0             PS8                          0.000     0.000 f  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/EMIOGPIOO[95]
                         net (fo=5, routed)           3.138     3.138    d_1_i/rst_100/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/ext_reset_in
    SLICE_X102Y63        LUT1 (Prop_A6LUT_SLICEL_I0_O)
                                                      0.050     3.188 r  d_1_i/rst_100/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1/O
                         net (fo=1, routed)           0.285     3.473    d_1_i/rst_100/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/exr_d1
    SLICE_X105Y61        FDRE                                         r  d_1_i/rst_100/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       2.141     2.323    d_1_i/rst_100/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/slowest_sync_clk
    SLICE_X105Y61        FDRE                                         r  d_1_i/rst_100/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_DAC0[15]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac10_fifo_irq/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.125ns  (logic 0.000ns (0.000%)  route 3.125ns (100.000%))
  Logic Levels:           0  
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.121ns (routing 0.599ns, distribution 1.522ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_DAC0[15]
                         net (fo=1, routed)           3.125     3.125    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac10_fifo_irq/src_in
    SLICE_X104Y140       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac10_fifo_irq/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       2.121     2.303    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac10_fifo_irq/dest_clk
    SLICE_X104Y140       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac10_fifo_irq/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_DAC3[14]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac13_data_irq/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.528ns  (logic 0.000ns (0.000%)  route 2.528ns (100.000%))
  Logic Levels:           0  
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.133ns (routing 0.599ns, distribution 1.534ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_DAC3[14]
                         net (fo=1, routed)           2.528     2.528    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac13_data_irq/src_in
    SLICE_X106Y132       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac13_data_irq/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       2.133     2.315    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac13_data_irq/dest_clk
    SLICE_X106Y132       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac13_data_irq/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_DAC2[14]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac12_data_irq/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.411ns  (logic 0.000ns (0.000%)  route 2.411ns (100.000%))
  Logic Levels:           0  
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.131ns (routing 0.599ns, distribution 1.532ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_DAC2[14]
                         net (fo=1, routed)           2.411     2.411    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac12_data_irq/src_in
    SLICE_X105Y135       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac12_data_irq/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       2.131     2.313    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac12_data_irq/dest_clk
    SLICE_X105Y135       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac12_data_irq/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_DAC3[15]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac13_fifo_irq/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.275ns  (logic 0.000ns (0.000%)  route 2.275ns (100.000%))
  Logic Levels:           0  
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.124ns (routing 0.599ns, distribution 1.525ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_DAC3[15]
                         net (fo=1, routed)           2.275     2.275    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac13_fifo_irq/src_in
    SLICE_X106Y142       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac13_fifo_irq/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       2.124     2.306    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac13_fifo_irq/dest_clk
    SLICE_X106Y142       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac13_fifo_irq/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_DAC2[15]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac12_fifo_irq/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.189ns  (logic 0.000ns (0.000%)  route 2.189ns (100.000%))
  Logic Levels:           0  
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.110ns (routing 0.599ns, distribution 1.511ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_DAC2[15]
                         net (fo=1, routed)           2.189     2.189    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac12_fifo_irq/src_in
    SLICE_X105Y146       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac12_fifo_irq/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       2.110     2.292    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac12_fifo_irq/dest_clk
    SLICE_X105Y146       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac12_fifo_irq/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_DAC1[15]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac11_fifo_irq/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.123ns  (logic 0.000ns (0.000%)  route 2.123ns (100.000%))
  Logic Levels:           0  
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.129ns (routing 0.599ns, distribution 1.530ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_DAC1[15]
                         net (fo=1, routed)           2.123     2.123    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac11_fifo_irq/src_in
    SLICE_X106Y137       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac11_fifo_irq/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       2.129     2.311    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac11_fifo_irq/dest_clk
    SLICE_X106Y137       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac11_fifo_irq/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/STATUS_DAC3[15]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac03_fifo_irq/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.081ns  (logic 0.000ns (0.000%)  route 2.081ns (100.000%))
  Logic Levels:           0  
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.136ns (routing 0.599ns, distribution 1.537ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/STATUS_DAC3[15]
                         net (fo=1, routed)           2.081     2.081    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac03_fifo_irq/src_in
    SLICE_X104Y133       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac03_fifo_irq/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       2.136     2.318    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac03_fifo_irq/dest_clk
    SLICE_X104Y133       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac03_fifo_irq/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/STATUS_DAC3[14]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac03_data_irq/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.049ns  (logic 0.000ns (0.000%)  route 2.049ns (100.000%))
  Logic Levels:           0  
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.127ns (routing 0.599ns, distribution 1.528ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/STATUS_DAC3[14]
                         net (fo=1, routed)           2.049     2.049    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac03_data_irq/src_in
    SLICE_X105Y139       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac03_data_irq/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       2.127     2.309    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac03_data_irq/dest_clk
    SLICE_X105Y139       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac03_data_irq/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_DAC0[14]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac10_data_irq/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.039ns  (logic 0.000ns (0.000%)  route 2.039ns (100.000%))
  Logic Levels:           0  
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.108ns (routing 0.599ns, distribution 1.509ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_DAC0[14]
                         net (fo=1, routed)           2.039     2.039    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac10_data_irq/src_in
    SLICE_X105Y147       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac10_data_irq/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       2.108     2.290    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac10_data_irq/dest_clk
    SLICE_X105Y147       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac10_data_irq/syncstages_ff_reg[0]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_ADC0[3]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc20_over_range/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.130ns  (logic 0.000ns (0.000%)  route 0.130ns (100.000%))
  Logic Levels:           0  
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.496ns (routing 0.405ns, distribution 1.091ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y2           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_ADC0[3]
                         net (fo=1, routed)           0.130     0.130    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc20_over_range/src_in
    SLICE_X117Y122       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc20_over_range/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.496     1.643    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc20_over_range/dest_clk
    SLICE_X117Y122       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc20_over_range/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_ADC1[0]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/por_state_machine_i/por_fsm_adc2/cdc_adc1_status_i/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.152ns  (logic 0.000ns (0.000%)  route 0.152ns (100.000%))
  Logic Levels:           0  
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.490ns (routing 0.405ns, distribution 1.085ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y2           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_ADC1[0]
                         net (fo=1, routed)           0.152     0.152    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/por_state_machine_i/por_fsm_adc2/cdc_adc1_status_i/src_in
    SLICE_X117Y132       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/por_state_machine_i/por_fsm_adc2/cdc_adc1_status_i/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.490     1.637    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/por_state_machine_i/por_fsm_adc2/cdc_adc1_status_i/dest_clk
    SLICE_X117Y132       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/por_state_machine_i/por_fsm_adc2/cdc_adc1_status_i/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_ADC0[14]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc20_data_irq/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.197ns  (logic 0.000ns (0.000%)  route 0.197ns (100.000%))
  Logic Levels:           0  
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.506ns (routing 0.405ns, distribution 1.101ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y2           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_ADC0[14]
                         net (fo=1, routed)           0.197     0.197    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc20_data_irq/src_in
    SLICE_X115Y128       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc20_data_irq/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.506     1.653    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc20_data_irq/dest_clk
    SLICE_X115Y128       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc20_data_irq/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_ADC2[0]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/por_state_machine_i/por_fsm_adc2/cdc_adc2_status_i/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.225ns  (logic 0.000ns (0.000%)  route 0.225ns (100.000%))
  Logic Levels:           0  
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.491ns (routing 0.405ns, distribution 1.086ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y2           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_ADC2[0]
                         net (fo=1, routed)           0.225     0.225    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/por_state_machine_i/por_fsm_adc2/cdc_adc2_status_i/src_in
    SLICE_X118Y152       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/por_state_machine_i/por_fsm_adc2/cdc_adc2_status_i/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.491     1.638    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/por_state_machine_i/por_fsm_adc2/cdc_adc2_status_i/dest_clk
    SLICE_X118Y152       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/por_state_machine_i/por_fsm_adc2/cdc_adc2_status_i/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_ADC1[3]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc21_over_range/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.225ns  (logic 0.000ns (0.000%)  route 0.225ns (100.000%))
  Logic Levels:           0  
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.492ns (routing 0.405ns, distribution 1.087ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y2           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_ADC1[3]
                         net (fo=1, routed)           0.225     0.225    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc21_over_range/src_in
    SLICE_X114Y134       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc21_over_range/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.492     1.639    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc21_over_range/dest_clk
    SLICE_X114Y134       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc21_over_range/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_ADC3[3]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc13_over_range/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.241ns  (logic 0.000ns (0.000%)  route 0.241ns (100.000%))
  Logic Levels:           0  
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.505ns (routing 0.405ns, distribution 1.100ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_ADC3[3]
                         net (fo=1, routed)           0.241     0.241    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc13_over_range/src_in
    SLICE_X108Y111       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc13_over_range/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.505     1.652    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc13_over_range/dest_clk
    SLICE_X108Y111       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc13_over_range/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_ADC3[0]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/por_state_machine_i/por_fsm_adc2/cdc_adc3_status_i/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.245ns  (logic 0.000ns (0.000%)  route 0.245ns (100.000%))
  Logic Levels:           0  
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.484ns (routing 0.405ns, distribution 1.079ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y2           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_ADC3[0]
                         net (fo=1, routed)           0.245     0.245    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/por_state_machine_i/por_fsm_adc2/cdc_adc3_status_i/src_in
    SLICE_X117Y161       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/por_state_machine_i/por_fsm_adc2/cdc_adc3_status_i/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.484     1.631    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/por_state_machine_i/por_fsm_adc2/cdc_adc3_status_i/dest_clk
    SLICE_X117Y161       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/por_state_machine_i/por_fsm_adc2/cdc_adc3_status_i/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_ADC2[14]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc12_data_irq/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.245ns  (logic 0.000ns (0.000%)  route 0.245ns (100.000%))
  Logic Levels:           0  
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.520ns (routing 0.405ns, distribution 1.115ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_ADC2[14]
                         net (fo=1, routed)           0.245     0.245    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc12_data_irq/src_in
    SLICE_X113Y106       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc12_data_irq/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.520     1.667    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc12_data_irq/dest_clk
    SLICE_X113Y106       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc12_data_irq/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_COMMON[1]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_adc2_supplies_up_i/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.247ns  (logic 0.000ns (0.000%)  route 0.247ns (100.000%))
  Logic Levels:           0  
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.478ns (routing 0.405ns, distribution 1.073ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y2           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_COMMON[1]
                         net (fo=2, routed)           0.247     0.247    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_adc2_supplies_up_i/src_in
    SLICE_X108Y139       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_adc2_supplies_up_i/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.478     1.625    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_adc2_supplies_up_i/dest_clk
    SLICE_X108Y139       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_adc2_supplies_up_i/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_ADC0[15]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc20_fifo_irq/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.271ns  (logic 0.000ns (0.000%)  route 0.271ns (100.000%))
  Logic Levels:           0  
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.507ns (routing 0.405ns, distribution 1.102ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y2           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_ADC0[15]
                         net (fo=1, routed)           0.271     0.271    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc20_fifo_irq/src_in
    SLICE_X113Y122       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc20_fifo_irq/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.507     1.654    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc20_fifo_irq/dest_clk
    SLICE_X113Y122       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc20_fifo_irq/syncstages_ff_reg[0]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  RFADC0_CLK
  To Clock:  clk_pl_0

Max Delay             8 Endpoints
Min Delay             8 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.192ns  (logic 1.154ns (36.153%)  route 2.038ns (63.847%))
  Logic Levels:           4  (LUT6=4)
  Clock Path Skew:        2.326ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.326ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.144ns (routing 0.599ns, distribution 1.545ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[14])
                                                      0.698     0.698 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/STATUS_COMMON[14]
                         net (fo=1, routed)           1.253     1.951    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/STATUS_COMMON[14]
    SLICE_X106Y99        LUT6 (Prop_H6LUT_SLICEL_I2_O)
                                                      0.150     2.101 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_35/O
                         net (fo=1, routed)           0.205     2.306    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_35_n_0
    SLICE_X105Y99        LUT6 (Prop_F6LUT_SLICEL_I5_O)
                                                      0.148     2.454 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_17/O
                         net (fo=1, routed)           0.150     2.604    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_17_n_0
    SLICE_X105Y100       LUT6 (Prop_C6LUT_SLICEL_I3_O)
                                                      0.035     2.639 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_5/O
                         net (fo=1, routed)           0.380     3.019    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_5_n_0
    SLICE_X106Y110       LUT6 (Prop_C6LUT_SLICEL_I3_O)
                                                      0.123     3.142 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_1/O
                         net (fo=1, routed)           0.050     3.192    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_70
    SLICE_X106Y110       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       2.144     2.326    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X106Y110       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.815ns  (logic 0.823ns (29.236%)  route 1.992ns (70.764%))
  Logic Levels:           4  (LUT6=4)
  Clock Path Skew:        2.322ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.322ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.140ns (routing 0.599ns, distribution 1.541ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[15])
                                                      0.525     0.525 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/STATUS_COMMON[15]
                         net (fo=1, routed)           1.156     1.681    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/STATUS_COMMON[15]
    SLICE_X106Y99        LUT6 (Prop_G6LUT_SLICEL_I2_O)
                                                      0.050     1.731 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_36/O
                         net (fo=1, routed)           0.554     2.285    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_36_n_0
    SLICE_X105Y100       LUT6 (Prop_H6LUT_SLICEL_I5_O)
                                                      0.124     2.409 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_15/O
                         net (fo=1, routed)           0.039     2.448    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_15_n_0
    SLICE_X105Y100       LUT6 (Prop_G6LUT_SLICEL_I1_O)
                                                      0.035     2.483 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_4/O
                         net (fo=1, routed)           0.194     2.677    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_4_n_0
    SLICE_X106Y104       LUT6 (Prop_D6LUT_SLICEL_I2_O)
                                                      0.089     2.766 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_1/O
                         net (fo=1, routed)           0.049     2.815    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_69
    SLICE_X106Y104       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       2.140     2.322    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X106Y104       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.436ns  (logic 0.820ns (33.662%)  route 1.616ns (66.338%))
  Logic Levels:           3  (LUT6=3)
  Clock Path Skew:        2.348ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.348ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.166ns (routing 0.599ns, distribution 1.567ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[12])
                                                      0.611     0.611 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/STATUS_COMMON[12]
                         net (fo=1, routed)           1.374     1.985    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/STATUS_COMMON[12]
    SLICE_X108Y103       LUT6 (Prop_H6LUT_SLICEL_I0_O)
                                                      0.036     2.021 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_13/O
                         net (fo=1, routed)           0.038     2.059    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_13_n_0
    SLICE_X108Y103       LUT6 (Prop_G6LUT_SLICEL_I4_O)
                                                      0.050     2.109 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_4/O
                         net (fo=1, routed)           0.154     2.263    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_4_n_0
    SLICE_X108Y107       LUT6 (Prop_C6LUT_SLICEL_I2_O)
                                                      0.123     2.386 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_1/O
                         net (fo=1, routed)           0.050     2.436    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_72
    SLICE_X108Y107       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       2.166     2.348    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X108Y107       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.401ns  (logic 0.972ns (40.483%)  route 1.429ns (59.517%))
  Logic Levels:           3  (LUT6=3)
  Clock Path Skew:        2.350ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.350ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.168ns (routing 0.599ns, distribution 1.569ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[8])
                                                      0.788     0.788 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/STATUS_COMMON[8]
                         net (fo=1, routed)           1.137     1.925    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/STATUS_COMMON[8]
    SLICE_X108Y102       LUT6 (Prop_B6LUT_SLICEL_I3_O)
                                                      0.098     2.023 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_13/O
                         net (fo=1, routed)           0.041     2.064    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_13_n_0
    SLICE_X108Y102       LUT6 (Prop_A6LUT_SLICEL_I2_O)
                                                      0.050     2.114 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_3/O
                         net (fo=1, routed)           0.202     2.316    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_3_n_0
    SLICE_X108Y109       LUT6 (Prop_B6LUT_SLICEL_I1_O)
                                                      0.036     2.352 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_1/O
                         net (fo=1, routed)           0.049     2.401    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_76
    SLICE_X108Y109       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       2.168     2.350    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X108Y109       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.357ns  (logic 0.814ns (34.535%)  route 1.543ns (65.465%))
  Logic Levels:           3  (LUT6=3)
  Clock Path Skew:        2.352ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.352ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.170ns (routing 0.599ns, distribution 1.571ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[11])
                                                      0.588     0.588 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/STATUS_COMMON[11]
                         net (fo=1, routed)           1.040     1.628    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/STATUS_COMMON[11]
    SLICE_X109Y98        LUT6 (Prop_G6LUT_SLICEM_I1_O)
                                                      0.037     1.665 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_9/O
                         net (fo=1, routed)           0.185     1.850    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_9_n_0
    SLICE_X108Y101       LUT6 (Prop_H6LUT_SLICEL_I2_O)
                                                      0.090     1.940 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_2/O
                         net (fo=1, routed)           0.267     2.207    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_2_n_0
    SLICE_X108Y109       LUT6 (Prop_H6LUT_SLICEL_I0_O)
                                                      0.099     2.306 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_1/O
                         net (fo=1, routed)           0.051     2.357    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_73
    SLICE_X108Y109       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       2.170     2.352    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X108Y109       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.313ns  (logic 0.797ns (34.457%)  route 1.516ns (65.543%))
  Logic Levels:           3  (LUT6=3)
  Clock Path Skew:        2.350ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.350ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.168ns (routing 0.599ns, distribution 1.569ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[9])
                                                      0.532     0.532 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/STATUS_COMMON[9]
                         net (fo=1, routed)           0.934     1.466    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/STATUS_COMMON[9]
    SLICE_X109Y97        LUT6 (Prop_E6LUT_SLICEM_I0_O)
                                                      0.091     1.557 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_12/O
                         net (fo=1, routed)           0.266     1.823    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_12_n_0
    SLICE_X108Y102       LUT6 (Prop_G6LUT_SLICEL_I2_O)
                                                      0.050     1.873 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_3/O
                         net (fo=1, routed)           0.268     2.141    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_3_n_0
    SLICE_X108Y109       LUT6 (Prop_A6LUT_SLICEL_I1_O)
                                                      0.124     2.265 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_1/O
                         net (fo=1, routed)           0.048     2.313    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_75
    SLICE_X108Y109       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       2.168     2.350    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X108Y109       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.251ns  (logic 0.756ns (33.585%)  route 1.495ns (66.415%))
  Logic Levels:           3  (LUT5=1 LUT6=2)
  Clock Path Skew:        2.348ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.348ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.166ns (routing 0.599ns, distribution 1.567ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[10])
                                                      0.536     0.536 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/STATUS_COMMON[10]
                         net (fo=1, routed)           0.984     1.520    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/STATUS_COMMON[10]
    SLICE_X108Y102       LUT6 (Prop_C6LUT_SLICEL_I0_O)
                                                      0.088     1.608 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_7/O
                         net (fo=1, routed)           0.211     1.819    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_7_n_0
    SLICE_X111Y102       LUT6 (Prop_H6LUT_SLICEL_I3_O)
                                                      0.036     1.855 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_2/O
                         net (fo=1, routed)           0.285     2.140    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_2_n_0
    SLICE_X108Y107       LUT5 (Prop_D5LUT_SLICEL_I0_O)
                                                      0.096     2.236 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_1/O
                         net (fo=1, routed)           0.015     2.251    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_74
    SLICE_X108Y107       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       2.166     2.348    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X108Y107       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.098ns  (logic 0.941ns (44.852%)  route 1.157ns (55.148%))
  Logic Levels:           3  (LUT6=3)
  Clock Path Skew:        2.348ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.348ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.166ns (routing 0.599ns, distribution 1.567ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[13])
                                                      0.771     0.771 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/STATUS_COMMON[13]
                         net (fo=1, routed)           0.879     1.650    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/STATUS_COMMON[13]
    SLICE_X108Y100       LUT6 (Prop_H6LUT_SLICEL_I0_O)
                                                      0.036     1.686 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_17/O
                         net (fo=1, routed)           0.133     1.819    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_17_n_0
    SLICE_X108Y103       LUT6 (Prop_F6LUT_SLICEL_I1_O)
                                                      0.035     1.854 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_4/O
                         net (fo=1, routed)           0.096     1.950    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_4_n_0
    SLICE_X108Y106       LUT6 (Prop_D6LUT_SLICEL_I2_O)
                                                      0.099     2.049 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_1/O
                         net (fo=1, routed)           0.049     2.098    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_71
    SLICE_X108Y106       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       2.166     2.348    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X108Y106       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.885ns  (logic 0.311ns (35.141%)  route 0.574ns (64.859%))
  Logic Levels:           3  (LUT6=3)
  Clock Path Skew:        1.647ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.647ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.500ns (routing 0.405ns, distribution 1.095ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[13])
                                                      0.241     0.241 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/STATUS_COMMON[13]
                         net (fo=1, routed)           0.436     0.677    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/STATUS_COMMON[13]
    SLICE_X108Y100       LUT6 (Prop_H6LUT_SLICEL_I0_O)
                                                      0.015     0.692 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_17/O
                         net (fo=1, routed)           0.071     0.763    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_17_n_0
    SLICE_X108Y103       LUT6 (Prop_F6LUT_SLICEL_I1_O)
                                                      0.014     0.777 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_4/O
                         net (fo=1, routed)           0.051     0.828    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_4_n_0
    SLICE_X108Y106       LUT6 (Prop_D6LUT_SLICEL_I2_O)
                                                      0.041     0.869 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_1/O
                         net (fo=1, routed)           0.016     0.885    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_71
    SLICE_X108Y106       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.500     1.647    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X108Y106       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.023ns  (logic 0.315ns (30.792%)  route 0.708ns (69.208%))
  Logic Levels:           3  (LUT6=3)
  Clock Path Skew:        1.648ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.648ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.501ns (routing 0.405ns, distribution 1.096ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[8])
                                                      0.237     0.237 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/STATUS_COMMON[8]
                         net (fo=1, routed)           0.563     0.800    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/STATUS_COMMON[8]
    SLICE_X108Y102       LUT6 (Prop_B6LUT_SLICEL_I3_O)
                                                      0.041     0.841 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_13/O
                         net (fo=1, routed)           0.023     0.864    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_13_n_0
    SLICE_X108Y102       LUT6 (Prop_A6LUT_SLICEL_I2_O)
                                                      0.022     0.886 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_3/O
                         net (fo=1, routed)           0.107     0.993    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_3_n_0
    SLICE_X108Y109       LUT6 (Prop_B6LUT_SLICEL_I1_O)
                                                      0.015     1.008 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_1/O
                         net (fo=1, routed)           0.015     1.023    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_76
    SLICE_X108Y109       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.501     1.648    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X108Y109       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.058ns  (logic 0.310ns (29.301%)  route 0.748ns (70.699%))
  Logic Levels:           3  (LUT5=1 LUT6=2)
  Clock Path Skew:        1.647ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.647ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.500ns (routing 0.405ns, distribution 1.095ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[10])
                                                      0.227     0.227 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/STATUS_COMMON[10]
                         net (fo=1, routed)           0.490     0.717    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/STATUS_COMMON[10]
    SLICE_X108Y102       LUT6 (Prop_C6LUT_SLICEL_I0_O)
                                                      0.035     0.752 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_7/O
                         net (fo=1, routed)           0.106     0.858    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_7_n_0
    SLICE_X111Y102       LUT6 (Prop_H6LUT_SLICEL_I3_O)
                                                      0.015     0.873 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_2/O
                         net (fo=1, routed)           0.146     1.019    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_2_n_0
    SLICE_X108Y107       LUT5 (Prop_D5LUT_SLICEL_I0_O)
                                                      0.033     1.052 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_1/O
                         net (fo=1, routed)           0.006     1.058    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_74
    SLICE_X108Y107       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.500     1.647    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X108Y107       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.081ns  (logic 0.335ns (30.990%)  route 0.746ns (69.010%))
  Logic Levels:           3  (LUT6=3)
  Clock Path Skew:        1.648ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.648ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.501ns (routing 0.405ns, distribution 1.096ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[9])
                                                      0.228     0.228 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/STATUS_COMMON[9]
                         net (fo=1, routed)           0.461     0.689    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/STATUS_COMMON[9]
    SLICE_X109Y97        LUT6 (Prop_E6LUT_SLICEM_I0_O)
                                                      0.035     0.724 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_12/O
                         net (fo=1, routed)           0.133     0.857    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_12_n_0
    SLICE_X108Y102       LUT6 (Prop_G6LUT_SLICEL_I2_O)
                                                      0.022     0.879 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_3/O
                         net (fo=1, routed)           0.136     1.015    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_3_n_0
    SLICE_X108Y109       LUT6 (Prop_A6LUT_SLICEL_I1_O)
                                                      0.050     1.065 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_1/O
                         net (fo=1, routed)           0.016     1.081    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_75
    SLICE_X108Y109       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.501     1.648    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X108Y109       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.121ns  (logic 0.355ns (31.668%)  route 0.766ns (68.332%))
  Logic Levels:           3  (LUT6=3)
  Clock Path Skew:        1.652ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.652ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.505ns (routing 0.405ns, distribution 1.100ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[11])
                                                      0.265     0.265 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/STATUS_COMMON[11]
                         net (fo=1, routed)           0.516     0.781    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/STATUS_COMMON[11]
    SLICE_X109Y98        LUT6 (Prop_G6LUT_SLICEM_I1_O)
                                                      0.014     0.795 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_9/O
                         net (fo=1, routed)           0.097     0.892    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_9_n_0
    SLICE_X108Y101       LUT6 (Prop_H6LUT_SLICEL_I2_O)
                                                      0.035     0.927 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_2/O
                         net (fo=1, routed)           0.136     1.063    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_2_n_0
    SLICE_X108Y109       LUT6 (Prop_H6LUT_SLICEL_I0_O)
                                                      0.041     1.104 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_1/O
                         net (fo=1, routed)           0.017     1.121    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_73
    SLICE_X108Y109       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.505     1.652    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X108Y109       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.173ns  (logic 0.361ns (30.776%)  route 0.812ns (69.224%))
  Logic Levels:           3  (LUT6=3)
  Clock Path Skew:        1.647ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.647ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.500ns (routing 0.405ns, distribution 1.095ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[12])
                                                      0.274     0.274 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/STATUS_COMMON[12]
                         net (fo=1, routed)           0.693     0.967    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/STATUS_COMMON[12]
    SLICE_X108Y103       LUT6 (Prop_H6LUT_SLICEL_I0_O)
                                                      0.015     0.982 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_13/O
                         net (fo=1, routed)           0.021     1.003    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_13_n_0
    SLICE_X108Y103       LUT6 (Prop_G6LUT_SLICEL_I4_O)
                                                      0.022     1.025 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_4/O
                         net (fo=1, routed)           0.081     1.106    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_4_n_0
    SLICE_X108Y107       LUT6 (Prop_C6LUT_SLICEL_I2_O)
                                                      0.050     1.156 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_1/O
                         net (fo=1, routed)           0.017     1.173    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_72
    SLICE_X108Y107       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.500     1.647    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X108Y107       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.376ns  (logic 0.371ns (26.962%)  route 1.005ns (73.038%))
  Logic Levels:           4  (LUT6=4)
  Clock Path Skew:        1.633ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.633ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.486ns (routing 0.405ns, distribution 1.081ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[15])
                                                      0.250     0.250 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/STATUS_COMMON[15]
                         net (fo=1, routed)           0.579     0.829    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/STATUS_COMMON[15]
    SLICE_X106Y99        LUT6 (Prop_G6LUT_SLICEL_I2_O)
                                                      0.022     0.851 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_36/O
                         net (fo=1, routed)           0.287     1.138    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_36_n_0
    SLICE_X105Y100       LUT6 (Prop_H6LUT_SLICEL_I5_O)
                                                      0.050     1.188 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_15/O
                         net (fo=1, routed)           0.021     1.209    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_15_n_0
    SLICE_X105Y100       LUT6 (Prop_G6LUT_SLICEL_I1_O)
                                                      0.014     1.223 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_4/O
                         net (fo=1, routed)           0.102     1.325    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_4_n_0
    SLICE_X106Y104       LUT6 (Prop_D6LUT_SLICEL_I2_O)
                                                      0.035     1.360 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_1/O
                         net (fo=1, routed)           0.016     1.376    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_69
    SLICE_X106Y104       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.486     1.633    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X106Y104       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.493ns  (logic 0.468ns (31.346%)  route 1.025ns (68.654%))
  Logic Levels:           4  (LUT6=4)
  Clock Path Skew:        1.635ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.635ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.488ns (routing 0.405ns, distribution 1.083ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[14])
                                                      0.285     0.285 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/STATUS_COMMON[14]
                         net (fo=1, routed)           0.633     0.918    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/STATUS_COMMON[14]
    SLICE_X106Y99        LUT6 (Prop_H6LUT_SLICEL_I2_O)
                                                      0.060     0.978 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_35/O
                         net (fo=1, routed)           0.104     1.082    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_35_n_0
    SLICE_X105Y99        LUT6 (Prop_F6LUT_SLICEL_I5_O)
                                                      0.059     1.141 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_17/O
                         net (fo=1, routed)           0.078     1.219    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_17_n_0
    SLICE_X105Y100       LUT6 (Prop_C6LUT_SLICEL_I3_O)
                                                      0.014     1.233 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_5/O
                         net (fo=1, routed)           0.193     1.426    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_5_n_0
    SLICE_X106Y110       LUT6 (Prop_C6LUT_SLICEL_I3_O)
                                                      0.050     1.476 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_1/O
                         net (fo=1, routed)           0.017     1.493    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_70
    SLICE_X106Y110       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.488     1.635    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X106Y110       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  RFADC1_CLK
  To Clock:  clk_pl_0

Max Delay             8 Endpoints
Min Delay             8 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC1_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.880ns  (logic 0.882ns (30.625%)  route 1.998ns (69.375%))
  Logic Levels:           4  (LUT5=1 LUT6=3)
  Clock Path Skew:        2.322ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.322ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.140ns (routing 0.599ns, distribution 1.541ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[15])
                                                      0.525     0.525 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_COMMON[15]
                         net (fo=1, routed)           0.830     1.355    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_23_0[15]
    SLICE_X107Y103       LUT6 (Prop_F6LUT_SLICEM_I1_O)
                                                      0.098     1.453 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_52/O
                         net (fo=1, routed)           0.231     1.684    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_52_n_0
    SLICE_X105Y105       LUT5 (Prop_E6LUT_SLICEL_I2_O)
                                                      0.035     1.719 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_23/O
                         net (fo=1, routed)           0.464     2.183    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_23_n_0
    SLICE_X112Y107       LUT6 (Prop_H6LUT_SLICEM_I3_O)
                                                      0.125     2.308 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_5/O
                         net (fo=1, routed)           0.424     2.732    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_5_n_0
    SLICE_X106Y104       LUT6 (Prop_D6LUT_SLICEL_I4_O)
                                                      0.099     2.831 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_1/O
                         net (fo=1, routed)           0.049     2.880    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_69
    SLICE_X106Y104       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       2.140     2.322    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X106Y104       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC1_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.725ns  (logic 1.127ns (41.358%)  route 1.598ns (58.642%))
  Logic Levels:           4  (LUT5=1 LUT6=3)
  Clock Path Skew:        2.350ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.350ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.168ns (routing 0.599ns, distribution 1.569ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[8])
                                                      0.788     0.788 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_COMMON[8]
                         net (fo=1, routed)           0.815     1.603    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_23_0[8]
    SLICE_X106Y104       LUT5 (Prop_E6LUT_SLICEL_I4_O)
                                                      0.051     1.654 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_26/O
                         net (fo=1, routed)           0.102     1.756    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_26_n_0
    SLICE_X106Y105       LUT6 (Prop_F6LUT_SLICEL_I5_O)
                                                      0.148     1.904 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_16/O
                         net (fo=1, routed)           0.441     2.345    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_16_n_0
    SLICE_X108Y105       LUT6 (Prop_G6LUT_SLICEL_I2_O)
                                                      0.089     2.434 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_4/O
                         net (fo=1, routed)           0.191     2.625    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_4_n_0
    SLICE_X108Y109       LUT6 (Prop_B6LUT_SLICEL_I2_O)
                                                      0.051     2.676 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_1/O
                         net (fo=1, routed)           0.049     2.725    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_76
    SLICE_X108Y109       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       2.168     2.350    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X108Y109       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC1_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.542ns  (logic 1.094ns (43.037%)  route 1.448ns (56.963%))
  Logic Levels:           3  (LUT5=1 LUT6=2)
  Clock Path Skew:        2.348ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.348ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.166ns (routing 0.599ns, distribution 1.567ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[13])
                                                      0.771     0.771 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_COMMON[13]
                         net (fo=1, routed)           0.848     1.619    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_23_0[13]
    SLICE_X107Y104       LUT5 (Prop_C6LUT_SLICEM_I4_O)
                                                      0.051     1.670 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_21/O
                         net (fo=1, routed)           0.208     1.878    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_21_n_0
    SLICE_X106Y105       LUT6 (Prop_H6LUT_SLICEL_I5_O)
                                                      0.150     2.028 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_5/O
                         net (fo=1, routed)           0.343     2.371    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_5_n_0
    SLICE_X108Y106       LUT6 (Prop_D6LUT_SLICEL_I3_O)
                                                      0.122     2.493 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_1/O
                         net (fo=1, routed)           0.049     2.542    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_71
    SLICE_X108Y106       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       2.166     2.348    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X108Y106       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC1_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.405ns  (logic 0.921ns (38.295%)  route 1.484ns (61.705%))
  Logic Levels:           3  (LUT5=1 LUT6=2)
  Clock Path Skew:        2.348ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.348ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.166ns (routing 0.599ns, distribution 1.567ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[12])
                                                      0.611     0.611 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_COMMON[12]
                         net (fo=1, routed)           0.755     1.366    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_23_0[12]
    SLICE_X107Y104       LUT5 (Prop_F6LUT_SLICEM_I4_O)
                                                      0.123     1.489 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_14/O
                         net (fo=1, routed)           0.252     1.741    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_14_n_0
    SLICE_X107Y107       LUT6 (Prop_H6LUT_SLICEM_I5_O)
                                                      0.152     1.893 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_5/O
                         net (fo=1, routed)           0.427     2.320    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_5_n_0
    SLICE_X108Y107       LUT6 (Prop_C6LUT_SLICEL_I3_O)
                                                      0.035     2.355 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_1/O
                         net (fo=1, routed)           0.050     2.405    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_72
    SLICE_X108Y107       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       2.166     2.348    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X108Y107       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC1_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.264ns  (logic 1.061ns (46.864%)  route 1.203ns (53.136%))
  Logic Levels:           4  (LUT6=4)
  Clock Path Skew:        2.326ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.326ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.144ns (routing 0.599ns, distribution 1.545ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[14])
                                                      0.698     0.698 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_COMMON[14]
                         net (fo=1, routed)           0.742     1.440    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_23_0[14]
    SLICE_X107Y103       LUT6 (Prop_H6LUT_SLICEM_I0_O)
                                                      0.053     1.493 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_41/O
                         net (fo=1, routed)           0.102     1.595    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_41_n_0
    SLICE_X107Y105       LUT6 (Prop_D6LUT_SLICEM_I3_O)
                                                      0.122     1.717 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_20/O
                         net (fo=1, routed)           0.152     1.869    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_20_n_0
    SLICE_X107Y110       LUT6 (Prop_G6LUT_SLICEM_I2_O)
                                                      0.100     1.969 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_6/O
                         net (fo=1, routed)           0.157     2.126    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_6_n_0
    SLICE_X106Y110       LUT6 (Prop_C6LUT_SLICEL_I5_O)
                                                      0.088     2.214 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_1/O
                         net (fo=1, routed)           0.050     2.264    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_70
    SLICE_X106Y110       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       2.144     2.326    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X106Y110       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC1_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.945ns  (logic 0.964ns (49.563%)  route 0.981ns (50.437%))
  Logic Levels:           3  (LUT5=2 LUT6=1)
  Clock Path Skew:        2.348ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.348ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.166ns (routing 0.599ns, distribution 1.567ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[10])
                                                      0.536     0.536 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_COMMON[10]
                         net (fo=1, routed)           0.669     1.205    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_23_0[10]
    SLICE_X108Y104       LUT5 (Prop_F6LUT_SLICEL_I4_O)
                                                      0.148     1.353 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_10/O
                         net (fo=1, routed)           0.097     1.450    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_10_n_0
    SLICE_X109Y104       LUT6 (Prop_G6LUT_SLICEM_I2_O)
                                                      0.123     1.573 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_3/O
                         net (fo=1, routed)           0.200     1.773    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_3_n_0
    SLICE_X108Y107       LUT5 (Prop_D5LUT_SLICEL_I1_O)
                                                      0.157     1.930 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_1/O
                         net (fo=1, routed)           0.015     1.945    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_74
    SLICE_X108Y107       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       2.166     2.348    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X108Y107       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC1_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.938ns  (logic 0.889ns (45.872%)  route 1.049ns (54.128%))
  Logic Levels:           4  (LUT5=1 LUT6=3)
  Clock Path Skew:        2.352ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.352ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.170ns (routing 0.599ns, distribution 1.571ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[11])
                                                      0.588     0.588 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_COMMON[11]
                         net (fo=1, routed)           0.550     1.138    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_23_0[11]
    SLICE_X108Y103       LUT5 (Prop_D6LUT_SLICEL_I4_O)
                                                      0.099     1.237 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_25/O
                         net (fo=1, routed)           0.094     1.331    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_25_n_0
    SLICE_X108Y105       LUT6 (Prop_H6LUT_SLICEL_I5_O)
                                                      0.099     1.430 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_13/O
                         net (fo=1, routed)           0.087     1.517    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_13_n_0
    SLICE_X109Y105       LUT6 (Prop_G6LUT_SLICEM_I2_O)
                                                      0.052     1.569 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_3/O
                         net (fo=1, routed)           0.267     1.836    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_3_n_0
    SLICE_X108Y109       LUT6 (Prop_H6LUT_SLICEL_I1_O)
                                                      0.051     1.887 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_1/O
                         net (fo=1, routed)           0.051     1.938    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_73
    SLICE_X108Y109       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       2.170     2.352    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X108Y109       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC1_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.889ns  (logic 0.984ns (52.091%)  route 0.905ns (47.909%))
  Logic Levels:           4  (LUT5=1 LUT6=3)
  Clock Path Skew:        2.350ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.350ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.168ns (routing 0.599ns, distribution 1.569ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[9])
                                                      0.532     0.532 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_COMMON[9]
                         net (fo=1, routed)           0.556     1.088    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_23_0[9]
    SLICE_X108Y103       LUT5 (Prop_E6LUT_SLICEL_I4_O)
                                                      0.123     1.211 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_23/O
                         net (fo=1, routed)           0.107     1.318    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_23_n_0
    SLICE_X108Y105       LUT6 (Prop_C6LUT_SLICEL_I5_O)
                                                      0.146     1.464 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_15/O
                         net (fo=1, routed)           0.058     1.522    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_15_n_0
    SLICE_X108Y105       LUT6 (Prop_F6LUT_SLICEL_I2_O)
                                                      0.148     1.670 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_4/O
                         net (fo=1, routed)           0.136     1.806    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_4_n_0
    SLICE_X108Y109       LUT6 (Prop_A6LUT_SLICEL_I2_O)
                                                      0.035     1.841 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_1/O
                         net (fo=1, routed)           0.048     1.889    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_75
    SLICE_X108Y109       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       2.168     2.350    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X108Y109       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC1_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.853ns  (logic 0.410ns (48.066%)  route 0.443ns (51.934%))
  Logic Levels:           4  (LUT5=1 LUT6=3)
  Clock Path Skew:        1.648ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.648ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.501ns (routing 0.405ns, distribution 1.096ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[9])
                                                      0.228     0.228 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_COMMON[9]
                         net (fo=1, routed)           0.266     0.494    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_23_0[9]
    SLICE_X108Y103       LUT5 (Prop_E6LUT_SLICEL_I4_O)
                                                      0.050     0.544 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_23/O
                         net (fo=1, routed)           0.059     0.603    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_23_n_0
    SLICE_X108Y105       LUT6 (Prop_C6LUT_SLICEL_I5_O)
                                                      0.059     0.662 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_15/O
                         net (fo=1, routed)           0.030     0.692    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_15_n_0
    SLICE_X108Y105       LUT6 (Prop_F6LUT_SLICEL_I2_O)
                                                      0.059     0.751 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_4/O
                         net (fo=1, routed)           0.072     0.823    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_4_n_0
    SLICE_X108Y109       LUT6 (Prop_A6LUT_SLICEL_I2_O)
                                                      0.014     0.837 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_1/O
                         net (fo=1, routed)           0.016     0.853    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_75
    SLICE_X108Y109       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.501     1.648    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X108Y109       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC1_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.875ns  (logic 0.393ns (44.914%)  route 0.482ns (55.086%))
  Logic Levels:           3  (LUT5=2 LUT6=1)
  Clock Path Skew:        1.647ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.647ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.500ns (routing 0.405ns, distribution 1.095ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[10])
                                                      0.227     0.227 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_COMMON[10]
                         net (fo=1, routed)           0.321     0.548    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_23_0[10]
    SLICE_X108Y104       LUT5 (Prop_F6LUT_SLICEL_I4_O)
                                                      0.059     0.607 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_10/O
                         net (fo=1, routed)           0.052     0.659    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_10_n_0
    SLICE_X109Y104       LUT6 (Prop_G6LUT_SLICEM_I2_O)
                                                      0.050     0.709 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_3/O
                         net (fo=1, routed)           0.103     0.812    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_3_n_0
    SLICE_X108Y107       LUT5 (Prop_D5LUT_SLICEL_I1_O)
                                                      0.057     0.869 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_1/O
                         net (fo=1, routed)           0.006     0.875    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_74
    SLICE_X108Y107       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.500     1.647    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X108Y107       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC1_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.906ns  (logic 0.392ns (43.267%)  route 0.514ns (56.733%))
  Logic Levels:           4  (LUT5=1 LUT6=3)
  Clock Path Skew:        1.652ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.652ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.505ns (routing 0.405ns, distribution 1.100ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[11])
                                                      0.265     0.265 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_COMMON[11]
                         net (fo=1, routed)           0.262     0.527    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_23_0[11]
    SLICE_X108Y103       LUT5 (Prop_D6LUT_SLICEL_I4_O)
                                                      0.041     0.568 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_25/O
                         net (fo=1, routed)           0.050     0.618    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_25_n_0
    SLICE_X108Y105       LUT6 (Prop_H6LUT_SLICEL_I5_O)
                                                      0.041     0.659 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_13/O
                         net (fo=1, routed)           0.048     0.707    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_13_n_0
    SLICE_X109Y105       LUT6 (Prop_G6LUT_SLICEM_I2_O)
                                                      0.022     0.729 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_3/O
                         net (fo=1, routed)           0.137     0.866    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_3_n_0
    SLICE_X108Y109       LUT6 (Prop_H6LUT_SLICEL_I1_O)
                                                      0.023     0.889 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_1/O
                         net (fo=1, routed)           0.017     0.906    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_73
    SLICE_X108Y109       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.505     1.652    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X108Y109       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC1_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.018ns  (logic 0.433ns (42.534%)  route 0.585ns (57.466%))
  Logic Levels:           4  (LUT6=4)
  Clock Path Skew:        1.635ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.635ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.488ns (routing 0.405ns, distribution 1.083ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[14])
                                                      0.285     0.285 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_COMMON[14]
                         net (fo=1, routed)           0.354     0.639    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_23_0[14]
    SLICE_X107Y103       LUT6 (Prop_H6LUT_SLICEM_I0_O)
                                                      0.023     0.662 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_41/O
                         net (fo=1, routed)           0.053     0.715    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_41_n_0
    SLICE_X107Y105       LUT6 (Prop_D6LUT_SLICEM_I3_O)
                                                      0.050     0.765 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_20/O
                         net (fo=1, routed)           0.082     0.847    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_20_n_0
    SLICE_X107Y110       LUT6 (Prop_G6LUT_SLICEM_I2_O)
                                                      0.040     0.887 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_6/O
                         net (fo=1, routed)           0.079     0.966    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_6_n_0
    SLICE_X106Y110       LUT6 (Prop_C6LUT_SLICEL_I5_O)
                                                      0.035     1.001 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_1/O
                         net (fo=1, routed)           0.017     1.018    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_70
    SLICE_X106Y110       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.488     1.635    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X106Y110       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC1_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.059ns  (logic 0.373ns (35.222%)  route 0.686ns (64.778%))
  Logic Levels:           3  (LUT5=1 LUT6=2)
  Clock Path Skew:        1.647ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.647ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.500ns (routing 0.405ns, distribution 1.095ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[13])
                                                      0.241     0.241 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_COMMON[13]
                         net (fo=1, routed)           0.400     0.641    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_23_0[13]
    SLICE_X107Y104       LUT5 (Prop_C6LUT_SLICEM_I4_O)
                                                      0.022     0.663 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_21/O
                         net (fo=1, routed)           0.101     0.764    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_21_n_0
    SLICE_X106Y105       LUT6 (Prop_H6LUT_SLICEL_I5_O)
                                                      0.060     0.824 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_5/O
                         net (fo=1, routed)           0.169     0.993    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_5_n_0
    SLICE_X108Y106       LUT6 (Prop_D6LUT_SLICEL_I3_O)
                                                      0.050     1.043 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_1/O
                         net (fo=1, routed)           0.016     1.059    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_71
    SLICE_X108Y106       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.500     1.647    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X108Y106       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC1_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.131ns  (logic 0.399ns (35.279%)  route 0.732ns (64.721%))
  Logic Levels:           3  (LUT5=1 LUT6=2)
  Clock Path Skew:        1.647ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.647ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.500ns (routing 0.405ns, distribution 1.095ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[12])
                                                      0.274     0.274 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_COMMON[12]
                         net (fo=1, routed)           0.372     0.646    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_23_0[12]
    SLICE_X107Y104       LUT5 (Prop_F6LUT_SLICEM_I4_O)
                                                      0.050     0.696 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_14/O
                         net (fo=1, routed)           0.126     0.822    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_14_n_0
    SLICE_X107Y107       LUT6 (Prop_H6LUT_SLICEM_I5_O)
                                                      0.061     0.883 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_5/O
                         net (fo=1, routed)           0.217     1.100    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_5_n_0
    SLICE_X108Y107       LUT6 (Prop_C6LUT_SLICEL_I3_O)
                                                      0.014     1.114 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_1/O
                         net (fo=1, routed)           0.017     1.131    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_72
    SLICE_X108Y107       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.500     1.647    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X108Y107       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC1_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.160ns  (logic 0.376ns (32.414%)  route 0.784ns (67.586%))
  Logic Levels:           4  (LUT5=1 LUT6=3)
  Clock Path Skew:        1.648ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.648ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.501ns (routing 0.405ns, distribution 1.096ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[8])
                                                      0.237     0.237 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_COMMON[8]
                         net (fo=1, routed)           0.400     0.637    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_23_0[8]
    SLICE_X106Y104       LUT5 (Prop_E6LUT_SLICEL_I4_O)
                                                      0.022     0.659 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_26/O
                         net (fo=1, routed)           0.056     0.715    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_26_n_0
    SLICE_X106Y105       LUT6 (Prop_F6LUT_SLICEL_I5_O)
                                                      0.059     0.774 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_16/O
                         net (fo=1, routed)           0.213     0.987    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_16_n_0
    SLICE_X108Y105       LUT6 (Prop_G6LUT_SLICEL_I2_O)
                                                      0.035     1.022 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_4/O
                         net (fo=1, routed)           0.100     1.122    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_4_n_0
    SLICE_X108Y109       LUT6 (Prop_B6LUT_SLICEL_I2_O)
                                                      0.023     1.145 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_1/O
                         net (fo=1, routed)           0.015     1.160    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_76
    SLICE_X108Y109       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.501     1.648    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X108Y109       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC1_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.394ns  (logic 0.396ns (28.407%)  route 0.998ns (71.593%))
  Logic Levels:           4  (LUT5=1 LUT6=3)
  Clock Path Skew:        1.633ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.633ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.486ns (routing 0.405ns, distribution 1.081ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[15])
                                                      0.250     0.250 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_COMMON[15]
                         net (fo=1, routed)           0.389     0.639    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_23_0[15]
    SLICE_X107Y103       LUT6 (Prop_F6LUT_SLICEM_I1_O)
                                                      0.040     0.679 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_52/O
                         net (fo=1, routed)           0.120     0.799    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_52_n_0
    SLICE_X105Y105       LUT5 (Prop_E6LUT_SLICEL_I2_O)
                                                      0.014     0.813 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_23/O
                         net (fo=1, routed)           0.245     1.058    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_23_n_0
    SLICE_X112Y107       LUT6 (Prop_H6LUT_SLICEM_I3_O)
                                                      0.051     1.109 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_5/O
                         net (fo=1, routed)           0.228     1.337    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_5_n_0
    SLICE_X106Y104       LUT6 (Prop_D6LUT_SLICEL_I4_O)
                                                      0.041     1.378 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_1/O
                         net (fo=1, routed)           0.016     1.394    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_69
    SLICE_X106Y104       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.486     1.633    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X106Y104       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  RFADC2_CLK
  To Clock:  clk_pl_0

Max Delay             8 Endpoints
Min Delay             8 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC2_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.025ns  (logic 1.271ns (42.017%)  route 1.754ns (57.983%))
  Logic Levels:           5  (LUT5=2 LUT6=3)
  Clock Path Skew:        2.350ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.350ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.168ns (routing 0.599ns, distribution 1.569ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y2           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y2           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[8])
                                                      0.788     0.788 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_COMMON[8]
                         net (fo=1, routed)           0.829     1.617    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_22_1[8]
    SLICE_X113Y119       LUT5 (Prop_F6LUT_SLICEM_I3_O)
                                                      0.148     1.765 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_31/O
                         net (fo=1, routed)           0.229     1.994    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_31_n_0
    SLICE_X112Y117       LUT6 (Prop_F6LUT_SLICEM_I5_O)
                                                      0.098     2.092 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_29/O
                         net (fo=1, routed)           0.088     2.180    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_29_n_0
    SLICE_X112Y117       LUT5 (Prop_E6LUT_SLICEM_I1_O)
                                                      0.037     2.217 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_19/O
                         net (fo=1, routed)           0.142     2.359    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_19_n_0
    SLICE_X112Y116       LUT6 (Prop_G6LUT_SLICEM_I0_O)
                                                      0.052     2.411 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_6/O
                         net (fo=1, routed)           0.417     2.828    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_6_n_0
    SLICE_X108Y109       LUT6 (Prop_B6LUT_SLICEL_I4_O)
                                                      0.148     2.976 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_1/O
                         net (fo=1, routed)           0.049     3.025    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_76
    SLICE_X108Y109       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       2.168     2.350    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X108Y109       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC2_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.018ns  (logic 1.110ns (36.779%)  route 1.908ns (63.221%))
  Logic Levels:           5  (LUT5=1 LUT6=4)
  Clock Path Skew:        2.326ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.326ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.144ns (routing 0.599ns, distribution 1.545ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y2           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y2           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[14])
                                                      0.698     0.698 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_COMMON[14]
                         net (fo=1, routed)           0.862     1.560    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_22_1[14]
    SLICE_X111Y119       LUT6 (Prop_G6LUT_SLICEL_I2_O)
                                                      0.035     1.595 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_63/O
                         net (fo=1, routed)           0.146     1.741    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_63_n_0
    SLICE_X111Y117       LUT5 (Prop_D6LUT_SLICEL_I2_O)
                                                      0.089     1.830 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_46/O
                         net (fo=1, routed)           0.143     1.973    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_46_n_0
    SLICE_X111Y121       LUT6 (Prop_D6LUT_SLICEL_I5_O)
                                                      0.050     2.023 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_21/O
                         net (fo=1, routed)           0.550     2.573    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_21_n_0
    SLICE_X107Y110       LUT6 (Prop_G6LUT_SLICEM_I3_O)
                                                      0.150     2.723 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_6/O
                         net (fo=1, routed)           0.157     2.880    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_6_n_0
    SLICE_X106Y110       LUT6 (Prop_C6LUT_SLICEL_I5_O)
                                                      0.088     2.968 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_1/O
                         net (fo=1, routed)           0.050     3.018    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_70
    SLICE_X106Y110       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       2.144     2.326    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X106Y110       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC2_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.847ns  (logic 1.008ns (35.406%)  route 1.839ns (64.594%))
  Logic Levels:           5  (LUT5=2 LUT6=3)
  Clock Path Skew:        2.352ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.352ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.170ns (routing 0.599ns, distribution 1.571ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y2           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y2           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[11])
                                                      0.588     0.588 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_COMMON[11]
                         net (fo=1, routed)           0.923     1.511    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_22_1[11]
    SLICE_X113Y119       LUT5 (Prop_G6LUT_SLICEM_I3_O)
                                                      0.100     1.611 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_41/O
                         net (fo=1, routed)           0.216     1.827    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_41_n_0
    SLICE_X112Y117       LUT6 (Prop_D6LUT_SLICEM_I5_O)
                                                      0.037     1.864 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_31/O
                         net (fo=1, routed)           0.174     2.038    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_31_n_0
    SLICE_X111Y117       LUT5 (Prop_E6LUT_SLICEL_I1_O)
                                                      0.123     2.161 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_19/O
                         net (fo=1, routed)           0.089     2.250    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_19_n_0
    SLICE_X111Y116       LUT6 (Prop_H6LUT_SLICEL_I0_O)
                                                      0.036     2.286 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_5/O
                         net (fo=1, routed)           0.386     2.672    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_5_n_0
    SLICE_X108Y109       LUT6 (Prop_H6LUT_SLICEL_I3_O)
                                                      0.124     2.796 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_1/O
                         net (fo=1, routed)           0.051     2.847    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_73
    SLICE_X108Y109       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       2.170     2.352    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X108Y109       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC2_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.763ns  (logic 0.984ns (35.613%)  route 1.779ns (64.387%))
  Logic Levels:           4  (LUT5=1 LUT6=3)
  Clock Path Skew:        2.348ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.348ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.166ns (routing 0.599ns, distribution 1.567ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y2           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y2           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[12])
                                                      0.611     0.611 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_COMMON[12]
                         net (fo=1, routed)           0.941     1.552    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_22_1[12]
    SLICE_X107Y118       LUT5 (Prop_G6LUT_SLICEM_I3_O)
                                                      0.090     1.642 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_20/O
                         net (fo=1, routed)           0.137     1.779    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_20_n_0
    SLICE_X107Y115       LUT6 (Prop_H6LUT_SLICEM_I5_O)
                                                      0.039     1.818 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_15/O
                         net (fo=1, routed)           0.553     2.371    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_15_n_0
    SLICE_X108Y106       LUT6 (Prop_B6LUT_SLICEL_I0_O)
                                                      0.098     2.469 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_6/O
                         net (fo=1, routed)           0.098     2.567    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_6_n_0
    SLICE_X108Y107       LUT6 (Prop_C6LUT_SLICEL_I5_O)
                                                      0.146     2.713 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_1/O
                         net (fo=1, routed)           0.050     2.763    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_72
    SLICE_X108Y107       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       2.166     2.348    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X108Y107       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC2_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.570ns  (logic 1.009ns (39.261%)  route 1.561ns (60.739%))
  Logic Levels:           5  (LUT5=2 LUT6=3)
  Clock Path Skew:        2.348ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.348ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.166ns (routing 0.599ns, distribution 1.567ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y2           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y2           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[10])
                                                      0.536     0.536 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_COMMON[10]
                         net (fo=1, routed)           0.758     1.294    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_22_1[10]
    SLICE_X112Y116       LUT5 (Prop_E6LUT_SLICEM_I3_O)
                                                      0.148     1.442 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_29/O
                         net (fo=1, routed)           0.158     1.600    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_29_n_0
    SLICE_X112Y117       LUT6 (Prop_G6LUT_SLICEM_I5_O)
                                                      0.123     1.723 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_24/O
                         net (fo=1, routed)           0.047     1.770    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_24_n_0
    SLICE_X112Y117       LUT6 (Prop_H6LUT_SLICEM_I4_O)
                                                      0.101     1.871 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_16/O
                         net (fo=1, routed)           0.146     2.017    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_16_n_0
    SLICE_X114Y117       LUT6 (Prop_G6LUT_SLICEL_I4_O)
                                                      0.035     2.052 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_4/O
                         net (fo=1, routed)           0.437     2.489    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_4_n_0
    SLICE_X108Y107       LUT5 (Prop_D5LUT_SLICEL_I2_O)
                                                      0.066     2.555 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_1/O
                         net (fo=1, routed)           0.015     2.570    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_74
    SLICE_X108Y107       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       2.166     2.348    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X108Y107       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC2_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.542ns  (logic 1.035ns (40.716%)  route 1.507ns (59.284%))
  Logic Levels:           5  (LUT5=2 LUT6=3)
  Clock Path Skew:        2.350ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.350ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.168ns (routing 0.599ns, distribution 1.569ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y2           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y2           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[9])
                                                      0.532     0.532 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_COMMON[9]
                         net (fo=1, routed)           0.693     1.225    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_22_1[9]
    SLICE_X113Y119       LUT5 (Prop_E6LUT_SLICEM_I3_O)
                                                      0.148     1.373 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_29/O
                         net (fo=1, routed)           0.143     1.516    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_29_n_0
    SLICE_X112Y118       LUT6 (Prop_D6LUT_SLICEM_I5_O)
                                                      0.037     1.553 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_26/O
                         net (fo=1, routed)           0.052     1.605    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_26_n_0
    SLICE_X112Y118       LUT5 (Prop_C6LUT_SLICEM_I1_O)
                                                      0.145     1.750 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_18/O
                         net (fo=1, routed)           0.101     1.851    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_18_n_0
    SLICE_X112Y116       LUT6 (Prop_F6LUT_SLICEM_I0_O)
                                                      0.123     1.974 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_6/O
                         net (fo=1, routed)           0.470     2.444    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_6_n_0
    SLICE_X108Y109       LUT6 (Prop_A6LUT_SLICEL_I4_O)
                                                      0.050     2.494 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_1/O
                         net (fo=1, routed)           0.048     2.542    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_75
    SLICE_X108Y109       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       2.168     2.350    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X108Y109       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC2_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.387ns  (logic 0.798ns (33.431%)  route 1.589ns (66.569%))
  Logic Levels:           4  (LUT5=1 LUT6=3)
  Clock Path Skew:        2.322ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.322ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.140ns (routing 0.599ns, distribution 1.541ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y2           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y2           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[15])
                                                      0.525     0.525 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_COMMON[15]
                         net (fo=1, routed)           0.803     1.328    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_22_1[15]
    SLICE_X112Y118       LUT6 (Prop_G6LUT_SLICEM_I5_O)
                                                      0.037     1.365 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_47/O
                         net (fo=1, routed)           0.045     1.410    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_47_n_0
    SLICE_X112Y118       LUT5 (Prop_F6LUT_SLICEM_I0_O)
                                                      0.098     1.508 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_22/O
                         net (fo=1, routed)           0.268     1.776    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_22_n_0
    SLICE_X112Y107       LUT6 (Prop_H6LUT_SLICEM_I2_O)
                                                      0.039     1.815 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_5/O
                         net (fo=1, routed)           0.424     2.239    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_5_n_0
    SLICE_X106Y104       LUT6 (Prop_D6LUT_SLICEL_I4_O)
                                                      0.099     2.338 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_1/O
                         net (fo=1, routed)           0.049     2.387    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_69
    SLICE_X106Y104       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       2.140     2.322    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X106Y104       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC2_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.375ns  (logic 1.071ns (45.095%)  route 1.304ns (54.905%))
  Logic Levels:           4  (LUT5=1 LUT6=3)
  Clock Path Skew:        2.348ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.348ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.166ns (routing 0.599ns, distribution 1.567ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y2           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y2           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[13])
                                                      0.771     0.771 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_COMMON[13]
                         net (fo=1, routed)           0.759     1.530    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_22_1[13]
    SLICE_X109Y119       LUT5 (Prop_H6LUT_SLICEM_I3_O)
                                                      0.039     1.569 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_60/O
                         net (fo=1, routed)           0.151     1.720    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_60_n_0
    SLICE_X109Y115       LUT6 (Prop_G6LUT_SLICEM_I5_O)
                                                      0.123     1.843 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_27/O
                         net (fo=1, routed)           0.258     2.101    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_27_n_0
    SLICE_X109Y106       LUT6 (Prop_D6LUT_SLICEM_I0_O)
                                                      0.088     2.189 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_7/O
                         net (fo=1, routed)           0.087     2.276    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_7_n_0
    SLICE_X108Y106       LUT6 (Prop_D6LUT_SLICEL_I5_O)
                                                      0.050     2.326 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_1/O
                         net (fo=1, routed)           0.049     2.375    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_71
    SLICE_X108Y106       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       2.166     2.348    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X108Y106       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC2_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.014ns  (logic 0.363ns (35.799%)  route 0.651ns (64.201%))
  Logic Levels:           4  (LUT5=1 LUT6=3)
  Clock Path Skew:        1.647ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.647ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.500ns (routing 0.405ns, distribution 1.095ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y2           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y2           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[13])
                                                      0.241     0.241 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_COMMON[13]
                         net (fo=1, routed)           0.375     0.616    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_22_1[13]
    SLICE_X109Y119       LUT5 (Prop_H6LUT_SLICEM_I3_O)
                                                      0.015     0.631 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_60/O
                         net (fo=1, routed)           0.080     0.711    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_60_n_0
    SLICE_X109Y115       LUT6 (Prop_G6LUT_SLICEM_I5_O)
                                                      0.050     0.761 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_27/O
                         net (fo=1, routed)           0.133     0.894    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_27_n_0
    SLICE_X109Y106       LUT6 (Prop_D6LUT_SLICEM_I0_O)
                                                      0.035     0.929 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_7/O
                         net (fo=1, routed)           0.047     0.976    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_7_n_0
    SLICE_X108Y106       LUT6 (Prop_D6LUT_SLICEL_I5_O)
                                                      0.022     0.998 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_1/O
                         net (fo=1, routed)           0.016     1.014    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_71
    SLICE_X108Y106       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.500     1.647    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X108Y106       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC2_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.164ns  (logic 0.360ns (30.928%)  route 0.804ns (69.072%))
  Logic Levels:           4  (LUT5=1 LUT6=3)
  Clock Path Skew:        1.633ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.633ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.486ns (routing 0.405ns, distribution 1.081ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y2           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y2           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[15])
                                                      0.250     0.250 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_COMMON[15]
                         net (fo=1, routed)           0.393     0.643    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_22_1[15]
    SLICE_X112Y118       LUT6 (Prop_G6LUT_SLICEM_I5_O)
                                                      0.014     0.657 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_47/O
                         net (fo=1, routed)           0.025     0.682    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_47_n_0
    SLICE_X112Y118       LUT5 (Prop_F6LUT_SLICEM_I0_O)
                                                      0.040     0.722 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_22/O
                         net (fo=1, routed)           0.142     0.864    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_22_n_0
    SLICE_X112Y107       LUT6 (Prop_H6LUT_SLICEM_I2_O)
                                                      0.015     0.879 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_5/O
                         net (fo=1, routed)           0.228     1.107    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_5_n_0
    SLICE_X106Y104       LUT6 (Prop_D6LUT_SLICEL_I4_O)
                                                      0.041     1.148 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_1/O
                         net (fo=1, routed)           0.016     1.164    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_69
    SLICE_X106Y104       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.486     1.633    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X106Y104       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC2_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.178ns  (logic 0.432ns (36.672%)  route 0.746ns (63.328%))
  Logic Levels:           5  (LUT5=2 LUT6=3)
  Clock Path Skew:        1.648ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.648ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.501ns (routing 0.405ns, distribution 1.096ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y2           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y2           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[9])
                                                      0.228     0.228 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_COMMON[9]
                         net (fo=1, routed)           0.335     0.563    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_22_1[9]
    SLICE_X113Y119       LUT5 (Prop_E6LUT_SLICEM_I3_O)
                                                      0.059     0.622 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_29/O
                         net (fo=1, routed)           0.077     0.699    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_29_n_0
    SLICE_X112Y118       LUT6 (Prop_D6LUT_SLICEM_I5_O)
                                                      0.014     0.713 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_26/O
                         net (fo=1, routed)           0.029     0.742    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_26_n_0
    SLICE_X112Y118       LUT5 (Prop_C6LUT_SLICEM_I1_O)
                                                      0.059     0.801 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_18/O
                         net (fo=1, routed)           0.053     0.854    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_18_n_0
    SLICE_X112Y116       LUT6 (Prop_F6LUT_SLICEM_I0_O)
                                                      0.050     0.904 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_6/O
                         net (fo=1, routed)           0.236     1.140    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_6_n_0
    SLICE_X108Y109       LUT6 (Prop_A6LUT_SLICEL_I4_O)
                                                      0.022     1.162 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_1/O
                         net (fo=1, routed)           0.016     1.178    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_75
    SLICE_X108Y109       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.501     1.648    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X108Y109       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC2_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.198ns  (logic 0.411ns (34.307%)  route 0.787ns (65.693%))
  Logic Levels:           5  (LUT5=2 LUT6=3)
  Clock Path Skew:        1.647ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.647ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.500ns (routing 0.405ns, distribution 1.095ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y2           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y2           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[10])
                                                      0.227     0.227 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_COMMON[10]
                         net (fo=1, routed)           0.370     0.597    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_22_1[10]
    SLICE_X112Y116       LUT5 (Prop_E6LUT_SLICEM_I3_O)
                                                      0.059     0.656 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_29/O
                         net (fo=1, routed)           0.079     0.735    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_29_n_0
    SLICE_X112Y117       LUT6 (Prop_G6LUT_SLICEM_I5_O)
                                                      0.050     0.785 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_24/O
                         net (fo=1, routed)           0.026     0.811    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_24_n_0
    SLICE_X112Y117       LUT6 (Prop_H6LUT_SLICEM_I4_O)
                                                      0.041     0.852 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_16/O
                         net (fo=1, routed)           0.075     0.927    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_16_n_0
    SLICE_X114Y117       LUT6 (Prop_G6LUT_SLICEL_I4_O)
                                                      0.014     0.941 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_4/O
                         net (fo=1, routed)           0.231     1.172    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_4_n_0
    SLICE_X108Y107       LUT5 (Prop_D5LUT_SLICEL_I2_O)
                                                      0.020     1.192 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_1/O
                         net (fo=1, routed)           0.006     1.198    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_74
    SLICE_X108Y107       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.500     1.647    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X108Y107       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC2_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.288ns  (logic 0.432ns (33.540%)  route 0.856ns (66.460%))
  Logic Levels:           5  (LUT5=2 LUT6=3)
  Clock Path Skew:        1.648ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.648ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.501ns (routing 0.405ns, distribution 1.096ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y2           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y2           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[8])
                                                      0.237     0.237 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_COMMON[8]
                         net (fo=1, routed)           0.401     0.638    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_22_1[8]
    SLICE_X113Y119       LUT5 (Prop_F6LUT_SLICEM_I3_O)
                                                      0.059     0.697 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_31/O
                         net (fo=1, routed)           0.116     0.813    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_31_n_0
    SLICE_X112Y117       LUT6 (Prop_F6LUT_SLICEM_I5_O)
                                                      0.040     0.853 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_29/O
                         net (fo=1, routed)           0.042     0.895    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_29_n_0
    SLICE_X112Y117       LUT5 (Prop_E6LUT_SLICEM_I1_O)
                                                      0.014     0.909 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_19/O
                         net (fo=1, routed)           0.072     0.981    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_19_n_0
    SLICE_X112Y116       LUT6 (Prop_G6LUT_SLICEM_I0_O)
                                                      0.022     1.003 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_6/O
                         net (fo=1, routed)           0.210     1.213    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_6_n_0
    SLICE_X108Y109       LUT6 (Prop_B6LUT_SLICEL_I4_O)
                                                      0.060     1.273 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_1/O
                         net (fo=1, routed)           0.015     1.288    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_76
    SLICE_X108Y109       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.501     1.648    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X108Y109       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC2_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.315ns  (logic 0.424ns (32.243%)  route 0.891ns (67.757%))
  Logic Levels:           4  (LUT5=1 LUT6=3)
  Clock Path Skew:        1.647ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.647ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.500ns (routing 0.405ns, distribution 1.095ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y2           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y2           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[12])
                                                      0.274     0.274 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_COMMON[12]
                         net (fo=1, routed)           0.463     0.737    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_22_1[12]
    SLICE_X107Y118       LUT5 (Prop_G6LUT_SLICEM_I3_O)
                                                      0.035     0.772 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_20/O
                         net (fo=1, routed)           0.076     0.848    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_20_n_0
    SLICE_X107Y115       LUT6 (Prop_H6LUT_SLICEM_I5_O)
                                                      0.015     0.863 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_15/O
                         net (fo=1, routed)           0.282     1.145    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_15_n_0
    SLICE_X108Y106       LUT6 (Prop_B6LUT_SLICEL_I0_O)
                                                      0.041     1.186 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_6/O
                         net (fo=1, routed)           0.053     1.239    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_6_n_0
    SLICE_X108Y107       LUT6 (Prop_C6LUT_SLICEL_I5_O)
                                                      0.059     1.298 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_1/O
                         net (fo=1, routed)           0.017     1.315    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_72
    SLICE_X108Y107       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.500     1.647    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X108Y107       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC2_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.337ns  (logic 0.434ns (32.461%)  route 0.903ns (67.539%))
  Logic Levels:           5  (LUT5=2 LUT6=3)
  Clock Path Skew:        1.652ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.652ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.505ns (routing 0.405ns, distribution 1.100ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y2           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y2           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[11])
                                                      0.265     0.265 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_COMMON[11]
                         net (fo=1, routed)           0.451     0.716    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_22_1[11]
    SLICE_X113Y119       LUT5 (Prop_G6LUT_SLICEM_I3_O)
                                                      0.040     0.756 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_41/O
                         net (fo=1, routed)           0.110     0.866    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_41_n_0
    SLICE_X112Y117       LUT6 (Prop_D6LUT_SLICEM_I5_O)
                                                      0.014     0.880 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_31/O
                         net (fo=1, routed)           0.087     0.967    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_31_n_0
    SLICE_X111Y117       LUT5 (Prop_E6LUT_SLICEL_I1_O)
                                                      0.050     1.017 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_19/O
                         net (fo=1, routed)           0.045     1.062    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_19_n_0
    SLICE_X111Y116       LUT6 (Prop_H6LUT_SLICEL_I0_O)
                                                      0.015     1.077 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_5/O
                         net (fo=1, routed)           0.193     1.270    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_5_n_0
    SLICE_X108Y109       LUT6 (Prop_H6LUT_SLICEL_I3_O)
                                                      0.050     1.320 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_1/O
                         net (fo=1, routed)           0.017     1.337    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_73
    SLICE_X108Y109       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.505     1.652    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X108Y109       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC2_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.413ns  (logic 0.451ns (31.918%)  route 0.962ns (68.082%))
  Logic Levels:           5  (LUT5=1 LUT6=4)
  Clock Path Skew:        1.635ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.635ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.488ns (routing 0.405ns, distribution 1.083ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y2           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y2           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[14])
                                                      0.285     0.285 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_COMMON[14]
                         net (fo=1, routed)           0.430     0.715    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_22_1[14]
    SLICE_X111Y119       LUT6 (Prop_G6LUT_SLICEL_I2_O)
                                                      0.014     0.729 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_63/O
                         net (fo=1, routed)           0.073     0.802    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_63_n_0
    SLICE_X111Y117       LUT5 (Prop_D6LUT_SLICEL_I2_O)
                                                      0.035     0.837 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_46/O
                         net (fo=1, routed)           0.075     0.912    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_46_n_0
    SLICE_X111Y121       LUT6 (Prop_D6LUT_SLICEL_I5_O)
                                                      0.022     0.934 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_21/O
                         net (fo=1, routed)           0.288     1.222    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_21_n_0
    SLICE_X107Y110       LUT6 (Prop_G6LUT_SLICEM_I3_O)
                                                      0.060     1.282 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_6/O
                         net (fo=1, routed)           0.079     1.361    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_6_n_0
    SLICE_X106Y110       LUT6 (Prop_C6LUT_SLICEL_I5_O)
                                                      0.035     1.396 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_1/O
                         net (fo=1, routed)           0.017     1.413    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_70
    SLICE_X106Y110       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.488     1.635    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X106Y110       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  RFADC3_CLK
  To Clock:  clk_pl_0

Max Delay             8 Endpoints
Min Delay             8 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC3_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.176ns  (logic 0.959ns (30.195%)  route 2.217ns (69.805%))
  Logic Levels:           4  (LUT5=1 LUT6=3)
  Clock Path Skew:        2.326ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.326ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.144ns (routing 0.599ns, distribution 1.545ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC3_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y3           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y3           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[14])
                                                      0.698     0.698 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/STATUS_COMMON[14]
                         net (fo=1, routed)           1.245     1.943    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_55_0[14]
    SLICE_X115Y115       LUT5 (Prop_H6LUT_SLICEM_I4_O)
                                                      0.039     1.982 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_38/O
                         net (fo=1, routed)           0.332     2.314    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_38_n_0
    SLICE_X114Y113       LUT6 (Prop_G6LUT_SLICEL_I3_O)
                                                      0.097     2.411 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_19/O
                         net (fo=1, routed)           0.433     2.844    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_19_n_0
    SLICE_X107Y110       LUT6 (Prop_G6LUT_SLICEM_I0_O)
                                                      0.037     2.881 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_6/O
                         net (fo=1, routed)           0.157     3.038    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_6_n_0
    SLICE_X106Y110       LUT6 (Prop_C6LUT_SLICEL_I5_O)
                                                      0.088     3.126 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_1/O
                         net (fo=1, routed)           0.050     3.176    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_70
    SLICE_X106Y110       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       2.144     2.326    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X106Y110       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC3_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.158ns  (logic 0.901ns (28.531%)  route 2.257ns (71.469%))
  Logic Levels:           5  (LUT4=1 LUT5=1 LUT6=3)
  Clock Path Skew:        2.322ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.322ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.140ns (routing 0.599ns, distribution 1.541ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC3_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y3           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y3           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[15])
                                                      0.525     0.525 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/STATUS_COMMON[15]
                         net (fo=1, routed)           1.189     1.714    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_55_0[15]
    SLICE_X117Y115       LUT4 (Prop_F6LUT_SLICEL_I0_O)
                                                      0.049     1.763 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_84/O
                         net (fo=1, routed)           0.281     2.044    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_84_n_0
    SLICE_X113Y113       LUT5 (Prop_G6LUT_SLICEM_I2_O)
                                                      0.052     2.096 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_55/O
                         net (fo=1, routed)           0.102     2.198    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_55_n_0
    SLICE_X113Y111       LUT6 (Prop_G6LUT_SLICEM_I3_O)
                                                      0.123     2.321 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_25/O
                         net (fo=1, routed)           0.212     2.533    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_25_n_0
    SLICE_X112Y107       LUT6 (Prop_H6LUT_SLICEM_I5_O)
                                                      0.053     2.586 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_5/O
                         net (fo=1, routed)           0.424     3.010    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_5_n_0
    SLICE_X106Y104       LUT6 (Prop_D6LUT_SLICEL_I4_O)
                                                      0.099     3.109 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_1/O
                         net (fo=1, routed)           0.049     3.158    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_69
    SLICE_X106Y104       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       2.140     2.322    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X106Y104       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC3_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.961ns  (logic 1.005ns (33.941%)  route 1.956ns (66.059%))
  Logic Levels:           4  (LUT5=2 LUT6=2)
  Clock Path Skew:        2.352ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.352ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.170ns (routing 0.599ns, distribution 1.571ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC3_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y3           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y3           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[11])
                                                      0.588     0.588 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/STATUS_COMMON[11]
                         net (fo=1, routed)           1.115     1.703    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_55_0[11]
    SLICE_X117Y116       LUT5 (Prop_A6LUT_SLICEL_I4_O)
                                                      0.090     1.793 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_29/O
                         net (fo=1, routed)           0.311     2.104    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_29_n_0
    SLICE_X114Y116       LUT6 (Prop_C6LUT_SLICEL_I4_O)
                                                      0.088     2.192 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_18/O
                         net (fo=1, routed)           0.064     2.256    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_18_n_0
    SLICE_X114Y116       LUT5 (Prop_G6LUT_SLICEL_I4_O)
                                                      0.149     2.405 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_4/O
                         net (fo=1, routed)           0.415     2.820    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_4_n_0
    SLICE_X108Y109       LUT6 (Prop_H6LUT_SLICEL_I2_O)
                                                      0.090     2.910 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_1/O
                         net (fo=1, routed)           0.051     2.961    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_73
    SLICE_X108Y109       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       2.170     2.352    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X108Y109       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC3_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.932ns  (logic 1.093ns (37.278%)  route 1.839ns (62.722%))
  Logic Levels:           4  (LUT5=1 LUT6=3)
  Clock Path Skew:        2.348ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.348ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.166ns (routing 0.599ns, distribution 1.567ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC3_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y3           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y3           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[13])
                                                      0.771     0.771 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/STATUS_COMMON[13]
                         net (fo=1, routed)           1.218     1.989    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_55_0[13]
    SLICE_X116Y114       LUT5 (Prop_H6LUT_SLICEL_I4_O)
                                                      0.090     2.079 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_37/O
                         net (fo=1, routed)           0.146     2.225    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_37_n_0
    SLICE_X114Y112       LUT6 (Prop_H6LUT_SLICEL_I5_O)
                                                      0.036     2.261 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_12/O
                         net (fo=1, routed)           0.038     2.299    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_12_n_0
    SLICE_X114Y112       LUT6 (Prop_G6LUT_SLICEL_I2_O)
                                                      0.050     2.349 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_3/O
                         net (fo=1, routed)           0.388     2.737    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_3_n_0
    SLICE_X108Y106       LUT6 (Prop_D6LUT_SLICEL_I1_O)
                                                      0.146     2.883 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_1/O
                         net (fo=1, routed)           0.049     2.932    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_71
    SLICE_X108Y106       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       2.166     2.348    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X108Y106       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC3_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.913ns  (logic 0.986ns (33.848%)  route 1.927ns (66.152%))
  Logic Levels:           4  (LUT5=1 LUT6=3)
  Clock Path Skew:        2.348ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.348ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.166ns (routing 0.599ns, distribution 1.567ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC3_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y3           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y3           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[12])
                                                      0.611     0.611 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/STATUS_COMMON[12]
                         net (fo=1, routed)           1.141     1.752    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_55_0[12]
    SLICE_X116Y115       LUT5 (Prop_H6LUT_SLICEL_I4_O)
                                                      0.150     1.902 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_18/O
                         net (fo=1, routed)           0.287     2.189    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_18_n_0
    SLICE_X112Y115       LUT6 (Prop_H6LUT_SLICEM_I0_O)
                                                      0.090     2.279 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_10/O
                         net (fo=1, routed)           0.091     2.370    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_10_n_0
    SLICE_X112Y114       LUT6 (Prop_H6LUT_SLICEM_I2_O)
                                                      0.039     2.409 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_3/O
                         net (fo=1, routed)           0.358     2.767    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_3_n_0
    SLICE_X108Y107       LUT6 (Prop_C6LUT_SLICEL_I1_O)
                                                      0.096     2.863 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_1/O
                         net (fo=1, routed)           0.050     2.913    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_72
    SLICE_X108Y107       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       2.166     2.348    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X108Y107       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC3_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.906ns  (logic 1.200ns (41.294%)  route 1.706ns (58.706%))
  Logic Levels:           4  (LUT5=2 LUT6=2)
  Clock Path Skew:        2.350ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.350ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.168ns (routing 0.599ns, distribution 1.569ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC3_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y3           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y3           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[8])
                                                      0.788     0.788 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/STATUS_COMMON[8]
                         net (fo=1, routed)           1.200     1.988    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_55_0[8]
    SLICE_X115Y115       LUT5 (Prop_G6LUT_SLICEM_I4_O)
                                                      0.100     2.088 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_28/O
                         net (fo=1, routed)           0.089     2.177    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_28_n_0
    SLICE_X114Y115       LUT6 (Prop_G6LUT_SLICEL_I4_O)
                                                      0.089     2.266 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_18/O
                         net (fo=1, routed)           0.046     2.312    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_18_n_0
    SLICE_X114Y115       LUT5 (Prop_E6LUT_SLICEL_I4_O)
                                                      0.099     2.411 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_5/O
                         net (fo=1, routed)           0.322     2.733    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_5_n_0
    SLICE_X108Y109       LUT6 (Prop_B6LUT_SLICEL_I3_O)
                                                      0.124     2.857 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_1/O
                         net (fo=1, routed)           0.049     2.906    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_76
    SLICE_X108Y109       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       2.168     2.350    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X108Y109       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC3_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.743ns  (logic 0.878ns (32.009%)  route 1.865ns (67.991%))
  Logic Levels:           4  (LUT5=2 LUT6=2)
  Clock Path Skew:        2.350ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.350ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.168ns (routing 0.599ns, distribution 1.569ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC3_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y3           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y3           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[9])
                                                      0.532     0.532 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/STATUS_COMMON[9]
                         net (fo=1, routed)           1.015     1.547    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_55_0[9]
    SLICE_X117Y116       LUT5 (Prop_G6LUT_SLICEL_I4_O)
                                                      0.123     1.670 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_25/O
                         net (fo=1, routed)           0.280     1.950    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_25_n_0
    SLICE_X114Y116       LUT6 (Prop_H6LUT_SLICEL_I4_O)
                                                      0.036     1.986 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_17/O
                         net (fo=1, routed)           0.037     2.023    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_17_n_0
    SLICE_X114Y116       LUT5 (Prop_F6LUT_SLICEL_I4_O)
                                                      0.089     2.112 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_5/O
                         net (fo=1, routed)           0.485     2.597    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_5_n_0
    SLICE_X108Y109       LUT6 (Prop_A6LUT_SLICEL_I3_O)
                                                      0.098     2.695 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_1/O
                         net (fo=1, routed)           0.048     2.743    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_75
    SLICE_X108Y109       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       2.168     2.350    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X108Y109       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC3_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.640ns  (logic 0.800ns (30.303%)  route 1.840ns (69.697%))
  Logic Levels:           4  (LUT5=2 LUT6=2)
  Clock Path Skew:        2.348ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.348ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.166ns (routing 0.599ns, distribution 1.567ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC3_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y3           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y3           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[10])
                                                      0.536     0.536 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/STATUS_COMMON[10]
                         net (fo=1, routed)           1.155     1.691    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_55_0[10]
    SLICE_X116Y116       LUT5 (Prop_B6LUT_SLICEL_I4_O)
                                                      0.051     1.742 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_23/O
                         net (fo=1, routed)           0.096     1.838    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_23_n_0
    SLICE_X114Y116       LUT6 (Prop_D6LUT_SLICEL_I4_O)
                                                      0.050     1.888 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_13/O
                         net (fo=1, routed)           0.137     2.025    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_13_n_0
    SLICE_X114Y117       LUT6 (Prop_G6LUT_SLICEL_I0_O)
                                                      0.097     2.122 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_4/O
                         net (fo=1, routed)           0.437     2.559    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_4_n_0
    SLICE_X108Y107       LUT5 (Prop_D5LUT_SLICEL_I2_O)
                                                      0.066     2.625 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_1/O
                         net (fo=1, routed)           0.015     2.640    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_74
    SLICE_X108Y107       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       2.166     2.348    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X108Y107       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC3_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.251ns  (logic 0.403ns (32.214%)  route 0.848ns (67.786%))
  Logic Levels:           4  (LUT5=2 LUT6=2)
  Clock Path Skew:        1.648ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.648ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.501ns (routing 0.405ns, distribution 1.096ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC3_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y3           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y3           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[8])
                                                      0.237     0.237 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/STATUS_COMMON[8]
                         net (fo=1, routed)           0.593     0.830    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_55_0[8]
    SLICE_X115Y115       LUT5 (Prop_G6LUT_SLICEM_I4_O)
                                                      0.040     0.870 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_28/O
                         net (fo=1, routed)           0.048     0.918    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_28_n_0
    SLICE_X114Y115       LUT6 (Prop_G6LUT_SLICEL_I4_O)
                                                      0.035     0.953 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_18/O
                         net (fo=1, routed)           0.025     0.978    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_18_n_0
    SLICE_X114Y115       LUT5 (Prop_E6LUT_SLICEL_I4_O)
                                                      0.041     1.019 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_5/O
                         net (fo=1, routed)           0.167     1.186    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_5_n_0
    SLICE_X108Y109       LUT6 (Prop_B6LUT_SLICEL_I3_O)
                                                      0.050     1.236 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_1/O
                         net (fo=1, routed)           0.015     1.251    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_76
    SLICE_X108Y109       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.501     1.648    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X108Y109       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC3_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.267ns  (logic 0.332ns (26.204%)  route 0.935ns (73.796%))
  Logic Levels:           4  (LUT5=2 LUT6=2)
  Clock Path Skew:        1.647ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.647ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.500ns (routing 0.405ns, distribution 1.095ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC3_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y3           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y3           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[10])
                                                      0.227     0.227 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/STATUS_COMMON[10]
                         net (fo=1, routed)           0.578     0.805    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_55_0[10]
    SLICE_X116Y116       LUT5 (Prop_B6LUT_SLICEL_I4_O)
                                                      0.023     0.828 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_23/O
                         net (fo=1, routed)           0.051     0.879    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_23_n_0
    SLICE_X114Y116       LUT6 (Prop_D6LUT_SLICEL_I4_O)
                                                      0.022     0.901 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_13/O
                         net (fo=1, routed)           0.069     0.970    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_13_n_0
    SLICE_X114Y117       LUT6 (Prop_G6LUT_SLICEL_I0_O)
                                                      0.040     1.010 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_4/O
                         net (fo=1, routed)           0.231     1.241    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_4_n_0
    SLICE_X108Y107       LUT5 (Prop_D5LUT_SLICEL_I2_O)
                                                      0.020     1.261 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_1/O
                         net (fo=1, routed)           0.006     1.267    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_74
    SLICE_X108Y107       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.500     1.647    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X108Y107       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC3_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.279ns  (logic 0.369ns (28.851%)  route 0.910ns (71.149%))
  Logic Levels:           4  (LUT5=2 LUT6=2)
  Clock Path Skew:        1.648ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.648ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.501ns (routing 0.405ns, distribution 1.096ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC3_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y3           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y3           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[9])
                                                      0.228     0.228 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/STATUS_COMMON[9]
                         net (fo=1, routed)           0.502     0.730    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_55_0[9]
    SLICE_X117Y116       LUT5 (Prop_G6LUT_SLICEL_I4_O)
                                                      0.050     0.780 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_25/O
                         net (fo=1, routed)           0.146     0.926    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_25_n_0
    SLICE_X114Y116       LUT6 (Prop_H6LUT_SLICEL_I4_O)
                                                      0.015     0.941 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_17/O
                         net (fo=1, routed)           0.021     0.962    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_17_n_0
    SLICE_X114Y116       LUT5 (Prop_F6LUT_SLICEL_I4_O)
                                                      0.035     0.997 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_5/O
                         net (fo=1, routed)           0.225     1.222    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_5_n_0
    SLICE_X108Y109       LUT6 (Prop_A6LUT_SLICEL_I3_O)
                                                      0.041     1.263 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_1/O
                         net (fo=1, routed)           0.016     1.279    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_75
    SLICE_X108Y109       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.501     1.648    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X108Y109       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC3_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.285ns  (logic 0.372ns (28.949%)  route 0.913ns (71.051%))
  Logic Levels:           4  (LUT5=1 LUT6=3)
  Clock Path Skew:        1.647ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.647ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.500ns (routing 0.405ns, distribution 1.095ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC3_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y3           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y3           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[13])
                                                      0.241     0.241 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/STATUS_COMMON[13]
                         net (fo=1, routed)           0.606     0.847    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_55_0[13]
    SLICE_X116Y114       LUT5 (Prop_H6LUT_SLICEL_I4_O)
                                                      0.035     0.882 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_37/O
                         net (fo=1, routed)           0.076     0.958    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_37_n_0
    SLICE_X114Y112       LUT6 (Prop_H6LUT_SLICEL_I5_O)
                                                      0.015     0.973 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_12/O
                         net (fo=1, routed)           0.021     0.994    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_12_n_0
    SLICE_X114Y112       LUT6 (Prop_G6LUT_SLICEL_I2_O)
                                                      0.022     1.016 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_3/O
                         net (fo=1, routed)           0.194     1.210    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_3_n_0
    SLICE_X108Y106       LUT6 (Prop_D6LUT_SLICEL_I1_O)
                                                      0.059     1.269 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_1/O
                         net (fo=1, routed)           0.016     1.285    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_71
    SLICE_X108Y106       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.500     1.647    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X108Y106       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC3_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.366ns  (logic 0.424ns (31.040%)  route 0.942ns (68.960%))
  Logic Levels:           4  (LUT5=1 LUT6=3)
  Clock Path Skew:        1.647ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.647ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.500ns (routing 0.405ns, distribution 1.095ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC3_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y3           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y3           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[12])
                                                      0.274     0.274 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/STATUS_COMMON[12]
                         net (fo=1, routed)           0.569     0.843    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_55_0[12]
    SLICE_X116Y115       LUT5 (Prop_H6LUT_SLICEL_I4_O)
                                                      0.060     0.903 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_18/O
                         net (fo=1, routed)           0.123     1.026    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_18_n_0
    SLICE_X112Y115       LUT6 (Prop_H6LUT_SLICEM_I0_O)
                                                      0.035     1.061 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_10/O
                         net (fo=1, routed)           0.050     1.111    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_10_n_0
    SLICE_X112Y114       LUT6 (Prop_H6LUT_SLICEM_I2_O)
                                                      0.015     1.126 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_3/O
                         net (fo=1, routed)           0.183     1.309    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_3_n_0
    SLICE_X108Y107       LUT6 (Prop_C6LUT_SLICEL_I1_O)
                                                      0.040     1.349 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_1/O
                         net (fo=1, routed)           0.017     1.366    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_72
    SLICE_X108Y107       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.500     1.647    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X108Y107       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC3_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.371ns  (logic 0.430ns (31.364%)  route 0.941ns (68.636%))
  Logic Levels:           4  (LUT5=2 LUT6=2)
  Clock Path Skew:        1.652ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.652ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.505ns (routing 0.405ns, distribution 1.100ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC3_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y3           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y3           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[11])
                                                      0.265     0.265 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/STATUS_COMMON[11]
                         net (fo=1, routed)           0.548     0.813    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_55_0[11]
    SLICE_X117Y116       LUT5 (Prop_A6LUT_SLICEL_I4_O)
                                                      0.035     0.848 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_29/O
                         net (fo=1, routed)           0.134     0.982    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_29_n_0
    SLICE_X114Y116       LUT6 (Prop_C6LUT_SLICEL_I4_O)
                                                      0.035     1.017 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_18/O
                         net (fo=1, routed)           0.031     1.048    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_18_n_0
    SLICE_X114Y116       LUT5 (Prop_G6LUT_SLICEL_I4_O)
                                                      0.060     1.108 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_4/O
                         net (fo=1, routed)           0.211     1.319    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_4_n_0
    SLICE_X108Y109       LUT6 (Prop_H6LUT_SLICEL_I2_O)
                                                      0.035     1.354 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_1/O
                         net (fo=1, routed)           0.017     1.371    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_73
    SLICE_X108Y109       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.505     1.652    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X108Y109       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC3_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.502ns  (logic 0.389ns (25.899%)  route 1.113ns (74.101%))
  Logic Levels:           4  (LUT5=1 LUT6=3)
  Clock Path Skew:        1.635ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.635ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.488ns (routing 0.405ns, distribution 1.083ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC3_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y3           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y3           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[14])
                                                      0.285     0.285 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/STATUS_COMMON[14]
                         net (fo=1, routed)           0.619     0.904    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_55_0[14]
    SLICE_X115Y115       LUT5 (Prop_H6LUT_SLICEM_I4_O)
                                                      0.015     0.919 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_38/O
                         net (fo=1, routed)           0.168     1.087    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_38_n_0
    SLICE_X114Y113       LUT6 (Prop_G6LUT_SLICEL_I3_O)
                                                      0.040     1.127 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_19/O
                         net (fo=1, routed)           0.230     1.357    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_19_n_0
    SLICE_X107Y110       LUT6 (Prop_G6LUT_SLICEM_I0_O)
                                                      0.014     1.371 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_6/O
                         net (fo=1, routed)           0.079     1.450    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_6_n_0
    SLICE_X106Y110       LUT6 (Prop_C6LUT_SLICEL_I5_O)
                                                      0.035     1.485 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_1/O
                         net (fo=1, routed)           0.017     1.502    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_70
    SLICE_X106Y110       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.488     1.635    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X106Y110       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC3_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.557ns  (logic 0.408ns (26.204%)  route 1.149ns (73.796%))
  Logic Levels:           5  (LUT4=1 LUT5=1 LUT6=3)
  Clock Path Skew:        1.633ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.633ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.486ns (routing 0.405ns, distribution 1.081ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC3_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y3           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y3           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[15])
                                                      0.250     0.250 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/STATUS_COMMON[15]
                         net (fo=1, routed)           0.596     0.846    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_55_0[15]
    SLICE_X117Y115       LUT4 (Prop_F6LUT_SLICEL_I0_O)
                                                      0.022     0.868 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_84/O
                         net (fo=1, routed)           0.145     1.013    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_84_n_0
    SLICE_X113Y113       LUT5 (Prop_G6LUT_SLICEM_I2_O)
                                                      0.022     1.035 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_55/O
                         net (fo=1, routed)           0.054     1.089    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_55_n_0
    SLICE_X113Y111       LUT6 (Prop_G6LUT_SLICEM_I3_O)
                                                      0.050     1.139 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_25/O
                         net (fo=1, routed)           0.110     1.249    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_25_n_0
    SLICE_X112Y107       LUT6 (Prop_H6LUT_SLICEM_I5_O)
                                                      0.023     1.272 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_5/O
                         net (fo=1, routed)           0.228     1.500    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_5_n_0
    SLICE_X106Y104       LUT6 (Prop_D6LUT_SLICEL_I4_O)
                                                      0.041     1.541 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_1/O
                         net (fo=1, routed)           0.016     1.557    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_69
    SLICE_X106Y104       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.486     1.633    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X106Y104       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  RFDAC0_CLK
  To Clock:  clk_pl_0

Max Delay            10 Endpoints
Min Delay            10 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/cdc_dac1_clk_valid_i/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.301ns  (logic 0.244ns (10.604%)  route 2.057ns (89.396%))
  Logic Levels:           2  (BUFGCE=1 LUT1=1)
  Clock Path Skew:        -1.430ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.345ns
    Source Clock Delay      (SCD):    3.774ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      3.101ns (routing 1.460ns, distribution 1.641ns)
  Clock Net Delay (Destination): 2.163ns (routing 0.599ns, distribution 1.564ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y100       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89456, routed)       3.101     3.774    d_1_i/rst_dac0/U0/slowest_sync_clk
    SLICE_X86Y270        FDRE                                         r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X86Y270        FDRE (Prop_AFF_SLICEM_C_Q)
                                                      0.077     3.851 r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           0.590     4.441    d_1_i/rst_dac0/U0/peripheral_aresetn[0]
    BUFGCE_X0Y101        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     4.469 r  d_1_i/rst_dac0/U0/peripheral_aresetn[0]_BUFG_inst/O
                         net (fo=29042, routed)       1.444     5.913    d_1_i/usp_rf_data_converter_0/inst/cdc_dac1_clk_valid_i/src_in
    SLICE_X113Y143       LUT1 (Prop_A5LUT_SLICEM_I0_O)
                                                      0.139     6.052 r  d_1_i/usp_rf_data_converter_0/inst/cdc_dac1_clk_valid_i/syncstages_ff_reg[0]_xlnx_opt/O
                         net (fo=1, routed)           0.023     6.075    d_1_i/usp_rf_data_converter_0/inst/cdc_dac1_clk_valid_i/syncstages_ff_reg[0]_xlnx_opt_1
    SLICE_X113Y143       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/cdc_dac1_clk_valid_i/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       2.163     2.345    d_1_i/usp_rf_data_converter_0/inst/cdc_dac1_clk_valid_i/dest_clk
    SLICE_X113Y143       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/cdc_dac1_clk_valid_i/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/cdc_dac0_clk_valid_i/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.277ns  (logic 0.266ns (11.682%)  route 2.011ns (88.318%))
  Logic Levels:           2  (BUFGCE=1 LUT1=1)
  Clock Path Skew:        -1.480ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.295ns
    Source Clock Delay      (SCD):    3.774ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      3.101ns (routing 1.460ns, distribution 1.641ns)
  Clock Net Delay (Destination): 2.113ns (routing 0.599ns, distribution 1.514ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y100       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89456, routed)       3.101     3.774    d_1_i/rst_dac0/U0/slowest_sync_clk
    SLICE_X86Y270        FDRE                                         r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X86Y270        FDRE (Prop_AFF_SLICEM_C_Q)
                                                      0.077     3.851 r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           0.590     4.441    d_1_i/rst_dac0/U0/peripheral_aresetn[0]
    BUFGCE_X0Y101        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     4.469 r  d_1_i/rst_dac0/U0/peripheral_aresetn[0]_BUFG_inst/O
                         net (fo=29042, routed)       1.404     5.873    d_1_i/usp_rf_data_converter_0/inst/cdc_dac0_clk_valid_i/src_in
    SLICE_X105Y142       LUT1 (Prop_A5LUT_SLICEL_I0_O)
                                                      0.161     6.034 r  d_1_i/usp_rf_data_converter_0/inst/cdc_dac0_clk_valid_i/syncstages_ff_reg[0]_xlnx_opt/O
                         net (fo=1, routed)           0.017     6.051    d_1_i/usp_rf_data_converter_0/inst/cdc_dac0_clk_valid_i/syncstages_ff_reg[0]_xlnx_opt_1
    SLICE_X105Y142       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/cdc_dac0_clk_valid_i/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       2.113     2.295    d_1_i/usp_rf_data_converter_0/inst/cdc_dac0_clk_valid_i/dest_clk
    SLICE_X105Y142       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/cdc_dac0_clk_valid_i/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell HSDAC clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        4.444ns  (logic 1.332ns (29.973%)  route 3.112ns (70.027%))
  Logic Levels:           5  (LUT5=1 LUT6=4)
  Clock Path Skew:        2.352ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.352ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.170ns (routing 0.599ns, distribution 1.571ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[11])
                                                      0.753     0.753 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/STATUS_COMMON[11]
                         net (fo=1, routed)           1.871     2.624    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_31_0[11]
    SLICE_X104Y122       LUT6 (Prop_D6LUT_SLICEM_I5_O)
                                                      0.145     2.769 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_48/O
                         net (fo=1, routed)           0.214     2.983    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_48_n_0
    SLICE_X100Y123       LUT6 (Prop_H6LUT_SLICEL_I0_O)
                                                      0.099     3.082 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_39/O
                         net (fo=1, routed)           0.417     3.499    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_39_n_0
    SLICE_X106Y123       LUT5 (Prop_A6LUT_SLICEL_I1_O)
                                                      0.149     3.648 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_23/O
                         net (fo=1, routed)           0.093     3.741    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_23_n_0
    SLICE_X106Y120       LUT6 (Prop_H6LUT_SLICEL_I5_O)
                                                      0.036     3.777 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_6/O
                         net (fo=1, routed)           0.466     4.243    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_6_n_0
    SLICE_X108Y109       LUT6 (Prop_H6LUT_SLICEL_I5_O)
                                                      0.150     4.393 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_1/O
                         net (fo=1, routed)           0.051     4.444    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_73
    SLICE_X108Y109       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       2.170     2.352    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X108Y109       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell HSDAC clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        4.338ns  (logic 1.260ns (29.046%)  route 3.078ns (70.954%))
  Logic Levels:           5  (LUT4=1 LUT5=1 LUT6=3)
  Clock Path Skew:        2.322ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.322ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.140ns (routing 0.599ns, distribution 1.541ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[15])
                                                      0.840     0.840 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/STATUS_COMMON[15]
                         net (fo=1, routed)           1.868     2.708    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_31_0[15]
    SLICE_X101Y128       LUT4 (Prop_B6LUT_SLICEL_I0_O)
                                                      0.124     2.832 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_65/O
                         net (fo=1, routed)           0.149     2.981    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_65_n_0
    SLICE_X101Y126       LUT5 (Prop_G6LUT_SLICEL_I3_O)
                                                      0.050     3.031 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_31/O
                         net (fo=1, routed)           0.330     3.361    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_31_n_0
    SLICE_X105Y125       LUT6 (Prop_B6LUT_SLICEL_I0_O)
                                                      0.036     3.397 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_11/O
                         net (fo=1, routed)           0.317     3.714    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_11_n_0
    SLICE_X106Y124       LUT6 (Prop_C6LUT_SLICEL_I5_O)
                                                      0.088     3.802 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_2/O
                         net (fo=1, routed)           0.365     4.167    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_2_n_0
    SLICE_X106Y104       LUT6 (Prop_D6LUT_SLICEL_I0_O)
                                                      0.122     4.289 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_1/O
                         net (fo=1, routed)           0.049     4.338    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_69
    SLICE_X106Y104       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       2.140     2.322    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X106Y104       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell HSDAC clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        4.280ns  (logic 1.344ns (31.402%)  route 2.936ns (68.598%))
  Logic Levels:           4  (LUT5=2 LUT6=2)
  Clock Path Skew:        2.348ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.348ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.166ns (routing 0.599ns, distribution 1.567ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[13])
                                                      1.059     1.059 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/STATUS_COMMON[13]
                         net (fo=1, routed)           1.818     2.877    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_31_0[13]
    SLICE_X101Y124       LUT5 (Prop_G6LUT_SLICEL_I4_O)
                                                      0.123     3.000 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_33/O
                         net (fo=1, routed)           0.086     3.086    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_33_n_0
    SLICE_X100Y124       LUT6 (Prop_H6LUT_SLICEL_I5_O)
                                                      0.090     3.176 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_10/O
                         net (fo=1, routed)           0.676     3.852    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_10_n_0
    SLICE_X108Y124       LUT5 (Prop_H6LUT_SLICEL_I3_O)
                                                      0.036     3.888 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_2/O
                         net (fo=1, routed)           0.307     4.195    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_2_n_0
    SLICE_X108Y106       LUT6 (Prop_D6LUT_SLICEL_I0_O)
                                                      0.036     4.231 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_1/O
                         net (fo=1, routed)           0.049     4.280    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_71
    SLICE_X108Y106       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       2.166     2.348    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X108Y106       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell HSDAC clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        4.160ns  (logic 1.160ns (27.885%)  route 3.000ns (72.115%))
  Logic Levels:           4  (LUT5=2 LUT6=2)
  Clock Path Skew:        2.348ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.348ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.166ns (routing 0.599ns, distribution 1.567ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[10])
                                                      0.753     0.753 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/STATUS_COMMON[10]
                         net (fo=1, routed)           1.923     2.676    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_31_0[10]
    SLICE_X105Y128       LUT5 (Prop_F6LUT_SLICEL_I4_O)
                                                      0.148     2.824 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_26/O
                         net (fo=1, routed)           0.177     3.001    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_26_n_0
    SLICE_X106Y126       LUT6 (Prop_H6LUT_SLICEL_I2_O)
                                                      0.036     3.037 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_17/O
                         net (fo=1, routed)           0.436     3.473    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_17_n_0
    SLICE_X108Y126       LUT6 (Prop_H6LUT_SLICEL_I0_O)
                                                      0.090     3.563 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_5/O
                         net (fo=1, routed)           0.449     4.012    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_5_n_0
    SLICE_X108Y107       LUT5 (Prop_D5LUT_SLICEL_I4_O)
                                                      0.133     4.145 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_1/O
                         net (fo=1, routed)           0.015     4.160    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_74
    SLICE_X108Y107       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       2.166     2.348    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X108Y107       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell HSDAC clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        4.036ns  (logic 1.229ns (30.451%)  route 2.807ns (69.549%))
  Logic Levels:           5  (LUT5=1 LUT6=4)
  Clock Path Skew:        2.350ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.350ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.168ns (routing 0.599ns, distribution 1.569ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[8])
                                                      0.731     0.731 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/STATUS_COMMON[8]
                         net (fo=1, routed)           1.727     2.458    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_31_0[8]
    SLICE_X105Y126       LUT6 (Prop_G6LUT_SLICEL_I5_O)
                                                      0.149     2.607 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_30/O
                         net (fo=1, routed)           0.092     2.699    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_30_n_0
    SLICE_X105Y124       LUT6 (Prop_H6LUT_SLICEL_I5_O)
                                                      0.036     2.735 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_21/O
                         net (fo=1, routed)           0.246     2.981    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_21_n_0
    SLICE_X106Y126       LUT5 (Prop_E6LUT_SLICEL_I0_O)
                                                      0.123     3.104 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_8/O
                         net (fo=1, routed)           0.147     3.251    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_8_n_0
    SLICE_X107Y126       LUT6 (Prop_E6LUT_SLICEM_I2_O)
                                                      0.100     3.351 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_2/O
                         net (fo=1, routed)           0.546     3.897    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_2_n_0
    SLICE_X108Y109       LUT6 (Prop_B6LUT_SLICEL_I0_O)
                                                      0.090     3.987 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_1/O
                         net (fo=1, routed)           0.049     4.036    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_76
    SLICE_X108Y109       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       2.168     2.350    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X108Y109       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell HSDAC clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.806ns  (logic 0.969ns (25.460%)  route 2.837ns (74.540%))
  Logic Levels:           4  (LUT5=2 LUT6=2)
  Clock Path Skew:        2.348ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.348ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.166ns (routing 0.599ns, distribution 1.567ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[12])
                                                      0.759     0.759 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/STATUS_COMMON[12]
                         net (fo=1, routed)           1.767     2.526    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_31_0[12]
    SLICE_X104Y129       LUT5 (Prop_C6LUT_SLICEM_I4_O)
                                                      0.088     2.614 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_17/O
                         net (fo=1, routed)           0.086     2.700    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_17_n_0
    SLICE_X104Y127       LUT6 (Prop_G6LUT_SLICEM_I5_O)
                                                      0.037     2.737 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_9/O
                         net (fo=1, routed)           0.295     3.032    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_9_n_0
    SLICE_X106Y126       LUT5 (Prop_F6LUT_SLICEL_I3_O)
                                                      0.035     3.067 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_2/O
                         net (fo=1, routed)           0.639     3.706    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_2_n_0
    SLICE_X108Y107       LUT6 (Prop_C6LUT_SLICEL_I0_O)
                                                      0.050     3.756 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_1/O
                         net (fo=1, routed)           0.050     3.806    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_72
    SLICE_X108Y107       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       2.166     2.348    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X108Y107       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell HSDAC clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.785ns  (logic 1.028ns (27.160%)  route 2.757ns (72.840%))
  Logic Levels:           5  (LUT5=1 LUT6=4)
  Clock Path Skew:        2.350ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.350ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.168ns (routing 0.599ns, distribution 1.569ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[9])
                                                      0.674     0.674 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/STATUS_COMMON[9]
                         net (fo=1, routed)           1.787     2.461    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_31_0[9]
    SLICE_X104Y122       LUT6 (Prop_F6LUT_SLICEM_I5_O)
                                                      0.088     2.549 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_27/O
                         net (fo=1, routed)           0.082     2.631    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_27_n_0
    SLICE_X104Y121       LUT6 (Prop_F6LUT_SLICEM_I5_O)
                                                      0.051     2.682 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_19/O
                         net (fo=1, routed)           0.169     2.851    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_19_n_0
    SLICE_X106Y121       LUT5 (Prop_F6LUT_SLICEL_I0_O)
                                                      0.089     2.940 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_9/O
                         net (fo=1, routed)           0.201     3.141    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_9_n_0
    SLICE_X106Y117       LUT6 (Prop_H6LUT_SLICEL_I4_O)
                                                      0.036     3.177 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_2/O
                         net (fo=1, routed)           0.470     3.647    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_2_n_0
    SLICE_X108Y109       LUT6 (Prop_A6LUT_SLICEL_I0_O)
                                                      0.090     3.737 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_1/O
                         net (fo=1, routed)           0.048     3.785    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_75
    SLICE_X108Y109       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       2.168     2.350    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X108Y109       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell HSDAC clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.709ns  (logic 1.096ns (29.550%)  route 2.613ns (70.450%))
  Logic Levels:           4  (LUT3=1 LUT6=3)
  Clock Path Skew:        2.326ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.326ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.144ns (routing 0.599ns, distribution 1.545ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[14])
                                                      0.779     0.779 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/STATUS_COMMON[14]
                         net (fo=1, routed)           1.785     2.564    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_31_0[14]
    SLICE_X105Y128       LUT6 (Prop_B6LUT_SLICEL_I0_O)
                                                      0.036     2.600 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_27/O
                         net (fo=1, routed)           0.146     2.746    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_27_n_0
    SLICE_X105Y127       LUT3 (Prop_E6LUT_SLICEL_I1_O)
                                                      0.099     2.845 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_9/O
                         net (fo=1, routed)           0.320     3.165    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_9_n_0
    SLICE_X106Y125       LUT6 (Prop_H6LUT_SLICEL_I3_O)
                                                      0.036     3.201 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_2/O
                         net (fo=1, routed)           0.312     3.513    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_2_n_0
    SLICE_X106Y110       LUT6 (Prop_C6LUT_SLICEL_I0_O)
                                                      0.146     3.659 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_1/O
                         net (fo=1, routed)           0.050     3.709    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_70
    SLICE_X106Y110       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       2.144     2.326    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X106Y110       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell HSDAC clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.845ns  (logic 0.528ns (28.618%)  route 1.317ns (71.382%))
  Logic Levels:           4  (LUT3=1 LUT6=3)
  Clock Path Skew:        1.635ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.635ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.488ns (routing 0.405ns, distribution 1.083ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[14])
                                                      0.398     0.398 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/STATUS_COMMON[14]
                         net (fo=1, routed)           0.903     1.301    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_31_0[14]
    SLICE_X105Y128       LUT6 (Prop_B6LUT_SLICEL_I0_O)
                                                      0.015     1.316 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_27/O
                         net (fo=1, routed)           0.072     1.388    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_27_n_0
    SLICE_X105Y127       LUT3 (Prop_E6LUT_SLICEL_I1_O)
                                                      0.041     1.429 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_9/O
                         net (fo=1, routed)           0.162     1.591    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_9_n_0
    SLICE_X106Y125       LUT6 (Prop_H6LUT_SLICEL_I3_O)
                                                      0.015     1.606 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_2/O
                         net (fo=1, routed)           0.163     1.769    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_2_n_0
    SLICE_X106Y110       LUT6 (Prop_C6LUT_SLICEL_I0_O)
                                                      0.059     1.828 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_1/O
                         net (fo=1, routed)           0.017     1.845    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_70
    SLICE_X106Y110       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.488     1.635    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X106Y110       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell HSDAC clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.862ns  (logic 0.480ns (25.779%)  route 1.382ns (74.221%))
  Logic Levels:           5  (LUT5=1 LUT6=4)
  Clock Path Skew:        1.648ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.648ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.501ns (routing 0.405ns, distribution 1.096ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[9])
                                                      0.338     0.338 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/STATUS_COMMON[9]
                         net (fo=1, routed)           0.895     1.233    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_31_0[9]
    SLICE_X104Y122       LUT6 (Prop_F6LUT_SLICEM_I5_O)
                                                      0.035     1.268 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_27/O
                         net (fo=1, routed)           0.045     1.313    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_27_n_0
    SLICE_X104Y121       LUT6 (Prop_F6LUT_SLICEM_I5_O)
                                                      0.022     1.335 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_19/O
                         net (fo=1, routed)           0.090     1.425    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_19_n_0
    SLICE_X106Y121       LUT5 (Prop_F6LUT_SLICEL_I0_O)
                                                      0.035     1.460 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_9/O
                         net (fo=1, routed)           0.103     1.563    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_9_n_0
    SLICE_X106Y117       LUT6 (Prop_H6LUT_SLICEL_I4_O)
                                                      0.015     1.578 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_2/O
                         net (fo=1, routed)           0.233     1.811    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_2_n_0
    SLICE_X108Y109       LUT6 (Prop_A6LUT_SLICEL_I0_O)
                                                      0.035     1.846 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_1/O
                         net (fo=1, routed)           0.016     1.862    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_75
    SLICE_X108Y109       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.501     1.648    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X108Y109       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell HSDAC clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.902ns  (logic 0.471ns (24.763%)  route 1.431ns (75.237%))
  Logic Levels:           4  (LUT5=2 LUT6=2)
  Clock Path Skew:        1.647ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.647ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.500ns (routing 0.405ns, distribution 1.095ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[12])
                                                      0.386     0.386 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/STATUS_COMMON[12]
                         net (fo=1, routed)           0.890     1.276    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_31_0[12]
    SLICE_X104Y129       LUT5 (Prop_C6LUT_SLICEM_I4_O)
                                                      0.035     1.311 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_17/O
                         net (fo=1, routed)           0.046     1.357    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_17_n_0
    SLICE_X104Y127       LUT6 (Prop_G6LUT_SLICEM_I5_O)
                                                      0.014     1.371 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_9/O
                         net (fo=1, routed)           0.144     1.515    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_9_n_0
    SLICE_X106Y126       LUT5 (Prop_F6LUT_SLICEL_I3_O)
                                                      0.014     1.529 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_2/O
                         net (fo=1, routed)           0.334     1.863    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_2_n_0
    SLICE_X108Y107       LUT6 (Prop_C6LUT_SLICEL_I0_O)
                                                      0.022     1.885 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_1/O
                         net (fo=1, routed)           0.017     1.902    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_72
    SLICE_X108Y107       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.500     1.647    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X108Y107       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell HSDAC clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        2.010ns  (logic 0.583ns (29.005%)  route 1.427ns (70.995%))
  Logic Levels:           5  (LUT5=1 LUT6=4)
  Clock Path Skew:        1.648ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.648ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.501ns (routing 0.405ns, distribution 1.096ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[8])
                                                      0.382     0.382 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/STATUS_COMMON[8]
                         net (fo=1, routed)           0.879     1.261    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_31_0[8]
    SLICE_X105Y126       LUT6 (Prop_G6LUT_SLICEL_I5_O)
                                                      0.060     1.321 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_30/O
                         net (fo=1, routed)           0.048     1.369    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_30_n_0
    SLICE_X105Y124       LUT6 (Prop_H6LUT_SLICEL_I5_O)
                                                      0.015     1.384 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_21/O
                         net (fo=1, routed)           0.124     1.508    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_21_n_0
    SLICE_X106Y126       LUT5 (Prop_E6LUT_SLICEL_I0_O)
                                                      0.050     1.558 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_8/O
                         net (fo=1, routed)           0.074     1.632    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_8_n_0
    SLICE_X107Y126       LUT6 (Prop_E6LUT_SLICEM_I2_O)
                                                      0.040     1.672 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_2/O
                         net (fo=1, routed)           0.287     1.959    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_2_n_0
    SLICE_X108Y109       LUT6 (Prop_B6LUT_SLICEL_I0_O)
                                                      0.036     1.995 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_1/O
                         net (fo=1, routed)           0.015     2.010    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_76
    SLICE_X108Y109       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.501     1.648    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X108Y109       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell HSDAC clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        2.037ns  (logic 0.532ns (26.117%)  route 1.505ns (73.883%))
  Logic Levels:           4  (LUT5=2 LUT6=2)
  Clock Path Skew:        1.647ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.647ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.500ns (routing 0.405ns, distribution 1.095ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[10])
                                                      0.375     0.375 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/STATUS_COMMON[10]
                         net (fo=1, routed)           0.971     1.346    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_31_0[10]
    SLICE_X105Y128       LUT5 (Prop_F6LUT_SLICEL_I4_O)
                                                      0.059     1.405 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_26/O
                         net (fo=1, routed)           0.093     1.498    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_26_n_0
    SLICE_X106Y126       LUT6 (Prop_H6LUT_SLICEL_I2_O)
                                                      0.015     1.513 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_17/O
                         net (fo=1, routed)           0.208     1.721    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_17_n_0
    SLICE_X108Y126       LUT6 (Prop_H6LUT_SLICEL_I0_O)
                                                      0.035     1.756 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_5/O
                         net (fo=1, routed)           0.227     1.983    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_5_n_0
    SLICE_X108Y107       LUT5 (Prop_D5LUT_SLICEL_I4_O)
                                                      0.048     2.031 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_1/O
                         net (fo=1, routed)           0.006     2.037    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_74
    SLICE_X108Y107       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.500     1.647    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X108Y107       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell HSDAC clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        2.084ns  (logic 0.638ns (30.614%)  route 1.446ns (69.386%))
  Logic Levels:           4  (LUT5=2 LUT6=2)
  Clock Path Skew:        1.647ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.647ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.500ns (routing 0.405ns, distribution 1.095ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[13])
                                                      0.524     0.524 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/STATUS_COMMON[13]
                         net (fo=1, routed)           0.908     1.432    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_31_0[13]
    SLICE_X101Y124       LUT5 (Prop_G6LUT_SLICEL_I4_O)
                                                      0.050     1.482 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_33/O
                         net (fo=1, routed)           0.046     1.528    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_33_n_0
    SLICE_X100Y124       LUT6 (Prop_H6LUT_SLICEL_I5_O)
                                                      0.035     1.563 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_10/O
                         net (fo=1, routed)           0.319     1.882    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_10_n_0
    SLICE_X108Y124       LUT5 (Prop_H6LUT_SLICEL_I3_O)
                                                      0.015     1.897 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_2/O
                         net (fo=1, routed)           0.157     2.054    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_2_n_0
    SLICE_X108Y106       LUT6 (Prop_D6LUT_SLICEL_I0_O)
                                                      0.014     2.068 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_1/O
                         net (fo=1, routed)           0.016     2.084    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_71
    SLICE_X108Y106       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.500     1.647    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X108Y106       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell HSDAC clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        2.104ns  (logic 0.585ns (27.804%)  route 1.519ns (72.196%))
  Logic Levels:           5  (LUT4=1 LUT5=1 LUT6=3)
  Clock Path Skew:        1.633ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.633ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.486ns (routing 0.405ns, distribution 1.081ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[15])
                                                      0.413     0.413 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/STATUS_COMMON[15]
                         net (fo=1, routed)           0.941     1.354    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_31_0[15]
    SLICE_X101Y128       LUT4 (Prop_B6LUT_SLICEL_I0_O)
                                                      0.050     1.404 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_65/O
                         net (fo=1, routed)           0.073     1.477    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_65_n_0
    SLICE_X101Y126       LUT5 (Prop_G6LUT_SLICEL_I3_O)
                                                      0.022     1.499 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_31/O
                         net (fo=1, routed)           0.143     1.642    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_31_n_0
    SLICE_X105Y125       LUT6 (Prop_B6LUT_SLICEL_I0_O)
                                                      0.015     1.657 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_11/O
                         net (fo=1, routed)           0.157     1.814    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_11_n_0
    SLICE_X106Y124       LUT6 (Prop_C6LUT_SLICEL_I5_O)
                                                      0.035     1.849 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_2/O
                         net (fo=1, routed)           0.189     2.038    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_2_n_0
    SLICE_X106Y104       LUT6 (Prop_D6LUT_SLICEL_I0_O)
                                                      0.050     2.088 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_1/O
                         net (fo=1, routed)           0.016     2.104    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_69
    SLICE_X106Y104       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.486     1.633    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X106Y104       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell HSDAC clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        2.158ns  (logic 0.602ns (27.896%)  route 1.556ns (72.104%))
  Logic Levels:           5  (LUT5=1 LUT6=4)
  Clock Path Skew:        1.652ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.652ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.505ns (routing 0.405ns, distribution 1.100ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[11])
                                                      0.367     0.367 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/STATUS_COMMON[11]
                         net (fo=1, routed)           0.944     1.311    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_31_0[11]
    SLICE_X104Y122       LUT6 (Prop_D6LUT_SLICEM_I5_O)
                                                      0.059     1.370 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_48/O
                         net (fo=1, routed)           0.112     1.482    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_48_n_0
    SLICE_X100Y123       LUT6 (Prop_H6LUT_SLICEL_I0_O)
                                                      0.041     1.523 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_39/O
                         net (fo=1, routed)           0.186     1.709    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_39_n_0
    SLICE_X106Y123       LUT5 (Prop_A6LUT_SLICEL_I1_O)
                                                      0.060     1.769 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_23/O
                         net (fo=1, routed)           0.049     1.818    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_23_n_0
    SLICE_X106Y120       LUT6 (Prop_H6LUT_SLICEL_I5_O)
                                                      0.015     1.833 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_6/O
                         net (fo=1, routed)           0.248     2.081    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_6_n_0
    SLICE_X108Y109       LUT6 (Prop_H6LUT_SLICEL_I5_O)
                                                      0.060     2.141 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_1/O
                         net (fo=1, routed)           0.017     2.158    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_73
    SLICE_X108Y109       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.505     1.652    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X108Y109       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/C

Slack:                    inf
  Source:                 d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/cdc_dac0_clk_valid_i/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.214ns  (logic 0.112ns (9.226%)  route 1.102ns (90.774%))
  Logic Levels:           2  (BUFGCE=1 LUT1=1)
  Clock Path Skew:        -0.430ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.607ns
    Source Clock Delay      (SCD):    2.038ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.689ns (routing 0.786ns, distribution 0.903ns)
  Clock Net Delay (Destination): 1.460ns (routing 0.405ns, distribution 1.055ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y100       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89456, routed)       1.689     2.038    d_1_i/rst_dac0/U0/slowest_sync_clk
    SLICE_X86Y270        FDRE                                         r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X86Y270        FDRE (Prop_AFF_SLICEM_C_Q)
                                                      0.038     2.076 r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           0.314     2.390    d_1_i/rst_dac0/U0/peripheral_aresetn[0]
    BUFGCE_X0Y101        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.407 r  d_1_i/rst_dac0/U0/peripheral_aresetn[0]_BUFG_inst/O
                         net (fo=29042, routed)       0.781     3.188    d_1_i/usp_rf_data_converter_0/inst/cdc_dac0_clk_valid_i/src_in
    SLICE_X105Y142       LUT1 (Prop_A5LUT_SLICEL_I0_O)
                                                      0.057     3.245 r  d_1_i/usp_rf_data_converter_0/inst/cdc_dac0_clk_valid_i/syncstages_ff_reg[0]_xlnx_opt/O
                         net (fo=1, routed)           0.007     3.252    d_1_i/usp_rf_data_converter_0/inst/cdc_dac0_clk_valid_i/syncstages_ff_reg[0]_xlnx_opt_1
    SLICE_X105Y142       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/cdc_dac0_clk_valid_i/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.460     1.607    d_1_i/usp_rf_data_converter_0/inst/cdc_dac0_clk_valid_i/dest_clk
    SLICE_X105Y142       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/cdc_dac0_clk_valid_i/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/cdc_dac1_clk_valid_i/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.225ns  (logic 0.103ns (8.408%)  route 1.122ns (91.592%))
  Logic Levels:           2  (BUFGCE=1 LUT1=1)
  Clock Path Skew:        -0.395ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.642ns
    Source Clock Delay      (SCD):    2.038ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.689ns (routing 0.786ns, distribution 0.903ns)
  Clock Net Delay (Destination): 1.495ns (routing 0.405ns, distribution 1.090ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y100       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89456, routed)       1.689     2.038    d_1_i/rst_dac0/U0/slowest_sync_clk
    SLICE_X86Y270        FDRE                                         r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X86Y270        FDRE (Prop_AFF_SLICEM_C_Q)
                                                      0.038     2.076 r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           0.314     2.390    d_1_i/rst_dac0/U0/peripheral_aresetn[0]
    BUFGCE_X0Y101        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.407 r  d_1_i/rst_dac0/U0/peripheral_aresetn[0]_BUFG_inst/O
                         net (fo=29042, routed)       0.801     3.208    d_1_i/usp_rf_data_converter_0/inst/cdc_dac1_clk_valid_i/src_in
    SLICE_X113Y143       LUT1 (Prop_A5LUT_SLICEM_I0_O)
                                                      0.048     3.256 r  d_1_i/usp_rf_data_converter_0/inst/cdc_dac1_clk_valid_i/syncstages_ff_reg[0]_xlnx_opt/O
                         net (fo=1, routed)           0.007     3.263    d_1_i/usp_rf_data_converter_0/inst/cdc_dac1_clk_valid_i/syncstages_ff_reg[0]_xlnx_opt_1
    SLICE_X113Y143       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/cdc_dac1_clk_valid_i/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.495     1.642    d_1_i/usp_rf_data_converter_0/inst/cdc_dac1_clk_valid_i/dest_clk
    SLICE_X113Y143       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/cdc_dac1_clk_valid_i/syncstages_ff_reg[0]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  RFDAC1_CLK
  To Clock:  clk_pl_0

Max Delay             8 Endpoints
Min Delay             8 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell HSDAC clocked by RFDAC1_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        5.032ns  (logic 1.268ns (25.199%)  route 3.764ns (74.801%))
  Logic Levels:           5  (LUT6=5)
  Clock Path Skew:        2.352ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.352ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.170ns (routing 0.599ns, distribution 1.571ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[11])
                                                      0.753     0.753 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[11]
                         net (fo=1, routed)           2.297     3.050    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_28_0[11]
    SLICE_X104Y125       LUT6 (Prop_H6LUT_SLICEM_I5_O)
                                                      0.101     3.151 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_46/O
                         net (fo=1, routed)           0.319     3.470    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_46_n_0
    SLICE_X102Y123       LUT6 (Prop_G6LUT_SLICEL_I0_O)
                                                      0.089     3.559 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_35/O
                         net (fo=1, routed)           0.420     3.979    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_35_n_0
    SLICE_X107Y126       LUT6 (Prop_D6LUT_SLICEM_I2_O)
                                                      0.051     4.030 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_22/O
                         net (fo=1, routed)           0.211     4.241    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_22_n_0
    SLICE_X106Y120       LUT6 (Prop_H6LUT_SLICEL_I4_O)
                                                      0.124     4.365 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_6/O
                         net (fo=1, routed)           0.466     4.831    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_6_n_0
    SLICE_X108Y109       LUT6 (Prop_H6LUT_SLICEL_I5_O)
                                                      0.150     4.981 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_1/O
                         net (fo=1, routed)           0.051     5.032    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_73
    SLICE_X108Y109       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       2.170     2.352    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X108Y109       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell HSDAC clocked by RFDAC1_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        4.708ns  (logic 1.242ns (26.381%)  route 3.466ns (73.619%))
  Logic Levels:           5  (LUT5=1 LUT6=4)
  Clock Path Skew:        2.322ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.322ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.140ns (routing 0.599ns, distribution 1.541ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[15])
                                                      0.840     0.840 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[15]
                         net (fo=1, routed)           2.159     2.999    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_28_0[15]
    SLICE_X106Y128       LUT5 (Prop_F6LUT_SLICEL_I1_O)
                                                      0.089     3.088 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_59/O
                         net (fo=1, routed)           0.206     3.294    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_59_n_0
    SLICE_X105Y127       LUT6 (Prop_F6LUT_SLICEL_I5_O)
                                                      0.089     3.383 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_28/O
                         net (fo=1, routed)           0.376     3.759    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_28_n_0
    SLICE_X104Y124       LUT6 (Prop_G6LUT_SLICEM_I3_O)
                                                      0.052     3.811 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_10/O
                         net (fo=1, routed)           0.311     4.122    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_10_n_0
    SLICE_X106Y124       LUT6 (Prop_C6LUT_SLICEL_I4_O)
                                                      0.050     4.172 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_2/O
                         net (fo=1, routed)           0.365     4.537    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_2_n_0
    SLICE_X106Y104       LUT6 (Prop_D6LUT_SLICEL_I0_O)
                                                      0.122     4.659 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_1/O
                         net (fo=1, routed)           0.049     4.708    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_69
    SLICE_X106Y104       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       2.140     2.322    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X106Y104       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell HSDAC clocked by RFDAC1_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        4.689ns  (logic 1.162ns (24.781%)  route 3.527ns (75.219%))
  Logic Levels:           4  (LUT5=2 LUT6=2)
  Clock Path Skew:        2.348ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.348ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.166ns (routing 0.599ns, distribution 1.567ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[10])
                                                      0.753     0.753 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[10]
                         net (fo=1, routed)           2.616     3.369    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_28_0[10]
    SLICE_X107Y129       LUT5 (Prop_G6LUT_SLICEM_I4_O)
                                                      0.150     3.519 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_28/O
                         net (fo=1, routed)           0.139     3.658    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_28_n_0
    SLICE_X107Y126       LUT6 (Prop_H6LUT_SLICEM_I3_O)
                                                      0.090     3.748 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_18/O
                         net (fo=1, routed)           0.308     4.056    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_18_n_0
    SLICE_X108Y126       LUT6 (Prop_H6LUT_SLICEL_I1_O)
                                                      0.036     4.092 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_5/O
                         net (fo=1, routed)           0.449     4.541    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_5_n_0
    SLICE_X108Y107       LUT5 (Prop_D5LUT_SLICEL_I4_O)
                                                      0.133     4.674 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_1/O
                         net (fo=1, routed)           0.015     4.689    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_74
    SLICE_X108Y107       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       2.166     2.348    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X108Y107       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell HSDAC clocked by RFDAC1_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        4.647ns  (logic 1.223ns (26.318%)  route 3.424ns (73.682%))
  Logic Levels:           5  (LUT6=5)
  Clock Path Skew:        2.350ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.350ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.168ns (routing 0.599ns, distribution 1.569ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[9])
                                                      0.674     0.674 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[9]
                         net (fo=1, routed)           2.298     2.972    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_28_0[9]
    SLICE_X105Y125       LUT6 (Prop_G6LUT_SLICEL_I5_O)
                                                      0.123     3.095 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_28/O
                         net (fo=1, routed)           0.086     3.181    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_28_n_0
    SLICE_X105Y124       LUT6 (Prop_G6LUT_SLICEL_I0_O)
                                                      0.089     3.270 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_20/O
                         net (fo=1, routed)           0.240     3.510    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_20_n_0
    SLICE_X106Y125       LUT6 (Prop_F6LUT_SLICEL_I3_O)
                                                      0.123     3.633 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_10/O
                         net (fo=1, routed)           0.282     3.915    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_10_n_0
    SLICE_X106Y117       LUT6 (Prop_H6LUT_SLICEL_I5_O)
                                                      0.124     4.039 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_2/O
                         net (fo=1, routed)           0.470     4.509    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_2_n_0
    SLICE_X108Y109       LUT6 (Prop_A6LUT_SLICEL_I0_O)
                                                      0.090     4.599 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_1/O
                         net (fo=1, routed)           0.048     4.647    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_75
    SLICE_X108Y109       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       2.168     2.350    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X108Y109       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell HSDAC clocked by RFDAC1_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        4.588ns  (logic 1.252ns (27.289%)  route 3.336ns (72.711%))
  Logic Levels:           5  (LUT4=1 LUT5=1 LUT6=3)
  Clock Path Skew:        2.348ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.348ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.166ns (routing 0.599ns, distribution 1.567ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[12])
                                                      0.759     0.759 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[12]
                         net (fo=1, routed)           1.978     2.737    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_28_0[12]
    SLICE_X108Y128       LUT4 (Prop_F6LUT_SLICEL_I0_O)
                                                      0.123     2.860 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_21/O
                         net (fo=1, routed)           0.402     3.262    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_21_n_0
    SLICE_X106Y127       LUT6 (Prop_H6LUT_SLICEL_I5_O)
                                                      0.124     3.386 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_16/O
                         net (fo=1, routed)           0.181     3.567    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_16_n_0
    SLICE_X106Y127       LUT6 (Prop_D6LUT_SLICEL_I1_O)
                                                      0.099     3.666 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_8/O
                         net (fo=1, routed)           0.086     3.752    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_8_n_0
    SLICE_X106Y126       LUT5 (Prop_F6LUT_SLICEL_I2_O)
                                                      0.097     3.849 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_2/O
                         net (fo=1, routed)           0.639     4.488    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_2_n_0
    SLICE_X108Y107       LUT6 (Prop_C6LUT_SLICEL_I0_O)
                                                      0.050     4.538 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_1/O
                         net (fo=1, routed)           0.050     4.588    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_72
    SLICE_X108Y107       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       2.166     2.348    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X108Y107       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell HSDAC clocked by RFDAC1_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        4.395ns  (logic 1.109ns (25.233%)  route 3.286ns (74.767%))
  Logic Levels:           4  (LUT4=1 LUT6=3)
  Clock Path Skew:        2.350ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.350ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.168ns (routing 0.599ns, distribution 1.569ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[8])
                                                      0.731     0.731 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[8]
                         net (fo=1, routed)           2.302     3.033    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_28_0[8]
    SLICE_X108Y127       LUT4 (Prop_F6LUT_SLICEL_I0_O)
                                                      0.148     3.181 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_22/O
                         net (fo=1, routed)           0.304     3.485    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_22_n_0
    SLICE_X107Y127       LUT6 (Prop_F6LUT_SLICEM_I2_O)
                                                      0.088     3.573 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_10/O
                         net (fo=1, routed)           0.085     3.658    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_10_n_0
    SLICE_X107Y126       LUT6 (Prop_E6LUT_SLICEM_I4_O)
                                                      0.052     3.710 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_2/O
                         net (fo=1, routed)           0.546     4.256    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_2_n_0
    SLICE_X108Y109       LUT6 (Prop_B6LUT_SLICEL_I0_O)
                                                      0.090     4.346 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_1/O
                         net (fo=1, routed)           0.049     4.395    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_76
    SLICE_X108Y109       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       2.168     2.350    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X108Y109       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell HSDAC clocked by RFDAC1_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        4.364ns  (logic 1.306ns (29.927%)  route 3.058ns (70.073%))
  Logic Levels:           5  (LUT4=1 LUT5=1 LUT6=3)
  Clock Path Skew:        2.348ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.348ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.166ns (routing 0.599ns, distribution 1.567ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[13])
                                                      1.059     1.059 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[13]
                         net (fo=1, routed)           2.112     3.171    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_28_0[13]
    SLICE_X106Y129       LUT4 (Prop_G6LUT_SLICEL_I0_O)
                                                      0.035     3.206 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_62/O
                         net (fo=1, routed)           0.092     3.298    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_62_n_0
    SLICE_X106Y127       LUT6 (Prop_G6LUT_SLICEL_I5_O)
                                                      0.035     3.333 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_31/O
                         net (fo=1, routed)           0.093     3.426    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_31_n_0
    SLICE_X107Y127       LUT6 (Prop_H6LUT_SLICEM_I1_O)
                                                      0.090     3.516 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_9/O
                         net (fo=1, routed)           0.405     3.921    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_9_n_0
    SLICE_X108Y124       LUT5 (Prop_H6LUT_SLICEL_I2_O)
                                                      0.051     3.972 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_2/O
                         net (fo=1, routed)           0.307     4.279    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_2_n_0
    SLICE_X108Y106       LUT6 (Prop_D6LUT_SLICEL_I0_O)
                                                      0.036     4.315 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_1/O
                         net (fo=1, routed)           0.049     4.364    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_71
    SLICE_X108Y106       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       2.166     2.348    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X108Y106       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell HSDAC clocked by RFDAC1_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        4.280ns  (logic 1.233ns (28.808%)  route 3.047ns (71.192%))
  Logic Levels:           5  (LUT5=1 LUT6=4)
  Clock Path Skew:        2.326ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.326ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.144ns (routing 0.599ns, distribution 1.545ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[14])
                                                      0.779     0.779 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[14]
                         net (fo=1, routed)           2.287     3.066    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_28_0[14]
    SLICE_X106Y123       LUT5 (Prop_F6LUT_SLICEL_I3_O)
                                                      0.123     3.189 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_50/O
                         net (fo=1, routed)           0.129     3.318    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_50_n_0
    SLICE_X105Y123       LUT6 (Prop_H6LUT_SLICEL_I5_O)
                                                      0.036     3.354 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_24/O
                         net (fo=1, routed)           0.173     3.527    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_24_n_0
    SLICE_X106Y123       LUT6 (Prop_G6LUT_SLICEL_I2_O)
                                                      0.050     3.577 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_8/O
                         net (fo=1, routed)           0.096     3.673    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_8_n_0
    SLICE_X106Y125       LUT6 (Prop_H6LUT_SLICEL_I2_O)
                                                      0.099     3.772 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_2/O
                         net (fo=1, routed)           0.312     4.084    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_2_n_0
    SLICE_X106Y110       LUT6 (Prop_C6LUT_SLICEL_I0_O)
                                                      0.146     4.230 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_1/O
                         net (fo=1, routed)           0.050     4.280    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_70
    SLICE_X106Y110       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       2.144     2.326    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X106Y110       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell HSDAC clocked by RFDAC1_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        2.137ns  (logic 0.585ns (27.375%)  route 1.552ns (72.625%))
  Logic Levels:           5  (LUT5=1 LUT6=4)
  Clock Path Skew:        1.635ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.635ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.488ns (routing 0.405ns, distribution 1.083ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[14])
                                                      0.398     0.398 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[14]
                         net (fo=1, routed)           1.162     1.560    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_28_0[14]
    SLICE_X106Y123       LUT5 (Prop_F6LUT_SLICEL_I3_O)
                                                      0.050     1.610 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_50/O
                         net (fo=1, routed)           0.068     1.678    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_50_n_0
    SLICE_X105Y123       LUT6 (Prop_H6LUT_SLICEL_I5_O)
                                                      0.015     1.693 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_24/O
                         net (fo=1, routed)           0.091     1.784    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_24_n_0
    SLICE_X106Y123       LUT6 (Prop_G6LUT_SLICEL_I2_O)
                                                      0.022     1.806 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_8/O
                         net (fo=1, routed)           0.051     1.857    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_8_n_0
    SLICE_X106Y125       LUT6 (Prop_H6LUT_SLICEL_I2_O)
                                                      0.041     1.898 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_2/O
                         net (fo=1, routed)           0.163     2.061    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_2_n_0
    SLICE_X106Y110       LUT6 (Prop_C6LUT_SLICEL_I0_O)
                                                      0.059     2.120 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_1/O
                         net (fo=1, routed)           0.017     2.137    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_70
    SLICE_X106Y110       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.488     1.635    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X106Y110       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell HSDAC clocked by RFDAC1_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        2.175ns  (logic 0.624ns (28.690%)  route 1.551ns (71.310%))
  Logic Levels:           5  (LUT4=1 LUT5=1 LUT6=3)
  Clock Path Skew:        1.647ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.647ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.500ns (routing 0.405ns, distribution 1.095ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[13])
                                                      0.524     0.524 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[13]
                         net (fo=1, routed)           1.069     1.593    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_28_0[13]
    SLICE_X106Y129       LUT4 (Prop_G6LUT_SLICEL_I0_O)
                                                      0.014     1.607 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_62/O
                         net (fo=1, routed)           0.048     1.655    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_62_n_0
    SLICE_X106Y127       LUT6 (Prop_G6LUT_SLICEL_I5_O)
                                                      0.014     1.669 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_31/O
                         net (fo=1, routed)           0.050     1.719    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_31_n_0
    SLICE_X107Y127       LUT6 (Prop_H6LUT_SLICEM_I1_O)
                                                      0.035     1.754 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_9/O
                         net (fo=1, routed)           0.211     1.965    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_9_n_0
    SLICE_X108Y124       LUT5 (Prop_H6LUT_SLICEL_I2_O)
                                                      0.023     1.988 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_2/O
                         net (fo=1, routed)           0.157     2.145    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_2_n_0
    SLICE_X108Y106       LUT6 (Prop_D6LUT_SLICEL_I0_O)
                                                      0.014     2.159 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_1/O
                         net (fo=1, routed)           0.016     2.175    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_71
    SLICE_X108Y106       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.500     1.647    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X108Y106       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell HSDAC clocked by RFDAC1_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        2.211ns  (logic 0.534ns (24.152%)  route 1.677ns (75.848%))
  Logic Levels:           4  (LUT4=1 LUT6=3)
  Clock Path Skew:        1.648ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.648ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.501ns (routing 0.405ns, distribution 1.096ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[8])
                                                      0.382     0.382 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[8]
                         net (fo=1, routed)           1.167     1.549    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_28_0[8]
    SLICE_X108Y127       LUT4 (Prop_F6LUT_SLICEL_I0_O)
                                                      0.059     1.608 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_22/O
                         net (fo=1, routed)           0.161     1.769    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_22_n_0
    SLICE_X107Y127       LUT6 (Prop_F6LUT_SLICEM_I2_O)
                                                      0.035     1.804 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_10/O
                         net (fo=1, routed)           0.047     1.851    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_10_n_0
    SLICE_X107Y126       LUT6 (Prop_E6LUT_SLICEM_I4_O)
                                                      0.022     1.873 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_2/O
                         net (fo=1, routed)           0.287     2.160    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_2_n_0
    SLICE_X108Y109       LUT6 (Prop_B6LUT_SLICEL_I0_O)
                                                      0.036     2.196 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_1/O
                         net (fo=1, routed)           0.015     2.211    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_76
    SLICE_X108Y109       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.501     1.648    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X108Y109       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell HSDAC clocked by RFDAC1_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        2.270ns  (logic 0.589ns (25.947%)  route 1.681ns (74.053%))
  Logic Levels:           5  (LUT4=1 LUT5=1 LUT6=3)
  Clock Path Skew:        1.647ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.647ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.500ns (routing 0.405ns, distribution 1.095ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[12])
                                                      0.386     0.386 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[12]
                         net (fo=1, routed)           0.998     1.384    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_28_0[12]
    SLICE_X108Y128       LUT4 (Prop_F6LUT_SLICEL_I0_O)
                                                      0.050     1.434 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_21/O
                         net (fo=1, routed)           0.210     1.644    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_21_n_0
    SLICE_X106Y127       LUT6 (Prop_H6LUT_SLICEL_I5_O)
                                                      0.050     1.694 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_16/O
                         net (fo=1, routed)           0.074     1.768    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_16_n_0
    SLICE_X106Y127       LUT6 (Prop_D6LUT_SLICEL_I1_O)
                                                      0.041     1.809 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_8/O
                         net (fo=1, routed)           0.048     1.857    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_8_n_0
    SLICE_X106Y126       LUT5 (Prop_F6LUT_SLICEL_I2_O)
                                                      0.040     1.897 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_2/O
                         net (fo=1, routed)           0.334     2.231    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_2_n_0
    SLICE_X108Y107       LUT6 (Prop_C6LUT_SLICEL_I0_O)
                                                      0.022     2.253 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_1/O
                         net (fo=1, routed)           0.017     2.270    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_72
    SLICE_X108Y107       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.500     1.647    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X108Y107       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell HSDAC clocked by RFDAC1_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        2.289ns  (logic 0.558ns (24.377%)  route 1.731ns (75.623%))
  Logic Levels:           5  (LUT6=5)
  Clock Path Skew:        1.648ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.648ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.501ns (routing 0.405ns, distribution 1.096ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[9])
                                                      0.338     0.338 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[9]
                         net (fo=1, routed)           1.167     1.505    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_28_0[9]
    SLICE_X105Y125       LUT6 (Prop_G6LUT_SLICEL_I5_O)
                                                      0.050     1.555 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_28/O
                         net (fo=1, routed)           0.048     1.603    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_28_n_0
    SLICE_X105Y124       LUT6 (Prop_G6LUT_SLICEL_I0_O)
                                                      0.035     1.638 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_20/O
                         net (fo=1, routed)           0.121     1.759    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_20_n_0
    SLICE_X106Y125       LUT6 (Prop_F6LUT_SLICEL_I3_O)
                                                      0.050     1.809 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_10/O
                         net (fo=1, routed)           0.146     1.955    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_10_n_0
    SLICE_X106Y117       LUT6 (Prop_H6LUT_SLICEL_I5_O)
                                                      0.050     2.005 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_2/O
                         net (fo=1, routed)           0.233     2.238    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_2_n_0
    SLICE_X108Y109       LUT6 (Prop_A6LUT_SLICEL_I0_O)
                                                      0.035     2.273 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_1/O
                         net (fo=1, routed)           0.016     2.289    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_75
    SLICE_X108Y109       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.501     1.648    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X108Y109       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell HSDAC clocked by RFDAC1_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        2.328ns  (logic 0.577ns (24.785%)  route 1.751ns (75.215%))
  Logic Levels:           5  (LUT5=1 LUT6=4)
  Clock Path Skew:        1.633ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.633ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.486ns (routing 0.405ns, distribution 1.081ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[15])
                                                      0.413     0.413 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[15]
                         net (fo=1, routed)           1.094     1.507    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_28_0[15]
    SLICE_X106Y128       LUT5 (Prop_F6LUT_SLICEL_I1_O)
                                                      0.035     1.542 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_59/O
                         net (fo=1, routed)           0.107     1.649    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_59_n_0
    SLICE_X105Y127       LUT6 (Prop_F6LUT_SLICEL_I5_O)
                                                      0.035     1.684 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_28/O
                         net (fo=1, routed)           0.193     1.877    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_28_n_0
    SLICE_X104Y124       LUT6 (Prop_G6LUT_SLICEM_I3_O)
                                                      0.022     1.899 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_10/O
                         net (fo=1, routed)           0.152     2.051    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_10_n_0
    SLICE_X106Y124       LUT6 (Prop_C6LUT_SLICEL_I4_O)
                                                      0.022     2.073 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_2/O
                         net (fo=1, routed)           0.189     2.262    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_2_n_0
    SLICE_X106Y104       LUT6 (Prop_D6LUT_SLICEL_I0_O)
                                                      0.050     2.312 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_1/O
                         net (fo=1, routed)           0.016     2.328    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_69
    SLICE_X106Y104       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.486     1.633    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X106Y104       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell HSDAC clocked by RFDAC1_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        2.329ns  (logic 0.533ns (22.885%)  route 1.796ns (77.115%))
  Logic Levels:           4  (LUT5=2 LUT6=2)
  Clock Path Skew:        1.647ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.647ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.500ns (routing 0.405ns, distribution 1.095ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[10])
                                                      0.375     0.375 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[10]
                         net (fo=1, routed)           1.326     1.701    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_28_0[10]
    SLICE_X107Y129       LUT5 (Prop_G6LUT_SLICEM_I4_O)
                                                      0.060     1.761 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_28/O
                         net (fo=1, routed)           0.075     1.836    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_28_n_0
    SLICE_X107Y126       LUT6 (Prop_H6LUT_SLICEM_I3_O)
                                                      0.035     1.871 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_18/O
                         net (fo=1, routed)           0.162     2.033    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_18_n_0
    SLICE_X108Y126       LUT6 (Prop_H6LUT_SLICEL_I1_O)
                                                      0.015     2.048 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_5/O
                         net (fo=1, routed)           0.227     2.275    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_5_n_0
    SLICE_X108Y107       LUT5 (Prop_D5LUT_SLICEL_I4_O)
                                                      0.048     2.323 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_1/O
                         net (fo=1, routed)           0.006     2.329    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_74
    SLICE_X108Y107       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.500     1.647    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X108Y107       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell HSDAC clocked by RFDAC1_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        2.479ns  (logic 0.575ns (23.195%)  route 1.904ns (76.805%))
  Logic Levels:           5  (LUT6=5)
  Clock Path Skew:        1.652ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.652ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.505ns (routing 0.405ns, distribution 1.100ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[11])
                                                      0.367     0.367 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[11]
                         net (fo=1, routed)           1.157     1.524    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_28_0[11]
    SLICE_X104Y125       LUT6 (Prop_H6LUT_SLICEM_I5_O)
                                                      0.041     1.565 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_46/O
                         net (fo=1, routed)           0.159     1.724    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_46_n_0
    SLICE_X102Y123       LUT6 (Prop_G6LUT_SLICEL_I0_O)
                                                      0.035     1.759 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_35/O
                         net (fo=1, routed)           0.214     1.973    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_35_n_0
    SLICE_X107Y126       LUT6 (Prop_D6LUT_SLICEM_I2_O)
                                                      0.022     1.995 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_22/O
                         net (fo=1, routed)           0.109     2.104    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_22_n_0
    SLICE_X106Y120       LUT6 (Prop_H6LUT_SLICEL_I4_O)
                                                      0.050     2.154 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_6/O
                         net (fo=1, routed)           0.248     2.402    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_6_n_0
    SLICE_X108Y109       LUT6 (Prop_H6LUT_SLICEL_I5_O)
                                                      0.060     2.462 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_1/O
                         net (fo=1, routed)           0.017     2.479    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_73
    SLICE_X108Y109       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.505     1.652    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X108Y109       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  clk_out1_d_1_clk_adc0_x2_0
  To Clock:  clk_pl_0

Max Delay           269 Endpoints
Min Delay           269 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/FABRIC_CLK
                            (rising edge-triggered cell HSADC clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[5]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.419ns  (logic 0.625ns (25.837%)  route 1.794ns (74.163%))
  Logic Levels:           3  (LUT6=3)
  Clock Path Skew:        -4.267ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.346ns
    Source Clock Delay      (SCD):    6.613ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.243ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.323ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      3.283ns (routing 1.545ns, distribution 1.738ns)
  Clock Net Delay (Destination): 2.164ns (routing 0.599ns, distribution 1.565ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.657     3.184    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     3.057 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     3.302    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.330 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86296, routed)       3.283     6.613    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/m0_axis_aclk
    HSADC_X0Y0           HSADC                                        r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/FABRIC_CLK
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y0           HSADC (Prop_HSADC_FABRIC_CLK_STATUS_COMMON[5])
                                                      0.450     7.063 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/STATUS_COMMON[5]
                         net (fo=1, routed)           1.208     8.271    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/STATUS_COMMON[5]
    SLICE_X106Y97        LUT6 (Prop_H6LUT_SLICEL_I3_O)
                                                      0.051     8.322 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_12/O
                         net (fo=1, routed)           0.094     8.416    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_12_n_0
    SLICE_X106Y100       LUT6 (Prop_B6LUT_SLICEL_I1_O)
                                                      0.036     8.452 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_4/O
                         net (fo=1, routed)           0.442     8.894    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_4_n_0
    SLICE_X108Y104       LUT6 (Prop_C6LUT_SLICEL_I2_O)
                                                      0.088     8.982 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_1/O
                         net (fo=1, routed)           0.050     9.032    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_79
    SLICE_X108Y104       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[5]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       2.164     2.346    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X108Y104       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[5]/C

Slack:                    inf
  Source:                 d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/cdc_adc0_clk_valid_i/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.014ns  (logic 0.079ns (7.789%)  route 0.935ns (92.211%))
  Logic Levels:           0  
  Clock Path Skew:        -4.188ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.342ns
    Source Clock Delay      (SCD):    6.530ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.243ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.323ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      3.200ns (routing 1.545ns, distribution 1.655ns)
  Clock Net Delay (Destination): 2.160ns (routing 0.599ns, distribution 1.561ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.657     3.184    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     3.057 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     3.302    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.330 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86296, routed)       3.200     6.530    d_1_i/rst_adc0_x2/U0/slowest_sync_clk
    SLICE_X108Y118       FDRE                                         r  d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X108Y118       FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     6.609 r  d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=2, routed)           0.935     7.544    d_1_i/usp_rf_data_converter_0/inst/cdc_adc0_clk_valid_i/src_in
    SLICE_X108Y99        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/cdc_adc0_clk_valid_i/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       2.160     2.342    d_1_i/usp_rf_data_converter_0/inst/cdc_adc0_clk_valid_i/dest_clk
    SLICE_X108Y99        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/cdc_adc0_clk_valid_i/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/cdc_adc2_clk_valid_i/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.730ns  (logic 0.079ns (10.819%)  route 0.651ns (89.181%))
  Logic Levels:           0  
  Clock Path Skew:        -4.189ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.341ns
    Source Clock Delay      (SCD):    6.530ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.243ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.323ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      3.200ns (routing 1.545ns, distribution 1.655ns)
  Clock Net Delay (Destination): 2.159ns (routing 0.599ns, distribution 1.560ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.657     3.184    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     3.057 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     3.302    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.330 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86296, routed)       3.200     6.530    d_1_i/rst_adc0_x2/U0/slowest_sync_clk
    SLICE_X108Y118       FDRE                                         r  d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X108Y118       FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     6.609 r  d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=2, routed)           0.651     7.260    d_1_i/usp_rf_data_converter_0/inst/cdc_adc2_clk_valid_i/src_in
    SLICE_X108Y122       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/cdc_adc2_clk_valid_i/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       2.159     2.341    d_1_i/usp_rf_data_converter_0/inst/cdc_adc2_clk_valid_i/dest_clk
    SLICE_X108Y122       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/cdc_adc2_clk_valid_i/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_req_ff_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.482ns  (logic 0.079ns (16.380%)  route 0.403ns (83.620%))
  Logic Levels:           0  
  Clock Path Skew:        -4.283ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    1.998ns
    Source Clock Delay      (SCD):    6.281ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.243ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.323ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      2.951ns (routing 1.545ns, distribution 1.406ns)
  Clock Net Delay (Destination): 1.816ns (routing 0.599ns, distribution 1.217ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.657     3.184    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     3.057 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     3.302    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.330 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86296, routed)       2.951     6.281    d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_clk
    SLICE_X55Y206        FDRE                                         r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_req_ff_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X55Y206        FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.079     6.360 r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_req_ff_reg/Q
                         net (fo=2, routed)           0.403     6.763    d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/src_in
    SLICE_X56Y194        FDRE                                         r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.816     1.998    d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/dest_clk
    SLICE_X56Y194        FDRE                                         r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_req_ff_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.303ns  (logic 0.078ns (25.740%)  route 0.225ns (74.261%))
  Logic Levels:           0  
  Clock Path Skew:        -4.205ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.239ns
    Source Clock Delay      (SCD):    6.444ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.243ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.323ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      3.114ns (routing 1.545ns, distribution 1.569ns)
  Clock Net Delay (Destination): 2.057ns (routing 0.599ns, distribution 1.458ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.657     3.184    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     3.057 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     3.302    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.330 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86296, routed)       3.114     6.444    d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_clk
    SLICE_X87Y70         FDRE                                         r  d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_req_ff_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X87Y70         FDRE (Prop_DFF_SLICEM_C_Q)
                                                      0.078     6.522 r  d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_req_ff_reg/Q
                         net (fo=2, routed)           0.225     6.747    d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/src_in
    SLICE_X85Y70         FDRE                                         r  d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       2.057     2.239    d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/dest_clk
    SLICE_X85Y70         FDRE                                         r  d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/wptr_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/wptr_g_i/data_int_reg_reg[0][0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.077ns  (logic 0.231ns (11.122%)  route 1.846ns (88.878%))
  Logic Levels:           1  (LUT2=1)
  Clock Path Skew:        -4.080ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.239ns
    Source Clock Delay      (SCD):    6.319ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.243ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.323ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      2.989ns (routing 1.545ns, distribution 1.444ns)
  Clock Net Delay (Destination): 2.057ns (routing 0.599ns, distribution 1.458ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.657     3.184    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     3.057 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     3.302    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.330 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86296, routed)       2.989     6.319    d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/s_axis_aclk
    SLICE_X80Y61         FDRE                                         r  d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/wptr_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X80Y61         FDRE (Prop_DFF2_SLICEL_C_Q)
                                                      0.081     6.400 r  d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/wptr_reg[0]/Q
                         net (fo=83, routed)          0.750     7.150    d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/wptr_g_i/Q[0]
    SLICE_X81Y57         LUT2 (Prop_H6LUT_SLICEL_I0_O)
                                                      0.150     7.300 r  d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/wptr_g_i/wptr[1]_i_1__1/O
                         net (fo=2, routed)           1.096     8.396    d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/wptr_g_i/D[0]
    SLICE_X81Y57         FDRE                                         r  d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/wptr_g_i/data_int_reg_reg[0][0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       2.057     2.239    d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/wptr_g_i/m_axis_aclk
    SLICE_X81Y57         FDRE                                         r  d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/wptr_g_i/data_int_reg_reg[0][0]/C

Slack:                    inf
  Source:                 d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/RAM_reg_0_3_56_63/RAMA_D1/CLK
                            (rising edge-triggered cell RAMD32 clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/dob_reg[57]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.468ns  (logic 0.305ns (20.777%)  route 1.163ns (79.223%))
  Logic Levels:           0  
  Clock Path Skew:        -4.196ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.230ns
    Source Clock Delay      (SCD):    6.426ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.243ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.323ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      3.096ns (routing 1.545ns, distribution 1.551ns)
  Clock Net Delay (Destination): 2.048ns (routing 0.599ns, distribution 1.449ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.657     3.184    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     3.057 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     3.302    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.330 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86296, routed)       3.096     6.426    d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/RAM_reg_0_3_56_63/WCLK
    SLICE_X82Y60         RAMD32                                       r  d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/RAM_reg_0_3_56_63/RAMA_D1/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X82Y60         RAMD32 (Prop_A6LUT_SLICEM_CLK_O)
                                                      0.305     6.731 r  d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/RAM_reg_0_3_56_63/RAMA_D1/O
                         net (fo=1, routed)           1.163     7.894    d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/dob0__0[57]
    SLICE_X81Y60         FDRE                                         r  d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/dob_reg[57]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       2.048     2.230    d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/m_axis_aclk
    SLICE_X81Y60         FDRE                                         r  d_1_i/axis_avg_buffer_2/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/dob_reg[57]/C

Slack:                    inf
  Source:                 d_1_i/axis_avg_buffer_3/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/RAM_reg_0_3_42_55/RAMA/CLK
                            (rising edge-triggered cell RAMD32 clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_avg_buffer_3/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/dob_reg[42]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.452ns  (logic 0.289ns (19.904%)  route 1.163ns (80.096%))
  Logic Levels:           0  
  Clock Path Skew:        -4.419ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    1.993ns
    Source Clock Delay      (SCD):    6.412ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.243ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.323ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      3.082ns (routing 1.545ns, distribution 1.537ns)
  Clock Net Delay (Destination): 1.811ns (routing 0.599ns, distribution 1.212ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.657     3.184    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     3.057 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     3.302    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.330 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86296, routed)       3.082     6.412    d_1_i/axis_avg_buffer_3/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/RAM_reg_0_3_42_55/WCLK
    SLICE_X39Y167        RAMD32                                       r  d_1_i/axis_avg_buffer_3/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/RAM_reg_0_3_42_55/RAMA/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X39Y167        RAMD32 (Prop_A5LUT_SLICEM_CLK_O)
                                                      0.289     6.701 r  d_1_i/axis_avg_buffer_3/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/RAM_reg_0_3_42_55/RAMA/O
                         net (fo=1, routed)           1.163     7.864    d_1_i/axis_avg_buffer_3/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/dob0__0[42]
    SLICE_X38Y166        FDRE                                         r  d_1_i/axis_avg_buffer_3/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/dob_reg[42]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.811     1.993    d_1_i/axis_avg_buffer_3/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/m_axis_aclk
    SLICE_X38Y166        FDRE                                         r  d_1_i/axis_avg_buffer_3/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/dob_reg[42]/C

Slack:                    inf
  Source:                 d_1_i/axis_avg_buffer_3/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/RAM_reg_0_3_42_55/RAMB_D1/CLK
                            (rising edge-triggered cell RAMD32 clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_avg_buffer_3/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/dob_reg[45]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.383ns  (logic 0.307ns (22.198%)  route 1.076ns (77.802%))
  Logic Levels:           0  
  Clock Path Skew:        -4.421ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    1.991ns
    Source Clock Delay      (SCD):    6.412ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.243ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.323ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      3.082ns (routing 1.545ns, distribution 1.537ns)
  Clock Net Delay (Destination): 1.809ns (routing 0.599ns, distribution 1.210ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.657     3.184    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     3.057 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     3.302    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.330 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86296, routed)       3.082     6.412    d_1_i/axis_avg_buffer_3/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/RAM_reg_0_3_42_55/WCLK
    SLICE_X39Y167        RAMD32                                       r  d_1_i/axis_avg_buffer_3/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/RAM_reg_0_3_42_55/RAMB_D1/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X39Y167        RAMD32 (Prop_B6LUT_SLICEM_CLK_O)
                                                      0.307     6.719 r  d_1_i/axis_avg_buffer_3/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/RAM_reg_0_3_42_55/RAMB_D1/O
                         net (fo=1, routed)           1.076     7.795    d_1_i/axis_avg_buffer_3/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/dob0__0[45]
    SLICE_X39Y169        FDRE                                         r  d_1_i/axis_avg_buffer_3/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/dob_reg[45]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.809     1.991    d_1_i/axis_avg_buffer_3/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/m_axis_aclk
    SLICE_X39Y169        FDRE                                         r  d_1_i/axis_avg_buffer_3/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/dob_reg[45]/C

Slack:                    inf
  Source:                 d_1_i/axis_avg_buffer_3/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/RAM_reg_0_3_28_41/RAMD_D1/CLK
                            (rising edge-triggered cell RAMD32 clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_avg_buffer_3/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/dob_reg[35]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.326ns  (logic 0.301ns (22.700%)  route 1.025ns (77.300%))
  Logic Levels:           0  
  Clock Path Skew:        -4.423ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    1.987ns
    Source Clock Delay      (SCD):    6.410ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.243ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.323ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      3.080ns (routing 1.545ns, distribution 1.535ns)
  Clock Net Delay (Destination): 1.805ns (routing 0.599ns, distribution 1.206ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.657     3.184    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     3.057 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     3.302    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.330 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86296, routed)       3.080     6.410    d_1_i/axis_avg_buffer_3/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/RAM_reg_0_3_28_41/WCLK
    SLICE_X39Y165        RAMD32                                       r  d_1_i/axis_avg_buffer_3/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/RAM_reg_0_3_28_41/RAMD_D1/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X39Y165        RAMD32 (Prop_D6LUT_SLICEM_CLK_O)
                                                      0.301     6.711 r  d_1_i/axis_avg_buffer_3/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/RAM_reg_0_3_28_41/RAMD_D1/O
                         net (fo=1, routed)           1.025     7.736    d_1_i/axis_avg_buffer_3/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/dob0__0[35]
    SLICE_X38Y165        FDRE                                         r  d_1_i/axis_avg_buffer_3/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/dob_reg[35]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.805     1.987    d_1_i/axis_avg_buffer_3/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/m_axis_aclk
    SLICE_X38Y165        FDRE                                         r  d_1_i/axis_avg_buffer_3/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/dob_reg[35]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_req_ff_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.133ns  (logic 0.039ns (29.393%)  route 0.094ns (70.607%))
  Logic Levels:           0  
  Clock Path Skew:        -2.238ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.575ns
    Source Clock Delay      (SCD):    3.813ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.243ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.323ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      1.706ns (routing 0.846ns, distribution 0.860ns)
  Clock Net Delay (Destination): 1.428ns (routing 0.405ns, distribution 1.023ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.451     1.714    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.944 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     2.090    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.107 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86296, routed)       1.706     3.813    d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_clk
    SLICE_X87Y70         FDRE                                         r  d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_req_ff_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X87Y70         FDRE (Prop_DFF_SLICEM_C_Q)
                                                      0.039     3.852 r  d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_req_ff_reg/Q
                         net (fo=2, routed)           0.094     3.945    d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/src_in
    SLICE_X85Y70         FDRE                                         r  d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.428     1.575    d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/dest_clk
    SLICE_X85Y70         FDRE                                         r  d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_req_ff_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.226ns  (logic 0.039ns (17.250%)  route 0.187ns (82.750%))
  Logic Levels:           0  
  Clock Path Skew:        -2.330ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.402ns
    Source Clock Delay      (SCD):    3.732ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.243ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.323ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      1.625ns (routing 0.846ns, distribution 0.779ns)
  Clock Net Delay (Destination): 1.255ns (routing 0.405ns, distribution 0.850ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.451     1.714    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.944 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     2.090    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.107 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86296, routed)       1.625     3.732    d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_clk
    SLICE_X55Y206        FDRE                                         r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_req_ff_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X55Y206        FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.039     3.771 r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_req_ff_reg/Q
                         net (fo=2, routed)           0.187     3.958    d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/src_in
    SLICE_X56Y194        FDRE                                         r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.255     1.402    d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/dest_clk
    SLICE_X56Y194        FDRE                                         r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/cdc_adc2_clk_valid_i/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.358ns  (logic 0.039ns (10.904%)  route 0.319ns (89.096%))
  Logic Levels:           0  
  Clock Path Skew:        -2.231ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.638ns
    Source Clock Delay      (SCD):    3.869ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.243ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.323ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      1.762ns (routing 0.846ns, distribution 0.916ns)
  Clock Net Delay (Destination): 1.491ns (routing 0.405ns, distribution 1.086ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.451     1.714    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.944 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     2.090    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.107 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86296, routed)       1.762     3.869    d_1_i/rst_adc0_x2/U0/slowest_sync_clk
    SLICE_X108Y118       FDRE                                         r  d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X108Y118       FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.039     3.908 r  d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=2, routed)           0.319     4.227    d_1_i/usp_rf_data_converter_0/inst/cdc_adc2_clk_valid_i/src_in
    SLICE_X108Y122       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/cdc_adc2_clk_valid_i/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.491     1.638    d_1_i/usp_rf_data_converter_0/inst/cdc_adc2_clk_valid_i/dest_clk
    SLICE_X108Y122       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/cdc_adc2_clk_valid_i/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/cdc_adc0_clk_valid_i/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.486ns  (logic 0.039ns (8.030%)  route 0.447ns (91.970%))
  Logic Levels:           0  
  Clock Path Skew:        -2.226ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.643ns
    Source Clock Delay      (SCD):    3.869ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.243ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.323ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      1.762ns (routing 0.846ns, distribution 0.916ns)
  Clock Net Delay (Destination): 1.496ns (routing 0.405ns, distribution 1.091ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.451     1.714    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.944 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     2.090    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.107 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86296, routed)       1.762     3.869    d_1_i/rst_adc0_x2/U0/slowest_sync_clk
    SLICE_X108Y118       FDRE                                         r  d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X108Y118       FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.039     3.908 r  d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=2, routed)           0.447     4.355    d_1_i/usp_rf_data_converter_0/inst/cdc_adc0_clk_valid_i/src_in
    SLICE_X108Y99        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/cdc_adc0_clk_valid_i/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.496     1.643    d_1_i/usp_rf_data_converter_0/inst/cdc_adc0_clk_valid_i/dest_clk
    SLICE_X108Y99        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/cdc_adc0_clk_valid_i/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/FABRIC_CLK
                            (rising edge-triggered cell HSADC clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[5]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.121ns  (logic 0.378ns (33.720%)  route 0.743ns (66.280%))
  Logic Levels:           5  (LUT5=2 LUT6=3)
  Clock Path Skew:        -2.232ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.646ns
    Source Clock Delay      (SCD):    3.878ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.243ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.323ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      1.771ns (routing 0.846ns, distribution 0.925ns)
  Clock Net Delay (Destination): 1.499ns (routing 0.405ns, distribution 1.094ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.451     1.714    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.944 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     2.090    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.107 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86296, routed)       1.771     3.878    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/m2_axis_aclk
    HSADC_X0Y2           HSADC                                        r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/FABRIC_CLK
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y2           HSADC (Prop_HSADC_FABRIC_CLK_STATUS_COMMON[5])
                                                      0.228     4.106 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_COMMON[5]
                         net (fo=1, routed)           0.332     4.438    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_22_1[5]
    SLICE_X112Y118       LUT5 (Prop_E6LUT_SLICEM_I3_O)
                                                      0.022     4.460 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_28/O
                         net (fo=1, routed)           0.138     4.598    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_28_n_0
    SLICE_X109Y116       LUT6 (Prop_D6LUT_SLICEM_I0_O)
                                                      0.050     4.648 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_25/O
                         net (fo=1, routed)           0.021     4.669    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_25_n_0
    SLICE_X109Y116       LUT6 (Prop_F6LUT_SLICEM_I5_O)
                                                      0.014     4.683 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_16/O
                         net (fo=1, routed)           0.213     4.896    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_16_n_0
    SLICE_X108Y104       LUT5 (Prop_E6LUT_SLICEL_I0_O)
                                                      0.050     4.946 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_6/O
                         net (fo=1, routed)           0.022     4.968    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_6_n_0
    SLICE_X108Y104       LUT6 (Prop_C6LUT_SLICEL_I4_O)
                                                      0.014     4.982 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_1/O
                         net (fo=1, routed)           0.017     4.999    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_79
    SLICE_X108Y104       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[5]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.499     1.646    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X108Y104       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[5]/C

Slack:                    inf
  Source:                 d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/wptr_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/wptr_g_i/data_int_reg_reg[0][1]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.103ns  (logic 0.039ns (37.981%)  route 0.064ns (62.019%))
  Logic Levels:           0  
  Clock Path Skew:        -2.229ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.496ns
    Source Clock Delay      (SCD):    3.725ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.243ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.323ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      1.618ns (routing 0.846ns, distribution 0.772ns)
  Clock Net Delay (Destination): 1.349ns (routing 0.405ns, distribution 0.944ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.451     1.714    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.944 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     2.090    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.107 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86296, routed)       1.618     3.725    d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/s_axis_aclk
    SLICE_X74Y123        FDRE                                         r  d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/wptr_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X74Y123        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.039     3.764 r  d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/wptr_reg[1]/Q
                         net (fo=83, routed)          0.064     3.828    d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/wptr_g_i/Q[1]
    SLICE_X74Y122        FDRE                                         r  d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/wptr_g_i/data_int_reg_reg[0][1]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.349     1.496    d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/wptr_g_i/m_axis_aclk
    SLICE_X74Y122        FDRE                                         r  d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/wptr_g_i/data_int_reg_reg[0][1]/C

Slack:                    inf
  Source:                 d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/RAM_reg_0_3_0_13/RAME/CLK
                            (rising edge-triggered cell RAMD32 clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/dob_reg[8]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.182ns  (logic 0.108ns (59.341%)  route 0.074ns (40.659%))
  Logic Levels:           0  
  Clock Path Skew:        -2.235ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.495ns
    Source Clock Delay      (SCD):    3.730ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.243ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.323ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      1.623ns (routing 0.846ns, distribution 0.777ns)
  Clock Net Delay (Destination): 1.348ns (routing 0.405ns, distribution 0.943ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.451     1.714    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.944 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     2.090    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.107 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86296, routed)       1.623     3.730    d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/RAM_reg_0_3_0_13/WCLK
    SLICE_X69Y122        RAMD32                                       r  d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/RAM_reg_0_3_0_13/RAME/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X69Y122        RAMD32 (Prop_E5LUT_SLICEM_CLK_O)
                                                      0.108     3.838 r  d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/RAM_reg_0_3_0_13/RAME/O
                         net (fo=1, routed)           0.074     3.912    d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/dob0__0[8]
    SLICE_X68Y122        FDRE                                         r  d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/dob_reg[8]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.348     1.495    d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/m_axis_aclk
    SLICE_X68Y122        FDRE                                         r  d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/dob_reg[8]/C

Slack:                    inf
  Source:                 d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/wptr_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/wptr_g_i/data_int_reg_reg[0][1]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.200ns  (logic 0.039ns (19.524%)  route 0.161ns (80.476%))
  Logic Levels:           0  
  Clock Path Skew:        -2.230ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.485ns
    Source Clock Delay      (SCD):    3.715ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.243ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.323ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      1.608ns (routing 0.846ns, distribution 0.762ns)
  Clock Net Delay (Destination): 1.338ns (routing 0.405ns, distribution 0.933ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.451     1.714    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.944 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     2.090    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.107 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86296, routed)       1.608     3.715    d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/s_axis_aclk
    SLICE_X66Y98         FDRE                                         r  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/wptr_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X66Y98         FDRE (Prop_HFF2_SLICEM_C_Q)
                                                      0.039     3.754 r  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/wptr_reg[1]/Q
                         net (fo=83, routed)          0.161     3.915    d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/wptr_g_i/Q[1]
    SLICE_X62Y97         FDRE                                         r  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/wptr_g_i/data_int_reg_reg[0][1]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.338     1.485    d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/wptr_g_i/m_axis_aclk
    SLICE_X62Y97         FDRE                                         r  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/wptr_g_i/data_int_reg_reg[0][1]/C

Slack:                    inf
  Source:                 d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/RAM_reg_0_3_56_63/RAMB_D1/CLK
                            (rising edge-triggered cell RAMD32 clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/dob_reg[59]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.184ns  (logic 0.110ns (59.783%)  route 0.074ns (40.217%))
  Logic Levels:           0  
  Clock Path Skew:        -2.240ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.493ns
    Source Clock Delay      (SCD):    3.733ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.243ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.323ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      1.626ns (routing 0.846ns, distribution 0.780ns)
  Clock Net Delay (Destination): 1.346ns (routing 0.405ns, distribution 0.941ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.451     1.714    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.944 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     2.090    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.107 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86296, routed)       1.626     3.733    d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/RAM_reg_0_3_56_63/WCLK
    SLICE_X72Y123        RAMD32                                       r  d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/RAM_reg_0_3_56_63/RAMB_D1/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X72Y123        RAMD32 (Prop_B6LUT_SLICEM_CLK_O)
                                                      0.110     3.843 r  d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/RAM_reg_0_3_56_63/RAMB_D1/O
                         net (fo=1, routed)           0.074     3.917    d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/dob0__0[59]
    SLICE_X72Y122        FDRE                                         r  d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/dob_reg[59]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.346     1.493    d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/m_axis_aclk
    SLICE_X72Y122        FDRE                                         r  d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/dob_reg[59]/C

Slack:                    inf
  Source:                 d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/RAM_reg_0_3_14_27/RAMG_D1/CLK
                            (rising edge-triggered cell RAMD32 clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/dob_reg[27]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.187ns  (logic 0.105ns (56.150%)  route 0.082ns (43.850%))
  Logic Levels:           0  
  Clock Path Skew:        -2.249ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.481ns
    Source Clock Delay      (SCD):    3.730ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.243ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.323ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      1.623ns (routing 0.846ns, distribution 0.777ns)
  Clock Net Delay (Destination): 1.334ns (routing 0.405ns, distribution 0.929ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.451     1.714    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.944 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     2.090    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.107 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86296, routed)       1.623     3.730    d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/RAM_reg_0_3_14_27/WCLK
    SLICE_X69Y125        RAMD32                                       r  d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/RAM_reg_0_3_14_27/RAMG_D1/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X69Y125        RAMD32 (Prop_G6LUT_SLICEM_CLK_O)
                                                      0.105     3.835 r  d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/RAM_reg_0_3_14_27/RAMG_D1/O
                         net (fo=1, routed)           0.082     3.917    d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/dob0__0[27]
    SLICE_X68Y126        FDRE                                         r  d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/dob_reg[27]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.334     1.481    d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/m_axis_aclk
    SLICE_X68Y126        FDRE                                         r  d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/dob_reg[27]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  clk_out1_d_1_clk_core_0
  To Clock:  clk_pl_0

Max Delay          1759 Endpoints
Min Delay          1759 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.046ns  (logic 0.178ns (8.701%)  route 1.868ns (91.299%))
  Logic Levels:           1  (LUT1=1)
  Clock Path Skew:        -2.703ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.314ns
    Source Clock Delay      (SCD):    5.017ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.217ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      2.503ns (routing 1.461ns, distribution 1.042ns)
  Clock Net Delay (Destination): 2.132ns (routing 0.599ns, distribution 1.533ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=48236, routed)       2.142     2.368    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.241 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.486    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y133        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.514 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=4540, routed)        2.503     5.017    d_1_i/rst_core/U0/slowest_sync_clk
    SLICE_X69Y131        FDRE                                         r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X69Y131        FDRE (Prop_AFF_SLICEM_C_Q)
                                                      0.077     5.094 f  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=4, routed)           1.555     6.649    d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/m_axis_aresetn
    SLICE_X97Y66         LUT1 (Prop_H6LUT_SLICEM_I0_O)
                                                      0.101     6.750 r  d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst_i_1/O
                         net (fo=1, routed)           0.313     7.063    d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst/src_rst
    SLICE_X100Y67        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       2.132     2.314    d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst/dest_clk
    SLICE_X100Y67        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.673ns  (logic 0.112ns (6.694%)  route 1.561ns (93.306%))
  Logic Levels:           1  (LUT1=1)
  Clock Path Skew:        -3.018ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    1.999ns
    Source Clock Delay      (SCD):    5.017ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.217ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      2.503ns (routing 1.461ns, distribution 1.042ns)
  Clock Net Delay (Destination): 1.817ns (routing 0.599ns, distribution 1.218ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=48236, routed)       2.142     2.368    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.241 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.486    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y133        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.514 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=4540, routed)        2.503     5.017    d_1_i/rst_core/U0/slowest_sync_clk
    SLICE_X69Y131        FDRE                                         r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X69Y131        FDRE (Prop_AFF_SLICEM_C_Q)
                                                      0.077     5.094 f  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=4, routed)           1.339     6.433    d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/m_axis_aresetn
    SLICE_X40Y169        LUT1 (Prop_E6LUT_SLICEL_I0_O)
                                                      0.035     6.468 r  d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst_i_1/O
                         net (fo=1, routed)           0.222     6.690    d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst/src_rst
    SLICE_X40Y175        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.817     1.999    d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst/dest_clk
    SLICE_X40Y175        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.926ns  (logic 0.177ns (19.123%)  route 0.749ns (80.877%))
  Logic Levels:           1  (LUT1=1)
  Clock Path Skew:        -2.925ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.092ns
    Source Clock Delay      (SCD):    5.017ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.217ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      2.503ns (routing 1.461ns, distribution 1.042ns)
  Clock Net Delay (Destination): 1.910ns (routing 0.599ns, distribution 1.311ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=48236, routed)       2.142     2.368    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.241 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.486    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y133        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.514 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=4540, routed)        2.503     5.017    d_1_i/rst_core/U0/slowest_sync_clk
    SLICE_X69Y131        FDRE                                         r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X69Y131        FDRE (Prop_AFF_SLICEM_C_Q)
                                                      0.077     5.094 f  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=4, routed)           0.567     5.661    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/m_axis_aresetn
    SLICE_X63Y103        LUT1 (Prop_G6LUT_SLICEM_I0_O)
                                                      0.100     5.761 r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst_i_1/O
                         net (fo=1, routed)           0.182     5.943    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst/src_rst
    SLICE_X63Y103        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.910     2.092    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst/dest_clk
    SLICE_X63Y103        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.750ns  (logic 0.177ns (23.590%)  route 0.573ns (76.410%))
  Logic Levels:           1  (LUT1=1)
  Clock Path Skew:        -2.899ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.118ns
    Source Clock Delay      (SCD):    5.017ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.217ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      2.503ns (routing 1.461ns, distribution 1.042ns)
  Clock Net Delay (Destination): 1.936ns (routing 0.599ns, distribution 1.337ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=48236, routed)       2.142     2.368    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.241 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.486    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y133        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.514 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=4540, routed)        2.503     5.017    d_1_i/rst_core/U0/slowest_sync_clk
    SLICE_X69Y131        FDRE                                         r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X69Y131        FDRE (Prop_AFF_SLICEM_C_Q)
                                                      0.077     5.094 f  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=4, routed)           0.416     5.510    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/m_axis_aresetn
    SLICE_X69Y108        LUT1 (Prop_G6LUT_SLICEM_I0_O)
                                                      0.100     5.610 r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst_i_1/O
                         net (fo=1, routed)           0.157     5.767    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst/src_rst
    SLICE_X69Y108        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.936     2.118    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst/dest_clk
    SLICE_X69Y108        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.328ns  (logic 0.076ns (23.168%)  route 0.252ns (76.832%))
  Logic Levels:           0  
  Clock Path Skew:        -2.802ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.307ns
    Source Clock Delay      (SCD):    5.109ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.217ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      2.595ns (routing 1.461ns, distribution 1.134ns)
  Clock Net Delay (Destination): 2.125ns (routing 0.599ns, distribution 1.526ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=48236, routed)       2.142     2.368    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.241 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.486    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y133        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.514 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=4540, routed)        2.595     5.109    d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/rd_clk
    SLICE_X96Y67         FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X96Y67         FDRE (Prop_FFF_SLICEM_C_Q)
                                                      0.076     5.185 r  d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg/Q
                         net (fo=85, routed)          0.252     5.437    d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/src_rst
    SLICE_X98Y66         FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       2.125     2.307    d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/dest_clk
    SLICE_X98Y66         FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.234ns  (logic 0.079ns (33.756%)  route 0.155ns (66.245%))
  Logic Levels:           0  
  Clock Path Skew:        -3.151ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    1.998ns
    Source Clock Delay      (SCD):    5.149ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.217ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      2.635ns (routing 1.461ns, distribution 1.174ns)
  Clock Net Delay (Destination): 1.816ns (routing 0.599ns, distribution 1.217ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=48236, routed)       2.142     2.368    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.241 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.486    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y133        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.514 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=4540, routed)        2.635     5.149    d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/rd_clk
    SLICE_X38Y173        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X38Y173        FDRE (Prop_BFF_SLICEL_C_Q)
                                                      0.079     5.228 r  d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg/Q
                         net (fo=85, routed)          0.155     5.383    d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/src_rst
    SLICE_X38Y172        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.816     1.998    d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/dest_clk
    SLICE_X38Y172        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.314ns  (logic 0.078ns (24.838%)  route 0.236ns (75.162%))
  Logic Levels:           0  
  Clock Path Skew:        -2.887ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.084ns
    Source Clock Delay      (SCD):    4.971ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.217ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      2.457ns (routing 1.461ns, distribution 0.996ns)
  Clock Net Delay (Destination): 1.902ns (routing 0.599ns, distribution 1.303ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=48236, routed)       2.142     2.368    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.241 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.486    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y133        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.514 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=4540, routed)        2.457     4.971    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/rd_clk
    SLICE_X61Y106        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X61Y106        FDRE (Prop_CFF_SLICEM_C_Q)
                                                      0.078     5.049 r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg/Q
                         net (fo=85, routed)          0.236     5.285    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/src_rst
    SLICE_X61Y105        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.902     2.084    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/dest_clk
    SLICE_X61Y105        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.296ns  (logic 0.079ns (26.686%)  route 0.217ns (73.314%))
  Logic Levels:           0  
  Clock Path Skew:        -2.846ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.118ns
    Source Clock Delay      (SCD):    4.964ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.217ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      2.450ns (routing 1.461ns, distribution 0.989ns)
  Clock Net Delay (Destination): 1.936ns (routing 0.599ns, distribution 1.337ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=48236, routed)       2.142     2.368    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.241 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.486    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y133        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.514 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=4540, routed)        2.450     4.964    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/rd_clk
    SLICE_X68Y107        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X68Y107        FDRE (Prop_FFF_SLICEL_C_Q)
                                                      0.079     5.043 r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg/Q
                         net (fo=85, routed)          0.217     5.260    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/src_rst
    SLICE_X69Y108        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.936     2.118    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/dest_clk
    SLICE_X69Y108        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/TPROC_CFG_reg[3]_rep__0/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/axi_dma_tproc/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/ENABLE_AXIS_SKID.I_S2MM_STRM_SKID_BUF/sig_data_reg_out_reg[134]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        4.554ns  (logic 0.366ns (8.038%)  route 4.188ns (91.962%))
  Logic Levels:           3  (LUT3=2 LUT6=1)
  Clock Path Skew:        -3.076ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.083ns
    Source Clock Delay      (SCD):    5.159ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.217ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      2.645ns (routing 1.461ns, distribution 1.184ns)
  Clock Net Delay (Destination): 1.901ns (routing 0.599ns, distribution 1.302ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=48236, routed)       2.142     2.368    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.241 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.486    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y133        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.514 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=4540, routed)        2.645     5.159    d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/c_clk_i
    SLICE_X38Y140        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/TPROC_CFG_reg[3]_rep__0/C
  -------------------------------------------------------------------    -------------------
    SLICE_X38Y140        FDRE (Prop_EFF2_SLICEL_C_Q)
                                                      0.081     5.240 r  d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/TPROC_CFG_reg[3]_rep__0/Q
                         net (fo=209, routed)         2.095     7.335    d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/TPROC_CFG_reg[3]_rep__0_0
    SLICE_X38Y78         LUT3 (Prop_F6LUT_SLICEL_I0_O)
                                                      0.035     7.370 r  d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/m_dma_axis_tdata_o[167]_INST_0_i_1/O
                         net (fo=72, routed)          0.881     8.252    d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/m_dma_axis_tdata_o[167]_INST_0_i_1_n_0
    SLICE_X35Y80         LUT6 (Prop_A6LUT_SLICEM_I0_O)
                                                      0.150     8.402 r  d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/m_dma_axis_tdata_o[134]_INST_0/O
                         net (fo=2, routed)           1.156     9.558    d_1_i/axi_dma_tproc/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/ENABLE_AXIS_SKID.I_S2MM_STRM_SKID_BUF/s_axis_s2mm_tdata[134]
    SLICE_X35Y56         LUT3 (Prop_E6LUT_SLICEM_I0_O)
                                                      0.100     9.658 r  d_1_i/axi_dma_tproc/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/ENABLE_AXIS_SKID.I_S2MM_STRM_SKID_BUF/sig_data_reg_out[134]_i_1/O
                         net (fo=1, routed)           0.055     9.713    d_1_i/axi_dma_tproc/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/ENABLE_AXIS_SKID.I_S2MM_STRM_SKID_BUF/sig_data_skid_mux_out[134]
    SLICE_X35Y56         FDRE                                         r  d_1_i/axi_dma_tproc/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/ENABLE_AXIS_SKID.I_S2MM_STRM_SKID_BUF/sig_data_reg_out_reg[134]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.901     2.083    d_1_i/axi_dma_tproc/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/ENABLE_AXIS_SKID.I_S2MM_STRM_SKID_BUF/m_axi_s2mm_aclk
    SLICE_X35Y56         FDRE                                         r  d_1_i/axi_dma_tproc/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/ENABLE_AXIS_SKID.I_S2MM_STRM_SKID_BUF/sig_data_reg_out_reg[134]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/TPROC_CFG_reg[3]_rep__0/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/axi_dma_tproc/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/ENABLE_AXIS_SKID.I_S2MM_STRM_SKID_BUF/sig_data_reg_out_reg[137]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        4.472ns  (logic 0.418ns (9.348%)  route 4.054ns (90.652%))
  Logic Levels:           3  (LUT3=2 LUT6=1)
  Clock Path Skew:        -3.078ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.081ns
    Source Clock Delay      (SCD):    5.159ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.217ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      2.645ns (routing 1.461ns, distribution 1.184ns)
  Clock Net Delay (Destination): 1.899ns (routing 0.599ns, distribution 1.300ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=48236, routed)       2.142     2.368    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.241 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.486    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y133        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.514 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=4540, routed)        2.645     5.159    d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/c_clk_i
    SLICE_X38Y140        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/TPROC_CFG_reg[3]_rep__0/C
  -------------------------------------------------------------------    -------------------
    SLICE_X38Y140        FDRE (Prop_EFF2_SLICEL_C_Q)
                                                      0.081     5.240 r  d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/TPROC_CFG_reg[3]_rep__0/Q
                         net (fo=209, routed)         2.369     7.609    d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/TPROC_CFG_reg[3]_rep__0_0
    SLICE_X40Y80         LUT3 (Prop_H6LUT_SLICEL_I0_O)
                                                      0.090     7.699 r  d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/CORE_MEM/m_dma_axis_tdata_o[145]_INST_0_i_1/O
                         net (fo=2, routed)           0.814     8.513    d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/ext_mem_r_dt[137]
    SLICE_X38Y80         LUT6 (Prop_H6LUT_SLICEL_I1_O)
                                                      0.124     8.637 r  d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/m_dma_axis_tdata_o[137]_INST_0/O
                         net (fo=2, routed)           0.805     9.442    d_1_i/axi_dma_tproc/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/ENABLE_AXIS_SKID.I_S2MM_STRM_SKID_BUF/s_axis_s2mm_tdata[137]
    SLICE_X37Y55         LUT3 (Prop_C6LUT_SLICEM_I0_O)
                                                      0.123     9.565 r  d_1_i/axi_dma_tproc/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/ENABLE_AXIS_SKID.I_S2MM_STRM_SKID_BUF/sig_data_reg_out[137]_i_1/O
                         net (fo=1, routed)           0.066     9.631    d_1_i/axi_dma_tproc/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/ENABLE_AXIS_SKID.I_S2MM_STRM_SKID_BUF/sig_data_skid_mux_out[137]
    SLICE_X37Y55         FDRE                                         r  d_1_i/axi_dma_tproc/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/ENABLE_AXIS_SKID.I_S2MM_STRM_SKID_BUF/sig_data_reg_out_reg[137]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.899     2.081    d_1_i/axi_dma_tproc/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/ENABLE_AXIS_SKID.I_S2MM_STRM_SKID_BUF/m_axi_s2mm_aclk
    SLICE_X37Y55         FDRE                                         r  d_1_i/axi_dma_tproc/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/ENABLE_AXIS_SKID.I_S2MM_STRM_SKID_BUF/sig_data_reg_out_reg[137]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.107ns  (logic 0.039ns (36.449%)  route 0.068ns (63.551%))
  Logic Levels:           0  
  Clock Path Skew:        -1.531ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.509ns
    Source Clock Delay      (SCD):    3.040ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.217ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.354ns (routing 0.804ns, distribution 0.550ns)
  Clock Net Delay (Destination): 1.362ns (routing 0.405ns, distribution 0.957ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=48236, routed)       1.173     1.293    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.523 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.669    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y133        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.686 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=4540, routed)        1.354     3.040    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_clk
    SLICE_X71Y117        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X71Y117        FDRE (Prop_HFF2_SLICEL_C_Q)
                                                      0.039     3.079 r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[1]/Q
                         net (fo=1, routed)           0.068     3.147    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/async_path[1]
    SLICE_X72Y117        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.362     1.509    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_clk
    SLICE_X72Y117        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/C

Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.125ns  (logic 0.040ns (32.000%)  route 0.085ns (68.000%))
  Logic Levels:           0  
  Clock Path Skew:        -1.541ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.499ns
    Source Clock Delay      (SCD):    3.040ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.217ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.354ns (routing 0.804ns, distribution 0.550ns)
  Clock Net Delay (Destination): 1.352ns (routing 0.405ns, distribution 0.947ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=48236, routed)       1.173     1.293    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.523 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.669    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y133        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.686 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=4540, routed)        1.354     3.040    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_clk
    SLICE_X71Y117        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X71Y117        FDRE (Prop_GFF2_SLICEL_C_Q)
                                                      0.040     3.080 r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[3]/Q
                         net (fo=1, routed)           0.085     3.165    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/async_path[3]
    SLICE_X71Y114        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.352     1.499    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_clk
    SLICE_X71Y114        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/C

Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.128ns  (logic 0.039ns (30.544%)  route 0.089ns (69.456%))
  Logic Levels:           0  
  Clock Path Skew:        -1.543ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.497ns
    Source Clock Delay      (SCD):    3.040ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.217ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.354ns (routing 0.804ns, distribution 0.550ns)
  Clock Net Delay (Destination): 1.350ns (routing 0.405ns, distribution 0.945ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=48236, routed)       1.173     1.293    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.523 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.669    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y133        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.686 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=4540, routed)        1.354     3.040    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/rd_clk
    SLICE_X68Y107        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X68Y107        FDRE (Prop_FFF_SLICEL_C_Q)
                                                      0.039     3.079 r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg/Q
                         net (fo=85, routed)          0.089     3.168    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/src_rst
    SLICE_X69Y108        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.350     1.497    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/dest_clk
    SLICE_X69Y108        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.131ns  (logic 0.038ns (29.078%)  route 0.093ns (70.922%))
  Logic Levels:           0  
  Clock Path Skew:        -1.566ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.477ns
    Source Clock Delay      (SCD):    3.043ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.217ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.357ns (routing 0.804ns, distribution 0.553ns)
  Clock Net Delay (Destination): 1.330ns (routing 0.405ns, distribution 0.925ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=48236, routed)       1.173     1.293    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.523 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.669    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y133        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.686 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=4540, routed)        1.357     3.043    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/rd_clk
    SLICE_X61Y106        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X61Y106        FDRE (Prop_CFF_SLICEM_C_Q)
                                                      0.038     3.081 r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg/Q
                         net (fo=85, routed)          0.093     3.174    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/src_rst
    SLICE_X61Y105        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.330     1.477    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/dest_clk
    SLICE_X61Y105        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[4]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][4]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.146ns  (logic 0.039ns (26.712%)  route 0.107ns (73.288%))
  Logic Levels:           0  
  Clock Path Skew:        -1.545ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.495ns
    Source Clock Delay      (SCD):    3.040ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.217ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.354ns (routing 0.804ns, distribution 0.550ns)
  Clock Net Delay (Destination): 1.348ns (routing 0.405ns, distribution 0.943ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=48236, routed)       1.173     1.293    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.523 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.669    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y133        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.686 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=4540, routed)        1.354     3.040    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_clk
    SLICE_X71Y116        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X71Y116        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.039     3.079 r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[4]/Q
                         net (fo=1, routed)           0.107     3.186    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/async_path[4]
    SLICE_X71Y116        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][4]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.348     1.495    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_clk
    SLICE_X71Y116        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][4]/C

Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.098ns  (logic 0.039ns (39.796%)  route 0.059ns (60.204%))
  Logic Levels:           0  
  Clock Path Skew:        -1.528ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.580ns
    Source Clock Delay      (SCD):    3.109ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.217ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.423ns (routing 0.804ns, distribution 0.619ns)
  Clock Net Delay (Destination): 1.433ns (routing 0.405ns, distribution 1.028ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=48236, routed)       1.173     1.293    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.523 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.669    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y133        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.686 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=4540, routed)        1.423     3.109    d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_clk
    SLICE_X84Y61         FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X84Y61         FDRE (Prop_HFF2_SLICEL_C_Q)
                                                      0.039     3.148 r  d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[1]/Q
                         net (fo=1, routed)           0.059     3.207    d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/async_path[1]
    SLICE_X84Y60         FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.433     1.580    d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_clk
    SLICE_X84Y60         FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_2/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/C

Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.132ns  (logic 0.039ns (29.545%)  route 0.093ns (70.455%))
  Logic Levels:           0  
  Clock Path Skew:        -1.596ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.485ns
    Source Clock Delay      (SCD):    3.081ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.217ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.395ns (routing 0.804ns, distribution 0.591ns)
  Clock Net Delay (Destination): 1.338ns (routing 0.405ns, distribution 0.933ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=48236, routed)       1.173     1.293    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.523 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.669    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y133        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.686 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=4540, routed)        1.395     3.081    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_clk
    SLICE_X59Y104        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X59Y104        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.039     3.120 r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[2]/Q
                         net (fo=1, routed)           0.093     3.213    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/async_path[2]
    SLICE_X62Y104        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.338     1.485    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_clk
    SLICE_X62Y104        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/C

Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[4]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][4]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.157ns  (logic 0.038ns (24.204%)  route 0.119ns (75.796%))
  Logic Levels:           0  
  Clock Path Skew:        -1.635ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.441ns
    Source Clock Delay      (SCD):    3.076ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.217ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.390ns (routing 0.804ns, distribution 0.586ns)
  Clock Net Delay (Destination): 1.294ns (routing 0.405ns, distribution 0.889ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=48236, routed)       1.173     1.293    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.523 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.669    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y133        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.686 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=4540, routed)        1.390     3.076    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_clk
    SLICE_X60Y104        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X60Y104        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.038     3.114 r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[4]/Q
                         net (fo=1, routed)           0.119     3.233    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/async_path[4]
    SLICE_X60Y104        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][4]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.294     1.441    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_clk
    SLICE_X60Y104        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][4]/C

Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.098ns  (logic 0.039ns (39.925%)  route 0.059ns (60.075%))
  Logic Levels:           0  
  Clock Path Skew:        -1.726ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.411ns
    Source Clock Delay      (SCD):    3.137ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.217ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.451ns (routing 0.804ns, distribution 0.647ns)
  Clock Net Delay (Destination): 1.264ns (routing 0.405ns, distribution 0.859ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=48236, routed)       1.173     1.293    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.523 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.669    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y133        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.686 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=4540, routed)        1.451     3.137    d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/rd_clk
    SLICE_X38Y173        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X38Y173        FDRE (Prop_BFF_SLICEL_C_Q)
                                                      0.039     3.176 r  d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg/Q
                         net (fo=85, routed)          0.059     3.235    d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/src_rst
    SLICE_X38Y172        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.264     1.411    d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/dest_clk
    SLICE_X38Y172        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_3/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.208ns  (logic 0.039ns (18.750%)  route 0.169ns (81.250%))
  Logic Levels:           0  
  Clock Path Skew:        -1.531ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.509ns
    Source Clock Delay      (SCD):    3.040ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.217ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.354ns (routing 0.804ns, distribution 0.550ns)
  Clock Net Delay (Destination): 1.362ns (routing 0.405ns, distribution 0.957ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=48236, routed)       1.173     1.293    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.523 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.669    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y133        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.686 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=4540, routed)        1.354     3.040    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_clk
    SLICE_X71Y117        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X71Y117        FDRE (Prop_GFF_SLICEL_C_Q)
                                                      0.039     3.079 r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[2]/Q
                         net (fo=1, routed)           0.169     3.248    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/async_path[2]
    SLICE_X72Y117        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.362     1.509    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_clk
    SLICE_X72Y117        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  clk_pl_0
  To Clock:  clk_pl_0

Max Delay           240 Endpoints
Min Delay           240 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axi_dma_gen/U0/I_RST_MODULE/REG_HRD_RST/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.812ns  (logic 0.079ns (2.073%)  route 3.733ns (97.927%))
  Logic Levels:           0  
  Clock Path Skew:        -0.542ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.064ns
    Source Clock Delay      (SCD):    2.606ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.380ns (routing 0.662ns, distribution 1.718ns)
  Clock Net Delay (Destination): 1.882ns (routing 0.599ns, distribution 1.283ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       2.380     2.606    d_1_i/rst_100/U0/slowest_sync_clk
    SLICE_X102Y67        FDRE                                         r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/C
  -------------------------------------------------------------------    -------------------
    SLICE_X102Y67        FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.079     2.685 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/Q
                         net (fo=118, routed)         3.733     6.418    d_1_i/axi_dma_gen/U0/I_RST_MODULE/REG_HRD_RST/peripheral_aresetn[0]_bufg_place_replica
    SLICE_X32Y86         FDRE                                         r  d_1_i/axi_dma_gen/U0/I_RST_MODULE/REG_HRD_RST/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.882     2.064    d_1_i/axi_dma_gen/U0/I_RST_MODULE/REG_HRD_RST/s_axi_lite_aclk
    SLICE_X32Y86         FDRE                                         r  d_1_i/axi_dma_gen/U0/I_RST_MODULE/REG_HRD_RST/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/C

Slack:                    inf
  Source:                 d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axi_dma_buf/U0/I_RST_MODULE/REG_HRD_RST/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.739ns  (logic 0.079ns (2.113%)  route 3.660ns (97.887%))
  Logic Levels:           0  
  Clock Path Skew:        -0.467ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.139ns
    Source Clock Delay      (SCD):    2.606ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.380ns (routing 0.662ns, distribution 1.718ns)
  Clock Net Delay (Destination): 1.957ns (routing 0.599ns, distribution 1.358ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       2.380     2.606    d_1_i/rst_100/U0/slowest_sync_clk
    SLICE_X102Y67        FDRE                                         r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/C
  -------------------------------------------------------------------    -------------------
    SLICE_X102Y67        FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.079     2.685 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/Q
                         net (fo=118, routed)         3.660     6.345    d_1_i/axi_dma_buf/U0/I_RST_MODULE/REG_HRD_RST/peripheral_aresetn[0]_bufg_place_replica
    SLICE_X74Y32         FDRE                                         r  d_1_i/axi_dma_buf/U0/I_RST_MODULE/REG_HRD_RST/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.957     2.139    d_1_i/axi_dma_buf/U0/I_RST_MODULE/REG_HRD_RST/s_axi_lite_aclk
    SLICE_X74Y32         FDRE                                         r  d_1_i/axi_dma_buf/U0/I_RST_MODULE/REG_HRD_RST/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/C

Slack:                    inf
  Source:                 d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axi_dma_gen/U0/I_RST_MODULE/REG_HRD_RST_OUT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.263ns  (logic 0.079ns (2.421%)  route 3.184ns (97.579%))
  Logic Levels:           0  
  Clock Path Skew:        -0.582ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.024ns
    Source Clock Delay      (SCD):    2.606ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.380ns (routing 0.662ns, distribution 1.718ns)
  Clock Net Delay (Destination): 1.842ns (routing 0.599ns, distribution 1.243ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       2.380     2.606    d_1_i/rst_100/U0/slowest_sync_clk
    SLICE_X102Y67        FDRE                                         r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/C
  -------------------------------------------------------------------    -------------------
    SLICE_X102Y67        FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.079     2.685 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/Q
                         net (fo=118, routed)         3.184     5.869    d_1_i/axi_dma_gen/U0/I_RST_MODULE/REG_HRD_RST_OUT/peripheral_aresetn[0]_bufg_place_replica
    SLICE_X39Y76         FDRE                                         r  d_1_i/axi_dma_gen/U0/I_RST_MODULE/REG_HRD_RST_OUT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.842     2.024    d_1_i/axi_dma_gen/U0/I_RST_MODULE/REG_HRD_RST_OUT/s_axi_lite_aclk
    SLICE_X39Y76         FDRE                                         r  d_1_i/axi_dma_gen/U0/I_RST_MODULE/REG_HRD_RST_OUT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/C

Slack:                    inf
  Source:                 d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axi_dma_tproc/U0/I_RST_MODULE/REG_HRD_RST/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.194ns  (logic 0.079ns (2.474%)  route 3.115ns (97.526%))
  Logic Levels:           0  
  Clock Path Skew:        -0.548ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.058ns
    Source Clock Delay      (SCD):    2.606ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.380ns (routing 0.662ns, distribution 1.718ns)
  Clock Net Delay (Destination): 1.876ns (routing 0.599ns, distribution 1.277ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       2.380     2.606    d_1_i/rst_100/U0/slowest_sync_clk
    SLICE_X102Y67        FDRE                                         r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/C
  -------------------------------------------------------------------    -------------------
    SLICE_X102Y67        FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.079     2.685 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/Q
                         net (fo=118, routed)         3.115     5.800    d_1_i/axi_dma_tproc/U0/I_RST_MODULE/REG_HRD_RST/peripheral_aresetn[0]_bufg_place_replica
    SLICE_X46Y57         FDRE                                         r  d_1_i/axi_dma_tproc/U0/I_RST_MODULE/REG_HRD_RST/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.876     2.058    d_1_i/axi_dma_tproc/U0/I_RST_MODULE/REG_HRD_RST/s_axi_lite_aclk
    SLICE_X46Y57         FDRE                                         r  d_1_i/axi_dma_tproc/U0/I_RST_MODULE/REG_HRD_RST/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/C

Slack:                    inf
  Source:                 d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/EXT_LPF/ACTIVE_LOW_AUX.ACT_LO_AUX/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.067ns  (logic 0.176ns (5.738%)  route 2.891ns (94.262%))
  Logic Levels:           1  (LUT1=1)
  Clock Path Skew:        -0.555ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.051ns
    Source Clock Delay      (SCD):    2.606ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.380ns (routing 0.662ns, distribution 1.718ns)
  Clock Net Delay (Destination): 1.869ns (routing 0.599ns, distribution 1.270ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       2.380     2.606    d_1_i/rst_100/U0/slowest_sync_clk
    SLICE_X102Y67        FDRE                                         r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/C
  -------------------------------------------------------------------    -------------------
    SLICE_X102Y67        FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.079     2.685 f  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/Q
                         net (fo=118, routed)         2.739     5.424    d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/EXT_LPF/ACTIVE_LOW_AUX.ACT_LO_AUX/peripheral_aresetn[0]_bufg_place_replica
    SLICE_X49Y48         LUT1 (Prop_G6LUT_SLICEL_I0_O)
                                                      0.097     5.521 r  d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/EXT_LPF/ACTIVE_LOW_AUX.ACT_LO_AUX/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1/O
                         net (fo=1, routed)           0.152     5.673    d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/EXT_LPF/ACTIVE_LOW_AUX.ACT_LO_AUX/asr_d1
    SLICE_X49Y48         FDRE                                         r  d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/EXT_LPF/ACTIVE_LOW_AUX.ACT_LO_AUX/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.869     2.051    d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/EXT_LPF/ACTIVE_LOW_AUX.ACT_LO_AUX/aclk
    SLICE_X49Y48         FDRE                                         r  d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/EXT_LPF/ACTIVE_LOW_AUX.ACT_LO_AUX/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/C

Slack:                    inf
  Source:                 d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axi_dma_tproc/U0/I_RST_MODULE/REG_HRD_RST_OUT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.957ns  (logic 0.079ns (2.672%)  route 2.878ns (97.328%))
  Logic Levels:           0  
  Clock Path Skew:        -0.573ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.033ns
    Source Clock Delay      (SCD):    2.606ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.380ns (routing 0.662ns, distribution 1.718ns)
  Clock Net Delay (Destination): 1.851ns (routing 0.599ns, distribution 1.252ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       2.380     2.606    d_1_i/rst_100/U0/slowest_sync_clk
    SLICE_X102Y67        FDRE                                         r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/C
  -------------------------------------------------------------------    -------------------
    SLICE_X102Y67        FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.079     2.685 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/Q
                         net (fo=118, routed)         2.878     5.563    d_1_i/axi_dma_tproc/U0/I_RST_MODULE/REG_HRD_RST_OUT/peripheral_aresetn[0]_bufg_place_replica
    SLICE_X45Y62         FDRE                                         r  d_1_i/axi_dma_tproc/U0/I_RST_MODULE/REG_HRD_RST_OUT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.851     2.033    d_1_i/axi_dma_tproc/U0/I_RST_MODULE/REG_HRD_RST_OUT/s_axi_lite_aclk
    SLICE_X45Y62         FDRE                                         r  d_1_i/axi_dma_tproc/U0/I_RST_MODULE/REG_HRD_RST_OUT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/C

Slack:                    inf
  Source:                 d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axi_dma_mr/U0/I_RST_MODULE/REG_HRD_RST/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.664ns  (logic 0.079ns (2.965%)  route 2.585ns (97.035%))
  Logic Levels:           0  
  Clock Path Skew:        -0.492ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.114ns
    Source Clock Delay      (SCD):    2.606ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.380ns (routing 0.662ns, distribution 1.718ns)
  Clock Net Delay (Destination): 1.932ns (routing 0.599ns, distribution 1.333ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       2.380     2.606    d_1_i/rst_100/U0/slowest_sync_clk
    SLICE_X102Y67        FDRE                                         r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/C
  -------------------------------------------------------------------    -------------------
    SLICE_X102Y67        FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.079     2.685 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/Q
                         net (fo=118, routed)         2.585     5.270    d_1_i/axi_dma_mr/U0/I_RST_MODULE/REG_HRD_RST/peripheral_aresetn[0]_bufg_place_replica
    SLICE_X62Y48         FDRE                                         r  d_1_i/axi_dma_mr/U0/I_RST_MODULE/REG_HRD_RST/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.932     2.114    d_1_i/axi_dma_mr/U0/I_RST_MODULE/REG_HRD_RST/s_axi_lite_aclk
    SLICE_X62Y48         FDRE                                         r  d_1_i/axi_dma_mr/U0/I_RST_MODULE/REG_HRD_RST/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/C

Slack:                    inf
  Source:                 d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[0]/PRE
                            (recovery check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Recovery (Max at Slow Process Corner)
  Data Path Delay:        2.621ns  (logic 0.107ns (4.082%)  route 2.514ns (95.918%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        -0.514ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.106ns
    Source Clock Delay      (SCD):    2.620ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.394ns (routing 0.662ns, distribution 1.732ns)
  Clock Net Delay (Destination): 1.924ns (routing 0.599ns, distribution 1.325ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       2.394     2.620    d_1_i/rst_100/U0/slowest_sync_clk
    SLICE_X102Y71        FDRE                                         r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X102Y71        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     2.699 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           1.019     3.718    d_1_i/rst_100/U0/peripheral_aresetn[0]_bufg_place
    BUFGCE_X0Y44         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.746 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_bufg_place/O
                         net (fo=13331, routed)       1.495     5.241    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/src_arst
    SLICE_X25Y23         FDPE                                         f  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[0]/PRE  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.924     2.106    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/dest_clk
    SLICE_X25Y23         FDPE                                         r  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[1]/PRE
                            (recovery check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Recovery (Max at Slow Process Corner)
  Data Path Delay:        2.621ns  (logic 0.107ns (4.082%)  route 2.514ns (95.918%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        -0.514ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.106ns
    Source Clock Delay      (SCD):    2.620ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.394ns (routing 0.662ns, distribution 1.732ns)
  Clock Net Delay (Destination): 1.924ns (routing 0.599ns, distribution 1.325ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       2.394     2.620    d_1_i/rst_100/U0/slowest_sync_clk
    SLICE_X102Y71        FDRE                                         r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X102Y71        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     2.699 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           1.019     3.718    d_1_i/rst_100/U0/peripheral_aresetn[0]_bufg_place
    BUFGCE_X0Y44         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.746 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_bufg_place/O
                         net (fo=13331, routed)       1.495     5.241    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/src_arst
    SLICE_X25Y23         FDPE                                         f  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[1]/PRE  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.924     2.106    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/dest_clk
    SLICE_X25Y23         FDPE                                         r  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[1]/C

Slack:                    inf
  Source:                 d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[0]/PRE
                            (recovery check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Recovery (Max at Slow Process Corner)
  Data Path Delay:        2.618ns  (logic 0.107ns (4.087%)  route 2.511ns (95.913%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        -0.525ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.095ns
    Source Clock Delay      (SCD):    2.620ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.394ns (routing 0.662ns, distribution 1.732ns)
  Clock Net Delay (Destination): 1.913ns (routing 0.599ns, distribution 1.314ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       2.394     2.620    d_1_i/rst_100/U0/slowest_sync_clk
    SLICE_X102Y71        FDRE                                         r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X102Y71        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     2.699 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           1.019     3.718    d_1_i/rst_100/U0/peripheral_aresetn[0]_bufg_place
    BUFGCE_X0Y44         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.746 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_bufg_place/O
                         net (fo=13331, routed)       1.492     5.238    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/src_arst
    SLICE_X31Y28         FDPE                                         f  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[0]/PRE  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.913     2.095    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/dest_clk
    SLICE_X31Y28         FDPE                                         r  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[0]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/axis_switch_gen/inst/gen_static_router.inst_static_router/inst_start_router_config/ctrl_soft_reset_r_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_switch_gen/inst/gen_static_router.gen_synch.inst_rst_synch/inst_xpm_cdc_single/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.127ns  (logic 0.039ns (30.709%)  route 0.088ns (69.291%))
  Logic Levels:           0  
  Clock Path Skew:        0.167ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.412ns
    Source Clock Delay      (SCD):    1.246ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.126ns (routing 0.359ns, distribution 0.767ns)
  Clock Net Delay (Destination): 1.265ns (routing 0.405ns, distribution 0.860ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.126     1.246    d_1_i/axis_switch_gen/inst/gen_static_router.inst_static_router/inst_start_router_config/s_axi_ctrl_aclk
    SLICE_X39Y177        FDRE                                         r  d_1_i/axis_switch_gen/inst/gen_static_router.inst_static_router/inst_start_router_config/ctrl_soft_reset_r_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X39Y177        FDRE (Prop_DFF_SLICEM_C_Q)
                                                      0.039     1.285 r  d_1_i/axis_switch_gen/inst/gen_static_router.inst_static_router/inst_start_router_config/ctrl_soft_reset_r_reg/Q
                         net (fo=1, routed)           0.088     1.373    d_1_i/axis_switch_gen/inst/gen_static_router.gen_synch.inst_rst_synch/inst_xpm_cdc_single/src_in
    SLICE_X39Y178        FDRE                                         r  d_1_i/axis_switch_gen/inst/gen_static_router.gen_synch.inst_rst_synch/inst_xpm_cdc_single/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.265     1.412    d_1_i/axis_switch_gen/inst/gen_static_router.gen_synch.inst_rst_synch/inst_xpm_cdc_single/dest_clk
    SLICE_X39Y178        FDRE                                         r  d_1_i/axis_switch_gen/inst/gen_static_router.gen_synch.inst_rst_synch/inst_xpm_cdc_single/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axis_switch_gen/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_sendd_ff_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_switch_gen/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.158ns  (logic 0.038ns (24.099%)  route 0.120ns (75.901%))
  Logic Levels:           0  
  Clock Path Skew:        0.172ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.416ns
    Source Clock Delay      (SCD):    1.245ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.125ns (routing 0.359ns, distribution 0.766ns)
  Clock Net Delay (Destination): 1.269ns (routing 0.405ns, distribution 0.864ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.125     1.245    d_1_i/axis_switch_gen/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_clk
    SLICE_X39Y177        FDRE                                         r  d_1_i/axis_switch_gen/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_sendd_ff_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X39Y177        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.038     1.283 r  d_1_i/axis_switch_gen/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_sendd_ff_reg/Q
                         net (fo=2, routed)           0.120     1.402    d_1_i/axis_switch_gen/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/src_in
    SLICE_X39Y179        FDRE                                         r  d_1_i/axis_switch_gen/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.269     1.416    d_1_i/axis_switch_gen/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/dest_clk
    SLICE_X39Y179        FDRE                                         r  d_1_i/axis_switch_gen/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axis_switch_buf/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_req_ff_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_switch_buf/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.120ns  (logic 0.039ns (32.475%)  route 0.081ns (67.525%))
  Logic Levels:           0  
  Clock Path Skew:        0.187ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.496ns
    Source Clock Delay      (SCD):    1.309ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.189ns (routing 0.359ns, distribution 0.830ns)
  Clock Net Delay (Destination): 1.349ns (routing 0.405ns, distribution 0.944ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.189     1.309    d_1_i/axis_switch_buf/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_clk
    SLICE_X68Y93         FDRE                                         r  d_1_i/axis_switch_buf/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_req_ff_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X68Y93         FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.039     1.348 r  d_1_i/axis_switch_buf/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_req_ff_reg/Q
                         net (fo=2, routed)           0.081     1.429    d_1_i/axis_switch_buf/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/src_in
    SLICE_X68Y93         FDRE                                         r  d_1_i/axis_switch_buf/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.349     1.496    d_1_i/axis_switch_buf/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/dest_clk
    SLICE_X68Y93         FDRE                                         r  d_1_i/axis_switch_buf/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/attn_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/attn_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.098ns  (logic 0.039ns (39.925%)  route 0.059ns (60.075%))
  Logic Levels:           0  
  Clock Path Skew:        0.182ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.517ns
    Source Clock Delay      (SCD):    1.335ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.215ns (routing 0.359ns, distribution 0.856ns)
  Clock Net Delay (Destination): 1.370ns (routing 0.405ns, distribution 0.965ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.215     1.335    d_1_i/attn_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/rd_clk
    SLICE_X74Y38         FDRE                                         r  d_1_i/attn_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X74Y38         FDRE (Prop_BFF_SLICEL_C_Q)
                                                      0.039     1.374 r  d_1_i/attn_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg/Q
                         net (fo=35, routed)          0.059     1.432    d_1_i/attn_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/src_rst
    SLICE_X74Y37         FDRE                                         r  d_1_i/attn_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.370     1.517    d_1_i/attn_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/dest_clk
    SLICE_X74Y37         FDRE                                         r  d_1_i/attn_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/lo_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_wr_rst_ic_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/lo_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.103ns  (logic 0.039ns (37.981%)  route 0.064ns (62.019%))
  Logic Levels:           0  
  Clock Path Skew:        0.188ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.534ns
    Source Clock Delay      (SCD):    1.346ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.226ns (routing 0.359ns, distribution 0.867ns)
  Clock Net Delay (Destination): 1.387ns (routing 0.405ns, distribution 0.982ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.226     1.346    d_1_i/lo_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/wr_clk
    SLICE_X77Y40         FDRE                                         r  d_1_i/lo_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_wr_rst_ic_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X77Y40         FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.039     1.385 r  d_1_i/lo_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_wr_rst_ic_reg/Q
                         net (fo=2, routed)           0.064     1.448    d_1_i/lo_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst/src_rst
    SLICE_X77Y38         FDRE                                         r  d_1_i/lo_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.387     1.534    d_1_i/lo_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst/dest_clk
    SLICE_X77Y38         FDRE                                         r  d_1_i/lo_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/lo_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_wr_rst_ic_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/lo_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.103ns  (logic 0.039ns (37.858%)  route 0.064ns (62.142%))
  Logic Levels:           0  
  Clock Path Skew:        0.192ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.537ns
    Source Clock Delay      (SCD):    1.346ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.226ns (routing 0.359ns, distribution 0.867ns)
  Clock Net Delay (Destination): 1.390ns (routing 0.405ns, distribution 0.985ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.226     1.346    d_1_i/lo_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/wr_clk
    SLICE_X79Y39         FDRE                                         r  d_1_i/lo_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_wr_rst_ic_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X79Y39         FDRE (Prop_GFF_SLICEM_C_Q)
                                                      0.039     1.385 r  d_1_i/lo_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_wr_rst_ic_reg/Q
                         net (fo=2, routed)           0.064     1.449    d_1_i/lo_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst/src_rst
    SLICE_X79Y39         FDRE                                         r  d_1_i/lo_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.390     1.537    d_1_i/lo_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst/dest_clk
    SLICE_X79Y39         FDRE                                         r  d_1_i/lo_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axis_switch_buf/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_sendd_ff_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_switch_buf/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.156ns  (logic 0.038ns (24.287%)  route 0.118ns (75.713%))
  Logic Levels:           0  
  Clock Path Skew:        0.188ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.492ns
    Source Clock Delay      (SCD):    1.304ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.184ns (routing 0.359ns, distribution 0.825ns)
  Clock Net Delay (Destination): 1.345ns (routing 0.405ns, distribution 0.940ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.184     1.304    d_1_i/axis_switch_buf/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_clk
    SLICE_X66Y93         FDRE                                         r  d_1_i/axis_switch_buf/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_sendd_ff_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X66Y93         FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.038     1.342 r  d_1_i/axis_switch_buf/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_sendd_ff_reg/Q
                         net (fo=2, routed)           0.118     1.460    d_1_i/axis_switch_buf/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/src_in
    SLICE_X68Y93         FDRE                                         r  d_1_i/axis_switch_buf/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.345     1.492    d_1_i/axis_switch_buf/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/dest_clk
    SLICE_X68Y93         FDRE                                         r  d_1_i/axis_switch_buf/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/attn_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/attn_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.138ns  (logic 0.037ns (26.845%)  route 0.101ns (73.155%))
  Logic Levels:           0  
  Clock Path Skew:        0.200ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.524ns
    Source Clock Delay      (SCD):    1.324ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.204ns (routing 0.359ns, distribution 0.845ns)
  Clock Net Delay (Destination): 1.377ns (routing 0.405ns, distribution 0.972ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.204     1.324    d_1_i/attn_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/rd_clk
    SLICE_X66Y43         FDRE                                         r  d_1_i/attn_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X66Y43         FDRE (Prop_FFF_SLICEM_C_Q)
                                                      0.037     1.361 r  d_1_i/attn_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg/Q
                         net (fo=41, routed)          0.101     1.461    d_1_i/attn_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/src_rst
    SLICE_X68Y43         FDRE                                         r  d_1_i/attn_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.377     1.524    d_1_i/attn_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/dest_clk
    SLICE_X68Y43         FDRE                                         r  d_1_i/attn_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/attn_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_15_14_15__0/DP/CLK
                            (rising edge-triggered cell RAMD32 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/attn_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg_reg[15]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.113ns  (logic 0.105ns (92.920%)  route 0.008ns (7.080%))
  Logic Levels:           0  
  Clock Path Skew:        0.171ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.525ns
    Source Clock Delay      (SCD):    1.354ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.234ns (routing 0.359ns, distribution 0.875ns)
  Clock Net Delay (Destination): 1.378ns (routing 0.405ns, distribution 0.973ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.234     1.354    d_1_i/attn_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_15_14_15__0/WCLK
    SLICE_X69Y45         RAMD32                                       r  d_1_i/attn_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_15_14_15__0/DP/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X69Y45         RAMD32 (Prop_G5LUT_SLICEM_CLK_O)
                                                      0.105     1.459 r  d_1_i/attn_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_15_14_15__0/DP/O
                         net (fo=1, routed)           0.008     1.467    d_1_i/attn_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg_reg0[15]
    SLICE_X69Y45         FDRE                                         r  d_1_i/attn_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg_reg[15]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.378     1.525    d_1_i/attn_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X69Y45         FDRE                                         r  d_1_i/attn_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg_reg[15]/C

Slack:                    inf
  Source:                 d_1_i/attn_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_15_0_13/RAMG/CLK
                            (rising edge-triggered cell RAMD32 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/attn_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg_reg[12]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.113ns  (logic 0.105ns (92.920%)  route 0.008ns (7.080%))
  Logic Levels:           0  
  Clock Path Skew:        0.171ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.526ns
    Source Clock Delay      (SCD):    1.355ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.235ns (routing 0.359ns, distribution 0.876ns)
  Clock Net Delay (Destination): 1.379ns (routing 0.405ns, distribution 0.974ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.235     1.355    d_1_i/attn_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_15_0_13/WCLK
    SLICE_X69Y46         RAMD32                                       r  d_1_i/attn_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_15_0_13/RAMG/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X69Y46         RAMD32 (Prop_G5LUT_SLICEM_CLK_O)
                                                      0.105     1.460 r  d_1_i/attn_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_15_0_13/RAMG/O
                         net (fo=1, routed)           0.008     1.468    d_1_i/attn_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg_reg0[12]
    SLICE_X69Y46         FDRE                                         r  d_1_i/attn_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg_reg[12]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.379     1.526    d_1_i/attn_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X69Y46         FDRE                                         r  d_1_i/attn_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_nc_narrow_pipe.doutb_reg_reg[12]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  mmcm_clkout5
  To Clock:  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK

Max Delay            94 Endpoints
Min Delay           102 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[0]/R
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.333ns  (logic 0.076ns (5.701%)  route 1.257ns (94.299%))
  Logic Levels:           0  
  Clock Path Skew:        -0.979ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.267ns
    Source Clock Delay      (SCD):    4.246ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.499ns (routing 0.632ns, distribution 0.867ns)
  Clock Net Delay (Destination): 1.559ns (routing 0.470ns, distribution 1.089ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.524     2.610    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     2.483 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.236     2.719    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y115        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.747 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.499     4.246    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/clk
    SLICE_X103Y341       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X103Y341       FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     4.322 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/Q
                         net (fo=176, routed)         1.257     5.579    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/ctl_reg_reg[0]_0
    SLICE_X100Y356       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[0]/R
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.219     1.684    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y81         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.708 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.559     3.267    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/m_bscan_tck[0]
    SLICE_X100Y356       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[0]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[1]/R
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.333ns  (logic 0.076ns (5.701%)  route 1.257ns (94.299%))
  Logic Levels:           0  
  Clock Path Skew:        -0.979ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.267ns
    Source Clock Delay      (SCD):    4.246ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.499ns (routing 0.632ns, distribution 0.867ns)
  Clock Net Delay (Destination): 1.559ns (routing 0.470ns, distribution 1.089ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.524     2.610    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     2.483 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.236     2.719    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y115        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.747 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.499     4.246    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/clk
    SLICE_X103Y341       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X103Y341       FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     4.322 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/Q
                         net (fo=176, routed)         1.257     5.579    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/ctl_reg_reg[0]_0
    SLICE_X100Y356       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[1]/R
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.219     1.684    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y81         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.708 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.559     3.267    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/m_bscan_tck[0]
    SLICE_X100Y356       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[1]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[10]/R
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.308ns  (logic 0.076ns (5.811%)  route 1.232ns (94.189%))
  Logic Levels:           0  
  Clock Path Skew:        -0.974ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.272ns
    Source Clock Delay      (SCD):    4.246ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.499ns (routing 0.632ns, distribution 0.867ns)
  Clock Net Delay (Destination): 1.564ns (routing 0.470ns, distribution 1.094ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.524     2.610    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     2.483 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.236     2.719    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y115        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.747 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.499     4.246    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/clk
    SLICE_X103Y341       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X103Y341       FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     4.322 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/Q
                         net (fo=176, routed)         1.232     5.554    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/ctl_reg_reg[0]_0
    SLICE_X100Y355       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[10]/R
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.219     1.684    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y81         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.708 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.564     3.272    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/m_bscan_tck[0]
    SLICE_X100Y355       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[10]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[11]/R
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.308ns  (logic 0.076ns (5.811%)  route 1.232ns (94.189%))
  Logic Levels:           0  
  Clock Path Skew:        -0.974ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.272ns
    Source Clock Delay      (SCD):    4.246ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.499ns (routing 0.632ns, distribution 0.867ns)
  Clock Net Delay (Destination): 1.564ns (routing 0.470ns, distribution 1.094ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.524     2.610    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     2.483 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.236     2.719    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y115        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.747 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.499     4.246    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/clk
    SLICE_X103Y341       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X103Y341       FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     4.322 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/Q
                         net (fo=176, routed)         1.232     5.554    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/ctl_reg_reg[0]_0
    SLICE_X100Y355       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[11]/R
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.219     1.684    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y81         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.708 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.564     3.272    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/m_bscan_tck[0]
    SLICE_X100Y355       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[11]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[12]/R
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.308ns  (logic 0.076ns (5.811%)  route 1.232ns (94.189%))
  Logic Levels:           0  
  Clock Path Skew:        -0.974ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.272ns
    Source Clock Delay      (SCD):    4.246ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.499ns (routing 0.632ns, distribution 0.867ns)
  Clock Net Delay (Destination): 1.564ns (routing 0.470ns, distribution 1.094ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.524     2.610    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     2.483 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.236     2.719    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y115        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.747 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.499     4.246    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/clk
    SLICE_X103Y341       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X103Y341       FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     4.322 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/Q
                         net (fo=176, routed)         1.232     5.554    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/ctl_reg_reg[0]_0
    SLICE_X100Y355       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[12]/R
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.219     1.684    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y81         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.708 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.564     3.272    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/m_bscan_tck[0]
    SLICE_X100Y355       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[12]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[13]/R
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.308ns  (logic 0.076ns (5.811%)  route 1.232ns (94.189%))
  Logic Levels:           0  
  Clock Path Skew:        -0.974ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.272ns
    Source Clock Delay      (SCD):    4.246ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.499ns (routing 0.632ns, distribution 0.867ns)
  Clock Net Delay (Destination): 1.564ns (routing 0.470ns, distribution 1.094ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.524     2.610    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     2.483 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.236     2.719    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y115        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.747 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.499     4.246    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/clk
    SLICE_X103Y341       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X103Y341       FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     4.322 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/Q
                         net (fo=176, routed)         1.232     5.554    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/ctl_reg_reg[0]_0
    SLICE_X100Y355       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[13]/R
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.219     1.684    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y81         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.708 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.564     3.272    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/m_bscan_tck[0]
    SLICE_X100Y355       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[13]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[2]/R
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.308ns  (logic 0.076ns (5.811%)  route 1.232ns (94.189%))
  Logic Levels:           0  
  Clock Path Skew:        -0.974ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.272ns
    Source Clock Delay      (SCD):    4.246ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.499ns (routing 0.632ns, distribution 0.867ns)
  Clock Net Delay (Destination): 1.564ns (routing 0.470ns, distribution 1.094ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.524     2.610    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     2.483 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.236     2.719    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y115        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.747 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.499     4.246    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/clk
    SLICE_X103Y341       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X103Y341       FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     4.322 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/Q
                         net (fo=176, routed)         1.232     5.554    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/ctl_reg_reg[0]_0
    SLICE_X100Y355       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[2]/R
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.219     1.684    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y81         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.708 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.564     3.272    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/m_bscan_tck[0]
    SLICE_X100Y355       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[2]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[3]/R
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.308ns  (logic 0.076ns (5.811%)  route 1.232ns (94.189%))
  Logic Levels:           0  
  Clock Path Skew:        -0.974ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.272ns
    Source Clock Delay      (SCD):    4.246ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.499ns (routing 0.632ns, distribution 0.867ns)
  Clock Net Delay (Destination): 1.564ns (routing 0.470ns, distribution 1.094ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.524     2.610    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     2.483 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.236     2.719    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y115        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.747 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.499     4.246    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/clk
    SLICE_X103Y341       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X103Y341       FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     4.322 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/Q
                         net (fo=176, routed)         1.232     5.554    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/ctl_reg_reg[0]_0
    SLICE_X100Y355       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[3]/R
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.219     1.684    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y81         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.708 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.564     3.272    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/m_bscan_tck[0]
    SLICE_X100Y355       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[3]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[4]/R
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.308ns  (logic 0.076ns (5.811%)  route 1.232ns (94.189%))
  Logic Levels:           0  
  Clock Path Skew:        -0.974ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.272ns
    Source Clock Delay      (SCD):    4.246ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.499ns (routing 0.632ns, distribution 0.867ns)
  Clock Net Delay (Destination): 1.564ns (routing 0.470ns, distribution 1.094ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.524     2.610    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     2.483 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.236     2.719    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y115        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.747 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.499     4.246    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/clk
    SLICE_X103Y341       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X103Y341       FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     4.322 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/Q
                         net (fo=176, routed)         1.232     5.554    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/ctl_reg_reg[0]_0
    SLICE_X100Y355       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[4]/R
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.219     1.684    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y81         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.708 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.564     3.272    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/m_bscan_tck[0]
    SLICE_X100Y355       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[4]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[5]/R
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.308ns  (logic 0.076ns (5.811%)  route 1.232ns (94.189%))
  Logic Levels:           0  
  Clock Path Skew:        -0.974ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.272ns
    Source Clock Delay      (SCD):    4.246ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.499ns (routing 0.632ns, distribution 0.867ns)
  Clock Net Delay (Destination): 1.564ns (routing 0.470ns, distribution 1.094ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.524     2.610    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     2.483 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.236     2.719    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y115        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.747 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.499     4.246    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/clk
    SLICE_X103Y341       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X103Y341       FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     4.322 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/Q
                         net (fo=176, routed)         1.232     5.554    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/ctl_reg_reg[0]_0
    SLICE_X100Y355       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[5]/R
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.219     1.684    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y81         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.708 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.564     3.272    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/m_bscan_tck[0]
    SLICE_X100Y355       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[5]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/stat_reg_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/stat_reg_1_reg[1]/D
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.119ns  (logic 0.040ns (33.613%)  route 0.079ns (66.387%))
  Logic Levels:           0  
  Clock Path Skew:        3.991ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    6.665ns
    Source Clock Delay      (SCD):    2.674ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      0.831ns (routing 0.347ns, distribution 0.484ns)
  Clock Net Delay (Destination): 1.082ns (routing 0.313ns, distribution 0.769ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.839     1.456    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     1.686 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.140     1.826    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y115        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.843 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.831     2.674    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/clk
    SLICE_X105Y337       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/stat_reg_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X105Y337       FDRE (Prop_AFF2_SLICEL_C_Q)
                                                      0.040     2.714 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/stat_reg_reg[1]/Q
                         net (fo=1, routed)           0.079     2.793    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/stat_reg[1]
    SLICE_X105Y338       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/stat_reg_1_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.264     5.564    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y81         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     5.583 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.082     6.665    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/m_bscan_tck[0]
    SLICE_X105Y338       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/stat_reg_1_reg[1]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD3/stat_reg_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD3/stat_reg_1_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.119ns  (logic 0.040ns (33.613%)  route 0.079ns (66.387%))
  Logic Levels:           0  
  Clock Path Skew:        3.989ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    6.668ns
    Source Clock Delay      (SCD):    2.680ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      0.837ns (routing 0.347ns, distribution 0.490ns)
  Clock Net Delay (Destination): 1.085ns (routing 0.313ns, distribution 0.772ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.839     1.456    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     1.686 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.140     1.826    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y115        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.843 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.837     2.680    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD3/clk
    SLICE_X105Y341       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD3/stat_reg_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X105Y341       FDRE (Prop_AFF2_SLICEL_C_Q)
                                                      0.040     2.720 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD3/stat_reg_reg[0]/Q
                         net (fo=1, routed)           0.079     2.799    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD3/stat_reg[0]
    SLICE_X105Y342       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD3/stat_reg_1_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.264     5.564    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y81         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     5.583 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.085     6.668    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD3/m_bscan_tck[0]
    SLICE_X105Y342       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD3/stat_reg_1_reg[0]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/stat_reg_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/stat_reg_1_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.125ns  (logic 0.039ns (31.200%)  route 0.086ns (68.800%))
  Logic Levels:           0  
  Clock Path Skew:        3.997ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    6.673ns
    Source Clock Delay      (SCD):    2.676ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      0.833ns (routing 0.347ns, distribution 0.486ns)
  Clock Net Delay (Destination): 1.090ns (routing 0.313ns, distribution 0.777ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.839     1.456    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     1.686 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.140     1.826    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y115        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.843 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.833     2.676    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/clk
    SLICE_X104Y336       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/stat_reg_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X104Y336       FDRE (Prop_AFF2_SLICEM_C_Q)
                                                      0.039     2.715 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/stat_reg_reg[0]/Q
                         net (fo=1, routed)           0.086     2.801    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/stat_reg[0]
    SLICE_X104Y337       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/stat_reg_1_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.264     5.564    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y81         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     5.583 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.090     6.673    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/m_bscan_tck[0]
    SLICE_X104Y337       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/stat_reg_1_reg[0]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[3]/C
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[3]/D
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.125ns  (logic 0.039ns (31.200%)  route 0.086ns (68.800%))
  Logic Levels:           0  
  Clock Path Skew:        4.003ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    6.680ns
    Source Clock Delay      (SCD):    2.677ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      0.834ns (routing 0.347ns, distribution 0.487ns)
  Clock Net Delay (Destination): 1.097ns (routing 0.313ns, distribution 0.784ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.839     1.456    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     1.686 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.140     1.826    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y115        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.843 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.834     2.677    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_clk
    SLICE_X102Y349       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X102Y349       FDCE (Prop_EFF_SLICEL_C_Q)
                                                      0.039     2.716 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[3]/Q
                         net (fo=1, routed)           0.086     2.802    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q[3]
    SLICE_X101Y349       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[3]/D
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.264     5.564    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y81         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     5.583 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.097     6.680    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/rd_clk
    SLICE_X101Y349       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[3]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/stat_reg_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/stat_reg_1_reg[2]/D
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.124ns  (logic 0.039ns (31.452%)  route 0.085ns (68.548%))
  Logic Levels:           0  
  Clock Path Skew:        3.992ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    6.670ns
    Source Clock Delay      (SCD):    2.678ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      0.835ns (routing 0.347ns, distribution 0.488ns)
  Clock Net Delay (Destination): 1.087ns (routing 0.313ns, distribution 0.774ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.839     1.456    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     1.686 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.140     1.826    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y115        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.843 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.835     2.678    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/clk
    SLICE_X104Y338       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/stat_reg_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X104Y338       FDRE (Prop_AFF2_SLICEM_C_Q)
                                                      0.039     2.717 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/stat_reg_reg[2]/Q
                         net (fo=1, routed)           0.085     2.802    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/stat_reg[2]
    SLICE_X104Y339       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/stat_reg_1_reg[2]/D
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.264     5.564    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y81         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     5.583 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.087     6.670    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/m_bscan_tck[0]
    SLICE_X104Y339       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/stat_reg_1_reg[2]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD2/stat_reg_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD2/stat_reg_1_reg[3]/D
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.124ns  (logic 0.039ns (31.452%)  route 0.085ns (68.548%))
  Logic Levels:           0  
  Clock Path Skew:        3.996ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    6.676ns
    Source Clock Delay      (SCD):    2.680ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      0.837ns (routing 0.347ns, distribution 0.490ns)
  Clock Net Delay (Destination): 1.093ns (routing 0.313ns, distribution 0.780ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.839     1.456    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     1.686 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.140     1.826    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y115        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.843 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.837     2.680    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD2/clk
    SLICE_X103Y349       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD2/stat_reg_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X103Y349       FDRE (Prop_AFF2_SLICEM_C_Q)
                                                      0.039     2.719 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD2/stat_reg_reg[3]/Q
                         net (fo=1, routed)           0.085     2.804    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD2/stat_reg[3]
    SLICE_X103Y350       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD2/stat_reg_1_reg[3]/D
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.264     5.564    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y81         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     5.583 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.093     6.676    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD2/m_bscan_tck[0]
    SLICE_X103Y350       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD2/stat_reg_1_reg[3]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[1]/C
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[1]/D
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.129ns  (logic 0.039ns (30.233%)  route 0.090ns (69.767%))
  Logic Levels:           0  
  Clock Path Skew:        3.999ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    6.676ns
    Source Clock Delay      (SCD):    2.677ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      0.834ns (routing 0.347ns, distribution 0.487ns)
  Clock Net Delay (Destination): 1.093ns (routing 0.313ns, distribution 0.780ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.839     1.456    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     1.686 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.140     1.826    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y115        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.843 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.834     2.677    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_clk
    SLICE_X102Y349       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X102Y349       FDCE (Prop_HFF2_SLICEL_C_Q)
                                                      0.039     2.716 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[1]/Q
                         net (fo=1, routed)           0.090     2.806    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q[1]
    SLICE_X102Y349       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.264     5.564    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y81         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     5.583 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.093     6.676    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/rd_clk
    SLICE_X102Y349       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[1]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD3/stat_reg_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD3/stat_reg_1_reg[1]/D
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.124ns  (logic 0.039ns (31.452%)  route 0.085ns (68.548%))
  Logic Levels:           0  
  Clock Path Skew:        3.994ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    6.676ns
    Source Clock Delay      (SCD):    2.683ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      0.840ns (routing 0.347ns, distribution 0.493ns)
  Clock Net Delay (Destination): 1.093ns (routing 0.313ns, distribution 0.780ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.839     1.456    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     1.686 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.140     1.826    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y115        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.843 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.840     2.683    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD3/clk
    SLICE_X104Y341       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD3/stat_reg_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X104Y341       FDRE (Prop_AFF2_SLICEM_C_Q)
                                                      0.039     2.722 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD3/stat_reg_reg[1]/Q
                         net (fo=1, routed)           0.085     2.807    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD3/stat_reg[1]
    SLICE_X104Y342       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD3/stat_reg_1_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.264     5.564    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y81         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     5.583 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.093     6.676    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD3/m_bscan_tck[0]
    SLICE_X104Y342       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD3/stat_reg_1_reg[1]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD2/stat_reg_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD2/stat_reg_1_reg[1]/D
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.120ns  (logic 0.040ns (33.333%)  route 0.080ns (66.667%))
  Logic Levels:           0  
  Clock Path Skew:        3.984ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    6.671ns
    Source Clock Delay      (SCD):    2.687ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      0.844ns (routing 0.347ns, distribution 0.497ns)
  Clock Net Delay (Destination): 1.088ns (routing 0.313ns, distribution 0.775ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.839     1.456    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     1.686 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.140     1.826    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y115        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.843 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.844     2.687    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD2/clk
    SLICE_X105Y350       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD2/stat_reg_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X105Y350       FDRE (Prop_AFF2_SLICEL_C_Q)
                                                      0.040     2.727 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD2/stat_reg_reg[1]/Q
                         net (fo=1, routed)           0.080     2.807    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD2/stat_reg[1]
    SLICE_X105Y351       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD2/stat_reg_1_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.264     5.564    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y81         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     5.583 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.088     6.671    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD2/m_bscan_tck[0]
    SLICE_X105Y351       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD2/stat_reg_1_reg[1]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD2/stat_reg_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD2/stat_reg_1_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.124ns  (logic 0.039ns (31.452%)  route 0.085ns (68.548%))
  Logic Levels:           0  
  Clock Path Skew:        3.990ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    6.679ns
    Source Clock Delay      (SCD):    2.689ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      0.846ns (routing 0.347ns, distribution 0.499ns)
  Clock Net Delay (Destination): 1.096ns (routing 0.313ns, distribution 0.783ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.839     1.456    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     1.686 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.140     1.826    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y115        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.843 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.846     2.689    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD2/clk
    SLICE_X104Y348       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD2/stat_reg_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X104Y348       FDRE (Prop_AFF2_SLICEM_C_Q)
                                                      0.039     2.728 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD2/stat_reg_reg[0]/Q
                         net (fo=1, routed)           0.085     2.813    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD2/stat_reg[0]
    SLICE_X104Y349       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD2/stat_reg_1_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.264     5.564    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y81         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     5.583 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.096     6.679    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD2/m_bscan_tck[0]
    SLICE_X104Y349       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD2/stat_reg_1_reg[0]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  RFDAC0_CLK
  To Clock:  mmcm_clkout0

Max Delay             1 Endpoint
Min Delay             1 Endpoint
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[9]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/trigger_resync_i/data_int_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.556ns  (logic 0.079ns (14.201%)  route 0.477ns (85.799%))
  Logic Levels:           0  
  Clock Path Skew:        1.536ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.026ns
    Source Clock Delay      (SCD):    3.490ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.161ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      2.817ns (routing 1.460ns, distribution 1.357ns)
  Clock Net Delay (Destination): 1.879ns (routing 0.630ns, distribution 1.249ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y100       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89456, routed)       2.817     3.490    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
    SLICE_X52Y207        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[9]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X52Y207        FDCE (Prop_HFF_SLICEL_C_Q)
                                                      0.079     3.569 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[9]/Q
                         net (fo=2, routed)           0.477     4.047    d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/trigger_resync_i/trigger
    SLICE_X51Y190        FDRE                                         r  d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/trigger_resync_i/data_int_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.364     2.279    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.909 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.214     3.123    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.147 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.879     5.026    d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/trigger_resync_i/aclk
    SLICE_X51Y190        FDRE                                         r  d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/trigger_resync_i/data_int_reg_reg[0]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[9]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Destination:            d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/trigger_resync_i/data_int_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.270ns  (logic 0.039ns (14.439%)  route 0.231ns (85.561%))
  Logic Levels:           0  
  Clock Path Skew:        1.038ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.921ns
    Source Clock Delay      (SCD):    1.883ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.161ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.534ns (routing 0.786ns, distribution 0.748ns)
  Clock Net Delay (Destination): 1.305ns (routing 0.432ns, distribution 0.873ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y100       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89456, routed)       1.534     1.883    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
    SLICE_X52Y207        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[9]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X52Y207        FDCE (Prop_HFF_SLICEL_C_Q)
                                                      0.039     1.922 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[9]/Q
                         net (fo=2, routed)           0.231     2.153    d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/trigger_resync_i/trigger
    SLICE_X51Y190        FDRE                                         r  d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/trigger_resync_i/data_int_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.940     1.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.432 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.165     1.597    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.616 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.305     2.921    d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/trigger_resync_i/aclk
    SLICE_X51Y190        FDRE                                         r  d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/trigger_resync_i/data_int_reg_reg[0]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  clk_out1_d_1_clk_adc0_x2_0
  To Clock:  mmcm_clkout0

Max Delay           518 Endpoints
Min Delay           518 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_392_405/RAMD/CLK
                            (rising edge-triggered cell RAMD32 clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[398]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.185ns  (logic 0.287ns (24.219%)  route 0.898ns (75.781%))
  Logic Levels:           0  
  Clock Path Skew:        -1.415ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.075ns
    Source Clock Delay      (SCD):    6.490ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.220ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.176ns
    Phase Error              (PE):    0.125ns
  Clock Net Delay (Source):      3.160ns (routing 1.545ns, distribution 1.615ns)
  Clock Net Delay (Destination): 1.928ns (routing 0.630ns, distribution 1.298ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.657     3.184    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     3.057 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     3.302    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.330 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86296, routed)       3.160     6.490    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_392_405/WCLK
    SLICE_X37Y254        RAMD32                                       r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_392_405/RAMD/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X37Y254        RAMD32 (Prop_D5LUT_SLICEM_CLK_O)
                                                      0.287     6.777 r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_392_405/RAMD/O
                         net (fo=1, routed)           0.898     7.675    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0[398]
    SLICE_X44Y260        FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[398]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.364     2.279    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.909 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.214     3.123    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.147 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.928     5.075    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X44Y260        FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[398]/C

Slack:                    inf
  Source:                 d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_392_405/RAMG_D1/CLK
                            (rising edge-triggered cell RAMD32 clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[405]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.109ns  (logic 0.295ns (26.601%)  route 0.814ns (73.399%))
  Logic Levels:           0  
  Clock Path Skew:        -1.409ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.081ns
    Source Clock Delay      (SCD):    6.490ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.220ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.176ns
    Phase Error              (PE):    0.125ns
  Clock Net Delay (Source):      3.160ns (routing 1.545ns, distribution 1.615ns)
  Clock Net Delay (Destination): 1.934ns (routing 0.630ns, distribution 1.304ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.657     3.184    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     3.057 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     3.302    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.330 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86296, routed)       3.160     6.490    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_392_405/WCLK
    SLICE_X37Y254        RAMD32                                       r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_392_405/RAMG_D1/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X37Y254        RAMD32 (Prop_G6LUT_SLICEM_CLK_O)
                                                      0.295     6.785 r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_392_405/RAMG_D1/O
                         net (fo=1, routed)           0.814     7.599    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0[405]
    SLICE_X44Y259        FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[405]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.364     2.279    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.909 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.214     3.123    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.147 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.934     5.081    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X44Y259        FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[405]/C

Slack:                    inf
  Source:                 d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_392_405/RAME_D1/CLK
                            (rising edge-triggered cell RAMD32 clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[401]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.105ns  (logic 0.302ns (27.330%)  route 0.803ns (72.670%))
  Logic Levels:           0  
  Clock Path Skew:        -1.397ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.093ns
    Source Clock Delay      (SCD):    6.490ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.220ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.176ns
    Phase Error              (PE):    0.125ns
  Clock Net Delay (Source):      3.160ns (routing 1.545ns, distribution 1.615ns)
  Clock Net Delay (Destination): 1.946ns (routing 0.630ns, distribution 1.316ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.657     3.184    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     3.057 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     3.302    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.330 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86296, routed)       3.160     6.490    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_392_405/WCLK
    SLICE_X37Y254        RAMD32                                       r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_392_405/RAME_D1/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X37Y254        RAMD32 (Prop_E6LUT_SLICEM_CLK_O)
                                                      0.302     6.792 r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_392_405/RAME_D1/O
                         net (fo=1, routed)           0.803     7.595    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0[401]
    SLICE_X43Y258        FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[401]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.364     2.279    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.909 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.214     3.123    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.147 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.946     5.093    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X43Y258        FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[401]/C

Slack:                    inf
  Source:                 d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_420_433/RAMF_D1/CLK
                            (rising edge-triggered cell RAMD32 clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[431]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.082ns  (logic 0.304ns (28.096%)  route 0.778ns (71.904%))
  Logic Levels:           0  
  Clock Path Skew:        -1.400ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.091ns
    Source Clock Delay      (SCD):    6.491ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.220ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.176ns
    Phase Error              (PE):    0.125ns
  Clock Net Delay (Source):      3.161ns (routing 1.545ns, distribution 1.616ns)
  Clock Net Delay (Destination): 1.944ns (routing 0.630ns, distribution 1.314ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.657     3.184    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     3.057 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     3.302    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.330 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86296, routed)       3.161     6.491    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_420_433/WCLK
    SLICE_X37Y252        RAMD32                                       r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_420_433/RAMF_D1/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X37Y252        RAMD32 (Prop_F6LUT_SLICEM_CLK_O)
                                                      0.304     6.795 r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_420_433/RAMF_D1/O
                         net (fo=1, routed)           0.778     7.573    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0[431]
    SLICE_X43Y258        FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[431]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.364     2.279    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.909 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.214     3.123    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.147 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.944     5.091    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X43Y258        FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[431]/C

Slack:                    inf
  Source:                 d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_420_433/RAMB/CLK
                            (rising edge-triggered cell RAMD32 clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[422]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.072ns  (logic 0.292ns (27.239%)  route 0.780ns (72.761%))
  Logic Levels:           0  
  Clock Path Skew:        -1.398ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.093ns
    Source Clock Delay      (SCD):    6.491ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.220ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.176ns
    Phase Error              (PE):    0.125ns
  Clock Net Delay (Source):      3.161ns (routing 1.545ns, distribution 1.616ns)
  Clock Net Delay (Destination): 1.946ns (routing 0.630ns, distribution 1.316ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.657     3.184    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     3.057 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     3.302    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.330 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86296, routed)       3.161     6.491    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_420_433/WCLK
    SLICE_X37Y252        RAMD32                                       r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_420_433/RAMB/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X37Y252        RAMD32 (Prop_B5LUT_SLICEM_CLK_O)
                                                      0.292     6.783 r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_420_433/RAMB/O
                         net (fo=1, routed)           0.780     7.563    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0[422]
    SLICE_X43Y258        FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[422]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.364     2.279    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.909 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.214     3.123    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.147 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.946     5.093    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X43Y258        FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[422]/C

Slack:                    inf
  Source:                 d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_420_433/RAMD/CLK
                            (rising edge-triggered cell RAMD32 clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[426]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.070ns  (logic 0.287ns (26.822%)  route 0.783ns (73.178%))
  Logic Levels:           0  
  Clock Path Skew:        -1.408ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.083ns
    Source Clock Delay      (SCD):    6.491ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.220ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.176ns
    Phase Error              (PE):    0.125ns
  Clock Net Delay (Source):      3.161ns (routing 1.545ns, distribution 1.616ns)
  Clock Net Delay (Destination): 1.936ns (routing 0.630ns, distribution 1.306ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.657     3.184    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     3.057 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     3.302    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.330 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86296, routed)       3.161     6.491    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_420_433/WCLK
    SLICE_X37Y252        RAMD32                                       r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_420_433/RAMD/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X37Y252        RAMD32 (Prop_D5LUT_SLICEM_CLK_O)
                                                      0.287     6.778 r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_420_433/RAMD/O
                         net (fo=1, routed)           0.783     7.561    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0[426]
    SLICE_X45Y257        FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[426]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.364     2.279    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.909 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.214     3.123    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.147 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.936     5.083    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X45Y257        FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[426]/C

Slack:                    inf
  Source:                 d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_392_405/RAMG/CLK
                            (rising edge-triggered cell RAMD32 clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[404]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.070ns  (logic 0.281ns (26.262%)  route 0.789ns (73.738%))
  Logic Levels:           0  
  Clock Path Skew:        -1.399ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.091ns
    Source Clock Delay      (SCD):    6.490ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.220ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.176ns
    Phase Error              (PE):    0.125ns
  Clock Net Delay (Source):      3.160ns (routing 1.545ns, distribution 1.615ns)
  Clock Net Delay (Destination): 1.944ns (routing 0.630ns, distribution 1.314ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.657     3.184    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     3.057 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     3.302    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.330 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86296, routed)       3.160     6.490    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_392_405/WCLK
    SLICE_X37Y254        RAMD32                                       r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_392_405/RAMG/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X37Y254        RAMD32 (Prop_G5LUT_SLICEM_CLK_O)
                                                      0.281     6.771 r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_392_405/RAMG/O
                         net (fo=1, routed)           0.789     7.560    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0[404]
    SLICE_X43Y258        FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[404]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.364     2.279    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.909 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.214     3.123    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.147 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.944     5.091    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X43Y258        FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[404]/C

Slack:                    inf
  Source:                 d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_392_405/RAMD_D1/CLK
                            (rising edge-triggered cell RAMD32 clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[399]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.067ns  (logic 0.301ns (28.210%)  route 0.766ns (71.790%))
  Logic Levels:           0  
  Clock Path Skew:        -1.391ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.099ns
    Source Clock Delay      (SCD):    6.490ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.220ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.176ns
    Phase Error              (PE):    0.125ns
  Clock Net Delay (Source):      3.160ns (routing 1.545ns, distribution 1.615ns)
  Clock Net Delay (Destination): 1.952ns (routing 0.630ns, distribution 1.322ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.657     3.184    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     3.057 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     3.302    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.330 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86296, routed)       3.160     6.490    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_392_405/WCLK
    SLICE_X37Y254        RAMD32                                       r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_392_405/RAMD_D1/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X37Y254        RAMD32 (Prop_D6LUT_SLICEM_CLK_O)
                                                      0.301     6.791 r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_392_405/RAMD_D1/O
                         net (fo=1, routed)           0.766     7.557    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0[399]
    SLICE_X40Y254        FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[399]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.364     2.279    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.909 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.214     3.123    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.147 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.952     5.099    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X40Y254        FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[399]/C

Slack:                    inf
  Source:                 d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_392_405/RAME/CLK
                            (rising edge-triggered cell RAMD32 clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[400]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.058ns  (logic 0.288ns (27.221%)  route 0.770ns (72.779%))
  Logic Levels:           0  
  Clock Path Skew:        -1.397ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.093ns
    Source Clock Delay      (SCD):    6.490ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.220ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.176ns
    Phase Error              (PE):    0.125ns
  Clock Net Delay (Source):      3.160ns (routing 1.545ns, distribution 1.615ns)
  Clock Net Delay (Destination): 1.946ns (routing 0.630ns, distribution 1.316ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.657     3.184    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     3.057 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     3.302    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.330 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86296, routed)       3.160     6.490    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_392_405/WCLK
    SLICE_X37Y254        RAMD32                                       r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_392_405/RAME/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X37Y254        RAMD32 (Prop_E5LUT_SLICEM_CLK_O)
                                                      0.288     6.778 r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_392_405/RAME/O
                         net (fo=1, routed)           0.770     7.548    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0[400]
    SLICE_X43Y258        FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[400]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.364     2.279    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.909 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.214     3.123    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.147 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.946     5.093    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X43Y258        FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[400]/C

Slack:                    inf
  Source:                 d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_392_405/RAMB_D1/CLK
                            (rising edge-triggered cell RAMD32 clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[395]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.038ns  (logic 0.307ns (29.576%)  route 0.731ns (70.424%))
  Logic Levels:           0  
  Clock Path Skew:        -1.389ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.101ns
    Source Clock Delay      (SCD):    6.490ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.220ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.176ns
    Phase Error              (PE):    0.125ns
  Clock Net Delay (Source):      3.160ns (routing 1.545ns, distribution 1.615ns)
  Clock Net Delay (Destination): 1.954ns (routing 0.630ns, distribution 1.324ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.657     3.184    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     3.057 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     3.302    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.330 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86296, routed)       3.160     6.490    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_392_405/WCLK
    SLICE_X37Y254        RAMD32                                       r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_392_405/RAMB_D1/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X37Y254        RAMD32 (Prop_B6LUT_SLICEM_CLK_O)
                                                      0.307     6.797 r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_392_405/RAMB_D1/O
                         net (fo=1, routed)           0.731     7.528    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0[395]
    SLICE_X38Y254        FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[395]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.364     2.279    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.909 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.214     3.123    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.147 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.954     5.101    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X38Y254        FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[395]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41/RAMG_D1/CLK
                            (rising edge-triggered cell RAMD32 clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[41]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.169ns  (logic 0.105ns (62.130%)  route 0.064ns (37.870%))
  Logic Levels:           0  
  Clock Path Skew:        -0.848ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.942ns
    Source Clock Delay      (SCD):    3.790ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.220ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.176ns
    Phase Error              (PE):    0.125ns
  Clock Net Delay (Source):      1.683ns (routing 0.846ns, distribution 0.837ns)
  Clock Net Delay (Destination): 1.326ns (routing 0.432ns, distribution 0.894ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.451     1.714    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.944 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     2.090    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.107 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86296, routed)       1.683     3.790    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41/WCLK
    SLICE_X53Y255        RAMD32                                       r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41/RAMG_D1/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X53Y255        RAMD32 (Prop_G6LUT_SLICEM_CLK_O)
                                                      0.105     3.895 r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41/RAMG_D1/O
                         net (fo=1, routed)           0.064     3.959    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0[41]
    SLICE_X53Y256        FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[41]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.940     1.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.432 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.165     1.597    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.616 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.326     2.942    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X53Y256        FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[41]/C

Slack:                    inf
  Source:                 d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.144ns  (logic 0.039ns (27.083%)  route 0.105ns (72.917%))
  Logic Levels:           0  
  Clock Path Skew:        -0.820ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.995ns
    Source Clock Delay      (SCD):    3.815ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.220ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.176ns
    Phase Error              (PE):    0.125ns
  Clock Net Delay (Source):      1.708ns (routing 0.846ns, distribution 0.862ns)
  Clock Net Delay (Destination): 1.379ns (routing 0.432ns, distribution 0.947ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.451     1.714    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.944 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     2.090    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.107 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86296, routed)       1.708     3.815    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_clk
    SLICE_X37Y271        FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X37Y271        FDRE (Prop_DFF_SLICEM_C_Q)
                                                      0.039     3.854 r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[0]/Q
                         net (fo=1, routed)           0.105     3.959    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/async_path[0]
    SLICE_X36Y271        FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.940     1.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.432 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.165     1.597    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.616 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.379     2.995    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_clk
    SLICE_X36Y271        FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/C

Slack:                    inf
  Source:                 d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_wr_rst_ic_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.173ns  (logic 0.039ns (22.496%)  route 0.134ns (77.504%))
  Logic Levels:           0  
  Clock Path Skew:        -0.824ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.963ns
    Source Clock Delay      (SCD):    3.787ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.220ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.176ns
    Phase Error              (PE):    0.125ns
  Clock Net Delay (Source):      1.680ns (routing 0.846ns, distribution 0.834ns)
  Clock Net Delay (Destination): 1.347ns (routing 0.432ns, distribution 0.915ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.451     1.714    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.944 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     2.090    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.107 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86296, routed)       1.680     3.787    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/wr_clk
    SLICE_X48Y241        FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_wr_rst_ic_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X48Y241        FDRE (Prop_DFF_SLICEM_C_Q)
                                                      0.039     3.826 r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_wr_rst_ic_reg/Q
                         net (fo=2, routed)           0.134     3.960    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst/src_rst
    SLICE_X48Y241        FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.940     1.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.432 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.165     1.597    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.616 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.347     2.963    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst/dest_clk
    SLICE_X48Y241        FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.146ns  (logic 0.038ns (26.027%)  route 0.108ns (73.973%))
  Logic Levels:           0  
  Clock Path Skew:        -0.824ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.991ns
    Source Clock Delay      (SCD):    3.815ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.220ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.176ns
    Phase Error              (PE):    0.125ns
  Clock Net Delay (Source):      1.708ns (routing 0.846ns, distribution 0.862ns)
  Clock Net Delay (Destination): 1.375ns (routing 0.432ns, distribution 0.943ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.451     1.714    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.944 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     2.090    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.107 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86296, routed)       1.708     3.815    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_clk
    SLICE_X37Y271        FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X37Y271        FDRE (Prop_CFF_SLICEM_C_Q)
                                                      0.038     3.853 r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[2]/Q
                         net (fo=1, routed)           0.108     3.961    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/async_path[2]
    SLICE_X36Y271        FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.940     1.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.432 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.165     1.597    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.616 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.375     2.991    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_clk
    SLICE_X36Y271        FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/C

Slack:                    inf
  Source:                 d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_238_251/RAMD_D1/CLK
                            (rising edge-triggered cell RAMD32 clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[245]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.170ns  (logic 0.111ns (65.294%)  route 0.059ns (34.706%))
  Logic Levels:           0  
  Clock Path Skew:        -0.844ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.948ns
    Source Clock Delay      (SCD):    3.792ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.220ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.176ns
    Phase Error              (PE):    0.125ns
  Clock Net Delay (Source):      1.685ns (routing 0.846ns, distribution 0.839ns)
  Clock Net Delay (Destination): 1.332ns (routing 0.432ns, distribution 0.900ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.451     1.714    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.944 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     2.090    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.107 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86296, routed)       1.685     3.792    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_238_251/WCLK
    SLICE_X48Y271        RAMD32                                       r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_238_251/RAMD_D1/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X48Y271        RAMD32 (Prop_D6LUT_SLICEM_CLK_O)
                                                      0.111     3.903 r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_238_251/RAMD_D1/O
                         net (fo=1, routed)           0.059     3.962    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0[245]
    SLICE_X47Y271        FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[245]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.940     1.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.432 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.165     1.597    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.616 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.332     2.948    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X47Y271        FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[245]/C

Slack:                    inf
  Source:                 d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_238_251/RAMF_D1/CLK
                            (rising edge-triggered cell RAMD32 clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[249]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.170ns  (logic 0.111ns (65.294%)  route 0.059ns (34.706%))
  Logic Levels:           0  
  Clock Path Skew:        -0.844ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.948ns
    Source Clock Delay      (SCD):    3.792ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.220ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.176ns
    Phase Error              (PE):    0.125ns
  Clock Net Delay (Source):      1.685ns (routing 0.846ns, distribution 0.839ns)
  Clock Net Delay (Destination): 1.332ns (routing 0.432ns, distribution 0.900ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.451     1.714    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.944 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     2.090    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.107 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86296, routed)       1.685     3.792    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_238_251/WCLK
    SLICE_X48Y271        RAMD32                                       r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_238_251/RAMF_D1/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X48Y271        RAMD32 (Prop_F6LUT_SLICEM_CLK_O)
                                                      0.111     3.903 r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_238_251/RAMF_D1/O
                         net (fo=1, routed)           0.059     3.962    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0[249]
    SLICE_X47Y271        FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[249]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.940     1.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.432 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.165     1.597    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.616 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.332     2.948    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X47Y271        FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[249]/C

Slack:                    inf
  Source:                 d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_42_55/RAMA_D1/CLK
                            (rising edge-triggered cell RAMD32 clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[43]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.152ns  (logic 0.111ns (73.026%)  route 0.041ns (26.974%))
  Logic Levels:           0  
  Clock Path Skew:        -0.835ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.976ns
    Source Clock Delay      (SCD):    3.811ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.220ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.176ns
    Phase Error              (PE):    0.125ns
  Clock Net Delay (Source):      1.704ns (routing 0.846ns, distribution 0.858ns)
  Clock Net Delay (Destination): 1.361ns (routing 0.432ns, distribution 0.929ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.451     1.714    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.944 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     2.090    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.107 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86296, routed)       1.704     3.811    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_42_55/WCLK
    SLICE_X39Y264        RAMD32                                       r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_42_55/RAMA_D1/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X39Y264        RAMD32 (Prop_A6LUT_SLICEM_CLK_O)
                                                      0.111     3.922 r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_42_55/RAMA_D1/O
                         net (fo=1, routed)           0.041     3.963    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0[43]
    SLICE_X39Y263        FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[43]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.940     1.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.432 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.165     1.597    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.616 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.361     2.976    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X39Y263        FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[43]/C

Slack:                    inf
  Source:                 d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41/RAMF_D1/CLK
                            (rising edge-triggered cell RAMD32 clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[39]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.174ns  (logic 0.111ns (63.793%)  route 0.063ns (36.207%))
  Logic Levels:           0  
  Clock Path Skew:        -0.848ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.942ns
    Source Clock Delay      (SCD):    3.790ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.220ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.176ns
    Phase Error              (PE):    0.125ns
  Clock Net Delay (Source):      1.683ns (routing 0.846ns, distribution 0.837ns)
  Clock Net Delay (Destination): 1.326ns (routing 0.432ns, distribution 0.894ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.451     1.714    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.944 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     2.090    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.107 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86296, routed)       1.683     3.790    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41/WCLK
    SLICE_X53Y255        RAMD32                                       r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41/RAMF_D1/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X53Y255        RAMD32 (Prop_F6LUT_SLICEM_CLK_O)
                                                      0.111     3.901 r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41/RAMF_D1/O
                         net (fo=1, routed)           0.063     3.964    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0[39]
    SLICE_X53Y256        FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[39]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.940     1.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.432 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.165     1.597    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.616 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.326     2.942    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X53Y256        FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[39]/C

Slack:                    inf
  Source:                 d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[4]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][4]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.180ns  (logic 0.038ns (21.111%)  route 0.142ns (78.889%))
  Logic Levels:           0  
  Clock Path Skew:        -0.826ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.958ns
    Source Clock Delay      (SCD):    3.784ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.220ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.176ns
    Phase Error              (PE):    0.125ns
  Clock Net Delay (Source):      1.677ns (routing 0.846ns, distribution 0.831ns)
  Clock Net Delay (Destination): 1.342ns (routing 0.432ns, distribution 0.910ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.451     1.714    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.944 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     2.090    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.107 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86296, routed)       1.677     3.784    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_clk
    SLICE_X41Y271        FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X41Y271        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.038     3.822 r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[4]/Q
                         net (fo=1, routed)           0.142     3.964    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/async_path[4]
    SLICE_X41Y271        FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][4]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.940     1.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.432 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.165     1.597    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.616 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.342     2.958    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_clk
    SLICE_X41Y271        FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][4]/C

Slack:                    inf
  Source:                 d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41/RAMA_D1/CLK
                            (rising edge-triggered cell RAMD32 clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[29]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.175ns  (logic 0.111ns (63.429%)  route 0.064ns (36.571%))
  Logic Levels:           0  
  Clock Path Skew:        -0.848ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.942ns
    Source Clock Delay      (SCD):    3.790ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.220ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.176ns
    Phase Error              (PE):    0.125ns
  Clock Net Delay (Source):      1.683ns (routing 0.846ns, distribution 0.837ns)
  Clock Net Delay (Destination): 1.326ns (routing 0.432ns, distribution 0.894ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.451     1.714    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.944 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     2.090    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.107 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86296, routed)       1.683     3.790    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41/WCLK
    SLICE_X53Y255        RAMD32                                       r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41/RAMA_D1/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X53Y255        RAMD32 (Prop_A6LUT_SLICEM_CLK_O)
                                                      0.111     3.901 r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41/RAMA_D1/O
                         net (fo=1, routed)           0.064     3.965    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0[29]
    SLICE_X53Y256        FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[29]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.940     1.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.432 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.165     1.597    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.616 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.326     2.942    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X53Y256        FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[29]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  clk_pl_0
  To Clock:  mmcm_clkout0

Max Delay           106 Endpoints
Min Delay           106 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg4_reg[22]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/addr_reg_r_reg[22]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.895ns  (logic 0.079ns (8.829%)  route 0.816ns (91.171%))
  Logic Levels:           0  
  Clock Path Skew:        2.734ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.046ns
    Source Clock Delay      (SCD):    2.312ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.278ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.352ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      2.086ns (routing 0.662ns, distribution 1.424ns)
  Clock Net Delay (Destination): 1.899ns (routing 0.630ns, distribution 1.269ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       2.086     2.312    d_1_i/axis_buffer_ddr_v1_0/inst/axi_slv_i/s_axi_aclk
    SLICE_X47Y116        FDRE                                         r  d_1_i/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg4_reg[22]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X47Y116        FDRE (Prop_BFF_SLICEL_C_Q)
                                                      0.079     2.391 r  d_1_i/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg4_reg[22]/Q
                         net (fo=2, routed)           0.816     3.206    d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/WADDR_REG[22]
    SLICE_X46Y134        FDRE                                         r  d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/addr_reg_r_reg[22]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.364     2.279    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.909 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.214     3.123    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.147 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.899     5.046    d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/aclk
    SLICE_X46Y134        FDRE                                         r  d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/addr_reg_r_reg[22]/C

Slack:                    inf
  Source:                 d_1_i/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg4_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/addr_reg_r_reg[1]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.792ns  (logic 0.081ns (10.223%)  route 0.711ns (89.777%))
  Logic Levels:           0  
  Clock Path Skew:        2.727ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.049ns
    Source Clock Delay      (SCD):    2.322ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.278ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.352ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      2.096ns (routing 0.662ns, distribution 1.434ns)
  Clock Net Delay (Destination): 1.902ns (routing 0.630ns, distribution 1.272ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       2.096     2.322    d_1_i/axis_buffer_ddr_v1_0/inst/axi_slv_i/s_axi_aclk
    SLICE_X47Y115        FDRE                                         r  d_1_i/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg4_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X47Y115        FDRE (Prop_AFF2_SLICEL_C_Q)
                                                      0.081     2.403 r  d_1_i/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg4_reg[1]/Q
                         net (fo=2, routed)           0.711     3.114    d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/WADDR_REG[1]
    SLICE_X44Y138        FDRE                                         r  d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/addr_reg_r_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.364     2.279    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.909 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.214     3.123    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.147 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.902     5.049    d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/aclk
    SLICE_X44Y138        FDRE                                         r  d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/addr_reg_r_reg[1]/C

Slack:                    inf
  Source:                 d_1_i/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg4_reg[12]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/addr_reg_r_reg[12]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.772ns  (logic 0.079ns (10.228%)  route 0.693ns (89.772%))
  Logic Levels:           0  
  Clock Path Skew:        2.742ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.055ns
    Source Clock Delay      (SCD):    2.313ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.278ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.352ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      2.087ns (routing 0.662ns, distribution 1.425ns)
  Clock Net Delay (Destination): 1.908ns (routing 0.630ns, distribution 1.278ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       2.087     2.313    d_1_i/axis_buffer_ddr_v1_0/inst/axi_slv_i/s_axi_aclk
    SLICE_X51Y121        FDRE                                         r  d_1_i/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg4_reg[12]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X51Y121        FDRE (Prop_FFF_SLICEL_C_Q)
                                                      0.079     2.392 r  d_1_i/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg4_reg[12]/Q
                         net (fo=2, routed)           0.693     3.085    d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/WADDR_REG[12]
    SLICE_X46Y129        FDRE                                         r  d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/addr_reg_r_reg[12]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.364     2.279    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.909 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.214     3.123    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.147 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.908     5.055    d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/aclk
    SLICE_X46Y129        FDRE                                         r  d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/addr_reg_r_reg[12]/C

Slack:                    inf
  Source:                 d_1_i/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg4_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/addr_reg_r_reg[3]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.702ns  (logic 0.080ns (11.404%)  route 0.622ns (88.596%))
  Logic Levels:           0  
  Clock Path Skew:        2.732ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.054ns
    Source Clock Delay      (SCD):    2.322ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.278ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.352ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      2.096ns (routing 0.662ns, distribution 1.434ns)
  Clock Net Delay (Destination): 1.907ns (routing 0.630ns, distribution 1.277ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       2.096     2.322    d_1_i/axis_buffer_ddr_v1_0/inst/axi_slv_i/s_axi_aclk
    SLICE_X47Y115        FDRE                                         r  d_1_i/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg4_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X47Y115        FDRE (Prop_BFF2_SLICEL_C_Q)
                                                      0.080     2.402 r  d_1_i/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg4_reg[3]/Q
                         net (fo=2, routed)           0.622     3.023    d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/WADDR_REG[3]
    SLICE_X46Y129        FDRE                                         r  d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/addr_reg_r_reg[3]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.364     2.279    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.909 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.214     3.123    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.147 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.907     5.054    d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/aclk
    SLICE_X46Y129        FDRE                                         r  d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/addr_reg_r_reg[3]/C

Slack:                    inf
  Source:                 d_1_i/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg4_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/addr_reg_r_reg[2]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.694ns  (logic 0.079ns (11.379%)  route 0.615ns (88.621%))
  Logic Levels:           0  
  Clock Path Skew:        2.727ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.049ns
    Source Clock Delay      (SCD):    2.322ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.278ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.352ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      2.096ns (routing 0.662ns, distribution 1.434ns)
  Clock Net Delay (Destination): 1.902ns (routing 0.630ns, distribution 1.272ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       2.096     2.322    d_1_i/axis_buffer_ddr_v1_0/inst/axi_slv_i/s_axi_aclk
    SLICE_X47Y115        FDRE                                         r  d_1_i/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg4_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X47Y115        FDRE (Prop_BFF_SLICEL_C_Q)
                                                      0.079     2.401 r  d_1_i/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg4_reg[2]/Q
                         net (fo=2, routed)           0.615     3.016    d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/WADDR_REG[2]
    SLICE_X44Y138        FDRE                                         r  d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/addr_reg_r_reg[2]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.364     2.279    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.909 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.214     3.123    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.147 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.902     5.049    d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/aclk
    SLICE_X44Y138        FDRE                                         r  d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/addr_reg_r_reg[2]/C

Slack:                    inf
  Source:                 d_1_i/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg4_reg[4]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/addr_reg_r_reg[4]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.672ns  (logic 0.079ns (11.761%)  route 0.593ns (88.239%))
  Logic Levels:           0  
  Clock Path Skew:        2.732ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.054ns
    Source Clock Delay      (SCD):    2.322ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.278ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.352ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      2.096ns (routing 0.662ns, distribution 1.434ns)
  Clock Net Delay (Destination): 1.907ns (routing 0.630ns, distribution 1.277ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       2.096     2.322    d_1_i/axis_buffer_ddr_v1_0/inst/axi_slv_i/s_axi_aclk
    SLICE_X47Y115        FDRE                                         r  d_1_i/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg4_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X47Y115        FDRE (Prop_CFF_SLICEL_C_Q)
                                                      0.079     2.401 r  d_1_i/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg4_reg[4]/Q
                         net (fo=2, routed)           0.593     2.994    d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/WADDR_REG[4]
    SLICE_X46Y129        FDRE                                         r  d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/addr_reg_r_reg[4]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.364     2.279    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.909 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.214     3.123    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.147 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.907     5.054    d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/aclk
    SLICE_X46Y129        FDRE                                         r  d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/addr_reg_r_reg[4]/C

Slack:                    inf
  Source:                 d_1_i/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg4_reg[14]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/addr_reg_r_reg[14]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.698ns  (logic 0.079ns (11.314%)  route 0.619ns (88.686%))
  Logic Levels:           0  
  Clock Path Skew:        2.760ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.055ns
    Source Clock Delay      (SCD):    2.294ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.278ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.352ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      2.068ns (routing 0.662ns, distribution 1.406ns)
  Clock Net Delay (Destination): 1.908ns (routing 0.630ns, distribution 1.278ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       2.068     2.294    d_1_i/axis_buffer_ddr_v1_0/inst/axi_slv_i/s_axi_aclk
    SLICE_X52Y121        FDRE                                         r  d_1_i/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg4_reg[14]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X52Y121        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     2.373 r  d_1_i/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg4_reg[14]/Q
                         net (fo=2, routed)           0.619     2.993    d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/WADDR_REG[14]
    SLICE_X46Y129        FDRE                                         r  d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/addr_reg_r_reg[14]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.364     2.279    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.909 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.214     3.123    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.147 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.908     5.055    d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/aclk
    SLICE_X46Y129        FDRE                                         r  d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/addr_reg_r_reg[14]/C

Slack:                    inf
  Source:                 d_1_i/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg4_reg[11]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/addr_reg_r_reg[11]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.672ns  (logic 0.079ns (11.755%)  route 0.593ns (88.245%))
  Logic Levels:           0  
  Clock Path Skew:        2.742ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.055ns
    Source Clock Delay      (SCD):    2.313ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.278ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.352ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      2.087ns (routing 0.662ns, distribution 1.425ns)
  Clock Net Delay (Destination): 1.908ns (routing 0.630ns, distribution 1.278ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       2.087     2.313    d_1_i/axis_buffer_ddr_v1_0/inst/axi_slv_i/s_axi_aclk
    SLICE_X51Y121        FDRE                                         r  d_1_i/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg4_reg[11]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X51Y121        FDRE (Prop_GFF_SLICEL_C_Q)
                                                      0.079     2.392 r  d_1_i/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg4_reg[11]/Q
                         net (fo=2, routed)           0.593     2.985    d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/WADDR_REG[11]
    SLICE_X46Y129        FDRE                                         r  d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/addr_reg_r_reg[11]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.364     2.279    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.909 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.214     3.123    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.147 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.908     5.055    d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/aclk
    SLICE_X46Y129        FDRE                                         r  d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/addr_reg_r_reg[11]/C

Slack:                    inf
  Source:                 d_1_i/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg5_reg[30]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/nburst_reg_r_reg[30]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.658ns  (logic 0.079ns (12.007%)  route 0.579ns (87.993%))
  Logic Levels:           0  
  Clock Path Skew:        2.753ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.066ns
    Source Clock Delay      (SCD):    2.313ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.278ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.352ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      2.087ns (routing 0.662ns, distribution 1.425ns)
  Clock Net Delay (Destination): 1.919ns (routing 0.630ns, distribution 1.289ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       2.087     2.313    d_1_i/axis_buffer_ddr_v1_0/inst/axi_slv_i/s_axi_aclk
    SLICE_X50Y121        FDRE                                         r  d_1_i/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg5_reg[30]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X50Y121        FDRE (Prop_GFF_SLICEL_C_Q)
                                                      0.079     2.392 r  d_1_i/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg5_reg[30]/Q
                         net (fo=2, routed)           0.579     2.971    d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/WNBURST_REG[30]
    SLICE_X49Y118        FDRE                                         r  d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/nburst_reg_r_reg[30]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.364     2.279    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.909 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.214     3.123    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.147 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.919     5.066    d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/aclk
    SLICE_X49Y118        FDRE                                         r  d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/nburst_reg_r_reg[30]/C

Slack:                    inf
  Source:                 d_1_i/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg5_reg[11]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/nburst_reg_r_reg[11]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.665ns  (logic 0.081ns (12.175%)  route 0.584ns (87.825%))
  Logic Levels:           0  
  Clock Path Skew:        2.758ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.054ns
    Source Clock Delay      (SCD):    2.296ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.278ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.352ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      2.070ns (routing 0.662ns, distribution 1.408ns)
  Clock Net Delay (Destination): 1.907ns (routing 0.630ns, distribution 1.277ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       2.070     2.296    d_1_i/axis_buffer_ddr_v1_0/inst/axi_slv_i/s_axi_aclk
    SLICE_X51Y115        FDRE                                         r  d_1_i/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg5_reg[11]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X51Y115        FDRE (Prop_EFF2_SLICEL_C_Q)
                                                      0.081     2.377 r  d_1_i/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg5_reg[11]/Q
                         net (fo=2, routed)           0.584     2.961    d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/WNBURST_REG[11]
    SLICE_X51Y116        FDRE                                         r  d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/nburst_reg_r_reg[11]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.364     2.279    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.909 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.214     3.123    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.147 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.907     5.054    d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/aclk
    SLICE_X51Y116        FDRE                                         r  d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/nburst_reg_r_reg[11]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg5_reg[26]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/nburst_reg_r_reg[26]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.105ns  (logic 0.039ns (37.255%)  route 0.066ns (62.745%))
  Logic Levels:           0  
  Clock Path Skew:        1.719ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.968ns
    Source Clock Delay      (SCD):    1.250ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.278ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.352ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.130ns (routing 0.359ns, distribution 0.771ns)
  Clock Net Delay (Destination): 1.352ns (routing 0.432ns, distribution 0.920ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.130     1.250    d_1_i/axis_buffer_ddr_v1_0/inst/axi_slv_i/s_axi_aclk
    SLICE_X49Y120        FDRE                                         r  d_1_i/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg5_reg[26]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X49Y120        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.039     1.289 r  d_1_i/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg5_reg[26]/Q
                         net (fo=2, routed)           0.066     1.354    d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/WNBURST_REG[26]
    SLICE_X49Y119        FDRE                                         r  d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/nburst_reg_r_reg[26]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.940     1.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.432 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.165     1.597    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.616 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.352     2.968    d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/aclk
    SLICE_X49Y119        FDRE                                         r  d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/nburst_reg_r_reg[26]/C

Slack:                    inf
  Source:                 d_1_i/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg5_reg[14]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/nburst_reg_r_reg[14]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.108ns  (logic 0.039ns (36.217%)  route 0.069ns (63.783%))
  Logic Levels:           0  
  Clock Path Skew:        1.700ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.958ns
    Source Clock Delay      (SCD):    1.258ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.278ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.352ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.138ns (routing 0.359ns, distribution 0.779ns)
  Clock Net Delay (Destination): 1.342ns (routing 0.432ns, distribution 0.910ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.138     1.258    d_1_i/axis_buffer_ddr_v1_0/inst/axi_slv_i/s_axi_aclk
    SLICE_X51Y115        FDRE                                         r  d_1_i/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg5_reg[14]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X51Y115        FDRE (Prop_FFF_SLICEL_C_Q)
                                                      0.039     1.297 r  d_1_i/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg5_reg[14]/Q
                         net (fo=2, routed)           0.069     1.366    d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/WNBURST_REG[14]
    SLICE_X51Y116        FDRE                                         r  d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/nburst_reg_r_reg[14]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.940     1.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.432 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.165     1.597    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.616 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.342     2.958    d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/aclk
    SLICE_X51Y116        FDRE                                         r  d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/nburst_reg_r_reg[14]/C

Slack:                    inf
  Source:                 d_1_i/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg5_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/nburst_reg_r_reg[2]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.108ns  (logic 0.040ns (37.146%)  route 0.068ns (62.854%))
  Logic Levels:           0  
  Clock Path Skew:        1.707ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.967ns
    Source Clock Delay      (SCD):    1.260ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.278ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.352ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.140ns (routing 0.359ns, distribution 0.781ns)
  Clock Net Delay (Destination): 1.351ns (routing 0.432ns, distribution 0.919ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.140     1.260    d_1_i/axis_buffer_ddr_v1_0/inst/axi_slv_i/s_axi_aclk
    SLICE_X47Y116        FDRE                                         r  d_1_i/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg5_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X47Y116        FDRE (Prop_BFF2_SLICEL_C_Q)
                                                      0.040     1.300 r  d_1_i/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg5_reg[2]/Q
                         net (fo=2, routed)           0.068     1.368    d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/WNBURST_REG[2]
    SLICE_X47Y117        FDRE                                         r  d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/nburst_reg_r_reg[2]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.940     1.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.432 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.165     1.597    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.616 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.351     2.967    d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/aclk
    SLICE_X47Y117        FDRE                                         r  d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/nburst_reg_r_reg[2]/C

Slack:                    inf
  Source:                 d_1_i/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg5_reg[4]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/nburst_reg_r_reg[4]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.105ns  (logic 0.039ns (37.255%)  route 0.066ns (62.745%))
  Logic Levels:           0  
  Clock Path Skew:        1.705ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.968ns
    Source Clock Delay      (SCD):    1.263ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.278ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.352ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.143ns (routing 0.359ns, distribution 0.784ns)
  Clock Net Delay (Destination): 1.353ns (routing 0.432ns, distribution 0.921ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.143     1.263    d_1_i/axis_buffer_ddr_v1_0/inst/axi_slv_i/s_axi_aclk
    SLICE_X47Y116        FDRE                                         r  d_1_i/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg5_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X47Y116        FDRE (Prop_GFF_SLICEL_C_Q)
                                                      0.039     1.302 r  d_1_i/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg5_reg[4]/Q
                         net (fo=2, routed)           0.066     1.368    d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/WNBURST_REG[4]
    SLICE_X49Y116        FDRE                                         r  d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/nburst_reg_r_reg[4]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.940     1.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.432 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.165     1.597    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.616 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.353     2.968    d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/aclk
    SLICE_X49Y116        FDRE                                         r  d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/nburst_reg_r_reg[4]/C

Slack:                    inf
  Source:                 d_1_i/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg5_reg[9]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/nburst_reg_r_reg[9]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.100ns  (logic 0.039ns (39.124%)  route 0.061ns (60.876%))
  Logic Levels:           0  
  Clock Path Skew:        1.689ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.958ns
    Source Clock Delay      (SCD):    1.269ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.278ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.352ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.149ns (routing 0.359ns, distribution 0.790ns)
  Clock Net Delay (Destination): 1.342ns (routing 0.432ns, distribution 0.910ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.149     1.269    d_1_i/axis_buffer_ddr_v1_0/inst/axi_slv_i/s_axi_aclk
    SLICE_X51Y117        FDRE                                         r  d_1_i/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg5_reg[9]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X51Y117        FDRE (Prop_FFF_SLICEL_C_Q)
                                                      0.039     1.308 r  d_1_i/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg5_reg[9]/Q
                         net (fo=2, routed)           0.061     1.368    d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/WNBURST_REG[9]
    SLICE_X51Y116        FDRE                                         r  d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/nburst_reg_r_reg[9]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.940     1.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.432 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.165     1.597    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.616 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.342     2.958    d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/aclk
    SLICE_X51Y116        FDRE                                         r  d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/nburst_reg_r_reg[9]/C

Slack:                    inf
  Source:                 d_1_i/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg5_reg[7]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/nburst_reg_r_reg[7]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.113ns  (logic 0.040ns (35.490%)  route 0.073ns (64.510%))
  Logic Levels:           0  
  Clock Path Skew:        1.712ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.972ns
    Source Clock Delay      (SCD):    1.260ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.278ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.352ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.140ns (routing 0.359ns, distribution 0.781ns)
  Clock Net Delay (Destination): 1.357ns (routing 0.432ns, distribution 0.925ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.140     1.260    d_1_i/axis_buffer_ddr_v1_0/inst/axi_slv_i/s_axi_aclk
    SLICE_X47Y116        FDRE                                         r  d_1_i/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg5_reg[7]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X47Y116        FDRE (Prop_AFF2_SLICEL_C_Q)
                                                      0.040     1.300 r  d_1_i/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg5_reg[7]/Q
                         net (fo=2, routed)           0.073     1.373    d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/WNBURST_REG[7]
    SLICE_X49Y116        FDRE                                         r  d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/nburst_reg_r_reg[7]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.940     1.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.432 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.165     1.597    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.616 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.357     2.972    d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/aclk
    SLICE_X49Y116        FDRE                                         r  d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/nburst_reg_r_reg[7]/C

Slack:                    inf
  Source:                 d_1_i/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg1_reg[31]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/addr_reg_r_reg[31]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.125ns  (logic 0.039ns (31.177%)  route 0.086ns (68.823%))
  Logic Levels:           0  
  Clock Path Skew:        1.696ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.952ns
    Source Clock Delay      (SCD):    1.257ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.278ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.352ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.137ns (routing 0.359ns, distribution 0.778ns)
  Clock Net Delay (Destination): 1.336ns (routing 0.432ns, distribution 0.904ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.137     1.257    d_1_i/axis_buffer_ddr_v1_0/inst/axi_slv_i/s_axi_aclk
    SLICE_X49Y122        FDRE                                         r  d_1_i/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg1_reg[31]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X49Y122        FDRE (Prop_GFF_SLICEL_C_Q)
                                                      0.039     1.296 r  d_1_i/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg1_reg[31]/Q
                         net (fo=2, routed)           0.086     1.382    d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/RADDR_REG[31]
    SLICE_X47Y123        FDRE                                         r  d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/addr_reg_r_reg[31]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.940     1.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.432 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.165     1.597    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.616 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.336     2.952    d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/aclk
    SLICE_X47Y123        FDRE                                         r  d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/addr_reg_r_reg[31]/C

Slack:                    inf
  Source:                 d_1_i/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg5_reg[27]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/nburst_reg_r_reg[27]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.133ns  (logic 0.040ns (30.147%)  route 0.093ns (69.853%))
  Logic Levels:           0  
  Clock Path Skew:        1.719ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.968ns
    Source Clock Delay      (SCD):    1.250ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.278ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.352ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.130ns (routing 0.359ns, distribution 0.771ns)
  Clock Net Delay (Destination): 1.352ns (routing 0.432ns, distribution 0.920ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.130     1.250    d_1_i/axis_buffer_ddr_v1_0/inst/axi_slv_i/s_axi_aclk
    SLICE_X49Y120        FDRE                                         r  d_1_i/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg5_reg[27]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X49Y120        FDRE (Prop_EFF2_SLICEL_C_Q)
                                                      0.040     1.290 r  d_1_i/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg5_reg[27]/Q
                         net (fo=2, routed)           0.093     1.382    d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/WNBURST_REG[27]
    SLICE_X49Y119        FDRE                                         r  d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/nburst_reg_r_reg[27]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.940     1.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.432 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.165     1.597    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.616 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.352     2.968    d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/aclk
    SLICE_X49Y119        FDRE                                         r  d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/nburst_reg_r_reg[27]/C

Slack:                    inf
  Source:                 d_1_i/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg5_reg[28]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/nburst_reg_r_reg[28]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.131ns  (logic 0.039ns (29.843%)  route 0.092ns (70.157%))
  Logic Levels:           0  
  Clock Path Skew:        1.692ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.944ns
    Source Clock Delay      (SCD):    1.252ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.278ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.352ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.132ns (routing 0.359ns, distribution 0.773ns)
  Clock Net Delay (Destination): 1.328ns (routing 0.432ns, distribution 0.896ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.132     1.252    d_1_i/axis_buffer_ddr_v1_0/inst/axi_slv_i/s_axi_aclk
    SLICE_X48Y120        FDRE                                         r  d_1_i/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg5_reg[28]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X48Y120        FDRE (Prop_EFF2_SLICEM_C_Q)
                                                      0.039     1.291 r  d_1_i/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg5_reg[28]/Q
                         net (fo=2, routed)           0.092     1.382    d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/WNBURST_REG[28]
    SLICE_X48Y121        FDRE                                         r  d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/nburst_reg_r_reg[28]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.940     1.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.432 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.165     1.597    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.616 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.328     2.944    d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/aclk
    SLICE_X48Y121        FDRE                                         r  d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/nburst_reg_r_reg[28]/C

Slack:                    inf
  Source:                 d_1_i/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg4_reg[27]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/addr_reg_r_reg[27]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.132ns  (logic 0.040ns (30.376%)  route 0.092ns (69.624%))
  Logic Levels:           0  
  Clock Path Skew:        1.687ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.947ns
    Source Clock Delay      (SCD):    1.260ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.278ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.352ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.140ns (routing 0.359ns, distribution 0.781ns)
  Clock Net Delay (Destination): 1.331ns (routing 0.432ns, distribution 0.899ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.140     1.260    d_1_i/axis_buffer_ddr_v1_0/inst/axi_slv_i/s_axi_aclk
    SLICE_X48Y124        FDRE                                         r  d_1_i/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg4_reg[27]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X48Y124        FDRE (Prop_BFF2_SLICEM_C_Q)
                                                      0.040     1.300 r  d_1_i/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg4_reg[27]/Q
                         net (fo=2, routed)           0.092     1.391    d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/WADDR_REG[27]
    SLICE_X46Y124        FDRE                                         r  d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/addr_reg_r_reg[27]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.940     1.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.432 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.165     1.597    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.616 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.331     2.947    d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/aclk
    SLICE_X46Y124        FDRE                                         r  d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/addr_reg_r_reg[27]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  mmcm_clkout0
  To Clock:  mmcm_clkout0

Max Delay            68 Endpoints
Min Delay            68 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/axi_smc_1/inst/s00_entry_pipeline/s00_transaction_regulator/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[0]/CLR
                            (recovery check against rising-edge clock mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Recovery (Max at Slow Process Corner)
  Data Path Delay:        2.199ns  (logic 0.079ns (3.592%)  route 2.120ns (96.408%))
  Logic Levels:           0  
  Clock Path Skew:        0.282ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.139ns
    Source Clock Delay      (SCD):    4.857ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.102ns (routing 0.696ns, distribution 1.406ns)
  Clock Net Delay (Destination): 1.992ns (routing 0.630ns, distribution 1.362ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.524     2.610    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.483 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.244     2.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.755 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       2.102     4.857    d_1_i/axi_smc_1/inst/clk_map/psr_aclk/U0/aclk
    SLICE_X47Y200        FDRE                                         r  d_1_i/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X47Y200        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.079     4.936 r  d_1_i/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/Q
                         net (fo=66, routed)          2.120     7.056    d_1_i/axi_smc_1/inst/s00_entry_pipeline/s00_transaction_regulator/inst/xpm_cdc_async_rst_inst/src_arst
    SLICE_X29Y130        FDCE                                         f  d_1_i/axi_smc_1/inst/s00_entry_pipeline/s00_transaction_regulator/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[0]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.364     2.279    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.909 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.214     3.123    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.147 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.992     5.139    d_1_i/axi_smc_1/inst/s00_entry_pipeline/s00_transaction_regulator/inst/xpm_cdc_async_rst_inst/dest_clk
    SLICE_X29Y130        FDCE                                         r  d_1_i/axi_smc_1/inst/s00_entry_pipeline/s00_transaction_regulator/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/axi_smc_1/inst/s00_entry_pipeline/s00_transaction_regulator/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[1]/CLR
                            (recovery check against rising-edge clock mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Recovery (Max at Slow Process Corner)
  Data Path Delay:        2.199ns  (logic 0.079ns (3.592%)  route 2.120ns (96.408%))
  Logic Levels:           0  
  Clock Path Skew:        0.282ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.139ns
    Source Clock Delay      (SCD):    4.857ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.102ns (routing 0.696ns, distribution 1.406ns)
  Clock Net Delay (Destination): 1.992ns (routing 0.630ns, distribution 1.362ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.524     2.610    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.483 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.244     2.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.755 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       2.102     4.857    d_1_i/axi_smc_1/inst/clk_map/psr_aclk/U0/aclk
    SLICE_X47Y200        FDRE                                         r  d_1_i/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X47Y200        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.079     4.936 r  d_1_i/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/Q
                         net (fo=66, routed)          2.120     7.056    d_1_i/axi_smc_1/inst/s00_entry_pipeline/s00_transaction_regulator/inst/xpm_cdc_async_rst_inst/src_arst
    SLICE_X29Y130        FDCE                                         f  d_1_i/axi_smc_1/inst/s00_entry_pipeline/s00_transaction_regulator/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[1]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.364     2.279    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.909 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.214     3.123    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.147 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.992     5.139    d_1_i/axi_smc_1/inst/s00_entry_pipeline/s00_transaction_regulator/inst/xpm_cdc_async_rst_inst/dest_clk
    SLICE_X29Y130        FDCE                                         r  d_1_i/axi_smc_1/inst/s00_entry_pipeline/s00_transaction_regulator/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[1]/C

Slack:                    inf
  Source:                 d_1_i/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/axi_smc_1/inst/s00_entry_pipeline/s00_transaction_regulator/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[2]/CLR
                            (recovery check against rising-edge clock mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Recovery (Max at Slow Process Corner)
  Data Path Delay:        2.199ns  (logic 0.079ns (3.592%)  route 2.120ns (96.408%))
  Logic Levels:           0  
  Clock Path Skew:        0.282ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.139ns
    Source Clock Delay      (SCD):    4.857ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.102ns (routing 0.696ns, distribution 1.406ns)
  Clock Net Delay (Destination): 1.992ns (routing 0.630ns, distribution 1.362ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.524     2.610    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.483 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.244     2.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.755 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       2.102     4.857    d_1_i/axi_smc_1/inst/clk_map/psr_aclk/U0/aclk
    SLICE_X47Y200        FDRE                                         r  d_1_i/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X47Y200        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.079     4.936 r  d_1_i/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/Q
                         net (fo=66, routed)          2.120     7.056    d_1_i/axi_smc_1/inst/s00_entry_pipeline/s00_transaction_regulator/inst/xpm_cdc_async_rst_inst/src_arst
    SLICE_X29Y130        FDCE                                         f  d_1_i/axi_smc_1/inst/s00_entry_pipeline/s00_transaction_regulator/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[2]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.364     2.279    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.909 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.214     3.123    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.147 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.992     5.139    d_1_i/axi_smc_1/inst/s00_entry_pipeline/s00_transaction_regulator/inst/xpm_cdc_async_rst_inst/dest_clk
    SLICE_X29Y130        FDCE                                         r  d_1_i/axi_smc_1/inst/s00_entry_pipeline/s00_transaction_regulator/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[2]/C

Slack:                    inf
  Source:                 d_1_i/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/axi_smc_1/inst/s01_nodes/s01_ar_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[0]/CLR
                            (recovery check against rising-edge clock mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Recovery (Max at Slow Process Corner)
  Data Path Delay:        2.153ns  (logic 0.079ns (3.670%)  route 2.074ns (96.330%))
  Logic Levels:           0  
  Clock Path Skew:        0.276ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.133ns
    Source Clock Delay      (SCD):    4.857ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.102ns (routing 0.696ns, distribution 1.406ns)
  Clock Net Delay (Destination): 1.986ns (routing 0.630ns, distribution 1.356ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.524     2.610    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.483 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.244     2.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.755 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       2.102     4.857    d_1_i/axi_smc_1/inst/clk_map/psr_aclk/U0/aclk
    SLICE_X47Y200        FDRE                                         r  d_1_i/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X47Y200        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.079     4.936 r  d_1_i/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/Q
                         net (fo=66, routed)          2.074     7.010    d_1_i/axi_smc_1/inst/s01_nodes/s01_ar_node/inst/s_sc_xpm_cdc_async_rst_inst/src_arst
    SLICE_X30Y137        FDCE                                         f  d_1_i/axi_smc_1/inst/s01_nodes/s01_ar_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[0]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.364     2.279    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.909 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.214     3.123    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.147 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.986     5.133    d_1_i/axi_smc_1/inst/s01_nodes/s01_ar_node/inst/s_sc_xpm_cdc_async_rst_inst/dest_clk
    SLICE_X30Y137        FDCE                                         r  d_1_i/axi_smc_1/inst/s01_nodes/s01_ar_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/axi_smc_1/inst/s01_nodes/s01_ar_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[1]/CLR
                            (recovery check against rising-edge clock mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Recovery (Max at Slow Process Corner)
  Data Path Delay:        2.153ns  (logic 0.079ns (3.670%)  route 2.074ns (96.330%))
  Logic Levels:           0  
  Clock Path Skew:        0.276ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.133ns
    Source Clock Delay      (SCD):    4.857ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.102ns (routing 0.696ns, distribution 1.406ns)
  Clock Net Delay (Destination): 1.986ns (routing 0.630ns, distribution 1.356ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.524     2.610    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.483 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.244     2.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.755 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       2.102     4.857    d_1_i/axi_smc_1/inst/clk_map/psr_aclk/U0/aclk
    SLICE_X47Y200        FDRE                                         r  d_1_i/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X47Y200        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.079     4.936 r  d_1_i/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/Q
                         net (fo=66, routed)          2.074     7.010    d_1_i/axi_smc_1/inst/s01_nodes/s01_ar_node/inst/s_sc_xpm_cdc_async_rst_inst/src_arst
    SLICE_X30Y137        FDCE                                         f  d_1_i/axi_smc_1/inst/s01_nodes/s01_ar_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[1]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.364     2.279    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.909 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.214     3.123    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.147 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.986     5.133    d_1_i/axi_smc_1/inst/s01_nodes/s01_ar_node/inst/s_sc_xpm_cdc_async_rst_inst/dest_clk
    SLICE_X30Y137        FDCE                                         r  d_1_i/axi_smc_1/inst/s01_nodes/s01_ar_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[1]/C

Slack:                    inf
  Source:                 d_1_i/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/axi_smc_1/inst/s01_nodes/s01_ar_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[2]/CLR
                            (recovery check against rising-edge clock mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Recovery (Max at Slow Process Corner)
  Data Path Delay:        2.153ns  (logic 0.079ns (3.670%)  route 2.074ns (96.330%))
  Logic Levels:           0  
  Clock Path Skew:        0.276ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.133ns
    Source Clock Delay      (SCD):    4.857ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.102ns (routing 0.696ns, distribution 1.406ns)
  Clock Net Delay (Destination): 1.986ns (routing 0.630ns, distribution 1.356ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.524     2.610    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.483 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.244     2.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.755 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       2.102     4.857    d_1_i/axi_smc_1/inst/clk_map/psr_aclk/U0/aclk
    SLICE_X47Y200        FDRE                                         r  d_1_i/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X47Y200        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.079     4.936 r  d_1_i/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/Q
                         net (fo=66, routed)          2.074     7.010    d_1_i/axi_smc_1/inst/s01_nodes/s01_ar_node/inst/s_sc_xpm_cdc_async_rst_inst/src_arst
    SLICE_X30Y137        FDCE                                         f  d_1_i/axi_smc_1/inst/s01_nodes/s01_ar_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[2]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.364     2.279    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.909 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.214     3.123    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.147 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.986     5.133    d_1_i/axi_smc_1/inst/s01_nodes/s01_ar_node/inst/s_sc_xpm_cdc_async_rst_inst/dest_clk
    SLICE_X30Y137        FDCE                                         r  d_1_i/axi_smc_1/inst/s01_nodes/s01_ar_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[2]/C

Slack:                    inf
  Source:                 d_1_i/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/axi_smc_1/inst/s00_entry_pipeline/s00_mmu/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[0]/CLR
                            (recovery check against rising-edge clock mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Recovery (Max at Slow Process Corner)
  Data Path Delay:        2.143ns  (logic 0.079ns (3.686%)  route 2.064ns (96.314%))
  Logic Levels:           0  
  Clock Path Skew:        0.278ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.135ns
    Source Clock Delay      (SCD):    4.857ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.102ns (routing 0.696ns, distribution 1.406ns)
  Clock Net Delay (Destination): 1.988ns (routing 0.630ns, distribution 1.358ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.524     2.610    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.483 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.244     2.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.755 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       2.102     4.857    d_1_i/axi_smc_1/inst/clk_map/psr_aclk/U0/aclk
    SLICE_X47Y200        FDRE                                         r  d_1_i/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X47Y200        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.079     4.936 r  d_1_i/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/Q
                         net (fo=66, routed)          2.064     7.000    d_1_i/axi_smc_1/inst/s00_entry_pipeline/s00_mmu/inst/xpm_cdc_async_rst_inst/src_arst
    SLICE_X26Y132        FDCE                                         f  d_1_i/axi_smc_1/inst/s00_entry_pipeline/s00_mmu/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[0]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.364     2.279    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.909 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.214     3.123    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.147 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.988     5.135    d_1_i/axi_smc_1/inst/s00_entry_pipeline/s00_mmu/inst/xpm_cdc_async_rst_inst/dest_clk
    SLICE_X26Y132        FDCE                                         r  d_1_i/axi_smc_1/inst/s00_entry_pipeline/s00_mmu/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/axi_smc_1/inst/s00_entry_pipeline/s00_mmu/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[1]/CLR
                            (recovery check against rising-edge clock mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Recovery (Max at Slow Process Corner)
  Data Path Delay:        2.143ns  (logic 0.079ns (3.686%)  route 2.064ns (96.314%))
  Logic Levels:           0  
  Clock Path Skew:        0.278ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.135ns
    Source Clock Delay      (SCD):    4.857ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.102ns (routing 0.696ns, distribution 1.406ns)
  Clock Net Delay (Destination): 1.988ns (routing 0.630ns, distribution 1.358ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.524     2.610    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.483 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.244     2.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.755 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       2.102     4.857    d_1_i/axi_smc_1/inst/clk_map/psr_aclk/U0/aclk
    SLICE_X47Y200        FDRE                                         r  d_1_i/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X47Y200        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.079     4.936 r  d_1_i/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/Q
                         net (fo=66, routed)          2.064     7.000    d_1_i/axi_smc_1/inst/s00_entry_pipeline/s00_mmu/inst/xpm_cdc_async_rst_inst/src_arst
    SLICE_X26Y132        FDCE                                         f  d_1_i/axi_smc_1/inst/s00_entry_pipeline/s00_mmu/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[1]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.364     2.279    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.909 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.214     3.123    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.147 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.988     5.135    d_1_i/axi_smc_1/inst/s00_entry_pipeline/s00_mmu/inst/xpm_cdc_async_rst_inst/dest_clk
    SLICE_X26Y132        FDCE                                         r  d_1_i/axi_smc_1/inst/s00_entry_pipeline/s00_mmu/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[1]/C

Slack:                    inf
  Source:                 d_1_i/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/axi_smc_1/inst/s00_entry_pipeline/s00_mmu/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[2]/CLR
                            (recovery check against rising-edge clock mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Recovery (Max at Slow Process Corner)
  Data Path Delay:        2.143ns  (logic 0.079ns (3.686%)  route 2.064ns (96.314%))
  Logic Levels:           0  
  Clock Path Skew:        0.278ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.135ns
    Source Clock Delay      (SCD):    4.857ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.102ns (routing 0.696ns, distribution 1.406ns)
  Clock Net Delay (Destination): 1.988ns (routing 0.630ns, distribution 1.358ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.524     2.610    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.483 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.244     2.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.755 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       2.102     4.857    d_1_i/axi_smc_1/inst/clk_map/psr_aclk/U0/aclk
    SLICE_X47Y200        FDRE                                         r  d_1_i/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X47Y200        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.079     4.936 r  d_1_i/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/Q
                         net (fo=66, routed)          2.064     7.000    d_1_i/axi_smc_1/inst/s00_entry_pipeline/s00_mmu/inst/xpm_cdc_async_rst_inst/src_arst
    SLICE_X26Y132        FDCE                                         f  d_1_i/axi_smc_1/inst/s00_entry_pipeline/s00_mmu/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[2]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.364     2.279    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.909 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.214     3.123    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.147 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.988     5.135    d_1_i/axi_smc_1/inst/s00_entry_pipeline/s00_mmu/inst/xpm_cdc_async_rst_inst/dest_clk
    SLICE_X26Y132        FDCE                                         r  d_1_i/axi_smc_1/inst/s00_entry_pipeline/s00_mmu/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[2]/C

Slack:                    inf
  Source:                 d_1_i/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/axi_smc_1/inst/s01_entry_pipeline/s01_si_converter/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[0]/CLR
                            (recovery check against rising-edge clock mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Recovery (Max at Slow Process Corner)
  Data Path Delay:        2.047ns  (logic 0.079ns (3.860%)  route 1.968ns (96.140%))
  Logic Levels:           0  
  Clock Path Skew:        0.278ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.135ns
    Source Clock Delay      (SCD):    4.857ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.102ns (routing 0.696ns, distribution 1.406ns)
  Clock Net Delay (Destination): 1.988ns (routing 0.630ns, distribution 1.358ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.524     2.610    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.483 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.244     2.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.755 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       2.102     4.857    d_1_i/axi_smc_1/inst/clk_map/psr_aclk/U0/aclk
    SLICE_X47Y200        FDRE                                         r  d_1_i/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X47Y200        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.079     4.936 r  d_1_i/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/Q
                         net (fo=66, routed)          1.968     6.904    d_1_i/axi_smc_1/inst/s01_entry_pipeline/s01_si_converter/inst/xpm_cdc_async_rst_inst/src_arst
    SLICE_X26Y140        FDCE                                         f  d_1_i/axi_smc_1/inst/s01_entry_pipeline/s01_si_converter/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[0]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.364     2.279    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.909 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.214     3.123    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.147 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.988     5.135    d_1_i/axi_smc_1/inst/s01_entry_pipeline/s01_si_converter/inst/xpm_cdc_async_rst_inst/dest_clk
    SLICE_X26Y140        FDCE                                         r  d_1_i/axi_smc_1/inst/s01_entry_pipeline/s01_si_converter/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[0]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/axi_smc_1/inst/s01_nodes/s01_aw_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[0]/CLR
                            (removal check against rising-edge clock mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Removal (Min at Fast Process Corner)
  Data Path Delay:        0.251ns  (logic 0.039ns (15.540%)  route 0.212ns (84.460%))
  Logic Levels:           0  
  Clock Path Skew:        -0.087ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.924ns
    Source Clock Delay      (SCD):    3.011ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.163ns (routing 0.384ns, distribution 0.779ns)
  Clock Net Delay (Destination): 1.308ns (routing 0.432ns, distribution 0.876ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.839     1.456    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.686 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.145     1.831    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.848 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.163     3.011    d_1_i/axi_smc_1/inst/clk_map/psr_aclk/U0/aclk
    SLICE_X47Y200        FDRE                                         r  d_1_i/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X47Y200        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.039     3.050 r  d_1_i/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/Q
                         net (fo=66, routed)          0.212     3.262    d_1_i/axi_smc_1/inst/s01_nodes/s01_aw_node/inst/s_sc_xpm_cdc_async_rst_inst/src_arst
    SLICE_X47Y198        FDCE                                         f  d_1_i/axi_smc_1/inst/s01_nodes/s01_aw_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[0]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.940     1.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.432 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.165     1.597    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.616 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.308     2.924    d_1_i/axi_smc_1/inst/s01_nodes/s01_aw_node/inst/s_sc_xpm_cdc_async_rst_inst/dest_clk
    SLICE_X47Y198        FDCE                                         r  d_1_i/axi_smc_1/inst/s01_nodes/s01_aw_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/axi_smc_1/inst/s01_nodes/s01_aw_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[1]/CLR
                            (removal check against rising-edge clock mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Removal (Min at Fast Process Corner)
  Data Path Delay:        0.251ns  (logic 0.039ns (15.540%)  route 0.212ns (84.460%))
  Logic Levels:           0  
  Clock Path Skew:        -0.087ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.924ns
    Source Clock Delay      (SCD):    3.011ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.163ns (routing 0.384ns, distribution 0.779ns)
  Clock Net Delay (Destination): 1.308ns (routing 0.432ns, distribution 0.876ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.839     1.456    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.686 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.145     1.831    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.848 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.163     3.011    d_1_i/axi_smc_1/inst/clk_map/psr_aclk/U0/aclk
    SLICE_X47Y200        FDRE                                         r  d_1_i/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X47Y200        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.039     3.050 r  d_1_i/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/Q
                         net (fo=66, routed)          0.212     3.262    d_1_i/axi_smc_1/inst/s01_nodes/s01_aw_node/inst/s_sc_xpm_cdc_async_rst_inst/src_arst
    SLICE_X47Y198        FDCE                                         f  d_1_i/axi_smc_1/inst/s01_nodes/s01_aw_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[1]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.940     1.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.432 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.165     1.597    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.616 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.308     2.924    d_1_i/axi_smc_1/inst/s01_nodes/s01_aw_node/inst/s_sc_xpm_cdc_async_rst_inst/dest_clk
    SLICE_X47Y198        FDCE                                         r  d_1_i/axi_smc_1/inst/s01_nodes/s01_aw_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[1]/C

Slack:                    inf
  Source:                 d_1_i/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/axi_smc_1/inst/s01_nodes/s01_aw_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[2]/CLR
                            (removal check against rising-edge clock mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Removal (Min at Fast Process Corner)
  Data Path Delay:        0.251ns  (logic 0.039ns (15.540%)  route 0.212ns (84.460%))
  Logic Levels:           0  
  Clock Path Skew:        -0.087ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.924ns
    Source Clock Delay      (SCD):    3.011ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.163ns (routing 0.384ns, distribution 0.779ns)
  Clock Net Delay (Destination): 1.308ns (routing 0.432ns, distribution 0.876ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.839     1.456    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.686 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.145     1.831    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.848 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.163     3.011    d_1_i/axi_smc_1/inst/clk_map/psr_aclk/U0/aclk
    SLICE_X47Y200        FDRE                                         r  d_1_i/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X47Y200        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.039     3.050 r  d_1_i/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/Q
                         net (fo=66, routed)          0.212     3.262    d_1_i/axi_smc_1/inst/s01_nodes/s01_aw_node/inst/s_sc_xpm_cdc_async_rst_inst/src_arst
    SLICE_X47Y198        FDCE                                         f  d_1_i/axi_smc_1/inst/s01_nodes/s01_aw_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[2]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.940     1.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.432 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.165     1.597    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.616 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.308     2.924    d_1_i/axi_smc_1/inst/s01_nodes/s01_aw_node/inst/s_sc_xpm_cdc_async_rst_inst/dest_clk
    SLICE_X47Y198        FDCE                                         r  d_1_i/axi_smc_1/inst/s01_nodes/s01_aw_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[2]/C

Slack:                    inf
  Source:                 d_1_i/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/axi_smc_1/inst/m00_nodes/m00_aw_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[0]/CLR
                            (removal check against rising-edge clock mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Removal (Min at Fast Process Corner)
  Data Path Delay:        0.254ns  (logic 0.039ns (15.383%)  route 0.215ns (84.617%))
  Logic Levels:           0  
  Clock Path Skew:        -0.092ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.919ns
    Source Clock Delay      (SCD):    3.011ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.163ns (routing 0.384ns, distribution 0.779ns)
  Clock Net Delay (Destination): 1.303ns (routing 0.432ns, distribution 0.871ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.839     1.456    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.686 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.145     1.831    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.848 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.163     3.011    d_1_i/axi_smc_1/inst/clk_map/psr_aclk/U0/aclk
    SLICE_X47Y200        FDRE                                         r  d_1_i/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X47Y200        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.039     3.050 r  d_1_i/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/Q
                         net (fo=66, routed)          0.215     3.265    d_1_i/axi_smc_1/inst/m00_nodes/m00_aw_node/inst/s_sc_xpm_cdc_async_rst_inst/src_arst
    SLICE_X51Y197        FDCE                                         f  d_1_i/axi_smc_1/inst/m00_nodes/m00_aw_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[0]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.940     1.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.432 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.165     1.597    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.616 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.303     2.919    d_1_i/axi_smc_1/inst/m00_nodes/m00_aw_node/inst/s_sc_xpm_cdc_async_rst_inst/dest_clk
    SLICE_X51Y197        FDCE                                         r  d_1_i/axi_smc_1/inst/m00_nodes/m00_aw_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/axi_smc_1/inst/m00_nodes/m00_aw_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[1]/CLR
                            (removal check against rising-edge clock mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Removal (Min at Fast Process Corner)
  Data Path Delay:        0.254ns  (logic 0.039ns (15.383%)  route 0.215ns (84.617%))
  Logic Levels:           0  
  Clock Path Skew:        -0.092ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.919ns
    Source Clock Delay      (SCD):    3.011ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.163ns (routing 0.384ns, distribution 0.779ns)
  Clock Net Delay (Destination): 1.303ns (routing 0.432ns, distribution 0.871ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.839     1.456    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.686 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.145     1.831    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.848 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.163     3.011    d_1_i/axi_smc_1/inst/clk_map/psr_aclk/U0/aclk
    SLICE_X47Y200        FDRE                                         r  d_1_i/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X47Y200        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.039     3.050 r  d_1_i/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/Q
                         net (fo=66, routed)          0.215     3.265    d_1_i/axi_smc_1/inst/m00_nodes/m00_aw_node/inst/s_sc_xpm_cdc_async_rst_inst/src_arst
    SLICE_X51Y197        FDCE                                         f  d_1_i/axi_smc_1/inst/m00_nodes/m00_aw_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[1]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.940     1.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.432 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.165     1.597    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.616 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.303     2.919    d_1_i/axi_smc_1/inst/m00_nodes/m00_aw_node/inst/s_sc_xpm_cdc_async_rst_inst/dest_clk
    SLICE_X51Y197        FDCE                                         r  d_1_i/axi_smc_1/inst/m00_nodes/m00_aw_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[1]/C

Slack:                    inf
  Source:                 d_1_i/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/axi_smc_1/inst/m00_nodes/m00_aw_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[2]/CLR
                            (removal check against rising-edge clock mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Removal (Min at Fast Process Corner)
  Data Path Delay:        0.254ns  (logic 0.039ns (15.383%)  route 0.215ns (84.617%))
  Logic Levels:           0  
  Clock Path Skew:        -0.092ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.919ns
    Source Clock Delay      (SCD):    3.011ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.163ns (routing 0.384ns, distribution 0.779ns)
  Clock Net Delay (Destination): 1.303ns (routing 0.432ns, distribution 0.871ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.839     1.456    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.686 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.145     1.831    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.848 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.163     3.011    d_1_i/axi_smc_1/inst/clk_map/psr_aclk/U0/aclk
    SLICE_X47Y200        FDRE                                         r  d_1_i/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X47Y200        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.039     3.050 r  d_1_i/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/Q
                         net (fo=66, routed)          0.215     3.265    d_1_i/axi_smc_1/inst/m00_nodes/m00_aw_node/inst/s_sc_xpm_cdc_async_rst_inst/src_arst
    SLICE_X51Y197        FDCE                                         f  d_1_i/axi_smc_1/inst/m00_nodes/m00_aw_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[2]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.940     1.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.432 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.165     1.597    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.616 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.303     2.919    d_1_i/axi_smc_1/inst/m00_nodes/m00_aw_node/inst/s_sc_xpm_cdc_async_rst_inst/dest_clk
    SLICE_X51Y197        FDCE                                         r  d_1_i/axi_smc_1/inst/m00_nodes/m00_aw_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[2]/C

Slack:                    inf
  Source:                 d_1_i/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/axi_smc_1/inst/s01_entry_pipeline/s01_mmu/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[0]/CLR
                            (removal check against rising-edge clock mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Removal (Min at Fast Process Corner)
  Data Path Delay:        0.283ns  (logic 0.039ns (13.776%)  route 0.244ns (86.224%))
  Logic Levels:           0  
  Clock Path Skew:        -0.041ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.970ns
    Source Clock Delay      (SCD):    3.011ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.163ns (routing 0.384ns, distribution 0.779ns)
  Clock Net Delay (Destination): 1.354ns (routing 0.432ns, distribution 0.922ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.839     1.456    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.686 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.145     1.831    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.848 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.163     3.011    d_1_i/axi_smc_1/inst/clk_map/psr_aclk/U0/aclk
    SLICE_X47Y200        FDRE                                         r  d_1_i/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X47Y200        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.039     3.050 r  d_1_i/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/Q
                         net (fo=66, routed)          0.244     3.294    d_1_i/axi_smc_1/inst/s01_entry_pipeline/s01_mmu/inst/xpm_cdc_async_rst_inst/src_arst
    SLICE_X36Y200        FDCE                                         f  d_1_i/axi_smc_1/inst/s01_entry_pipeline/s01_mmu/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[0]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.940     1.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.432 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.165     1.597    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.616 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.354     2.970    d_1_i/axi_smc_1/inst/s01_entry_pipeline/s01_mmu/inst/xpm_cdc_async_rst_inst/dest_clk
    SLICE_X36Y200        FDCE                                         r  d_1_i/axi_smc_1/inst/s01_entry_pipeline/s01_mmu/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/axi_smc_1/inst/s01_entry_pipeline/s01_mmu/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[1]/CLR
                            (removal check against rising-edge clock mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Removal (Min at Fast Process Corner)
  Data Path Delay:        0.283ns  (logic 0.039ns (13.776%)  route 0.244ns (86.224%))
  Logic Levels:           0  
  Clock Path Skew:        -0.041ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.970ns
    Source Clock Delay      (SCD):    3.011ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.163ns (routing 0.384ns, distribution 0.779ns)
  Clock Net Delay (Destination): 1.354ns (routing 0.432ns, distribution 0.922ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.839     1.456    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.686 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.145     1.831    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.848 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.163     3.011    d_1_i/axi_smc_1/inst/clk_map/psr_aclk/U0/aclk
    SLICE_X47Y200        FDRE                                         r  d_1_i/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X47Y200        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.039     3.050 r  d_1_i/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/Q
                         net (fo=66, routed)          0.244     3.294    d_1_i/axi_smc_1/inst/s01_entry_pipeline/s01_mmu/inst/xpm_cdc_async_rst_inst/src_arst
    SLICE_X36Y200        FDCE                                         f  d_1_i/axi_smc_1/inst/s01_entry_pipeline/s01_mmu/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[1]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.940     1.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.432 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.165     1.597    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.616 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.354     2.970    d_1_i/axi_smc_1/inst/s01_entry_pipeline/s01_mmu/inst/xpm_cdc_async_rst_inst/dest_clk
    SLICE_X36Y200        FDCE                                         r  d_1_i/axi_smc_1/inst/s01_entry_pipeline/s01_mmu/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[1]/C

Slack:                    inf
  Source:                 d_1_i/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/axi_smc_1/inst/s01_entry_pipeline/s01_mmu/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[2]/CLR
                            (removal check against rising-edge clock mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Removal (Min at Fast Process Corner)
  Data Path Delay:        0.283ns  (logic 0.039ns (13.776%)  route 0.244ns (86.224%))
  Logic Levels:           0  
  Clock Path Skew:        -0.041ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.970ns
    Source Clock Delay      (SCD):    3.011ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.163ns (routing 0.384ns, distribution 0.779ns)
  Clock Net Delay (Destination): 1.354ns (routing 0.432ns, distribution 0.922ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.839     1.456    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.686 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.145     1.831    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.848 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.163     3.011    d_1_i/axi_smc_1/inst/clk_map/psr_aclk/U0/aclk
    SLICE_X47Y200        FDRE                                         r  d_1_i/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X47Y200        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.039     3.050 r  d_1_i/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/Q
                         net (fo=66, routed)          0.244     3.294    d_1_i/axi_smc_1/inst/s01_entry_pipeline/s01_mmu/inst/xpm_cdc_async_rst_inst/src_arst
    SLICE_X36Y200        FDCE                                         f  d_1_i/axi_smc_1/inst/s01_entry_pipeline/s01_mmu/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[2]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.940     1.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.432 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.165     1.597    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.616 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.354     2.970    d_1_i/axi_smc_1/inst/s01_entry_pipeline/s01_mmu/inst/xpm_cdc_async_rst_inst/dest_clk
    SLICE_X36Y200        FDCE                                         r  d_1_i/axi_smc_1/inst/s01_entry_pipeline/s01_mmu/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[2]/C

Slack:                    inf
  Source:                 d_1_i/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/axi_smc_1/inst/s00_nodes/s00_aw_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[0]/CLR
                            (removal check against rising-edge clock mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Removal (Min at Fast Process Corner)
  Data Path Delay:        0.300ns  (logic 0.039ns (13.012%)  route 0.261ns (86.988%))
  Logic Levels:           0  
  Clock Path Skew:        -0.067ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.944ns
    Source Clock Delay      (SCD):    3.011ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.163ns (routing 0.384ns, distribution 0.779ns)
  Clock Net Delay (Destination): 1.328ns (routing 0.432ns, distribution 0.896ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.839     1.456    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.686 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.145     1.831    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.848 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.163     3.011    d_1_i/axi_smc_1/inst/clk_map/psr_aclk/U0/aclk
    SLICE_X47Y200        FDRE                                         r  d_1_i/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X47Y200        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.039     3.050 r  d_1_i/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/Q
                         net (fo=66, routed)          0.261     3.311    d_1_i/axi_smc_1/inst/s00_nodes/s00_aw_node/inst/s_sc_xpm_cdc_async_rst_inst/src_arst
    SLICE_X40Y195        FDCE                                         f  d_1_i/axi_smc_1/inst/s00_nodes/s00_aw_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[0]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.940     1.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.432 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.165     1.597    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.616 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.328     2.944    d_1_i/axi_smc_1/inst/s00_nodes/s00_aw_node/inst/s_sc_xpm_cdc_async_rst_inst/dest_clk
    SLICE_X40Y195        FDCE                                         r  d_1_i/axi_smc_1/inst/s00_nodes/s00_aw_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[0]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  mmcm_clkout5
  To Clock:  mmcm_clkout0

Max Delay             0 Endpoints
Min Delay            28 Endpoints
--------------------------------------------------------------------------------------


Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_en_lvl_reg/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_en_sync/SYNC[0].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.110ns  (logic 0.039ns (35.425%)  route 0.071ns (64.576%))
  Logic Levels:           0  
  Clock Path Skew:        0.191ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.832ns
    Source Clock Delay      (SCD):    2.641ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.196ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      0.798ns (routing 0.347ns, distribution 0.451ns)
  Clock Net Delay (Destination): 1.216ns (routing 0.432ns, distribution 0.784ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.839     1.456    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     1.686 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.140     1.826    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y115        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.843 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.798     2.641    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/CLK
    SLICE_X96Y357        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_en_lvl_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X96Y357        FDRE (Prop_DFF_SLICEM_C_Q)
                                                      0.039     2.680 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_en_lvl_reg/Q
                         net (fo=2, routed)           0.071     2.751    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_en_sync/D[0]
    SLICE_X94Y357        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_en_sync/SYNC[0].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.940     1.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.432 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.165     1.597    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.616 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.216     2.832    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_en_sync/SYNC[0].sync_reg_reg[0]_0
    SLICE_X94Y357        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_en_sync/SYNC[0].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_di_r_reg[6]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_di_sync/SYNC[6].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.127ns  (logic 0.039ns (30.709%)  route 0.088ns (69.291%))
  Logic Levels:           0  
  Clock Path Skew:        0.189ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.831ns
    Source Clock Delay      (SCD):    2.642ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.196ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      0.799ns (routing 0.347ns, distribution 0.452ns)
  Clock Net Delay (Destination): 1.215ns (routing 0.432ns, distribution 0.783ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.839     1.456    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     1.686 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.140     1.826    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y115        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.843 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.799     2.642    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/CLK
    SLICE_X94Y351        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_di_r_reg[6]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X94Y351        FDRE (Prop_HFF_SLICEM_C_Q)
                                                      0.039     2.681 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_di_r_reg[6]/Q
                         net (fo=1, routed)           0.088     2.769    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_di_sync/out[6]
    SLICE_X94Y351        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_di_sync/SYNC[6].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.940     1.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.432 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.165     1.597    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.616 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.215     2.831    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_di_sync/SYNC[7].sync_reg_reg[1]_0
    SLICE_X94Y351        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_di_sync/SYNC[6].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[13]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[13].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.128ns  (logic 0.040ns (31.250%)  route 0.088ns (68.750%))
  Logic Levels:           0  
  Clock Path Skew:        0.188ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.832ns
    Source Clock Delay      (SCD):    2.644ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.196ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      0.801ns (routing 0.347ns, distribution 0.454ns)
  Clock Net Delay (Destination): 1.216ns (routing 0.432ns, distribution 0.784ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.839     1.456    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     1.686 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.140     1.826    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y115        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.843 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.801     2.644    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/CLK
    SLICE_X95Y358        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[13]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X95Y358        FDRE (Prop_GFF2_SLICEL_C_Q)
                                                      0.040     2.684 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[13]/Q
                         net (fo=1, routed)           0.088     2.772    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/out[13]
    SLICE_X94Y357        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[13].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.940     1.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.432 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.165     1.597    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.616 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.216     2.832    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[15].sync_reg_reg[1]_0
    SLICE_X94Y357        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[13].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_rdy_cptd_sclk_reg/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_rdy_cptd_sync/SYNC[0].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.129ns  (logic 0.039ns (30.233%)  route 0.090ns (69.767%))
  Logic Levels:           0  
  Clock Path Skew:        0.189ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.833ns
    Source Clock Delay      (SCD):    2.644ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.196ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      0.801ns (routing 0.347ns, distribution 0.454ns)
  Clock Net Delay (Destination): 1.217ns (routing 0.432ns, distribution 0.785ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.839     1.456    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     1.686 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.140     1.826    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y115        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.843 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.801     2.644    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/CLK
    SLICE_X95Y358        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_rdy_cptd_sclk_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X95Y358        FDRE (Prop_HFF_SLICEL_C_Q)
                                                      0.039     2.683 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_rdy_cptd_sclk_reg/Q
                         net (fo=1, routed)           0.090     2.773    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_rdy_cptd_sync/SYNC[0].sync_reg_reg[0]_0[0]
    SLICE_X93Y358        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_rdy_cptd_sync/SYNC[0].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.940     1.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.432 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.165     1.597    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.616 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.217     2.833    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_rdy_cptd_sync/SYNC[0].sync_reg_reg[1]_0
    SLICE_X93Y358        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_rdy_cptd_sync/SYNC[0].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[2].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.153ns  (logic 0.039ns (25.490%)  route 0.114ns (74.510%))
  Logic Levels:           0  
  Clock Path Skew:        0.192ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.831ns
    Source Clock Delay      (SCD):    2.639ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.196ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      0.796ns (routing 0.347ns, distribution 0.449ns)
  Clock Net Delay (Destination): 1.215ns (routing 0.432ns, distribution 0.783ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.839     1.456    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     1.686 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.140     1.826    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y115        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.843 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.796     2.639    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/CLK
    SLICE_X93Y357        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X93Y357        FDRE (Prop_HFF_SLICEM_C_Q)
                                                      0.039     2.678 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[2]/Q
                         net (fo=1, routed)           0.114     2.792    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/out[2]
    SLICE_X93Y357        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[2].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.940     1.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.432 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.165     1.597    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.616 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.215     2.831    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[15].sync_reg_reg[1]_0
    SLICE_X93Y357        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[2].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_di_r_reg[8]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_di_sync/SYNC[8].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.151ns  (logic 0.039ns (25.828%)  route 0.112ns (74.172%))
  Logic Levels:           0  
  Clock Path Skew:        0.200ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.841ns
    Source Clock Delay      (SCD):    2.642ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.196ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      0.799ns (routing 0.347ns, distribution 0.452ns)
  Clock Net Delay (Destination): 1.226ns (routing 0.432ns, distribution 0.794ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.839     1.456    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     1.686 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.140     1.826    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y115        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.843 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.799     2.642    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/CLK
    SLICE_X94Y352        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_di_r_reg[8]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X94Y352        FDRE (Prop_HFF2_SLICEM_C_Q)
                                                      0.039     2.681 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_di_r_reg[8]/Q
                         net (fo=1, routed)           0.112     2.793    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_di_sync/out[8]
    SLICE_X92Y351        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_di_sync/SYNC[8].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.940     1.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.432 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.165     1.597    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.616 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.226     2.841    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_di_sync/SYNC[7].sync_reg_reg[1]_0
    SLICE_X92Y351        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_di_sync/SYNC[8].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[10]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[10].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.151ns  (logic 0.038ns (25.166%)  route 0.113ns (74.834%))
  Logic Levels:           0  
  Clock Path Skew:        0.196ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.841ns
    Source Clock Delay      (SCD):    2.645ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.196ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      0.802ns (routing 0.347ns, distribution 0.455ns)
  Clock Net Delay (Destination): 1.226ns (routing 0.432ns, distribution 0.794ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.839     1.456    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     1.686 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.140     1.826    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y115        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.843 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.802     2.645    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/CLK
    SLICE_X90Y357        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[10]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X90Y357        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.038     2.683 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[10]/Q
                         net (fo=1, routed)           0.113     2.796    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/out[10]
    SLICE_X90Y356        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[10].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.940     1.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.432 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.165     1.597    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.616 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.226     2.841    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[15].sync_reg_reg[1]_0
    SLICE_X90Y356        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[10].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_di_r_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_di_sync/SYNC[2].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.157ns  (logic 0.039ns (24.841%)  route 0.118ns (75.159%))
  Logic Levels:           0  
  Clock Path Skew:        0.187ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.829ns
    Source Clock Delay      (SCD):    2.642ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.196ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      0.799ns (routing 0.347ns, distribution 0.452ns)
  Clock Net Delay (Destination): 1.213ns (routing 0.432ns, distribution 0.781ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.839     1.456    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     1.686 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.140     1.826    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y115        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.843 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.799     2.642    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/CLK
    SLICE_X94Y351        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_di_r_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X94Y351        FDRE (Prop_GFF2_SLICEM_C_Q)
                                                      0.039     2.681 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_di_r_reg[2]/Q
                         net (fo=1, routed)           0.118     2.799    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_di_sync/out[2]
    SLICE_X92Y349        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_di_sync/SYNC[2].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.940     1.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.432 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.165     1.597    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.616 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.213     2.829    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_di_sync/SYNC[7].sync_reg_reg[1]_0
    SLICE_X92Y349        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_di_sync/SYNC[2].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[9]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[9].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.159ns  (logic 0.039ns (24.528%)  route 0.120ns (75.472%))
  Logic Levels:           0  
  Clock Path Skew:        0.190ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.831ns
    Source Clock Delay      (SCD):    2.642ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.196ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      0.799ns (routing 0.347ns, distribution 0.452ns)
  Clock Net Delay (Destination): 1.215ns (routing 0.432ns, distribution 0.783ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.839     1.456    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     1.686 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.140     1.826    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y115        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.843 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.799     2.642    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/CLK
    SLICE_X94Y352        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[9]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X94Y352        FDRE (Prop_GFF2_SLICEM_C_Q)
                                                      0.039     2.681 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[9]/Q
                         net (fo=1, routed)           0.120     2.801    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/out[9]
    SLICE_X91Y352        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[9].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.940     1.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.432 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.165     1.597    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.616 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.215     2.831    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[15].sync_reg_reg[1]_0
    SLICE_X91Y352        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[9].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[3].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.173ns  (logic 0.038ns (21.965%)  route 0.135ns (78.035%))
  Logic Levels:           0  
  Clock Path Skew:        0.197ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.836ns
    Source Clock Delay      (SCD):    2.639ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.196ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      0.796ns (routing 0.347ns, distribution 0.449ns)
  Clock Net Delay (Destination): 1.220ns (routing 0.432ns, distribution 0.788ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.839     1.456    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     1.686 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.140     1.826    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y115        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.843 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.796     2.639    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/CLK
    SLICE_X93Y354        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X93Y354        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.038     2.677 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[3]/Q
                         net (fo=1, routed)           0.135     2.812    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/out[3]
    SLICE_X91Y353        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[3].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.940     1.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.432 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.165     1.597    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.616 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.220     2.836    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[15].sync_reg_reg[1]_0
    SLICE_X91Y353        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[3].sync_reg_reg[0]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  mmcm_clkout6
  To Clock:  mmcm_clkout0

Max Delay             0 Endpoints
Min Delay           129 Endpoints
--------------------------------------------------------------------------------------


Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/phy2clb_fixdly_rdy_upp_riuclk_int_reg[6]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_phy2clb_fixdly_rdy_upp/SYNC[6].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.102ns  (logic 0.038ns (37.371%)  route 0.064ns (62.629%))
  Logic Levels:           0  
  Clock Path Skew:        -0.121ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.800ns
    Source Clock Delay      (SCD):    2.921ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.188ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      1.063ns (routing 0.391ns, distribution 0.672ns)
  Clock Net Delay (Destination): 1.184ns (routing 0.432ns, distribution 0.752ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.839     1.456    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.230     1.686 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.155     1.841    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y104        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.858 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.063     2.921    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_clk
    SLICE_X82Y282        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/phy2clb_fixdly_rdy_upp_riuclk_int_reg[6]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X82Y282        FDRE (Prop_AFF_SLICEM_C_Q)
                                                      0.038     2.959 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/phy2clb_fixdly_rdy_upp_riuclk_int_reg[6]/Q
                         net (fo=2, routed)           0.064     3.023    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_phy2clb_fixdly_rdy_upp/phy2clb_fixdly_rdy_upp_riuclk[6]
    SLICE_X81Y282        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_phy2clb_fixdly_rdy_upp/SYNC[6].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.940     1.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.432 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.165     1.597    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.616 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.184     2.800    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_phy2clb_fixdly_rdy_upp/SYNC[19].sync_reg_reg[1]_0
    SLICE_X81Y282        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_phy2clb_fixdly_rdy_upp/SYNC[6].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/riu2clb_valid_r1_riuclk_reg[15]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_riu2clb_valid_sync/SYNC[15].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.104ns  (logic 0.039ns (37.500%)  route 0.065ns (62.500%))
  Logic Levels:           0  
  Clock Path Skew:        -0.104ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.818ns
    Source Clock Delay      (SCD):    2.922ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.188ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      1.064ns (routing 0.391ns, distribution 0.673ns)
  Clock Net Delay (Destination): 1.202ns (routing 0.432ns, distribution 0.770ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.839     1.456    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.230     1.686 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.155     1.841    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y104        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.858 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.064     2.922    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/CLK
    SLICE_X93Y260        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/riu2clb_valid_r1_riuclk_reg[15]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X93Y260        FDRE (Prop_EFF2_SLICEM_C_Q)
                                                      0.039     2.961 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/riu2clb_valid_r1_riuclk_reg[15]/Q
                         net (fo=1, routed)           0.065     3.026    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_riu2clb_valid_sync/SYNC[19].sync_reg_reg[0]_0[15]
    SLICE_X93Y259        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_riu2clb_valid_sync/SYNC[15].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.940     1.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.432 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.165     1.597    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.616 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.202     2.818    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_riu2clb_valid_sync/SYNC[19].sync_reg_reg[1]_0
    SLICE_X93Y259        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_riu2clb_valid_sync/SYNC[15].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/phy2clb_fixdly_rdy_upp_riuclk_int_reg[7]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_phy2clb_fixdly_rdy_upp/SYNC[7].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.099ns  (logic 0.039ns (39.521%)  route 0.060ns (60.480%))
  Logic Levels:           0  
  Clock Path Skew:        -0.121ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.808ns
    Source Clock Delay      (SCD):    2.930ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.188ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      1.072ns (routing 0.391ns, distribution 0.681ns)
  Clock Net Delay (Destination): 1.192ns (routing 0.432ns, distribution 0.760ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.839     1.456    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.230     1.686 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.155     1.841    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y104        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.858 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.072     2.930    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_clk
    SLICE_X81Y295        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/phy2clb_fixdly_rdy_upp_riuclk_int_reg[7]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y295        FDRE (Prop_FFF_SLICEL_C_Q)
                                                      0.039     2.969 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/phy2clb_fixdly_rdy_upp_riuclk_int_reg[7]/Q
                         net (fo=2, routed)           0.060     3.028    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_phy2clb_fixdly_rdy_upp/phy2clb_fixdly_rdy_upp_riuclk[7]
    SLICE_X81Y294        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_phy2clb_fixdly_rdy_upp/SYNC[7].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.940     1.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.432 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.165     1.597    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.616 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.192     2.808    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_phy2clb_fixdly_rdy_upp/SYNC[19].sync_reg_reg[1]_0
    SLICE_X81Y294        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_phy2clb_fixdly_rdy_upp/SYNC[7].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_write_data_riuclk_reg[15]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_write_data_sync/SYNC[15].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.102ns  (logic 0.037ns (36.388%)  route 0.065ns (63.612%))
  Logic Levels:           0  
  Clock Path Skew:        -0.114ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.816ns
    Source Clock Delay      (SCD):    2.930ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.188ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      1.072ns (routing 0.391ns, distribution 0.681ns)
  Clock Net Delay (Destination): 1.200ns (routing 0.432ns, distribution 0.768ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.839     1.456    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.230     1.686 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.155     1.841    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y104        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.858 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.072     2.930    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/CLK
    SLICE_X82Y326        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_write_data_riuclk_reg[15]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X82Y326        FDRE (Prop_FFF_SLICEM_C_Q)
                                                      0.037     2.967 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_write_data_riuclk_reg[15]/Q
                         net (fo=2, routed)           0.065     3.032    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_write_data_sync/SYNC[31].sync_reg_reg[0]_0[15]
    SLICE_X81Y326        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_write_data_sync/SYNC[15].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.940     1.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.432 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.165     1.597    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.616 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.200     2.816    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_write_data_sync/SYNC[30].sync_reg_reg[1]_0
    SLICE_X81Y326        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_write_data_sync/SYNC[15].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/riu2clb_valid_r1_riuclk_reg[12]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_riu2clb_valid_sync/SYNC[12].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.105ns  (logic 0.038ns (36.190%)  route 0.067ns (63.810%))
  Logic Levels:           0  
  Clock Path Skew:        -0.104ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.823ns
    Source Clock Delay      (SCD):    2.927ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.188ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      1.069ns (routing 0.391ns, distribution 0.678ns)
  Clock Net Delay (Destination): 1.207ns (routing 0.432ns, distribution 0.775ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.839     1.456    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.230     1.686 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.155     1.841    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y104        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.858 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.069     2.927    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/CLK
    SLICE_X96Y250        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/riu2clb_valid_r1_riuclk_reg[12]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X96Y250        FDRE (Prop_AFF_SLICEM_C_Q)
                                                      0.038     2.965 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/riu2clb_valid_r1_riuclk_reg[12]/Q
                         net (fo=1, routed)           0.067     3.032    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_riu2clb_valid_sync/SYNC[19].sync_reg_reg[0]_0[12]
    SLICE_X96Y249        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_riu2clb_valid_sync/SYNC[12].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.940     1.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.432 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.165     1.597    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.616 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.207     2.823    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_riu2clb_valid_sync/SYNC[19].sync_reg_reg[1]_0
    SLICE_X96Y249        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_riu2clb_valid_sync/SYNC[12].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/phy2clb_fixdly_rdy_upp_riuclk_int_reg[10]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_phy2clb_fixdly_rdy_upp/SYNC[10].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.100ns  (logic 0.037ns (36.966%)  route 0.063ns (63.034%))
  Logic Levels:           0  
  Clock Path Skew:        -0.110ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.822ns
    Source Clock Delay      (SCD):    2.932ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.188ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      1.074ns (routing 0.391ns, distribution 0.683ns)
  Clock Net Delay (Destination): 1.206ns (routing 0.432ns, distribution 0.774ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.839     1.456    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.230     1.686 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.155     1.841    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y104        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.858 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.074     2.932    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_clk
    SLICE_X82Y340        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/phy2clb_fixdly_rdy_upp_riuclk_int_reg[10]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X82Y340        FDRE (Prop_FFF_SLICEM_C_Q)
                                                      0.037     2.969 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/phy2clb_fixdly_rdy_upp_riuclk_int_reg[10]/Q
                         net (fo=2, routed)           0.063     3.032    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_phy2clb_fixdly_rdy_upp/phy2clb_fixdly_rdy_upp_riuclk[10]
    SLICE_X81Y340        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_phy2clb_fixdly_rdy_upp/SYNC[10].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.940     1.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.432 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.165     1.597    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.616 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.206     2.822    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_phy2clb_fixdly_rdy_upp/SYNC[19].sync_reg_reg[1]_0
    SLICE_X81Y340        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_phy2clb_fixdly_rdy_upp/SYNC[10].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/riu2clb_valid_r1_riuclk_reg[17]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_riu2clb_valid_sync/SYNC[17].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.118ns  (logic 0.039ns (33.051%)  route 0.079ns (66.949%))
  Logic Levels:           0  
  Clock Path Skew:        -0.115ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.801ns
    Source Clock Delay      (SCD):    2.916ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.188ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      1.058ns (routing 0.391ns, distribution 0.667ns)
  Clock Net Delay (Destination): 1.185ns (routing 0.432ns, distribution 0.753ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.839     1.456    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.230     1.686 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.155     1.841    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y104        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.858 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.058     2.916    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/CLK
    SLICE_X95Y272        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/riu2clb_valid_r1_riuclk_reg[17]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X95Y272        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.039     2.955 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/riu2clb_valid_r1_riuclk_reg[17]/Q
                         net (fo=1, routed)           0.079     3.034    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_riu2clb_valid_sync/SYNC[19].sync_reg_reg[0]_0[17]
    SLICE_X95Y272        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_riu2clb_valid_sync/SYNC[17].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.940     1.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.432 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.165     1.597    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.616 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.185     2.801    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_riu2clb_valid_sync/SYNC[19].sync_reg_reg[1]_0
    SLICE_X95Y272        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_riu2clb_valid_sync/SYNC[17].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/phy2clb_phy_rdy_low_riuclk_int_reg[7]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_phy2clb_phy_rdy_low/SYNC[7].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.099ns  (logic 0.039ns (39.521%)  route 0.060ns (60.480%))
  Logic Levels:           0  
  Clock Path Skew:        -0.117ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.821ns
    Source Clock Delay      (SCD):    2.938ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.188ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      1.080ns (routing 0.391ns, distribution 0.689ns)
  Clock Net Delay (Destination): 1.205ns (routing 0.432ns, distribution 0.773ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.839     1.456    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.230     1.686 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.155     1.841    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y104        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.858 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.080     2.938    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_clk
    SLICE_X81Y307        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/phy2clb_phy_rdy_low_riuclk_int_reg[7]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y307        FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.039     2.977 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/phy2clb_phy_rdy_low_riuclk_int_reg[7]/Q
                         net (fo=2, routed)           0.060     3.037    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_phy2clb_phy_rdy_low/phy2clb_phy_rdy_low_riuclk[7]
    SLICE_X81Y308        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_phy2clb_phy_rdy_low/SYNC[7].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.940     1.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.432 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.165     1.597    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.616 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.205     2.821    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_phy2clb_phy_rdy_low/SYNC[19].sync_reg_reg[1]_0
    SLICE_X81Y308        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_phy2clb_phy_rdy_low/SYNC[7].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_write_data_riuclk_reg[18]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_write_data_sync/SYNC[18].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.114ns  (logic 0.039ns (34.211%)  route 0.075ns (65.790%))
  Logic Levels:           0  
  Clock Path Skew:        -0.105ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.818ns
    Source Clock Delay      (SCD):    2.923ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.188ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      1.065ns (routing 0.391ns, distribution 0.674ns)
  Clock Net Delay (Destination): 1.202ns (routing 0.432ns, distribution 0.770ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.839     1.456    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.230     1.686 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.155     1.841    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y104        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.858 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.065     2.923    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/CLK
    SLICE_X88Y331        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_write_data_riuclk_reg[18]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X88Y331        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.039     2.962 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_write_data_riuclk_reg[18]/Q
                         net (fo=1, routed)           0.075     3.037    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_write_data_sync/SYNC[31].sync_reg_reg[0]_0[18]
    SLICE_X88Y331        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_write_data_sync/SYNC[18].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.940     1.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.432 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.165     1.597    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.616 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.202     2.818    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_write_data_sync/SYNC[30].sync_reg_reg[1]_0
    SLICE_X88Y331        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_write_data_sync/SYNC[18].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/phy2clb_phy_rdy_upp_riuclk_int_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_phy2clb_phy_rdy_upp/SYNC[2].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.144ns  (logic 0.039ns (27.080%)  route 0.105ns (72.920%))
  Logic Levels:           0  
  Clock Path Skew:        -0.125ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.771ns
    Source Clock Delay      (SCD):    2.896ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.188ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      1.038ns (routing 0.391ns, distribution 0.647ns)
  Clock Net Delay (Destination): 1.155ns (routing 0.432ns, distribution 0.723ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.839     1.456    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.230     1.686 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.155     1.841    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y104        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.858 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.038     2.896    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_clk
    SLICE_X81Y220        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/phy2clb_phy_rdy_upp_riuclk_int_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y220        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.039     2.935 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/phy2clb_phy_rdy_upp_riuclk_int_reg[2]/Q
                         net (fo=2, routed)           0.105     3.040    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_phy2clb_phy_rdy_upp/phy2clb_phy_rdy_upp_riuclk[2]
    SLICE_X81Y218        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_phy2clb_phy_rdy_upp/SYNC[2].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.940     1.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.432 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.165     1.597    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.616 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.155     2.771    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_phy2clb_phy_rdy_upp/SYNC[19].sync_reg_reg[1]_0
    SLICE_X81Y218        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_phy2clb_phy_rdy_upp/SYNC[2].sync_reg_reg[0]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  sys_clk_ddr4_clk_p
  To Clock:  mmcm_clkout0

Max Delay             1 Endpoint
Min Delay             1 Endpoint
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_async_riu_div_reg/C
                            (rising edge-triggered cell FDRE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_div_sync_r_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.381ns  (logic 0.081ns (21.258%)  route 0.300ns (78.742%))
  Logic Levels:           0  
  Clock Path Skew:        2.055ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.883ns
    Source Clock Delay      (SCD):    2.828ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.161ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.742ns (routing 0.700ns, distribution 1.042ns)
  Clock Net Delay (Destination): 1.736ns (routing 0.630ns, distribution 1.106ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y4 (CLOCK_ROOT)    net (fo=18, routed)          1.742     2.828    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X91Y355        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_async_riu_div_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X91Y355        FDRE (Prop_AFF2_SLICEL_C_Q)
                                                      0.081     2.909 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_async_riu_div_reg/Q
                         net (fo=2, routed)           0.300     3.209    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_async_riu_div
    SLICE_X91Y356        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_div_sync_r_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.364     2.279    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.909 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.214     3.123    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.147 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.736     4.883    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk_0
    SLICE_X91Y356        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_div_sync_r_reg[0]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_async_riu_div_reg/C
                            (rising edge-triggered cell FDRE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_div_sync_r_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.146ns  (logic 0.040ns (27.457%)  route 0.106ns (72.543%))
  Logic Levels:           0  
  Clock Path Skew:        1.255ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.836ns
    Source Clock Delay      (SCD):    1.581ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.161ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      0.964ns (routing 0.387ns, distribution 0.577ns)
  Clock Net Delay (Destination): 1.221ns (routing 0.432ns, distribution 0.789ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y4 (CLOCK_ROOT)    net (fo=18, routed)          0.964     1.581    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X91Y355        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_async_riu_div_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X91Y355        FDRE (Prop_AFF2_SLICEL_C_Q)
                                                      0.040     1.621 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_async_riu_div_reg/Q
                         net (fo=2, routed)           0.106     1.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_async_riu_div
    SLICE_X91Y356        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_div_sync_r_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.940     1.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.432 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.165     1.597    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.616 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.221     2.836    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk_0
    SLICE_X91Y356        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_div_sync_r_reg[0]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  To Clock:  mmcm_clkout5

Max Delay            78 Endpoints
Min Delay            86 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/icn_cmd_en_temp_reg/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/ctl_reg_en_1_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.784ns  (logic 0.078ns (9.944%)  route 0.706ns (90.056%))
  Logic Levels:           0  
  Clock Path Skew:        -3.393ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.493ns
    Source Clock Delay      (SCD):    7.886ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.751ns (routing 0.515ns, distribution 1.236ns)
  Clock Net Delay (Destination): 1.353ns (routing 0.575ns, distribution 0.778ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.807     6.107    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y81         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     6.135 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.751     7.886    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/m_bscan_tck[0]
    SLICE_X104Y344       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/icn_cmd_en_temp_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X104Y344       FDRE (Prop_CFF_SLICEM_C_Q)
                                                      0.078     7.964 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/icn_cmd_en_temp_reg/Q
                         net (fo=29, routed)          0.706     8.670    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/icn_cmd_en_temp
    SLICE_X104Y352       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/ctl_reg_en_1_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.364     2.279    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630     2.909 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.207     3.116    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y115        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.140 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.353     4.493    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/clk
    SLICE_X104Y352       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/ctl_reg_en_1_reg[0]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[17]/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/ctl_reg_reg[17]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.749ns  (logic 0.080ns (10.688%)  route 0.669ns (89.312%))
  Logic Levels:           0  
  Clock Path Skew:        -3.411ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.488ns
    Source Clock Delay      (SCD):    7.899ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.764ns (routing 0.515ns, distribution 1.249ns)
  Clock Net Delay (Destination): 1.348ns (routing 0.575ns, distribution 0.773ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.807     6.107    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y81         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     6.135 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.764     7.899    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/m_bscan_tck[0]
    SLICE_X100Y355       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[17]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X100Y355       FDRE (Prop_HFF2_SLICEL_C_Q)
                                                      0.080     7.979 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[17]/Q
                         net (fo=25, routed)          0.669     8.648    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in[17]
    SLICE_X104Y356       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/ctl_reg_reg[17]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.364     2.279    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630     2.909 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.207     3.116    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y115        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.140 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.348     4.488    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/clk
    SLICE_X104Y356       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/ctl_reg_reg[17]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMC/CLK
                            (rising edge-triggered cell RAMD32 clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/gpr1.dout_i_reg[4]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.709ns  (logic 0.288ns (40.621%)  route 0.421ns (59.379%))
  Logic Levels:           0  
  Clock Path Skew:        -3.453ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.471ns
    Source Clock Delay      (SCD):    7.924ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.789ns (routing 0.515ns, distribution 1.274ns)
  Clock Net Delay (Destination): 1.331ns (routing 0.575ns, distribution 0.756ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.807     6.107    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y81         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     6.135 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.789     7.924    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/WCLK
    SLICE_X103Y357       RAMD32                                       r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMC/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X103Y357       RAMD32 (Prop_C5LUT_SLICEM_CLK_O)
                                                      0.288     8.212 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMC/O
                         net (fo=1, routed)           0.421     8.633    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/dout_i0[4]
    SLICE_X101Y357       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/gpr1.dout_i_reg[4]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.364     2.279    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630     2.909 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.207     3.116    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y115        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.140 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.331     4.471    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/rd_clk
    SLICE_X101Y357       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/gpr1.dout_i_reg[4]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMA_D1/CLK
                            (rising edge-triggered cell RAMD32 clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/gpr1.dout_i_reg[1]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.703ns  (logic 0.305ns (43.386%)  route 0.398ns (56.615%))
  Logic Levels:           0  
  Clock Path Skew:        -3.453ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.471ns
    Source Clock Delay      (SCD):    7.924ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.789ns (routing 0.515ns, distribution 1.274ns)
  Clock Net Delay (Destination): 1.331ns (routing 0.575ns, distribution 0.756ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.807     6.107    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y81         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     6.135 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.789     7.924    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/WCLK
    SLICE_X103Y357       RAMD32                                       r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMA_D1/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X103Y357       RAMD32 (Prop_A6LUT_SLICEM_CLK_O)
                                                      0.305     8.229 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMA_D1/O
                         net (fo=1, routed)           0.398     8.627    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/dout_i0[1]
    SLICE_X101Y357       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/gpr1.dout_i_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.364     2.279    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630     2.909 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.207     3.116    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y115        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.140 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.331     4.471    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/rd_clk
    SLICE_X101Y357       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/gpr1.dout_i_reg[1]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMB_D1/CLK
                            (rising edge-triggered cell RAMD32 clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/gpr1.dout_i_reg[3]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.677ns  (logic 0.307ns (45.347%)  route 0.370ns (54.653%))
  Logic Levels:           0  
  Clock Path Skew:        -3.451ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.473ns
    Source Clock Delay      (SCD):    7.924ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.789ns (routing 0.515ns, distribution 1.274ns)
  Clock Net Delay (Destination): 1.333ns (routing 0.575ns, distribution 0.758ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.807     6.107    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y81         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     6.135 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.789     7.924    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/WCLK
    SLICE_X103Y357       RAMD32                                       r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMB_D1/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X103Y357       RAMD32 (Prop_B6LUT_SLICEM_CLK_O)
                                                      0.307     8.231 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMB_D1/O
                         net (fo=1, routed)           0.370     8.601    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/dout_i0[3]
    SLICE_X101Y357       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/gpr1.dout_i_reg[3]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.364     2.279    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630     2.909 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.207     3.116    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y115        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.140 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.333     4.473    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/rd_clk
    SLICE_X101Y357       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/gpr1.dout_i_reg[3]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[13]/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/ctl_reg_reg[13]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.693ns  (logic 0.080ns (11.544%)  route 0.613ns (88.456%))
  Logic Levels:           0  
  Clock Path Skew:        -3.423ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.476ns
    Source Clock Delay      (SCD):    7.899ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.764ns (routing 0.515ns, distribution 1.249ns)
  Clock Net Delay (Destination): 1.336ns (routing 0.575ns, distribution 0.761ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.807     6.107    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y81         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     6.135 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.764     7.899    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/m_bscan_tck[0]
    SLICE_X105Y346       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[13]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X105Y346       FDRE (Prop_BFF2_SLICEL_C_Q)
                                                      0.080     7.979 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[13]/Q
                         net (fo=2, routed)           0.613     8.592    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in[13]
    SLICE_X105Y345       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/ctl_reg_reg[13]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.364     2.279    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630     2.909 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.207     3.116    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y115        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.140 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.336     4.476    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/clk
    SLICE_X105Y345       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/ctl_reg_reg[13]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMF/CLK
                            (rising edge-triggered cell RAMD32 clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/gpr1.dout_i_reg[10]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.665ns  (logic 0.295ns (44.361%)  route 0.370ns (55.639%))
  Logic Levels:           0  
  Clock Path Skew:        -3.451ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.473ns
    Source Clock Delay      (SCD):    7.924ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.789ns (routing 0.515ns, distribution 1.274ns)
  Clock Net Delay (Destination): 1.333ns (routing 0.575ns, distribution 0.758ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.807     6.107    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y81         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     6.135 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.789     7.924    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/WCLK
    SLICE_X103Y357       RAMD32                                       r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMF/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X103Y357       RAMD32 (Prop_F5LUT_SLICEM_CLK_O)
                                                      0.295     8.219 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMF/O
                         net (fo=1, routed)           0.370     8.589    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/dout_i0[10]
    SLICE_X101Y357       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/gpr1.dout_i_reg[10]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.364     2.279    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630     2.909 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.207     3.116    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y115        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.140 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.333     4.473    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/rd_clk
    SLICE_X101Y357       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/gpr1.dout_i_reg[10]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMG_D1/CLK
                            (rising edge-triggered cell RAMD32 clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/gpr1.dout_i_reg[13]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.647ns  (logic 0.295ns (45.595%)  route 0.352ns (54.405%))
  Logic Levels:           0  
  Clock Path Skew:        -3.453ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.471ns
    Source Clock Delay      (SCD):    7.924ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.789ns (routing 0.515ns, distribution 1.274ns)
  Clock Net Delay (Destination): 1.331ns (routing 0.575ns, distribution 0.756ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.807     6.107    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y81         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     6.135 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.789     7.924    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/WCLK
    SLICE_X103Y357       RAMD32                                       r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMG_D1/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X103Y357       RAMD32 (Prop_G6LUT_SLICEM_CLK_O)
                                                      0.295     8.219 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMG_D1/O
                         net (fo=1, routed)           0.352     8.571    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/dout_i0[13]
    SLICE_X101Y357       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/gpr1.dout_i_reg[13]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.364     2.279    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630     2.909 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.207     3.116    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y115        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.140 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.331     4.471    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/rd_clk
    SLICE_X101Y357       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/gpr1.dout_i_reg[13]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAME/CLK
                            (rising edge-triggered cell RAMD32 clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/gpr1.dout_i_reg[8]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.637ns  (logic 0.288ns (45.212%)  route 0.349ns (54.788%))
  Logic Levels:           0  
  Clock Path Skew:        -3.453ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.471ns
    Source Clock Delay      (SCD):    7.924ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.789ns (routing 0.515ns, distribution 1.274ns)
  Clock Net Delay (Destination): 1.331ns (routing 0.575ns, distribution 0.756ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.807     6.107    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y81         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     6.135 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.789     7.924    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/WCLK
    SLICE_X103Y357       RAMD32                                       r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAME/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X103Y357       RAMD32 (Prop_E5LUT_SLICEM_CLK_O)
                                                      0.288     8.212 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAME/O
                         net (fo=1, routed)           0.349     8.561    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/dout_i0[8]
    SLICE_X101Y357       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/gpr1.dout_i_reg[8]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.364     2.279    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630     2.909 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.207     3.116    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y115        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.140 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.331     4.471    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/rd_clk
    SLICE_X101Y357       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/gpr1.dout_i_reg[8]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMD/CLK
                            (rising edge-triggered cell RAMD32 clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/gpr1.dout_i_reg[6]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.628ns  (logic 0.287ns (45.701%)  route 0.341ns (54.299%))
  Logic Levels:           0  
  Clock Path Skew:        -3.451ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.473ns
    Source Clock Delay      (SCD):    7.924ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.789ns (routing 0.515ns, distribution 1.274ns)
  Clock Net Delay (Destination): 1.333ns (routing 0.575ns, distribution 0.758ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.807     6.107    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y81         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     6.135 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.789     7.924    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/WCLK
    SLICE_X103Y357       RAMD32                                       r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMD/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X103Y357       RAMD32 (Prop_D5LUT_SLICEM_CLK_O)
                                                      0.287     8.211 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMD/O
                         net (fo=1, routed)           0.341     8.552    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/dout_i0[6]
    SLICE_X101Y357       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/gpr1.dout_i_reg[6]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.364     2.279    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630     2.909 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.207     3.116    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y115        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.140 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.333     4.473    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/rd_clk
    SLICE_X101Y357       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/gpr1.dout_i_reg[6]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[4]/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/ctl_reg_reg[4]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.102ns  (logic 0.040ns (39.338%)  route 0.062ns (60.662%))
  Logic Levels:           0  
  Clock Path Skew:        0.166ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.568ns
    Source Clock Delay      (SCD):    2.403ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      0.967ns (routing 0.283ns, distribution 0.684ns)
  Clock Net Delay (Destination): 0.958ns (routing 0.388ns, distribution 0.570ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.954     1.419    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y81         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.436 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         0.967     2.403    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/m_bscan_tck[0]
    SLICE_X105Y347       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X105Y347       FDRE (Prop_GFF2_SLICEL_C_Q)
                                                      0.040     2.443 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[4]/Q
                         net (fo=2, routed)           0.062     2.504    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in[4]
    SLICE_X105Y348       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/ctl_reg_reg[4]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.940     1.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     1.432 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.159     1.591    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y115        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.610 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.958     2.568    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/clk
    SLICE_X105Y348       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/ctl_reg_reg[4]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[1]/C
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[1]/D
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.099ns  (logic 0.039ns (39.394%)  route 0.060ns (60.606%))
  Logic Levels:           0  
  Clock Path Skew:        0.145ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.553ns
    Source Clock Delay      (SCD):    2.408ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      0.972ns (routing 0.283ns, distribution 0.689ns)
  Clock Net Delay (Destination): 0.943ns (routing 0.388ns, distribution 0.555ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.954     1.419    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y81         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.436 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         0.972     2.408    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_clk
    SLICE_X101Y349       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X101Y349       FDCE (Prop_HFF2_SLICEL_C_Q)
                                                      0.039     2.447 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[1]/Q
                         net (fo=1, routed)           0.060     2.507    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q[1]
    SLICE_X101Y347       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.940     1.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     1.432 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.159     1.591    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y115        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.610 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.943     2.553    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/wr_clk
    SLICE_X101Y347       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[1]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[7]/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/ctl_reg_reg[7]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.102ns  (logic 0.039ns (38.355%)  route 0.063ns (61.646%))
  Logic Levels:           0  
  Clock Path Skew:        0.154ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.561ns
    Source Clock Delay      (SCD):    2.407ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      0.971ns (routing 0.283ns, distribution 0.688ns)
  Clock Net Delay (Destination): 0.951ns (routing 0.388ns, distribution 0.563ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.954     1.419    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y81         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.436 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         0.971     2.407    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/m_bscan_tck[0]
    SLICE_X100Y355       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[7]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X100Y355       FDRE (Prop_FFF_SLICEL_C_Q)
                                                      0.039     2.446 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[7]/Q
                         net (fo=2, routed)           0.063     2.508    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in[7]
    SLICE_X100Y354       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/ctl_reg_reg[7]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.940     1.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     1.432 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.159     1.591    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y115        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.610 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.951     2.561    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/clk
    SLICE_X100Y354       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/ctl_reg_reg[7]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[16]/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/ctl_reg_reg[16]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.103ns  (logic 0.040ns (38.955%)  route 0.063ns (61.045%))
  Logic Levels:           0  
  Clock Path Skew:        0.157ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.563ns
    Source Clock Delay      (SCD):    2.406ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      0.970ns (routing 0.283ns, distribution 0.687ns)
  Clock Net Delay (Destination): 0.953ns (routing 0.388ns, distribution 0.565ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.954     1.419    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y81         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.436 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         0.970     2.406    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/m_bscan_tck[0]
    SLICE_X105Y346       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[16]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X105Y346       FDRE (Prop_EFF2_SLICEL_C_Q)
                                                      0.040     2.446 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[16]/Q
                         net (fo=2, routed)           0.063     2.509    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in[16]
    SLICE_X105Y345       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/ctl_reg_reg[16]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.940     1.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     1.432 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.159     1.591    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y115        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.610 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.953     2.563    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/clk
    SLICE_X105Y345       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/ctl_reg_reg[16]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[25]/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/ctl_reg_reg[25]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.113ns  (logic 0.039ns (34.610%)  route 0.074ns (65.390%))
  Logic Levels:           0  
  Clock Path Skew:        0.166ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.572ns
    Source Clock Delay      (SCD):    2.406ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      0.970ns (routing 0.283ns, distribution 0.687ns)
  Clock Net Delay (Destination): 0.962ns (routing 0.388ns, distribution 0.574ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.954     1.419    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y81         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.436 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         0.970     2.406    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/m_bscan_tck[0]
    SLICE_X105Y346       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[25]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X105Y346       FDRE (Prop_FFF_SLICEL_C_Q)
                                                      0.039     2.445 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[25]/Q
                         net (fo=2, routed)           0.074     2.519    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in[25]
    SLICE_X105Y348       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/ctl_reg_reg[25]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.940     1.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     1.432 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.159     1.591    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y115        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.610 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.962     2.572    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/clk
    SLICE_X105Y348       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/ctl_reg_reg[25]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[3]/C
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[3]/D
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.119ns  (logic 0.039ns (32.773%)  route 0.080ns (67.227%))
  Logic Levels:           0  
  Clock Path Skew:        0.153ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.558ns
    Source Clock Delay      (SCD):    2.405ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      0.969ns (routing 0.283ns, distribution 0.686ns)
  Clock Net Delay (Destination): 0.948ns (routing 0.388ns, distribution 0.560ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.954     1.419    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y81         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.436 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         0.969     2.405    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_clk
    SLICE_X102Y349       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X102Y349       FDCE (Prop_AFF_SLICEL_C_Q)
                                                      0.039     2.444 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[3]/Q
                         net (fo=1, routed)           0.080     2.524    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q[3]
    SLICE_X102Y349       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[3]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.940     1.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     1.432 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.159     1.591    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y115        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.610 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.948     2.558    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/wr_clk
    SLICE_X102Y349       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[3]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[9]/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/ctl_reg_reg[9]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.126ns  (logic 0.039ns (31.030%)  route 0.087ns (68.970%))
  Logic Levels:           0  
  Clock Path Skew:        0.173ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.572ns
    Source Clock Delay      (SCD):    2.400ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      0.964ns (routing 0.283ns, distribution 0.681ns)
  Clock Net Delay (Destination): 0.962ns (routing 0.388ns, distribution 0.574ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.954     1.419    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y81         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.436 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         0.964     2.400    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/m_bscan_tck[0]
    SLICE_X105Y347       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[9]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X105Y347       FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.039     2.439 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[9]/Q
                         net (fo=2, routed)           0.087     2.525    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in[9]
    SLICE_X105Y348       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/ctl_reg_reg[9]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.940     1.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     1.432 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.159     1.591    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y115        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.610 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.962     2.572    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/clk
    SLICE_X105Y348       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/ctl_reg_reg[9]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/ctl_reg_reg[1]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.127ns  (logic 0.040ns (31.575%)  route 0.087ns (68.425%))
  Logic Levels:           0  
  Clock Path Skew:        0.152ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.552ns
    Source Clock Delay      (SCD):    2.400ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      0.964ns (routing 0.283ns, distribution 0.681ns)
  Clock Net Delay (Destination): 0.942ns (routing 0.388ns, distribution 0.554ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.954     1.419    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y81         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.436 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         0.964     2.400    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/m_bscan_tck[0]
    SLICE_X100Y356       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X100Y356       FDRE (Prop_BFF2_SLICEL_C_Q)
                                                      0.040     2.440 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[1]/Q
                         net (fo=2, routed)           0.087     2.527    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in[1]
    SLICE_X98Y356        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/ctl_reg_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.940     1.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     1.432 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.159     1.591    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y115        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.610 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.942     2.552    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/clk
    SLICE_X98Y356        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/ctl_reg_reg[1]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/icn_cmd_en_temp_reg/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_en_1_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.129ns  (logic 0.038ns (29.530%)  route 0.091ns (70.470%))
  Logic Levels:           0  
  Clock Path Skew:        0.159ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.559ns
    Source Clock Delay      (SCD):    2.400ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      0.964ns (routing 0.283ns, distribution 0.681ns)
  Clock Net Delay (Destination): 0.949ns (routing 0.388ns, distribution 0.561ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.954     1.419    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y81         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.436 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         0.964     2.400    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/m_bscan_tck[0]
    SLICE_X103Y342       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/icn_cmd_en_temp_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X103Y342       FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.038     2.438 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/icn_cmd_en_temp_reg/Q
                         net (fo=3, routed)           0.091     2.529    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/icn_cmd_en_temp
    SLICE_X103Y342       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_en_1_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.940     1.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     1.432 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.159     1.591    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y115        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.610 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.949     2.559    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/clk
    SLICE_X103Y342       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_en_1_reg[0]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[11]/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/ctl_reg_reg[11]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.129ns  (logic 0.040ns (30.950%)  route 0.089ns (69.051%))
  Logic Levels:           0  
  Clock Path Skew:        0.167ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.567ns
    Source Clock Delay      (SCD):    2.400ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      0.964ns (routing 0.283ns, distribution 0.681ns)
  Clock Net Delay (Destination): 0.957ns (routing 0.388ns, distribution 0.569ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.954     1.419    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y81         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.436 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         0.964     2.400    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/m_bscan_tck[0]
    SLICE_X105Y347       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[11]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X105Y347       FDRE (Prop_CFF2_SLICEL_C_Q)
                                                      0.040     2.440 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[11]/Q
                         net (fo=2, routed)           0.089     2.529    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in[11]
    SLICE_X104Y347       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/ctl_reg_reg[11]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.940     1.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     1.432 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.159     1.591    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y115        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.610 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.957     2.567    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/clk
    SLICE_X104Y347       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/ctl_reg_reg[11]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  mmcm_clkout0
  To Clock:  mmcm_clkout5

Max Delay             0 Endpoints
Min Delay            10 Endpoints
--------------------------------------------------------------------------------------


Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[3].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.129ns  (logic 0.039ns (30.233%)  route 0.090ns (69.767%))
  Logic Levels:           0  
  Clock Path Skew:        -0.402ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.522ns
    Source Clock Delay      (SCD):    2.924ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.196ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      1.076ns (routing 0.384ns, distribution 0.692ns)
  Clock Net Delay (Destination): 0.912ns (routing 0.388ns, distribution 0.524ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.839     1.456    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.686 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.145     1.831    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.848 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.076     2.924    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/SYNC[0].sync_reg_reg[1]
    SLICE_X95Y356        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X95Y356        FDRE (Prop_HFF2_SLICEL_C_Q)
                                                      0.039     2.963 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[3]/Q
                         net (fo=1, routed)           0.090     3.053    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/out[3]
    SLICE_X94Y355        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[3].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.940     1.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     1.432 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.159     1.591    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y115        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.610 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.912     2.522    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/CLK
    SLICE_X94Y355        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[3].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[2].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.134ns  (logic 0.041ns (30.597%)  route 0.093ns (69.403%))
  Logic Levels:           0  
  Clock Path Skew:        -0.410ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.520ns
    Source Clock Delay      (SCD):    2.930ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.196ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      1.082ns (routing 0.384ns, distribution 0.698ns)
  Clock Net Delay (Destination): 0.910ns (routing 0.388ns, distribution 0.522ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.839     1.456    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.686 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.145     1.831    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.848 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.082     2.930    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/SYNC[0].sync_reg_reg[1]
    SLICE_X92Y351        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X92Y351        FDRE (Prop_DFF2_SLICEL_C_Q)
                                                      0.041     2.971 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[2]/Q
                         net (fo=1, routed)           0.093     3.064    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/out[2]
    SLICE_X94Y351        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[2].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.940     1.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     1.432 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.159     1.591    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y115        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.610 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.910     2.520    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/CLK
    SLICE_X94Y351        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[2].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[5]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[5].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.145ns  (logic 0.040ns (27.586%)  route 0.105ns (72.414%))
  Logic Levels:           0  
  Clock Path Skew:        -0.399ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.525ns
    Source Clock Delay      (SCD):    2.924ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.196ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      1.076ns (routing 0.384ns, distribution 0.692ns)
  Clock Net Delay (Destination): 0.915ns (routing 0.388ns, distribution 0.527ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.839     1.456    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.686 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.145     1.831    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.848 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.076     2.924    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/SYNC[0].sync_reg_reg[1]
    SLICE_X95Y356        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[5]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X95Y356        FDRE (Prop_GFF2_SLICEL_C_Q)
                                                      0.040     2.964 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[5]/Q
                         net (fo=1, routed)           0.105     3.069    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/out[5]
    SLICE_X94Y356        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[5].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.940     1.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     1.432 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.159     1.591    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y115        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.610 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.915     2.525    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/CLK
    SLICE_X94Y356        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[5].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_rdy_lvl_fclk_reg/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_rdy_sync/SYNC[0].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.149ns  (logic 0.040ns (26.903%)  route 0.109ns (73.097%))
  Logic Levels:           0  
  Clock Path Skew:        -0.396ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.525ns
    Source Clock Delay      (SCD):    2.921ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.196ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      1.073ns (routing 0.384ns, distribution 0.689ns)
  Clock Net Delay (Destination): 0.915ns (routing 0.388ns, distribution 0.527ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.839     1.456    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.686 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.145     1.831    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.848 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.073     2.921    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/SYNC[0].sync_reg_reg[1]
    SLICE_X95Y355        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_rdy_lvl_fclk_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X95Y355        FDRE (Prop_BFF2_SLICEL_C_Q)
                                                      0.040     2.961 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_rdy_lvl_fclk_reg/Q
                         net (fo=2, routed)           0.109     3.070    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_rdy_sync/D[0]
    SLICE_X94Y357        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_rdy_sync/SYNC[0].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.940     1.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     1.432 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.159     1.591    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y115        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.610 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.915     2.525    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_rdy_sync/CLK
    SLICE_X94Y357        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_rdy_sync/SYNC[0].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[7]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[7].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.159ns  (logic 0.040ns (25.157%)  route 0.119ns (74.843%))
  Logic Levels:           0  
  Clock Path Skew:        -0.400ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.522ns
    Source Clock Delay      (SCD):    2.922ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.196ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      1.074ns (routing 0.384ns, distribution 0.690ns)
  Clock Net Delay (Destination): 0.912ns (routing 0.388ns, distribution 0.524ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.839     1.456    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.686 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.145     1.831    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.848 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.074     2.922    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/SYNC[0].sync_reg_reg[1]
    SLICE_X93Y353        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[7]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X93Y353        FDRE (Prop_FFF2_SLICEM_C_Q)
                                                      0.040     2.962 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[7]/Q
                         net (fo=1, routed)           0.119     3.081    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/out[7]
    SLICE_X94Y355        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[7].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.940     1.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     1.432 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.159     1.591    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y115        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.610 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.912     2.522    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/CLK
    SLICE_X94Y355        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[7].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[6]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[6].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.176ns  (logic 0.039ns (22.159%)  route 0.137ns (77.841%))
  Logic Levels:           0  
  Clock Path Skew:        -0.392ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.530ns
    Source Clock Delay      (SCD):    2.922ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.196ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      1.074ns (routing 0.384ns, distribution 0.690ns)
  Clock Net Delay (Destination): 0.921ns (routing 0.388ns, distribution 0.533ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.839     1.456    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.686 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.145     1.831    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.848 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.074     2.922    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/SYNC[0].sync_reg_reg[1]
    SLICE_X93Y353        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[6]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X93Y353        FDRE (Prop_GFF2_SLICEM_C_Q)
                                                      0.039     2.961 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[6]/Q
                         net (fo=1, routed)           0.137     3.098    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/out[6]
    SLICE_X94Y354        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[6].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.940     1.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     1.432 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.159     1.591    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y115        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.610 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.921     2.530    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/CLK
    SLICE_X94Y354        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[6].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[1].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.184ns  (logic 0.039ns (21.196%)  route 0.145ns (78.804%))
  Logic Levels:           0  
  Clock Path Skew:        -0.401ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.521ns
    Source Clock Delay      (SCD):    2.922ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.196ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      1.074ns (routing 0.384ns, distribution 0.690ns)
  Clock Net Delay (Destination): 0.911ns (routing 0.388ns, distribution 0.523ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.839     1.456    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.686 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.145     1.831    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.848 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.074     2.922    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/SYNC[0].sync_reg_reg[1]
    SLICE_X93Y353        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X93Y353        FDRE (Prop_HFF2_SLICEM_C_Q)
                                                      0.039     2.961 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[1]/Q
                         net (fo=1, routed)           0.145     3.106    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/out[1]
    SLICE_X96Y355        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[1].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.940     1.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     1.432 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.159     1.591    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y115        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.610 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.911     2.521    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/CLK
    SLICE_X96Y355        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[1].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[4]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[4].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.194ns  (logic 0.040ns (20.619%)  route 0.154ns (79.381%))
  Logic Levels:           0  
  Clock Path Skew:        -0.412ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.516ns
    Source Clock Delay      (SCD):    2.928ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.196ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      1.080ns (routing 0.384ns, distribution 0.696ns)
  Clock Net Delay (Destination): 0.906ns (routing 0.388ns, distribution 0.518ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.839     1.456    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.686 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.145     1.831    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.848 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.080     2.928    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/SYNC[0].sync_reg_reg[1]
    SLICE_X91Y352        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X91Y352        FDRE (Prop_GFF2_SLICEL_C_Q)
                                                      0.040     2.968 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[4]/Q
                         net (fo=1, routed)           0.154     3.122    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/out[4]
    SLICE_X93Y354        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[4].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.940     1.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     1.432 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.159     1.591    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y115        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.610 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.906     2.516    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/CLK
    SLICE_X93Y354        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[4].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[0].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.261ns  (logic 0.039ns (14.943%)  route 0.222ns (85.058%))
  Logic Levels:           0  
  Clock Path Skew:        -0.406ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.522ns
    Source Clock Delay      (SCD):    2.928ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.196ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      1.080ns (routing 0.384ns, distribution 0.696ns)
  Clock Net Delay (Destination): 0.912ns (routing 0.388ns, distribution 0.524ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.839     1.456    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.686 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.145     1.831    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.848 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.080     2.928    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/SYNC[0].sync_reg_reg[1]
    SLICE_X91Y352        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X91Y352        FDRE (Prop_HFF2_SLICEL_C_Q)
                                                      0.039     2.967 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[0]/Q
                         net (fo=1, routed)           0.222     3.189    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/out[0]
    SLICE_X96Y355        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[0].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.940     1.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     1.432 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.159     1.591    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y115        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.610 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.912     2.522    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/CLK
    SLICE_X96Y355        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[0].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[8]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[8].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.337ns  (logic 0.040ns (11.869%)  route 0.297ns (88.131%))
  Logic Levels:           0  
  Clock Path Skew:        -0.407ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.521ns
    Source Clock Delay      (SCD):    2.928ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.196ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      1.080ns (routing 0.384ns, distribution 0.696ns)
  Clock Net Delay (Destination): 0.911ns (routing 0.388ns, distribution 0.523ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.839     1.456    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.686 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.145     1.831    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.848 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.080     2.928    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/SYNC[0].sync_reg_reg[1]
    SLICE_X91Y352        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[8]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X91Y352        FDRE (Prop_FFF2_SLICEL_C_Q)
                                                      0.040     2.968 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[8]/Q
                         net (fo=1, routed)           0.297     3.265    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/out[8]
    SLICE_X94Y352        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[8].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.940     1.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     1.432 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.159     1.591    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y115        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.610 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.911     2.521    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/CLK
    SLICE_X94Y352        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[8].sync_reg_reg[0]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  mmcm_clkout0
  To Clock:  mmcm_clkout6

Max Delay             0 Endpoints
Min Delay            35 Endpoints
--------------------------------------------------------------------------------------


Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[10]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[10].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.095ns  (logic 0.039ns (41.053%)  route 0.056ns (58.947%))
  Logic Levels:           0  
  Clock Path Skew:        -0.077ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.843ns
    Source Clock Delay      (SCD):    2.920ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.188ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      1.072ns (routing 0.384ns, distribution 0.688ns)
  Clock Net Delay (Destination): 1.216ns (routing 0.438ns, distribution 0.778ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.839     1.456    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.686 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.145     1.831    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.848 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.072     2.920    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/odt_shift_reg[0][17]
    SLICE_X91Y319        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[10]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X91Y319        FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.039     2.959 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[10]/Q
                         net (fo=1, routed)           0.056     3.015    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[31].sync_reg_reg[0]_0[10]
    SLICE_X91Y320        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[10].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.940     1.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.295     1.432 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.176     1.608    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y104        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.627 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.216     2.843    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/CLK
    SLICE_X91Y320        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[10].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[17]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[17].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.096ns  (logic 0.039ns (40.625%)  route 0.057ns (59.375%))
  Logic Levels:           0  
  Clock Path Skew:        -0.077ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.843ns
    Source Clock Delay      (SCD):    2.920ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.188ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      1.072ns (routing 0.384ns, distribution 0.688ns)
  Clock Net Delay (Destination): 1.216ns (routing 0.438ns, distribution 0.778ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.839     1.456    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.686 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.145     1.831    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.848 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.072     2.920    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/odt_shift_reg[0][17]
    SLICE_X91Y319        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[17]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X91Y319        FDRE (Prop_BFF_SLICEL_C_Q)
                                                      0.039     2.959 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[17]/Q
                         net (fo=1, routed)           0.057     3.016    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[31].sync_reg_reg[0]_0[17]
    SLICE_X91Y320        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[17].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.940     1.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.295     1.432 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.176     1.608    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y104        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.627 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.216     2.843    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/CLK
    SLICE_X91Y320        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[17].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[25]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[25].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.098ns  (logic 0.040ns (40.816%)  route 0.058ns (59.184%))
  Logic Levels:           0  
  Clock Path Skew:        -0.075ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.849ns
    Source Clock Delay      (SCD):    2.925ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.188ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      1.077ns (routing 0.384ns, distribution 0.693ns)
  Clock Net Delay (Destination): 1.222ns (routing 0.438ns, distribution 0.784ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.839     1.456    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.686 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.145     1.831    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.848 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.077     2.925    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/odt_shift_reg[0][17]
    SLICE_X91Y316        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[25]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X91Y316        FDRE (Prop_GFF2_SLICEL_C_Q)
                                                      0.040     2.965 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[25]/Q
                         net (fo=1, routed)           0.058     3.023    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[31].sync_reg_reg[0]_0[25]
    SLICE_X91Y317        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[25].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.940     1.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.295     1.432 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.176     1.608    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y104        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.627 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.222     2.849    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/CLK
    SLICE_X91Y317        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[25].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/rst_r1_reg/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_fab_rst_sync/SYNC[0].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.106ns  (logic 0.039ns (36.792%)  route 0.067ns (63.208%))
  Logic Levels:           0  
  Clock Path Skew:        -0.069ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.849ns
    Source Clock Delay      (SCD):    2.918ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.188ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      1.070ns (routing 0.384ns, distribution 0.686ns)
  Clock Net Delay (Destination): 1.222ns (routing 0.438ns, distribution 0.784ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.839     1.456    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.686 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.145     1.831    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.848 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.070     2.918    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/SYNC[19].sync_reg_reg[1]
    SLICE_X93Y341        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/rst_r1_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X93Y341        FDRE (Prop_HFF2_SLICEM_C_Q)
                                                      0.039     2.957 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/rst_r1_reg/Q
                         net (fo=1, routed)           0.067     3.024    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_fab_rst_sync/D[0]
    SLICE_X93Y340        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_fab_rst_sync/SYNC[0].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.940     1.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.295     1.432 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.176     1.608    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y104        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.627 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.222     2.849    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_fab_rst_sync/CLK
    SLICE_X93Y340        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_fab_rst_sync/SYNC[0].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[3].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.109ns  (logic 0.039ns (35.780%)  route 0.070ns (64.220%))
  Logic Levels:           0  
  Clock Path Skew:        -0.078ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.852ns
    Source Clock Delay      (SCD):    2.930ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.188ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      1.082ns (routing 0.384ns, distribution 0.698ns)
  Clock Net Delay (Destination): 1.225ns (routing 0.438ns, distribution 0.787ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.839     1.456    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.686 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.145     1.831    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.848 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.082     2.930    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/odt_shift_reg[0][17]
    SLICE_X94Y315        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X94Y315        FDRE (Prop_AFF2_SLICEM_C_Q)
                                                      0.039     2.969 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[3]/Q
                         net (fo=1, routed)           0.070     3.039    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[31].sync_reg_reg[0]_0[3]
    SLICE_X93Y315        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[3].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.940     1.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.295     1.432 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.176     1.608    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y104        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.627 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.225     2.852    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/CLK
    SLICE_X93Y315        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[3].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_ready_lvl_reg/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_ready_lvl_sync/SYNC[0].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.125ns  (logic 0.039ns (31.177%)  route 0.086ns (68.823%))
  Logic Levels:           0  
  Clock Path Skew:        -0.078ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.837ns
    Source Clock Delay      (SCD):    2.915ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.188ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      1.067ns (routing 0.384ns, distribution 0.683ns)
  Clock Net Delay (Destination): 1.210ns (routing 0.438ns, distribution 0.772ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.839     1.456    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.686 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.145     1.831    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.848 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.067     2.915    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/odt_shift_reg[0][17]
    SLICE_X89Y325        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_ready_lvl_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X89Y325        FDRE (Prop_DFF_SLICEM_C_Q)
                                                      0.039     2.954 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_ready_lvl_reg/Q
                         net (fo=2, routed)           0.086     3.040    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_ready_lvl_sync/D[0]
    SLICE_X89Y325        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_ready_lvl_sync/SYNC[0].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.940     1.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.295     1.432 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.176     1.608    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y104        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.627 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.210     2.837    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_ready_lvl_sync/CLK
    SLICE_X89Y325        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_ready_lvl_sync/SYNC[0].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[1].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.126ns  (logic 0.039ns (30.952%)  route 0.087ns (69.048%))
  Logic Levels:           0  
  Clock Path Skew:        -0.092ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.824ns
    Source Clock Delay      (SCD):    2.916ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.188ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      1.068ns (routing 0.384ns, distribution 0.684ns)
  Clock Net Delay (Destination): 1.197ns (routing 0.438ns, distribution 0.759ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.839     1.456    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.686 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.145     1.831    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.848 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.068     2.916    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/odt_shift_reg[0][17]
    SLICE_X91Y291        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X91Y291        FDRE (Prop_HFF2_SLICEL_C_Q)
                                                      0.039     2.955 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[1]/Q
                         net (fo=1, routed)           0.087     3.042    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[31].sync_reg_reg[0]_0[1]
    SLICE_X91Y295        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[1].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.940     1.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.295     1.432 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.176     1.608    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y104        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.627 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.197     2.824    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/CLK
    SLICE_X91Y295        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[1].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[21]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[21].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.115ns  (logic 0.039ns (33.913%)  route 0.076ns (66.087%))
  Logic Levels:           0  
  Clock Path Skew:        -0.078ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.852ns
    Source Clock Delay      (SCD):    2.930ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.188ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      1.082ns (routing 0.384ns, distribution 0.698ns)
  Clock Net Delay (Destination): 1.225ns (routing 0.438ns, distribution 0.787ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.839     1.456    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.686 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.145     1.831    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.848 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.082     2.930    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/odt_shift_reg[0][17]
    SLICE_X94Y315        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[21]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X94Y315        FDRE (Prop_CFF2_SLICEM_C_Q)
                                                      0.039     2.969 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[21]/Q
                         net (fo=1, routed)           0.076     3.045    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[31].sync_reg_reg[0]_0[21]
    SLICE_X93Y315        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[21].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.940     1.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.295     1.432 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.176     1.608    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y104        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.627 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.225     2.852    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/CLK
    SLICE_X93Y315        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[21].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[0].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.133ns  (logic 0.041ns (30.827%)  route 0.092ns (69.173%))
  Logic Levels:           0  
  Clock Path Skew:        -0.078ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.852ns
    Source Clock Delay      (SCD):    2.930ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.188ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      1.082ns (routing 0.384ns, distribution 0.698ns)
  Clock Net Delay (Destination): 1.225ns (routing 0.438ns, distribution 0.787ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.839     1.456    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.686 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.145     1.831    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.848 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.082     2.930    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/odt_shift_reg[0][17]
    SLICE_X94Y315        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X94Y315        FDRE (Prop_DFF2_SLICEM_C_Q)
                                                      0.041     2.971 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[0]/Q
                         net (fo=1, routed)           0.092     3.063    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[31].sync_reg_reg[0]_0[0]
    SLICE_X92Y315        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[0].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.940     1.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.295     1.432 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.176     1.608    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y104        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.627 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.225     2.852    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/CLK
    SLICE_X92Y315        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[0].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[14]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[14].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.153ns  (logic 0.040ns (26.144%)  route 0.113ns (73.856%))
  Logic Levels:           0  
  Clock Path Skew:        -0.072ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.848ns
    Source Clock Delay      (SCD):    2.920ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.188ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      1.072ns (routing 0.384ns, distribution 0.688ns)
  Clock Net Delay (Destination): 1.221ns (routing 0.438ns, distribution 0.783ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.839     1.456    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.686 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.145     1.831    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.848 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.072     2.920    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/odt_shift_reg[0][17]
    SLICE_X91Y319        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[14]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X91Y319        FDRE (Prop_AFF2_SLICEL_C_Q)
                                                      0.040     2.960 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[14]/Q
                         net (fo=1, routed)           0.113     3.073    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[31].sync_reg_reg[0]_0[14]
    SLICE_X89Y319        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[14].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.940     1.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.295     1.432 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.176     1.608    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y104        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.627 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.221     2.848    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/CLK
    SLICE_X89Y319        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[14].sync_reg_reg[0]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  mmcm_clkout6
  To Clock:  mmcm_clkout6

Max Delay             2 Endpoints
Min Delay           486 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/rst_0/U0/FDRE_inst/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Reset_DFF/Synchronize.use_sync_reset.sync_reg[1]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.333ns  (logic 0.076ns (22.823%)  route 0.257ns (77.177%))
  Logic Levels:           0  
  Clock Path Skew:        0.168ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.882ns
    Source Clock Delay      (SCD):    4.714ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.068ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.942ns (routing 0.708ns, distribution 1.234ns)
  Clock Net Delay (Destination): 1.723ns (routing 0.642ns, distribution 1.081ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.524     2.610    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.127     2.483 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.261     2.744    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y104        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.772 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.942     4.714    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/rst_0/U0/slowest_sync_clk
    SLICE_X93Y332        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/rst_0/U0/FDRE_inst/C
  -------------------------------------------------------------------    -------------------
    SLICE_X93Y332        FDRE (Prop_FFF_SLICEM_C_Q)
                                                      0.076     4.790 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/rst_0/U0/FDRE_inst/Q
                         net (fo=1, routed)           0.257     5.047    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Reset_DFF/Reset
    SLICE_X93Y332        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Reset_DFF/Synchronize.use_sync_reset.sync_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.364     2.279    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.630     2.909 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.226     3.135    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y104        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.159 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.723     4.882    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Reset_DFF/Clk
    SLICE_X93Y332        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Reset_DFF/Synchronize.use_sync_reset.sync_reg[1]/C

Slack:                    inf
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_mb_logic_r1_reg/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/rst_0/U0/EXT_LPF/ACTIVE_HIGH_EXT.ACT_HI_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.320ns  (logic 0.077ns (24.060%)  route 0.243ns (75.940%))
  Logic Levels:           0  
  Clock Path Skew:        0.174ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.887ns
    Source Clock Delay      (SCD):    4.713ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.068ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.941ns (routing 0.708ns, distribution 1.233ns)
  Clock Net Delay (Destination): 1.728ns (routing 0.642ns, distribution 1.086ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.524     2.610    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.127     2.483 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.261     2.744    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y104        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.772 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.941     4.713    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/c0_riu_clk
    SLICE_X93Y330        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_mb_logic_r1_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X93Y330        FDRE (Prop_AFF_SLICEM_C_Q)
                                                      0.077     4.790 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_mb_logic_r1_reg/Q
                         net (fo=5, routed)           0.243     5.033    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/rst_0/U0/EXT_LPF/ACTIVE_HIGH_EXT.ACT_HI_EXT/ext_reset_in
    SLICE_X93Y327        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/rst_0/U0/EXT_LPF/ACTIVE_HIGH_EXT.ACT_HI_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.364     2.279    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.630     2.909 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.226     3.135    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y104        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.159 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.728     4.887    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/rst_0/U0/EXT_LPF/ACTIVE_HIGH_EXT.ACT_HI_EXT/slowest_sync_clk
    SLICE_X93Y327        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/rst_0/U0/EXT_LPF/ACTIVE_HIGH_EXT.ACT_HI_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/rst_0/U0/FDRE_inst/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Reset_DFF/Synchronize.use_sync_reset.sync_reg[1]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.124ns  (logic 0.037ns (29.839%)  route 0.087ns (70.161%))
  Logic Levels:           0  
  Clock Path Skew:        -0.091ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.841ns
    Source Clock Delay      (SCD):    2.932ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.068ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.074ns (routing 0.391ns, distribution 0.683ns)
  Clock Net Delay (Destination): 1.214ns (routing 0.438ns, distribution 0.776ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.839     1.456    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.230     1.686 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.155     1.841    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y104        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.858 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.074     2.932    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/rst_0/U0/slowest_sync_clk
    SLICE_X93Y332        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/rst_0/U0/FDRE_inst/C
  -------------------------------------------------------------------    -------------------
    SLICE_X93Y332        FDRE (Prop_FFF_SLICEM_C_Q)
                                                      0.037     2.969 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/rst_0/U0/FDRE_inst/Q
                         net (fo=1, routed)           0.087     3.056    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Reset_DFF/Reset
    SLICE_X93Y332        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Reset_DFF/Synchronize.use_sync_reset.sync_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.940     1.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.295     1.432 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.176     1.608    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y104        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.627 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.214     2.841    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Reset_DFF/Clk
    SLICE_X93Y332        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Reset_DFF/Synchronize.use_sync_reset.sync_reg[1]/C

Slack:                    inf
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_mb_logic_r1_reg/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/rst_0/U0/EXT_LPF/ACTIVE_HIGH_EXT.ACT_HI_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.142ns  (logic 0.038ns (26.820%)  route 0.104ns (73.180%))
  Logic Levels:           0  
  Clock Path Skew:        -0.085ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.846ns
    Source Clock Delay      (SCD):    2.931ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.068ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.073ns (routing 0.391ns, distribution 0.682ns)
  Clock Net Delay (Destination): 1.219ns (routing 0.438ns, distribution 0.781ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.839     1.456    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.230     1.686 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.155     1.841    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y104        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.858 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.073     2.931    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/c0_riu_clk
    SLICE_X93Y330        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_mb_logic_r1_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X93Y330        FDRE (Prop_AFF_SLICEM_C_Q)
                                                      0.038     2.969 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_mb_logic_r1_reg/Q
                         net (fo=5, routed)           0.104     3.072    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/rst_0/U0/EXT_LPF/ACTIVE_HIGH_EXT.ACT_HI_EXT/ext_reset_in
    SLICE_X93Y327        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/rst_0/U0/EXT_LPF/ACTIVE_HIGH_EXT.ACT_HI_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.940     1.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.295     1.432 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.176     1.608    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y104        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.627 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.219     2.846    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/rst_0/U0/EXT_LPF/ACTIVE_HIGH_EXT.ACT_HI_EXT/slowest_sync_clk
    SLICE_X93Y327        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/rst_0/U0/EXT_LPF/ACTIVE_HIGH_EXT.ACT_HI_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/C

Slack:                    inf
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2riu_wr_data_reg[4]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_WR_DATA[4]
                            (rising edge-triggered cell BITSLICE_CONTROL clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.326ns  (logic 0.039ns (11.976%)  route 0.287ns (88.024%))
  Logic Levels:           0  
  Clock Path Skew:        -0.028ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.912ns
    Source Clock Delay      (SCD):    2.940ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.068ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.082ns (routing 0.391ns, distribution 0.691ns)
  Clock Net Delay (Destination): 1.285ns (routing 0.438ns, distribution 0.847ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.839     1.456    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.230     1.686 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.155     1.841    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y104        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.858 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.082     2.940    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_clk
    SLICE_X81Y320        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2riu_wr_data_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y320        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.039     2.979 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2riu_wr_data_reg[4]/Q
                         net (fo=22, routed)          0.287     3.265    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control_1[4]
    BITSLICE_CONTROL_X0Y42
                         BITSLICE_CONTROL                             r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_WR_DATA[4]
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.940     1.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.295     1.432 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.176     1.608    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y104        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.627 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.285     2.912    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/riu_clk
    BITSLICE_CONTROL_X0Y42
                         BITSLICE_CONTROL                             r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK

Slack:                    inf
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2riu_wr_data_reg[4]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_WR_DATA[4]
                            (rising edge-triggered cell BITSLICE_CONTROL clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.327ns  (logic 0.039ns (11.940%)  route 0.288ns (88.060%))
  Logic Levels:           0  
  Clock Path Skew:        -0.028ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.912ns
    Source Clock Delay      (SCD):    2.940ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.068ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.082ns (routing 0.391ns, distribution 0.691ns)
  Clock Net Delay (Destination): 1.285ns (routing 0.438ns, distribution 0.847ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.839     1.456    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.230     1.686 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.155     1.841    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y104        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.858 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.082     2.940    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_clk
    SLICE_X81Y320        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2riu_wr_data_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y320        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.039     2.979 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2riu_wr_data_reg[4]/Q
                         net (fo=22, routed)          0.288     3.266    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control_3[4]
    BITSLICE_CONTROL_X0Y43
                         BITSLICE_CONTROL                             r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_WR_DATA[4]
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.940     1.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.295     1.432 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.176     1.608    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y104        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.627 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.285     2.912    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/riu_clk
    BITSLICE_CONTROL_X0Y43
                         BITSLICE_CONTROL                             r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK

Slack:                    inf
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2riu_wr_data_reg[12]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_WR_DATA[12]
                            (rising edge-triggered cell BITSLICE_CONTROL clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.332ns  (logic 0.040ns (12.052%)  route 0.292ns (87.948%))
  Logic Levels:           0  
  Clock Path Skew:        -0.023ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.912ns
    Source Clock Delay      (SCD):    2.935ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.068ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.077ns (routing 0.391ns, distribution 0.686ns)
  Clock Net Delay (Destination): 1.285ns (routing 0.438ns, distribution 0.847ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.839     1.456    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.230     1.686 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.155     1.841    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y104        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.858 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.077     2.935    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_clk
    SLICE_X81Y327        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2riu_wr_data_reg[12]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y327        FDRE (Prop_EFF2_SLICEL_C_Q)
                                                      0.040     2.975 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2riu_wr_data_reg[12]/Q
                         net (fo=22, routed)          0.292     3.266    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control_1[12]
    BITSLICE_CONTROL_X0Y42
                         BITSLICE_CONTROL                             r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_WR_DATA[12]
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.940     1.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.295     1.432 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.176     1.608    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y104        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.627 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.285     2.912    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/riu_clk
    BITSLICE_CONTROL_X0Y42
                         BITSLICE_CONTROL                             r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK

Slack:                    inf
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2riu_wr_data_reg[12]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_WR_DATA[12]
                            (rising edge-triggered cell BITSLICE_CONTROL clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.332ns  (logic 0.040ns (12.052%)  route 0.292ns (87.948%))
  Logic Levels:           0  
  Clock Path Skew:        -0.023ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.912ns
    Source Clock Delay      (SCD):    2.935ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.068ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.077ns (routing 0.391ns, distribution 0.686ns)
  Clock Net Delay (Destination): 1.285ns (routing 0.438ns, distribution 0.847ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.839     1.456    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.230     1.686 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.155     1.841    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y104        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.858 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.077     2.935    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_clk
    SLICE_X81Y327        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2riu_wr_data_reg[12]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y327        FDRE (Prop_EFF2_SLICEL_C_Q)
                                                      0.040     2.975 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2riu_wr_data_reg[12]/Q
                         net (fo=22, routed)          0.292     3.266    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control_3[12]
    BITSLICE_CONTROL_X0Y43
                         BITSLICE_CONTROL                             r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_WR_DATA[12]
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.940     1.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.295     1.432 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.176     1.608    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y104        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.627 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.285     2.912    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/riu_clk
    BITSLICE_CONTROL_X0Y43
                         BITSLICE_CONTROL                             r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK

Slack:                    inf
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2riu_wr_data_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_WR_DATA[2]
                            (rising edge-triggered cell BITSLICE_CONTROL clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.345ns  (logic 0.039ns (11.311%)  route 0.306ns (88.689%))
  Logic Levels:           0  
  Clock Path Skew:        -0.023ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.912ns
    Source Clock Delay      (SCD):    2.935ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.068ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.077ns (routing 0.391ns, distribution 0.686ns)
  Clock Net Delay (Destination): 1.285ns (routing 0.438ns, distribution 0.847ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.839     1.456    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.230     1.686 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.155     1.841    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y104        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.858 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.077     2.935    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_clk
    SLICE_X81Y327        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2riu_wr_data_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y327        FDRE (Prop_HFF_SLICEL_C_Q)
                                                      0.039     2.974 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2riu_wr_data_reg[2]/Q
                         net (fo=22, routed)          0.306     3.279    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control_1[2]
    BITSLICE_CONTROL_X0Y42
                         BITSLICE_CONTROL                             r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_WR_DATA[2]
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.940     1.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.295     1.432 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.176     1.608    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y104        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.627 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.285     2.912    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/riu_clk
    BITSLICE_CONTROL_X0Y42
                         BITSLICE_CONTROL                             r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK

Slack:                    inf
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2riu_wr_data_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_WR_DATA[2]
                            (rising edge-triggered cell BITSLICE_CONTROL clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.345ns  (logic 0.039ns (11.311%)  route 0.306ns (88.689%))
  Logic Levels:           0  
  Clock Path Skew:        -0.023ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.912ns
    Source Clock Delay      (SCD):    2.935ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.068ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.077ns (routing 0.391ns, distribution 0.686ns)
  Clock Net Delay (Destination): 1.285ns (routing 0.438ns, distribution 0.847ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.839     1.456    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.230     1.686 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.155     1.841    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y104        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.858 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.077     2.935    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_clk
    SLICE_X81Y327        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2riu_wr_data_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y327        FDRE (Prop_HFF_SLICEL_C_Q)
                                                      0.039     2.974 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2riu_wr_data_reg[2]/Q
                         net (fo=22, routed)          0.306     3.279    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control_3[2]
    BITSLICE_CONTROL_X0Y43
                         BITSLICE_CONTROL                             r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_WR_DATA[2]
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.940     1.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.295     1.432 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.176     1.608    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y104        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.627 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.285     2.912    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/riu_clk
    BITSLICE_CONTROL_X0Y43
                         BITSLICE_CONTROL                             r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK

Slack:                    inf
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2riu_wr_data_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_WR_DATA[3]
                            (rising edge-triggered cell BITSLICE_CONTROL clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.374ns  (logic 0.038ns (10.150%)  route 0.336ns (89.849%))
  Logic Levels:           0  
  Clock Path Skew:        -0.026ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.904ns
    Source Clock Delay      (SCD):    2.930ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.068ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.072ns (routing 0.391ns, distribution 0.681ns)
  Clock Net Delay (Destination): 1.277ns (routing 0.438ns, distribution 0.839ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.839     1.456    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.230     1.686 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.155     1.841    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y104        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.858 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.072     2.930    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_clk
    SLICE_X82Y337        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2riu_wr_data_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X82Y337        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.038     2.968 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2riu_wr_data_reg[3]/Q
                         net (fo=22, routed)          0.336     3.304    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control_1[3]
    BITSLICE_CONTROL_X0Y44
                         BITSLICE_CONTROL                             r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_WR_DATA[3]
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.940     1.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.295     1.432 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.176     1.608    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y104        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.627 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.277     2.904    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/riu_clk
    BITSLICE_CONTROL_X0Y44
                         BITSLICE_CONTROL                             r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK

Slack:                    inf
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2riu_wr_data_reg[7]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_WR_DATA[7]
                            (rising edge-triggered cell BITSLICE_CONTROL clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.369ns  (logic 0.040ns (10.854%)  route 0.329ns (89.146%))
  Logic Levels:           0  
  Clock Path Skew:        -0.025ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.912ns
    Source Clock Delay      (SCD):    2.937ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.068ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.079ns (routing 0.391ns, distribution 0.688ns)
  Clock Net Delay (Destination): 1.285ns (routing 0.438ns, distribution 0.847ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.839     1.456    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.230     1.686 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.155     1.841    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y104        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.858 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.079     2.937    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_clk
    SLICE_X81Y320        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2riu_wr_data_reg[7]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y320        FDRE (Prop_AFF2_SLICEL_C_Q)
                                                      0.040     2.977 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2riu_wr_data_reg[7]/Q
                         net (fo=22, routed)          0.329     3.305    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control_1[7]
    BITSLICE_CONTROL_X0Y42
                         BITSLICE_CONTROL                             r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_WR_DATA[7]
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.940     1.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.295     1.432 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.176     1.608    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y104        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.627 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.285     2.912    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/riu_clk
    BITSLICE_CONTROL_X0Y42
                         BITSLICE_CONTROL                             r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  sys_clk_ddr4_clk_p
  To Clock:  mmcm_clkout6

Max Delay             2 Endpoints
Min Delay             2 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_async_riu_div_reg/C
                            (rising edge-triggered cell FDRE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_riu_sync_r_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.384ns  (logic 0.081ns (21.092%)  route 0.303ns (78.908%))
  Logic Levels:           0  
  Clock Path Skew:        2.072ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.900ns
    Source Clock Delay      (SCD):    2.828ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.167ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.742ns (routing 0.700ns, distribution 1.042ns)
  Clock Net Delay (Destination): 1.741ns (routing 0.642ns, distribution 1.099ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y4 (CLOCK_ROOT)    net (fo=18, routed)          1.742     2.828    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X91Y355        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_async_riu_div_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X91Y355        FDRE (Prop_AFF2_SLICEL_C_Q)
                                                      0.081     2.909 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_async_riu_div_reg/Q
                         net (fo=2, routed)           0.303     3.212    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_async_riu_div
    SLICE_X92Y357        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_riu_sync_r_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.364     2.279    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.630     2.909 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.226     3.135    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y104        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.159 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.741     4.900    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/c0_riu_clk
    SLICE_X92Y357        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_riu_sync_r_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_async_mb_reg/C
                            (rising edge-triggered cell FDRE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_mb_sync_r_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.282ns  (logic 0.081ns (28.723%)  route 0.201ns (71.277%))
  Logic Levels:           0  
  Clock Path Skew:        2.063ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.886ns
    Source Clock Delay      (SCD):    2.823ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.167ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.737ns (routing 0.700ns, distribution 1.037ns)
  Clock Net Delay (Destination): 1.727ns (routing 0.642ns, distribution 1.085ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y4 (CLOCK_ROOT)    net (fo=18, routed)          1.737     2.823    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X92Y341        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_async_mb_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X92Y341        FDRE (Prop_AFF2_SLICEL_C_Q)
                                                      0.081     2.904 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_async_mb_reg/Q
                         net (fo=1, routed)           0.201     3.105    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_async_mb
    SLICE_X92Y342        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_mb_sync_r_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.364     2.279    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.630     2.909 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.226     3.135    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y104        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.159 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.727     4.886    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/c0_riu_clk
    SLICE_X92Y342        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_mb_sync_r_reg[0]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_async_mb_reg/C
                            (rising edge-triggered cell FDRE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_mb_sync_r_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.119ns  (logic 0.040ns (33.613%)  route 0.079ns (66.387%))
  Logic Levels:           0  
  Clock Path Skew:        1.263ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.840ns
    Source Clock Delay      (SCD):    1.577ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.167ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      0.960ns (routing 0.387ns, distribution 0.573ns)
  Clock Net Delay (Destination): 1.213ns (routing 0.438ns, distribution 0.775ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y4 (CLOCK_ROOT)    net (fo=18, routed)          0.960     1.577    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X92Y341        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_async_mb_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X92Y341        FDRE (Prop_AFF2_SLICEL_C_Q)
                                                      0.040     1.617 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_async_mb_reg/Q
                         net (fo=1, routed)           0.079     1.696    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_async_mb
    SLICE_X92Y342        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_mb_sync_r_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.940     1.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.295     1.432 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.176     1.608    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y104        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.627 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.213     2.840    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/c0_riu_clk
    SLICE_X92Y342        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_mb_sync_r_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_async_riu_div_reg/C
                            (rising edge-triggered cell FDRE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_riu_sync_r_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.172ns  (logic 0.040ns (23.299%)  route 0.132ns (76.701%))
  Logic Levels:           0  
  Clock Path Skew:        1.271ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.852ns
    Source Clock Delay      (SCD):    1.581ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.167ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      0.964ns (routing 0.387ns, distribution 0.577ns)
  Clock Net Delay (Destination): 1.225ns (routing 0.438ns, distribution 0.787ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y4 (CLOCK_ROOT)    net (fo=18, routed)          0.964     1.581    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X91Y355        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_async_riu_div_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X91Y355        FDRE (Prop_AFF2_SLICEL_C_Q)
                                                      0.040     1.621 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_async_riu_div_reg/Q
                         net (fo=2, routed)           0.132     1.753    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_async_riu_div
    SLICE_X92Y357        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_riu_sync_r_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.940     1.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.295     1.432 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.176     1.608    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y104        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.627 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.225     2.852    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/c0_riu_clk
    SLICE_X92Y357        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_riu_sync_r_reg[0]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  clk_pl_0
  To Clock:  sys_clk_ddr4_clk_p

Max Delay             2 Endpoints
Min Delay             2 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/rst_100/U0/BSR_OUT_DFF[0].FDRE_BSR/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_input_async_reg[0]/PRE
                            (recovery check against rising-edge clock sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Path Group:             (none)
  Path Type:              Recovery (Max at Slow Process Corner)
  Data Path Delay:        1.416ns  (logic 0.079ns (5.579%)  route 1.337ns (94.421%))
  Logic Levels:           0  
  Clock Path Skew:        -0.177ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.454ns
    Source Clock Delay      (SCD):    2.631ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.405ns (routing 0.662ns, distribution 1.743ns)
  Clock Net Delay (Destination): 1.539ns (routing 0.635ns, distribution 0.904ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       2.405     2.631    d_1_i/rst_100/U0/slowest_sync_clk
    SLICE_X104Y71        FDRE                                         r  d_1_i/rst_100/U0/BSR_OUT_DFF[0].FDRE_BSR/C
  -------------------------------------------------------------------    -------------------
    SLICE_X104Y71        FDRE (Prop_EFF2_SLICEM_C_Q)
                                                      0.079     2.710 f  d_1_i/rst_100/U0/BSR_OUT_DFF[0].FDRE_BSR/Q
                         net (fo=2, routed)           1.337     4.047    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/sys_rst
    SLICE_X96Y180        FDPE                                         f  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_input_async_reg[0]/PRE
  -------------------------------------------------------------------    -------------------

                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y4 (CLOCK_ROOT)    net (fo=18, routed)          1.539     2.454    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X96Y180        FDPE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_input_async_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/rst_100/U0/BSR_OUT_DFF[0].FDRE_BSR/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_input_async_reg[1]/PRE
                            (recovery check against rising-edge clock sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Path Group:             (none)
  Path Type:              Recovery (Max at Slow Process Corner)
  Data Path Delay:        1.416ns  (logic 0.079ns (5.579%)  route 1.337ns (94.421%))
  Logic Levels:           0  
  Clock Path Skew:        -0.177ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.454ns
    Source Clock Delay      (SCD):    2.631ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.405ns (routing 0.662ns, distribution 1.743ns)
  Clock Net Delay (Destination): 1.539ns (routing 0.635ns, distribution 0.904ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       2.405     2.631    d_1_i/rst_100/U0/slowest_sync_clk
    SLICE_X104Y71        FDRE                                         r  d_1_i/rst_100/U0/BSR_OUT_DFF[0].FDRE_BSR/C
  -------------------------------------------------------------------    -------------------
    SLICE_X104Y71        FDRE (Prop_EFF2_SLICEM_C_Q)
                                                      0.079     2.710 f  d_1_i/rst_100/U0/BSR_OUT_DFF[0].FDRE_BSR/Q
                         net (fo=2, routed)           1.337     4.047    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/sys_rst
    SLICE_X96Y180        FDPE                                         f  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_input_async_reg[1]/PRE
  -------------------------------------------------------------------    -------------------

                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y4 (CLOCK_ROOT)    net (fo=18, routed)          1.539     2.454    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X96Y180        FDPE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_input_async_reg[1]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/rst_100/U0/BSR_OUT_DFF[0].FDRE_BSR/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_input_async_reg[0]/PRE
                            (removal check against rising-edge clock sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Path Group:             (none)
  Path Type:              Removal (Min at Fast Process Corner)
  Data Path Delay:        0.716ns  (logic 0.039ns (5.447%)  route 0.677ns (94.553%))
  Logic Levels:           0  
  Clock Path Skew:        0.444ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.885ns
    Source Clock Delay      (SCD):    1.441ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.321ns (routing 0.359ns, distribution 0.962ns)
  Clock Net Delay (Destination): 1.098ns (routing 0.434ns, distribution 0.664ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.321     1.441    d_1_i/rst_100/U0/slowest_sync_clk
    SLICE_X104Y71        FDRE                                         r  d_1_i/rst_100/U0/BSR_OUT_DFF[0].FDRE_BSR/C
  -------------------------------------------------------------------    -------------------
    SLICE_X104Y71        FDRE (Prop_EFF2_SLICEM_C_Q)
                                                      0.039     1.480 f  d_1_i/rst_100/U0/BSR_OUT_DFF[0].FDRE_BSR/Q
                         net (fo=2, routed)           0.677     2.157    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/sys_rst
    SLICE_X96Y180        FDPE                                         f  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_input_async_reg[0]/PRE
  -------------------------------------------------------------------    -------------------

                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y4 (CLOCK_ROOT)    net (fo=18, routed)          1.098     1.885    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X96Y180        FDPE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_input_async_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/rst_100/U0/BSR_OUT_DFF[0].FDRE_BSR/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_input_async_reg[1]/PRE
                            (removal check against rising-edge clock sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Path Group:             (none)
  Path Type:              Removal (Min at Fast Process Corner)
  Data Path Delay:        0.716ns  (logic 0.039ns (5.447%)  route 0.677ns (94.553%))
  Logic Levels:           0  
  Clock Path Skew:        0.444ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.885ns
    Source Clock Delay      (SCD):    1.441ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.321ns (routing 0.359ns, distribution 0.962ns)
  Clock Net Delay (Destination): 1.098ns (routing 0.434ns, distribution 0.664ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.321     1.441    d_1_i/rst_100/U0/slowest_sync_clk
    SLICE_X104Y71        FDRE                                         r  d_1_i/rst_100/U0/BSR_OUT_DFF[0].FDRE_BSR/C
  -------------------------------------------------------------------    -------------------
    SLICE_X104Y71        FDRE (Prop_EFF2_SLICEM_C_Q)
                                                      0.039     1.480 f  d_1_i/rst_100/U0/BSR_OUT_DFF[0].FDRE_BSR/Q
                         net (fo=2, routed)           0.677     2.157    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/sys_rst
    SLICE_X96Y180        FDPE                                         f  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_input_async_reg[1]/PRE
  -------------------------------------------------------------------    -------------------

                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y4 (CLOCK_ROOT)    net (fo=18, routed)          1.098     1.885    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X96Y180        FDPE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_input_async_reg[1]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  clk_pl_0
  To Clock:  

Max Delay            28 Endpoints
Min Delay            28 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/attn_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/LOGIC_FOR_MD_0_GEN.SPI_MODULE_I/OTHER_RATIO_GENERATE.Serial_Dout_reg/C
                            (rising edge-triggered cell FDSE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            ATTN_SI
                            (output port)
  Path Group:             (none)
  Path Type:              Max at Slow Process Corner
  Data Path Delay:        5.956ns  (logic 2.465ns (41.379%)  route 3.492ns (58.621%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.221ns (routing 0.662ns, distribution 1.559ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       2.221     2.447    d_1_i/attn_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/LOGIC_FOR_MD_0_GEN.SPI_MODULE_I/ext_spi_clk
    SLICE_X71Y44         FDSE                                         r  d_1_i/attn_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/LOGIC_FOR_MD_0_GEN.SPI_MODULE_I/OTHER_RATIO_GENERATE.Serial_Dout_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X71Y44         FDSE (Prop_BFF_SLICEL_C_Q)
                                                      0.079     2.526 r  d_1_i/attn_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/LOGIC_FOR_MD_0_GEN.SPI_MODULE_I/OTHER_RATIO_GENERATE.Serial_Dout_reg/Q
                         net (fo=3, routed)           3.492     6.017    ATTN_SI_OBUF
    A10                  OBUF (Prop_OUTBUF_HDIOB_M_I_O)
                                                      2.386     8.403 r  ATTN_SI_OBUF_inst/O
                         net (fo=0)                   0.000     8.403    ATTN_SI
    A10                                                               r  ATTN_SI (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/attn_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/LOGIC_FOR_MD_0_GEN.SPI_MODULE_I/SS_O_reg[0]/C
                            (rising edge-triggered cell FDSE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            ATTN_LE[0]
                            (output port)
  Path Group:             (none)
  Path Type:              Max at Slow Process Corner
  Data Path Delay:        5.519ns  (logic 2.484ns (45.007%)  route 3.035ns (54.993%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.233ns (routing 0.662ns, distribution 1.571ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       2.233     2.459    d_1_i/attn_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/LOGIC_FOR_MD_0_GEN.SPI_MODULE_I/ext_spi_clk
    SLICE_X73Y49         FDSE                                         r  d_1_i/attn_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/LOGIC_FOR_MD_0_GEN.SPI_MODULE_I/SS_O_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X73Y49         FDSE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     2.538 r  d_1_i/attn_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/LOGIC_FOR_MD_0_GEN.SPI_MODULE_I/SS_O_reg[0]/Q
                         net (fo=1, routed)           3.035     5.573    ATTN_LE_OBUF[0]
    A6                   OBUF (Prop_OUTBUF_HDIOB_S_I_O)
                                                      2.405     7.978 r  ATTN_LE_OBUF[0]_inst/O
                         net (fo=0)                   0.000     7.978    ATTN_LE[0]
    A6                                                                r  ATTN_LE[0] (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/attn_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/LOGIC_FOR_MD_0_GEN.SPI_MODULE_I/SS_O_reg[1]/C
                            (rising edge-triggered cell FDSE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            ATTN_LE[1]
                            (output port)
  Path Group:             (none)
  Path Type:              Max at Slow Process Corner
  Data Path Delay:        5.368ns  (logic 2.474ns (46.089%)  route 2.894ns (53.911%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.233ns (routing 0.662ns, distribution 1.571ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       2.233     2.459    d_1_i/attn_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/LOGIC_FOR_MD_0_GEN.SPI_MODULE_I/ext_spi_clk
    SLICE_X73Y49         FDSE                                         r  d_1_i/attn_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/LOGIC_FOR_MD_0_GEN.SPI_MODULE_I/SS_O_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X73Y49         FDSE (Prop_EFF2_SLICEL_C_Q)
                                                      0.081     2.540 r  d_1_i/attn_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/LOGIC_FOR_MD_0_GEN.SPI_MODULE_I/SS_O_reg[1]/Q
                         net (fo=1, routed)           2.894     5.434    ATTN_LE_OBUF[1]
    A7                   OBUF (Prop_OUTBUF_HDIOB_M_I_O)
                                                      2.393     7.827 r  ATTN_LE_OBUF[1]_inst/O
                         net (fo=0)                   0.000     7.827    ATTN_LE[1]
    A7                                                                r  ATTN_LE[1] (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                            (clock source 'clk_pl_0'  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/PLL_MONCLK
  Path Group:             (none)
  Path Type:              Max at Slow Process Corner
  Data Path Delay:        2.743ns  (logic 0.028ns (1.021%)  route 2.715ns (98.979%))
  Logic Levels:           1  (BUFG_PS=1)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 fall edge)
                                                      5.000     5.000 f  
    PS8_X0Y0             PS8                          0.000     5.000 f  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     5.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     5.226 f  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=48236, routed)       2.517     7.743    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/s_axi_aclk
    HSDAC_X0Y1           HSDAC                                        f  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/PLL_MONCLK
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                            (clock source 'clk_pl_0'  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/PLL_MONCLK
  Path Group:             (none)
  Path Type:              Max at Slow Process Corner
  Data Path Delay:        2.722ns  (logic 0.028ns (1.029%)  route 2.694ns (98.971%))
  Logic Levels:           1  (BUFG_PS=1)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 fall edge)
                                                      5.000     5.000 f  
    PS8_X0Y0             PS8                          0.000     5.000 f  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     5.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     5.226 f  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=48236, routed)       2.496     7.722    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/s_axi_aclk
    HSADC_X0Y0           HSADC                                        f  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/PLL_MONCLK
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                            (clock source 'clk_pl_0'  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/PLL_MONCLK
  Path Group:             (none)
  Path Type:              Max at Slow Process Corner
  Data Path Delay:        2.722ns  (logic 0.028ns (1.029%)  route 2.694ns (98.971%))
  Logic Levels:           1  (BUFG_PS=1)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 fall edge)
                                                      5.000     5.000 f  
    PS8_X0Y0             PS8                          0.000     5.000 f  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     5.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     5.226 f  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=48236, routed)       2.496     7.722    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/s_axi_aclk
    HSDAC_X0Y0           HSDAC                                        f  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/PLL_MONCLK
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                            (clock source 'clk_pl_0'  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/PLL_MONCLK
  Path Group:             (none)
  Path Type:              Max at Slow Process Corner
  Data Path Delay:        2.712ns  (logic 0.028ns (1.033%)  route 2.684ns (98.967%))
  Logic Levels:           1  (BUFG_PS=1)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 fall edge)
                                                      5.000     5.000 f  
    PS8_X0Y0             PS8                          0.000     5.000 f  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     5.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     5.226 f  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=48236, routed)       2.486     7.712    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/s_axi_aclk
    HSADC_X0Y2           HSADC                                        f  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/PLL_MONCLK
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                            (clock source 'clk_pl_0'  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/PLL_MONCLK
  Path Group:             (none)
  Path Type:              Max at Slow Process Corner
  Data Path Delay:        2.708ns  (logic 0.028ns (1.034%)  route 2.680ns (98.966%))
  Logic Levels:           1  (BUFG_PS=1)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 fall edge)
                                                      5.000     5.000 f  
    PS8_X0Y0             PS8                          0.000     5.000 f  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     5.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     5.226 f  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=48236, routed)       2.482     7.708    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/s_axi_aclk
    HSADC_X0Y1           HSADC                                        f  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/PLL_MONCLK
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/lo_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/LOGIC_FOR_MD_0_GEN.SPI_MODULE_I/SS_O_reg[1]_lopt_replica/C
                            (rising edge-triggered cell FDSE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            LO_CS1
                            (output port)
  Path Group:             (none)
  Path Type:              Max at Slow Process Corner
  Data Path Delay:        5.137ns  (logic 2.489ns (48.448%)  route 2.648ns (51.552%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.317ns (routing 0.662ns, distribution 1.655ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       2.317     2.543    d_1_i/lo_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/LOGIC_FOR_MD_0_GEN.SPI_MODULE_I/ext_spi_clk
    SLICE_X81Y49         FDSE                                         r  d_1_i/lo_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/LOGIC_FOR_MD_0_GEN.SPI_MODULE_I/SS_O_reg[1]_lopt_replica/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y49         FDSE (Prop_FFF2_SLICEL_C_Q)
                                                      0.081     2.624 r  d_1_i/lo_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/LOGIC_FOR_MD_0_GEN.SPI_MODULE_I/SS_O_reg[1]_lopt_replica/Q
                         net (fo=1, routed)           2.648     5.272    lopt_1
    C8                   OBUF (Prop_OUTBUF_HDIOB_M_I_O)
                                                      2.408     7.680 r  LO_CS1_OBUF_inst/O
                         net (fo=0)                   0.000     7.680    LO_CS1
    C8                                                                r  LO_CS1 (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                            (clock source 'clk_pl_0'  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/PLL_MONCLK
  Path Group:             (none)
  Path Type:              Max at Slow Process Corner
  Data Path Delay:        2.657ns  (logic 0.028ns (1.054%)  route 2.629ns (98.946%))
  Logic Levels:           1  (BUFG_PS=1)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 fall edge)
                                                      5.000     5.000 f  
    PS8_X0Y0             PS8                          0.000     5.000 f  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     5.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     5.226 f  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=48236, routed)       2.431     7.657    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/s_axi_aclk
    HSADC_X0Y3           HSADC                                        f  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/PLL_MONCLK
  -------------------------------------------------------------------    -------------------





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                            (clock source 'clk_pl_0'  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/PLL_MONCLK
  Path Group:             (none)
  Path Type:              Min at Fast Process Corner
  Data Path Delay:        1.436ns  (logic 0.017ns (1.184%)  route 1.419ns (98.816%))
  Logic Levels:           1  (BUFG_PS=1)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=48236, routed)       1.316     1.436    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/s_axi_aclk
    HSADC_X0Y3           HSADC                                        r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/PLL_MONCLK
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                            (clock source 'clk_pl_0'  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/PLL_MONCLK
  Path Group:             (none)
  Path Type:              Min at Fast Process Corner
  Data Path Delay:        1.455ns  (logic 0.017ns (1.168%)  route 1.438ns (98.832%))
  Logic Levels:           1  (BUFG_PS=1)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=48236, routed)       1.335     1.455    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/s_axi_aclk
    HSADC_X0Y2           HSADC                                        r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/PLL_MONCLK
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                            (clock source 'clk_pl_0'  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/PLL_MONCLK
  Path Group:             (none)
  Path Type:              Min at Fast Process Corner
  Data Path Delay:        1.462ns  (logic 0.017ns (1.163%)  route 1.445ns (98.837%))
  Logic Levels:           1  (BUFG_PS=1)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=48236, routed)       1.342     1.462    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/s_axi_aclk
    HSDAC_X0Y0           HSDAC                                        r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/PLL_MONCLK
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                            (clock source 'clk_pl_0'  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/PLL_MONCLK
  Path Group:             (none)
  Path Type:              Min at Fast Process Corner
  Data Path Delay:        1.465ns  (logic 0.017ns (1.161%)  route 1.448ns (98.839%))
  Logic Levels:           1  (BUFG_PS=1)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=48236, routed)       1.345     1.465    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/s_axi_aclk
    HSADC_X0Y1           HSADC                                        r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/PLL_MONCLK
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                            (clock source 'clk_pl_0'  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/PLL_MONCLK
  Path Group:             (none)
  Path Type:              Min at Fast Process Corner
  Data Path Delay:        1.475ns  (logic 0.017ns (1.153%)  route 1.458ns (98.847%))
  Logic Levels:           1  (BUFG_PS=1)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=48236, routed)       1.355     1.475    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/s_axi_aclk
    HSDAC_X0Y1           HSDAC                                        r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/PLL_MONCLK
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                            (clock source 'clk_pl_0'  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/PLL_MONCLK
  Path Group:             (none)
  Path Type:              Min at Fast Process Corner
  Data Path Delay:        1.478ns  (logic 0.017ns (1.150%)  route 1.461ns (98.850%))
  Logic Levels:           1  (BUFG_PS=1)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=48236, routed)       1.358     1.478    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/s_axi_aclk
    HSADC_X0Y0           HSADC                                        r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/PLL_MONCLK
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/lo_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/LOGIC_FOR_MD_0_GEN.SPI_MODULE_I/RATIO_NOT_EQUAL_4_GENERATE.SCK_O_NQ_4_NO_STARTUP_USED.SCK_O_NE_4_FDRE_INST/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            LO_SCLK
                            (output port)
  Path Group:             (none)
  Path Type:              Min at Fast Process Corner
  Data Path Delay:        1.309ns  (logic 1.307ns (99.847%)  route 0.002ns (0.153%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.304ns (routing 0.359ns, distribution 0.945ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.304     1.424    d_1_i/lo_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/LOGIC_FOR_MD_0_GEN.SPI_MODULE_I/ext_spi_clk
    HDIOLOGIC_S_X0Y18    FDRE                                         r  d_1_i/lo_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/LOGIC_FOR_MD_0_GEN.SPI_MODULE_I/RATIO_NOT_EQUAL_4_GENERATE.SCK_O_NQ_4_NO_STARTUP_USED.SCK_O_NE_4_FDRE_INST/C
  -------------------------------------------------------------------    -------------------
    HDIOLOGIC_S_X0Y18    FDRE (Prop_OPFF_HDIOLOGIC_S_C_Q)
                                                      0.173     1.597 r  d_1_i/lo_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/LOGIC_FOR_MD_0_GEN.SPI_MODULE_I/RATIO_NOT_EQUAL_4_GENERATE.SCK_O_NQ_4_NO_STARTUP_USED.SCK_O_NE_4_FDRE_INST/Q
                         net (fo=1, routed)           0.002     1.599    LO_SCLK_OBUF
    B7                   OBUF (Prop_OUTBUF_HDIOB_S_I_O)
                                                      1.134     2.733 r  LO_SCLK_OBUF_inst/O
                         net (fo=0)                   0.000     2.733    LO_SCLK
    B7                                                                r  LO_SCLK (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/attn_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/LOGIC_FOR_MD_0_GEN.SPI_MODULE_I/RATIO_NOT_EQUAL_4_GENERATE.SCK_O_NQ_4_NO_STARTUP_USED.SCK_O_NE_4_FDRE_INST/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            ATTN_CLK
                            (output port)
  Path Group:             (none)
  Path Type:              Min at Fast Process Corner
  Data Path Delay:        1.303ns  (logic 1.301ns (99.847%)  route 0.002ns (0.154%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.312ns (routing 0.359ns, distribution 0.953ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.312     1.432    d_1_i/attn_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/LOGIC_FOR_MD_0_GEN.SPI_MODULE_I/ext_spi_clk
    HDIOLOGIC_S_X0Y23    FDRE                                         r  d_1_i/attn_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/LOGIC_FOR_MD_0_GEN.SPI_MODULE_I/RATIO_NOT_EQUAL_4_GENERATE.SCK_O_NQ_4_NO_STARTUP_USED.SCK_O_NE_4_FDRE_INST/C
  -------------------------------------------------------------------    -------------------
    HDIOLOGIC_S_X0Y23    FDRE (Prop_OPFF_HDIOLOGIC_S_C_Q)
                                                      0.173     1.605 r  d_1_i/attn_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/LOGIC_FOR_MD_0_GEN.SPI_MODULE_I/RATIO_NOT_EQUAL_4_GENERATE.SCK_O_NQ_4_NO_STARTUP_USED.SCK_O_NE_4_FDRE_INST/Q
                         net (fo=1, routed)           0.002     1.607    ATTN_CLK_OBUF
    A9                   OBUF (Prop_OUTBUF_HDIOB_S_I_O)
                                                      1.128     2.735 r  ATTN_CLK_OBUF_inst/O
                         net (fo=0)                   0.000     2.735    ATTN_CLK
    A9                                                                r  ATTN_CLK (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/dac_bias_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/LOGIC_FOR_MD_0_GEN.SPI_MODULE_I/RATIO_NOT_EQUAL_4_GENERATE.SCK_O_NQ_4_NO_STARTUP_USED.SCK_O_NE_4_FDRE_INST/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            BIAS_SCLK
                            (output port)
  Path Group:             (none)
  Path Type:              Min at Fast Process Corner
  Data Path Delay:        1.277ns  (logic 1.275ns (99.843%)  route 0.002ns (0.157%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.353ns (routing 0.359ns, distribution 0.994ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.353     1.473    d_1_i/dac_bias_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/LOGIC_FOR_MD_0_GEN.SPI_MODULE_I/ext_spi_clk
    HDIOLOGIC_M_X0Y3     FDRE                                         r  d_1_i/dac_bias_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/LOGIC_FOR_MD_0_GEN.SPI_MODULE_I/RATIO_NOT_EQUAL_4_GENERATE.SCK_O_NQ_4_NO_STARTUP_USED.SCK_O_NE_4_FDRE_INST/C
  -------------------------------------------------------------------    -------------------
    HDIOLOGIC_M_X0Y3     FDRE (Prop_OPFF_HDIOLOGIC_M_C_Q)
                                                      0.174     1.647 r  d_1_i/dac_bias_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/LOGIC_FOR_MD_0_GEN.SPI_MODULE_I/RATIO_NOT_EQUAL_4_GENERATE.SCK_O_NQ_4_NO_STARTUP_USED.SCK_O_NE_4_FDRE_INST/Q
                         net (fo=1, routed)           0.002     1.649    BIAS_SCLK_OBUF
    AU2                  OBUF (Prop_OUTBUF_HDIOB_M_I_O)
                                                      1.101     2.750 r  BIAS_SCLK_OBUF_inst/O
                         net (fo=0)                   0.000     2.750    BIAS_SCLK
    AU2                                                               r  BIAS_SCLK (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/psf_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/LOGIC_FOR_MD_0_GEN.SPI_MODULE_I/RATIO_NOT_EQUAL_4_GENERATE.SCK_O_NQ_4_NO_STARTUP_USED.SCK_O_NE_4_FDRE_INST/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            SCLK
                            (output port)
  Path Group:             (none)
  Path Type:              Min at Fast Process Corner
  Data Path Delay:        1.327ns  (logic 1.325ns (99.849%)  route 0.002ns (0.151%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.310ns (routing 0.359ns, distribution 0.951ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.310     1.430    d_1_i/psf_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/LOGIC_FOR_MD_0_GEN.SPI_MODULE_I/ext_spi_clk
    HDIOLOGIC_M_X0Y21    FDRE                                         r  d_1_i/psf_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/LOGIC_FOR_MD_0_GEN.SPI_MODULE_I/RATIO_NOT_EQUAL_4_GENERATE.SCK_O_NQ_4_NO_STARTUP_USED.SCK_O_NE_4_FDRE_INST/C
  -------------------------------------------------------------------    -------------------
    HDIOLOGIC_M_X0Y21    FDRE (Prop_OPFF_HDIOLOGIC_M_C_Q)
                                                      0.174     1.604 r  d_1_i/psf_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/LOGIC_FOR_MD_0_GEN.SPI_MODULE_I/RATIO_NOT_EQUAL_4_GENERATE.SCK_O_NQ_4_NO_STARTUP_USED.SCK_O_NE_4_FDRE_INST/Q
                         net (fo=1, routed)           0.002     1.606    SCLK_OBUF
    B5                   OBUF (Prop_OUTBUF_HDIOB_M_I_O)
                                                      1.151     2.757 r  SCLK_OBUF_inst/O
                         net (fo=0)                   0.000     2.757    SCLK
    B5                                                                r  SCLK (OUT)
  -------------------------------------------------------------------    -------------------





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  clk_pl_1
  To Clock:  

Max Delay             1 Endpoint
Min Delay             1 Endpoint
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[1]
                            (clock source 'clk_pl_1'  {rise@0.000ns fall@250.003ns period=500.005ns})
  Destination:            PWR_SYNC[0]
                            (output port)
  Path Group:             (none)
  Path Type:              Max at Slow Process Corner
  Data Path Delay:        4.638ns  (logic 2.423ns (52.239%)  route 2.215ns (47.761%))
  Logic Levels:           2  (BUFG_PS=1 OBUF=1)
  Clock Uncertainty:      0.683ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    1.365ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_1 fall edge)
                                                    250.003   250.003 f  
    PS8_X0Y0             PS8                          0.000   250.003 f  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[1]
                         net (fo=1, routed)           0.198   250.201    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk1
    BUFG_PS_X0Y71        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028   250.229 f  d_1_i/zynq_ultra_ps_e_0/inst/pl_clk1_BUFG_inst/O
                         net (fo=1, routed)           2.017   252.245    PWR_SYNC_OBUF[0]
    C10                  OBUF (Prop_OUTBUF_HDIOB_S_I_O)
                                                      2.395   254.640 f  PWR_SYNC_OBUF[0]_inst/O
                         net (fo=0)                   0.000   254.640    PWR_SYNC[0]
    C10                                                               f  PWR_SYNC[0] (OUT)
  -------------------------------------------------------------------    -------------------





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[1]
                            (clock source 'clk_pl_1'  {rise@0.000ns fall@250.003ns period=500.005ns})
  Destination:            PWR_SYNC[0]
                            (output port)
  Path Group:             (none)
  Path Type:              Min at Fast Process Corner
  Data Path Delay:        2.315ns  (logic 1.154ns (49.843%)  route 1.161ns (50.157%))
  Logic Levels:           2  (BUFG_PS=1 OBUF=1)
  Clock Uncertainty:      0.683ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    1.365ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_1 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[1]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk1
    BUFG_PS_X0Y71        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/pl_clk1_BUFG_inst/O
                         net (fo=1, routed)           1.058     1.178    PWR_SYNC_OBUF[0]
    C10                  OBUF (Prop_OUTBUF_HDIOB_S_I_O)
                                                      1.137     2.315 r  PWR_SYNC_OBUF[0]_inst/O
                         net (fo=0)                   0.000     2.315    PWR_SYNC[0]
    C10                                                               r  PWR_SYNC[0] (OUT)
  -------------------------------------------------------------------    -------------------





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  mmcm_clkout0
  To Clock:  

Max Delay             1 Endpoint
Min Delay             1 Endpoint
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/cal_RESET_n_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            ddr4_pl_reset_n
                            (output port)
  Path Group:             (none)
  Path Type:              Max at Slow Process Corner
  Data Path Delay:        2.742ns  (logic 0.927ns (33.796%)  route 1.815ns (66.204%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.156ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.956ns (routing 0.696ns, distribution 1.260ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          1.524     2.610    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.483 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.244     2.727    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.755 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.956     4.711    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/dReg_reg[10]
    SLICE_X94Y285        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/cal_RESET_n_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X94Y285        FDRE (Prop_DFF2_SLICEM_C_Q)
                                                      0.080     4.791 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/cal_RESET_n_reg[0]/Q
                         net (fo=1, routed)           1.815     6.606    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/cal_RESET_n[0]
    A17                  OBUF (Prop_OUTBUF_HPIOB_M_I_O)
                                                      0.847     7.452 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/OBUF_reset_n/O
                         net (fo=0)                   0.000     7.452    ddr4_pl_reset_n
    A17                                                               r  ddr4_pl_reset_n (OUT)
  -------------------------------------------------------------------    -------------------





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/cal_RESET_n_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            ddr4_pl_reset_n
                            (output port)
  Path Group:             (none)
  Path Type:              Min at Fast Process Corner
  Data Path Delay:        1.297ns  (logic 0.461ns (35.551%)  route 0.836ns (64.449%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.156ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.072ns (routing 0.384ns, distribution 0.688ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.839     1.456    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.686 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.145     1.831    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y98         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.848 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41385, routed)       1.072     2.920    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/dReg_reg[10]
    SLICE_X94Y285        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/cal_RESET_n_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X94Y285        FDRE (Prop_DFF2_SLICEM_C_Q)
                                                      0.041     2.961 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/cal_RESET_n_reg[0]/Q
                         net (fo=1, routed)           0.836     3.797    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/cal_RESET_n[0]
    A17                  OBUF (Prop_OUTBUF_HPIOB_M_I_O)
                                                      0.420     4.217 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/OBUF_reset_n/O
                         net (fo=0)                   0.000     4.217    ddr4_pl_reset_n
    A17                                                               r  ddr4_pl_reset_n (OUT)
  -------------------------------------------------------------------    -------------------





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  
  To Clock:  RFDAC0_CLK

Max Delay             2 Endpoints
Min Delay             2 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 PMOD1_0_LS
                            (input port)
  Destination:            d_1_i/qick_processor_0/inst/QPROC/sync_ctrl_ps_t/data_cdc_reg[4]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        6.096ns  (logic 0.858ns (14.070%)  route 5.238ns (85.930%))
  Logic Levels:           4  (IBUFCTRL=1 INBUF=1 LUT4=1 LUT6=1)
  Clock Path Skew:        3.296ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.296ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.775ns (routing 1.327ns, distribution 1.448ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    L14                                               0.000     0.000 r  PMOD1_0_LS (IN)
                         net (fo=0)                   0.000     0.000    PMOD1_0_LS_IBUF_inst/I
    L14                  INBUF (Prop_INBUF_HPIOB_S_PAD_O)
                                                      0.643     0.643 r  PMOD1_0_LS_IBUF_inst/INBUF_INST/O
                         net (fo=1, routed)           0.000     0.643    PMOD1_0_LS_IBUF_inst/OUT
    L14                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_S_I_O)
                                                      0.000     0.643 r  PMOD1_0_LS_IBUF_inst/IBUFCTRL_INST/O
                         net (fo=2, routed)           3.101     3.744    d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/proc_start_i
    SLICE_X31Y159        LUT4 (Prop_H6LUT_SLICEM_I1_O)
                                                      0.090     3.834 r  d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/data_cdc[4]_i_2/O
                         net (fo=1, routed)           0.476     4.310    d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/data_cdc[4]_i_2_n_0
    SLICE_X37Y157        LUT6 (Prop_H6LUT_SLICEM_I0_O)
                                                      0.125     4.435 r  d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/data_cdc[4]_i_1/O
                         net (fo=1, routed)           1.661     6.096    d_1_i/qick_processor_0/inst/QPROC/sync_ctrl_ps_t/data_cdc_reg[6]_0[4]
    SLICE_X83Y167        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/sync_ctrl_ps_t/data_cdc_reg[4]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y100       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89456, routed)       2.775     3.296    d_1_i/qick_processor_0/inst/QPROC/sync_ctrl_ps_t/t_clk_i
    SLICE_X83Y167        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/sync_ctrl_ps_t/data_cdc_reg[4]/C

Slack:                    inf
  Source:                 PMOD1_1_LS
                            (input port)
  Destination:            d_1_i/qick_processor_0/inst/QPROC/sync_ctrl_ps_t/data_cdc_reg[2]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        5.801ns  (logic 0.731ns (12.608%)  route 5.070ns (87.392%))
  Logic Levels:           3  (IBUFCTRL=1 INBUF=1 LUT6=1)
  Clock Path Skew:        3.289ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.289ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.768ns (routing 1.327ns, distribution 1.441ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    L15                                               0.000     0.000 r  PMOD1_1_LS (IN)
                         net (fo=0)                   0.000     0.000    PMOD1_1_LS_IBUF_inst/I
    L15                  INBUF (Prop_INBUF_HPIOB_M_PAD_O)
                                                      0.642     0.642 r  PMOD1_1_LS_IBUF_inst/INBUF_INST/O
                         net (fo=1, routed)           0.000     0.642    PMOD1_1_LS_IBUF_inst/OUT
    L15                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.642 r  PMOD1_1_LS_IBUF_inst/IBUFCTRL_INST/O
                         net (fo=2, routed)           3.403     4.045    d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/proc_stop_i
    SLICE_X29Y158        LUT6 (Prop_D6LUT_SLICEL_I4_O)
                                                      0.089     4.134 r  d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/data_cdc[2]_i_1/O
                         net (fo=1, routed)           1.667     5.801    d_1_i/qick_processor_0/inst/QPROC/sync_ctrl_ps_t/data_cdc_reg[6]_0[2]
    SLICE_X84Y167        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/sync_ctrl_ps_t/data_cdc_reg[2]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y100       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89456, routed)       2.768     3.289    d_1_i/qick_processor_0/inst/QPROC/sync_ctrl_ps_t/t_clk_i
    SLICE_X84Y167        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/sync_ctrl_ps_t/data_cdc_reg[2]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 PMOD1_1_LS
                            (input port)
  Destination:            d_1_i/qick_processor_0/inst/QPROC/sync_ctrl_ps_t/data_cdc_reg[2]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        2.631ns  (logic 0.229ns (8.709%)  route 2.402ns (91.291%))
  Logic Levels:           3  (IBUFCTRL=1 INBUF=1 LUT6=1)
  Clock Path Skew:        2.335ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.335ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Net Delay (Destination): 1.887ns (routing 0.877ns, distribution 1.010ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    L15                                               0.000     0.000 r  PMOD1_1_LS (IN)
                         net (fo=0)                   0.000     0.000    PMOD1_1_LS_IBUF_inst/I
    L15                  INBUF (Prop_INBUF_HPIOB_M_PAD_O)
                                                      0.194     0.194 r  PMOD1_1_LS_IBUF_inst/INBUF_INST/O
                         net (fo=1, routed)           0.000     0.194    PMOD1_1_LS_IBUF_inst/OUT
    L15                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.194 r  PMOD1_1_LS_IBUF_inst/IBUFCTRL_INST/O
                         net (fo=2, routed)           1.601     1.795    d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/proc_stop_i
    SLICE_X29Y158        LUT6 (Prop_D6LUT_SLICEL_I4_O)
                                                      0.035     1.830 r  d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/data_cdc[2]_i_1/O
                         net (fo=1, routed)           0.801     2.631    d_1_i/qick_processor_0/inst/QPROC/sync_ctrl_ps_t/data_cdc_reg[6]_0[2]
    SLICE_X84Y167        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/sync_ctrl_ps_t/data_cdc_reg[2]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y100       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89456, routed)       1.887     2.335    d_1_i/qick_processor_0/inst/QPROC/sync_ctrl_ps_t/t_clk_i
    SLICE_X84Y167        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/sync_ctrl_ps_t/data_cdc_reg[2]/C

Slack:                    inf
  Source:                 PMOD1_0_LS
                            (input port)
  Destination:            d_1_i/qick_processor_0/inst/QPROC/sync_ctrl_ps_t/data_cdc_reg[4]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.302ns period=2.604ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        2.780ns  (logic 0.280ns (10.086%)  route 2.500ns (89.914%))
  Logic Levels:           4  (IBUFCTRL=1 INBUF=1 LUT4=1 LUT6=1)
  Clock Path Skew:        2.343ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.343ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Net Delay (Destination): 1.895ns (routing 0.877ns, distribution 1.018ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    L14                                               0.000     0.000 r  PMOD1_0_LS (IN)
                         net (fo=0)                   0.000     0.000    PMOD1_0_LS_IBUF_inst/I
    L14                  INBUF (Prop_INBUF_HPIOB_S_PAD_O)
                                                      0.194     0.194 r  PMOD1_0_LS_IBUF_inst/INBUF_INST/O
                         net (fo=1, routed)           0.000     0.194    PMOD1_0_LS_IBUF_inst/OUT
    L14                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_S_I_O)
                                                      0.000     0.194 r  PMOD1_0_LS_IBUF_inst/IBUFCTRL_INST/O
                         net (fo=2, routed)           1.476     1.670    d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/proc_start_i
    SLICE_X31Y159        LUT4 (Prop_H6LUT_SLICEM_I1_O)
                                                      0.035     1.705 r  d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/data_cdc[4]_i_2/O
                         net (fo=1, routed)           0.235     1.940    d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/data_cdc[4]_i_2_n_0
    SLICE_X37Y157        LUT6 (Prop_H6LUT_SLICEM_I0_O)
                                                      0.051     1.991 r  d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/data_cdc[4]_i_1/O
                         net (fo=1, routed)           0.789     2.780    d_1_i/qick_processor_0/inst/QPROC/sync_ctrl_ps_t/data_cdc_reg[6]_0[4]
    SLICE_X83Y167        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/sync_ctrl_ps_t/data_cdc_reg[4]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y100       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X2Y3 (CLOCK_ROOT)    net (fo=89456, routed)       1.895     2.343    d_1_i/qick_processor_0/inst/QPROC/sync_ctrl_ps_t/t_clk_i
    SLICE_X83Y167        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/sync_ctrl_ps_t/data_cdc_reg[4]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  
  To Clock:  clk_out1_d_1_clk_adc0_x2_0

Max Delay             1 Endpoint
Min Delay             1 Endpoint
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/LOCKED
                            (internal pin)
  Destination:            d_1_i/rst_adc0_x2/U0/EXT_LPF/lpf_int_reg/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.821ns  (logic 0.090ns (2.355%)  route 3.731ns (97.645%))
  Logic Levels:           1  (LUT4=1)
  Clock Uncertainty:      0.122ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.073ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Destination): 2.836ns (routing 1.400ns, distribution 1.436ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    MMCM_X0Y7            MMCME4_ADV                   0.000     0.000 f  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/LOCKED
                         net (fo=1, routed)           3.680     3.680    d_1_i/rst_adc0_x2/U0/EXT_LPF/dcm_locked
    SLICE_X101Y69        LUT4 (Prop_H6LUT_SLICEL_I0_O)
                                                      0.090     3.770 r  d_1_i/rst_adc0_x2/U0/EXT_LPF/lpf_int0/O
                         net (fo=1, routed)           0.051     3.821    d_1_i/rst_adc0_x2/U0/EXT_LPF/lpf_int0__0
    SLICE_X101Y69        FDRE                                         r  d_1_i/rst_adc0_x2/U0/EXT_LPF/lpf_int_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.389     2.775    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     3.405 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.216     3.621    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.645 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86296, routed)       2.836     6.481    d_1_i/rst_adc0_x2/U0/EXT_LPF/slowest_sync_clk
    SLICE_X101Y69        FDRE                                         r  d_1_i/rst_adc0_x2/U0/EXT_LPF/lpf_int_reg/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/LOCKED
                            (internal pin)
  Destination:            d_1_i/rst_adc0_x2/U0/EXT_LPF/lpf_int_reg/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.924ns  (logic 0.035ns (1.819%)  route 1.889ns (98.181%))
  Logic Levels:           1  (LUT4=1)
  Clock Uncertainty:      0.122ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.073ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Destination): 1.965ns (routing 0.950ns, distribution 1.015ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    MMCM_X0Y7            MMCME4_ADV                   0.000     0.000 f  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/LOCKED
                         net (fo=1, routed)           1.872     1.872    d_1_i/rst_adc0_x2/U0/EXT_LPF/dcm_locked
    SLICE_X101Y69        LUT4 (Prop_H6LUT_SLICEL_I0_O)
                                                      0.035     1.907 r  d_1_i/rst_adc0_x2/U0/EXT_LPF/lpf_int0/O
                         net (fo=1, routed)           0.017     1.924    d_1_i/rst_adc0_x2/U0/EXT_LPF/lpf_int0__0
    SLICE_X101Y69        FDRE                                         r  d_1_i/rst_adc0_x2/U0/EXT_LPF/lpf_int_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y1         BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.624     1.976    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.681 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.847    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.866 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=86296, routed)       1.965     3.831    d_1_i/rst_adc0_x2/U0/EXT_LPF/slowest_sync_clk
    SLICE_X101Y69        FDRE                                         r  d_1_i/rst_adc0_x2/U0/EXT_LPF/lpf_int_reg/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  
  To Clock:  clk_out1_d_1_clk_core_0

Max Delay             3 Endpoints
Min Delay             3 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 PMOD1_1_LS
                            (input port)
  Destination:            d_1_i/qick_processor_0/inst/QPROC/sync_ctrl_ps_c/data_cdc_reg[1]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        4.670ns  (logic 0.743ns (15.919%)  route 3.927ns (84.081%))
  Logic Levels:           4  (IBUFCTRL=1 INBUF=1 LUT4=1 LUT5=1)
  Clock Path Skew:        5.394ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.394ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.143ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Destination): 2.412ns (routing 1.325ns, distribution 1.087ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    L15                                               0.000     0.000 r  PMOD1_1_LS (IN)
                         net (fo=0)                   0.000     0.000    PMOD1_1_LS_IBUF_inst/I
    L15                  INBUF (Prop_INBUF_HPIOB_M_PAD_O)
                                                      0.642     0.642 r  PMOD1_1_LS_IBUF_inst/INBUF_INST/O
                         net (fo=1, routed)           0.000     0.642    PMOD1_1_LS_IBUF_inst/OUT
    L15                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.642 r  PMOD1_1_LS_IBUF_inst/IBUFCTRL_INST/O
                         net (fo=2, routed)           3.492     4.134    d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/proc_stop_i
    SLICE_X29Y155        LUT4 (Prop_D6LUT_SLICEL_I1_O)
                                                      0.050     4.184 r  d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/data_cdc[1]_i_2/O
                         net (fo=1, routed)           0.137     4.321    d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/data_cdc[1]_i_2_n_0
    SLICE_X29Y158        LUT5 (Prop_H6LUT_SLICEL_I0_O)
                                                      0.051     4.372 r  d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/data_cdc[1]_i_1/O
                         net (fo=1, routed)           0.298     4.670    d_1_i/qick_processor_0/inst/QPROC/sync_ctrl_ps_c/data_cdc_reg[6]_0[1]
    SLICE_X29Y158        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/sync_ctrl_ps_c/data_cdc_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=48236, routed)       1.931     2.113    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.743 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.958    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y133        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.982 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=4540, routed)        2.412     5.394    d_1_i/qick_processor_0/inst/QPROC/sync_ctrl_ps_c/c_clk_i
    SLICE_X29Y158        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/sync_ctrl_ps_c/data_cdc_reg[1]/C

Slack:                    inf
  Source:                 PMOD1_0_LS
                            (input port)
  Destination:            d_1_i/qick_processor_0/inst/QPROC/sync_ctrl_ps_c/data_cdc_reg[4]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        4.417ns  (logic 0.766ns (17.336%)  route 3.651ns (82.664%))
  Logic Levels:           3  (IBUFCTRL=1 INBUF=1 LUT6=1)
  Clock Path Skew:        5.397ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.397ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.143ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Destination): 2.415ns (routing 1.325ns, distribution 1.090ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    L14                                               0.000     0.000 r  PMOD1_0_LS (IN)
                         net (fo=0)                   0.000     0.000    PMOD1_0_LS_IBUF_inst/I
    L14                  INBUF (Prop_INBUF_HPIOB_S_PAD_O)
                                                      0.643     0.643 r  PMOD1_0_LS_IBUF_inst/INBUF_INST/O
                         net (fo=1, routed)           0.000     0.643    PMOD1_0_LS_IBUF_inst/OUT
    L14                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_S_I_O)
                                                      0.000     0.643 r  PMOD1_0_LS_IBUF_inst/IBUFCTRL_INST/O
                         net (fo=2, routed)           3.160     3.803    d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/proc_start_i
    SLICE_X30Y159        LUT6 (Prop_C6LUT_SLICEM_I4_O)
                                                      0.123     3.926 r  d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/data_cdc[4]_i_1__0/O
                         net (fo=1, routed)           0.491     4.417    d_1_i/qick_processor_0/inst/QPROC/sync_ctrl_ps_c/data_cdc_reg[6]_0[4]
    SLICE_X30Y159        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/sync_ctrl_ps_c/data_cdc_reg[4]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=48236, routed)       1.931     2.113    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.743 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.958    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y133        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.982 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=4540, routed)        2.415     5.397    d_1_i/qick_processor_0/inst/QPROC/sync_ctrl_ps_c/c_clk_i
    SLICE_X30Y159        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/sync_ctrl_ps_c/data_cdc_reg[4]/C

Slack:                    inf
  Source:                 d_1_i/clk_core/inst/mmcme4_adv_inst/LOCKED
                            (internal pin)
  Destination:            d_1_i/rst_core/U0/EXT_LPF/lpf_int_reg/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.786ns  (logic 0.123ns (4.415%)  route 2.663ns (95.585%))
  Logic Levels:           1  (LUT4=1)
  Clock Uncertainty:      0.143ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Destination): 2.377ns (routing 1.325ns, distribution 1.052ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    MMCM_X0Y5            MMCME4_ADV                   0.000     0.000 f  d_1_i/clk_core/inst/mmcme4_adv_inst/LOCKED
                         net (fo=1, routed)           2.613     2.613    d_1_i/rst_core/U0/EXT_LPF/dcm_locked
    SLICE_X102Y70        LUT4 (Prop_C6LUT_SLICEL_I0_O)
                                                      0.123     2.736 r  d_1_i/rst_core/U0/EXT_LPF/lpf_int0/O
                         net (fo=1, routed)           0.050     2.786    d_1_i/rst_core/U0/EXT_LPF/lpf_int0__0
    SLICE_X102Y70        FDRE                                         r  d_1_i/rst_core/U0/EXT_LPF/lpf_int_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=48236, routed)       1.931     2.113    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.743 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.958    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y133        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.982 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=4540, routed)        2.377     5.359    d_1_i/rst_core/U0/EXT_LPF/slowest_sync_clk
    SLICE_X102Y70        FDRE                                         r  d_1_i/rst_core/U0/EXT_LPF/lpf_int_reg/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/clk_core/inst/mmcme4_adv_inst/LOCKED
                            (internal pin)
  Destination:            d_1_i/rst_core/U0/EXT_LPF/lpf_int_reg/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.420ns  (logic 0.050ns (3.521%)  route 1.370ns (96.479%))
  Logic Levels:           1  (LUT4=1)
  Clock Uncertainty:      0.143ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Destination): 1.650ns (routing 0.896ns, distribution 0.754ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    MMCM_X0Y5            MMCME4_ADV                   0.000     0.000 f  d_1_i/clk_core/inst/mmcme4_adv_inst/LOCKED
                         net (fo=1, routed)           1.353     1.353    d_1_i/rst_core/U0/EXT_LPF/dcm_locked
    SLICE_X102Y70        LUT4 (Prop_C6LUT_SLICEL_I0_O)
                                                      0.050     1.403 r  d_1_i/rst_core/U0/EXT_LPF/lpf_int0/O
                         net (fo=1, routed)           0.017     1.420    d_1_i/rst_core/U0/EXT_LPF/lpf_int0__0
    SLICE_X102Y70        FDRE                                         r  d_1_i/rst_core/U0/EXT_LPF/lpf_int_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=48236, routed)       1.311     1.458    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.163 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.329    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y133        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.348 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=4540, routed)        1.650     2.998    d_1_i/rst_core/U0/EXT_LPF/slowest_sync_clk
    SLICE_X102Y70        FDRE                                         r  d_1_i/rst_core/U0/EXT_LPF/lpf_int_reg/C

Slack:                    inf
  Source:                 PMOD1_0_LS
                            (input port)
  Destination:            d_1_i/qick_processor_0/inst/QPROC/sync_ctrl_ps_c/data_cdc_reg[4]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.951ns  (logic 0.244ns (12.525%)  route 1.707ns (87.475%))
  Logic Levels:           3  (IBUFCTRL=1 INBUF=1 LUT6=1)
  Clock Path Skew:        3.024ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.024ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Net Delay (Destination): 1.676ns (routing 0.896ns, distribution 0.780ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    L14                                               0.000     0.000 r  PMOD1_0_LS (IN)
                         net (fo=0)                   0.000     0.000    PMOD1_0_LS_IBUF_inst/I
    L14                  INBUF (Prop_INBUF_HPIOB_S_PAD_O)
                                                      0.194     0.194 r  PMOD1_0_LS_IBUF_inst/INBUF_INST/O
                         net (fo=1, routed)           0.000     0.194    PMOD1_0_LS_IBUF_inst/OUT
    L14                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_S_I_O)
                                                      0.000     0.194 r  PMOD1_0_LS_IBUF_inst/IBUFCTRL_INST/O
                         net (fo=2, routed)           1.505     1.699    d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/proc_start_i
    SLICE_X30Y159        LUT6 (Prop_C6LUT_SLICEM_I4_O)
                                                      0.050     1.749 r  d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/data_cdc[4]_i_1__0/O
                         net (fo=1, routed)           0.202     1.951    d_1_i/qick_processor_0/inst/QPROC/sync_ctrl_ps_c/data_cdc_reg[6]_0[4]
    SLICE_X30Y159        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/sync_ctrl_ps_c/data_cdc_reg[4]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=48236, routed)       1.311     1.458    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.163 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.329    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y133        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.348 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=4540, routed)        1.676     3.024    d_1_i/qick_processor_0/inst/QPROC/sync_ctrl_ps_c/c_clk_i
    SLICE_X30Y159        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/sync_ctrl_ps_c/data_cdc_reg[4]/C

Slack:                    inf
  Source:                 PMOD1_1_LS
                            (input port)
  Destination:            d_1_i/qick_processor_0/inst/QPROC/sync_ctrl_ps_c/data_cdc_reg[1]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        2.064ns  (logic 0.239ns (11.586%)  route 1.825ns (88.414%))
  Logic Levels:           4  (IBUFCTRL=1 INBUF=1 LUT4=1 LUT5=1)
  Clock Path Skew:        3.019ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.019ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Net Delay (Destination): 1.671ns (routing 0.896ns, distribution 0.775ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    L15                                               0.000     0.000 r  PMOD1_1_LS (IN)
                         net (fo=0)                   0.000     0.000    PMOD1_1_LS_IBUF_inst/I
    L15                  INBUF (Prop_INBUF_HPIOB_M_PAD_O)
                                                      0.194     0.194 r  PMOD1_1_LS_IBUF_inst/INBUF_INST/O
                         net (fo=1, routed)           0.000     0.194    PMOD1_1_LS_IBUF_inst/OUT
    L15                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.194 r  PMOD1_1_LS_IBUF_inst/IBUFCTRL_INST/O
                         net (fo=2, routed)           1.649     1.843    d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/proc_stop_i
    SLICE_X29Y155        LUT4 (Prop_D6LUT_SLICEL_I1_O)
                                                      0.022     1.865 r  d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/data_cdc[1]_i_2/O
                         net (fo=1, routed)           0.071     1.936    d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/data_cdc[1]_i_2_n_0
    SLICE_X29Y158        LUT5 (Prop_H6LUT_SLICEL_I0_O)
                                                      0.023     1.959 r  d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/data_cdc[1]_i_1/O
                         net (fo=1, routed)           0.105     2.064    d_1_i/qick_processor_0/inst/QPROC/sync_ctrl_ps_c/data_cdc_reg[6]_0[1]
    SLICE_X29Y158        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/sync_ctrl_ps_c/data_cdc_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=48236, routed)       1.311     1.458    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.163 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.329    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y133        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.348 r  d_1_i/clk_core/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=4540, routed)        1.671     3.019    d_1_i/qick_processor_0/inst/QPROC/sync_ctrl_ps_c/c_clk_i
    SLICE_X29Y158        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/sync_ctrl_ps_c/data_cdc_reg[1]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  
  To Clock:  clk_pl_0

Max Delay            10 Endpoints
Min Delay            10 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[5]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[5]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        4.015ns  (logic 0.484ns (12.055%)  route 3.531ns (87.945%))
  Logic Levels:           5  (LUT6=5)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.164ns (routing 0.599ns, distribution 1.565ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[5]
                         net (fo=1, routed)           2.344     2.344    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_28_0[5]
    SLICE_X104Y122       LUT6 (Prop_G6LUT_SLICEM_I5_O)
                                                      0.150     2.494 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_27/O
                         net (fo=1, routed)           0.186     2.680    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_27_n_0
    SLICE_X103Y121       LUT6 (Prop_F6LUT_SLICEM_I0_O)
                                                      0.037     2.717 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_20/O
                         net (fo=1, routed)           0.152     2.869    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_20_n_0
    SLICE_X104Y121       LUT6 (Prop_C6LUT_SLICEM_I3_O)
                                                      0.123     2.992 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_10/O
                         net (fo=1, routed)           0.260     3.252    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_10_n_0
    SLICE_X106Y121       LUT6 (Prop_H6LUT_SLICEL_I4_O)
                                                      0.051     3.303 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_2/O
                         net (fo=1, routed)           0.539     3.842    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_2_n_0
    SLICE_X108Y104       LUT6 (Prop_C6LUT_SLICEL_I0_O)
                                                      0.123     3.965 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_1/O
                         net (fo=1, routed)           0.050     4.015    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_79
    SLICE_X108Y104       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[5]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       2.164     2.346    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X108Y104       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[5]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[1]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[1]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.987ns  (logic 0.545ns (13.671%)  route 3.442ns (86.329%))
  Logic Levels:           5  (LUT4=1 LUT5=1 LUT6=3)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.166ns (routing 0.599ns, distribution 1.567ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[1]
                         net (fo=2, routed)           2.222     2.222    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_28_0[1]
    SLICE_X106Y129       LUT4 (Prop_F6LUT_SLICEL_I0_O)
                                                      0.123     2.345 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[1]_i_71/O
                         net (fo=1, routed)           0.215     2.560    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[1]_i_71_n_0
    SLICE_X106Y126       LUT5 (Prop_B6LUT_SLICEL_I3_O)
                                                      0.124     2.684 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[1]_i_51/O
                         net (fo=1, routed)           0.149     2.833    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[1]_i_51_n_0
    SLICE_X107Y126       LUT6 (Prop_G6LUT_SLICEM_I3_O)
                                                      0.052     2.885 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[1]_i_21/O
                         net (fo=1, routed)           0.130     3.015    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[1]_i_21_n_0
    SLICE_X107Y126       LUT6 (Prop_F6LUT_SLICEM_I4_O)
                                                      0.098     3.113 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[1]_i_6/O
                         net (fo=1, routed)           0.677     3.790    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[1]_i_6_n_0
    SLICE_X108Y107       LUT6 (Prop_B6LUT_SLICEL_I5_O)
                                                      0.148     3.938 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[1]_i_1/O
                         net (fo=1, routed)           0.049     3.987    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_83
    SLICE_X108Y107       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       2.166     2.348    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X108Y107       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[1]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[3]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[3]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.833ns  (logic 0.482ns (12.575%)  route 3.351ns (87.425%))
  Logic Levels:           4  (LUT5=1 LUT6=3)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.164ns (routing 0.599ns, distribution 1.565ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[3]
                         net (fo=2, routed)           2.181     2.181    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_28_0[3]
    SLICE_X108Y128       LUT5 (Prop_G6LUT_SLICEL_I4_O)
                                                      0.123     2.304 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[3]_i_53/O
                         net (fo=1, routed)           0.527     2.831    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[3]_i_53_n_0
    SLICE_X106Y125       LUT6 (Prop_G6LUT_SLICEL_I2_O)
                                                      0.089     2.920 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[3]_i_21/O
                         net (fo=1, routed)           0.048     2.968    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[3]_i_21_n_0
    SLICE_X106Y125       LUT6 (Prop_B6LUT_SLICEL_I1_O)
                                                      0.124     3.092 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[3]_i_6/O
                         net (fo=1, routed)           0.546     3.638    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[3]_i_6_n_0
    SLICE_X108Y104       LUT6 (Prop_D6LUT_SLICEL_I5_O)
                                                      0.146     3.784 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[3]_i_1/O
                         net (fo=1, routed)           0.049     3.833    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_81
    SLICE_X108Y104       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[3]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       2.164     2.346    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X108Y104       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[3]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[2]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[2]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.563ns  (logic 0.392ns (11.002%)  route 3.171ns (88.998%))
  Logic Levels:           5  (LUT4=1 LUT5=1 LUT6=3)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.140ns (routing 0.599ns, distribution 1.541ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[2]
                         net (fo=2, routed)           1.987     1.987    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_28_0[2]
    SLICE_X108Y127       LUT4 (Prop_G6LUT_SLICEL_I0_O)
                                                      0.123     2.110 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[2]_i_58/O
                         net (fo=1, routed)           0.497     2.607    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[2]_i_58_n_0
    SLICE_X105Y125       LUT5 (Prop_C6LUT_SLICEL_I3_O)
                                                      0.050     2.657 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[2]_i_26/O
                         net (fo=1, routed)           0.129     2.786    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[2]_i_26_n_0
    SLICE_X106Y125       LUT6 (Prop_C6LUT_SLICEL_I3_O)
                                                      0.035     2.821 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[2]_i_8/O
                         net (fo=1, routed)           0.267     3.088    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[2]_i_8_n_0
    SLICE_X106Y121       LUT6 (Prop_A6LUT_SLICEL_I2_O)
                                                      0.149     3.237 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[2]_i_2/O
                         net (fo=1, routed)           0.241     3.478    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[2]_i_2_n_0
    SLICE_X106Y104       LUT6 (Prop_C6LUT_SLICEL_I0_O)
                                                      0.035     3.513 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[2]_i_1/O
                         net (fo=1, routed)           0.050     3.563    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_82
    SLICE_X106Y104       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[2]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       2.140     2.322    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X106Y104       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[2]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[7]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[7]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.516ns  (logic 0.354ns (10.068%)  route 3.162ns (89.932%))
  Logic Levels:           4  (LUT5=1 LUT6=3)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.168ns (routing 0.599ns, distribution 1.569ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[7]
                         net (fo=1, routed)           2.284     2.284    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_28_0[7]
    SLICE_X105Y129       LUT5 (Prop_E6LUT_SLICEL_I4_O)
                                                      0.099     2.383 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[7]_i_24/O
                         net (fo=1, routed)           0.088     2.471    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[7]_i_24_n_0
    SLICE_X105Y128       LUT6 (Prop_G6LUT_SLICEL_I3_O)
                                                      0.035     2.506 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[7]_i_10/O
                         net (fo=1, routed)           0.391     2.897    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[7]_i_10_n_0
    SLICE_X108Y128       LUT6 (Prop_H6LUT_SLICEL_I2_O)
                                                      0.124     3.021 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[7]_i_3/O
                         net (fo=1, routed)           0.349     3.370    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[7]_i_3_n_0
    SLICE_X108Y109       LUT6 (Prop_C6LUT_SLICEL_I1_O)
                                                      0.096     3.466 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[7]_i_1/O
                         net (fo=1, routed)           0.050     3.516    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_77
    SLICE_X108Y109       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[7]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       2.168     2.350    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X108Y109       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[7]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[0]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.376ns  (logic 0.421ns (12.472%)  route 2.955ns (87.528%))
  Logic Levels:           5  (LUT5=1 LUT6=4)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.168ns (routing 0.599ns, distribution 1.569ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[0]
                         net (fo=2, routed)           2.212     2.212    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_28_0[0]
    SLICE_X106Y123       LUT5 (Prop_D6LUT_SLICEL_I3_O)
                                                      0.050     2.262 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[0]_i_57/O
                         net (fo=1, routed)           0.051     2.313    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[0]_i_57_n_0
    SLICE_X106Y123       LUT6 (Prop_C6LUT_SLICEL_I2_O)
                                                      0.146     2.459 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[0]_i_27/O
                         net (fo=1, routed)           0.041     2.500    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[0]_i_27_n_0
    SLICE_X106Y123       LUT6 (Prop_B6LUT_SLICEL_I3_O)
                                                      0.090     2.590 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[0]_i_8/O
                         net (fo=1, routed)           0.045     2.635    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[0]_i_8_n_0
    SLICE_X106Y123       LUT6 (Prop_H6LUT_SLICEL_I3_O)
                                                      0.099     2.734 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[0]_i_2/O
                         net (fo=1, routed)           0.557     3.291    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[0]_i_2_n_0
    SLICE_X108Y109       LUT6 (Prop_D6LUT_SLICEL_I0_O)
                                                      0.036     3.327 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[0]_i_1/O
                         net (fo=1, routed)           0.049     3.376    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_84
    SLICE_X108Y109       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       2.168     2.350    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X108Y109       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[0]/C

Slack:                    inf
  Source:                 LO_MISO1
                            (input port)
  Destination:            d_1_i/lo_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/IO1_I_REG/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.324ns  (logic 1.247ns (37.508%)  route 2.077ns (62.492%))
  Logic Levels:           3  (IBUFCTRL=1 INBUF=1 LUT6=1)
  Clock Path Skew:        2.239ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.239ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.057ns (routing 0.599ns, distribution 1.458ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    C7                                                0.000     0.000 r  LO_MISO1 (IN)
                         net (fo=0)                   0.000     0.000    LO_MISO1_IBUF_inst/I
    C7                   INBUF (Prop_INBUF_HDIOB_S_PAD_O)
                                                      1.123     1.123 r  LO_MISO1_IBUF_inst/INBUF_INST/O
                         net (fo=1, routed)           0.000     1.123    LO_MISO1_IBUF_inst/OUT
    C7                   IBUFCTRL (Prop_IBUFCTRL_HDIOB_S_I_O)
                                                      0.000     1.123 r  LO_MISO1_IBUF_inst/IBUFCTRL_INST/O
                         net (fo=1, routed)           2.026     3.149    d_1_i/lo_spi_mux_v2_0/inst/sdo1_in
    SLICE_X81Y50         LUT6 (Prop_H6LUT_SLICEL_I4_O)
                                                      0.124     3.273 r  d_1_i/lo_spi_mux_v2_0/inst/sdo_out__0/O
                         net (fo=1, routed)           0.051     3.324    d_1_i/lo_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/io1_i
    SLICE_X81Y50         FDRE                                         r  d_1_i/lo_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/IO1_I_REG/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       2.057     2.239    d_1_i/lo_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/ext_spi_clk
    SLICE_X81Y50         FDRE                                         r  d_1_i/lo_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/IO1_I_REG/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[4]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[4]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.946ns  (logic 0.266ns (9.029%)  route 2.680ns (90.971%))
  Logic Levels:           4  (LUT5=1 LUT6=3)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.142ns (routing 0.599ns, distribution 1.543ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[4]
                         net (fo=1, routed)           2.075     2.075    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_28_0[4]
    SLICE_X107Y129       LUT5 (Prop_F6LUT_SLICEM_I4_O)
                                                      0.088     2.163 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[4]_i_51/O
                         net (fo=1, routed)           0.206     2.369    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[4]_i_51_n_0
    SLICE_X104Y128       LUT6 (Prop_G6LUT_SLICEM_I4_O)
                                                      0.090     2.459 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[4]_i_30/O
                         net (fo=1, routed)           0.092     2.551    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[4]_i_30_n_0
    SLICE_X104Y126       LUT6 (Prop_G6LUT_SLICEM_I1_O)
                                                      0.037     2.588 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[4]_i_7/O
                         net (fo=1, routed)           0.235     2.823    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[4]_i_7_n_0
    SLICE_X104Y109       LUT6 (Prop_D6LUT_SLICEM_I5_O)
                                                      0.051     2.874 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[4]_i_1/O
                         net (fo=1, routed)           0.072     2.946    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_80
    SLICE_X104Y109       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[4]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       2.142     2.324    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X104Y109       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[4]/C

Slack:                    inf
  Source:                 SDO
                            (input port)
  Destination:            d_1_i/psf_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/IO1_I_REG/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.212ns  (logic 1.111ns (91.667%)  route 0.101ns (8.333%))
  Logic Levels:           2  (IBUFCTRL=1 INBUF=1)
  Clock Path Skew:        2.300ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.300ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.118ns (routing 0.599ns, distribution 1.519ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    B9                                                0.000     0.000 r  SDO (IN)
                         net (fo=0)                   0.000     0.000    SDO_IBUF_inst/I
    B9                   INBUF (Prop_INBUF_HDIOB_S_PAD_O)
                                                      1.111     1.111 r  SDO_IBUF_inst/INBUF_INST/O
                         net (fo=1, routed)           0.000     1.111    SDO_IBUF_inst/OUT
    B9                   IBUFCTRL (Prop_IBUFCTRL_HDIOB_S_I_O)
                                                      0.000     1.111 r  SDO_IBUF_inst/IBUFCTRL_INST/O
                         net (fo=1, routed)           0.101     1.212    d_1_i/psf_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/io1_i
    HDIOLOGIC_S_X0Y19    FDRE                                         r  d_1_i/psf_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/IO1_I_REG/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       2.118     2.300    d_1_i/psf_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/ext_spi_clk
    HDIOLOGIC_S_X0Y19    FDRE                                         r  d_1_i/psf_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/IO1_I_REG/C

Slack:                    inf
  Source:                 BIAS_SDO
                            (input port)
  Destination:            d_1_i/dac_bias_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/IO1_I_REG/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.153ns  (logic 1.052ns (91.243%)  route 0.101ns (8.757%))
  Logic Levels:           2  (IBUFCTRL=1 INBUF=1)
  Clock Path Skew:        2.361ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.361ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.179ns (routing 0.599ns, distribution 1.580ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    AP5                                               0.000     0.000 r  BIAS_SDO (IN)
                         net (fo=0)                   0.000     0.000    BIAS_SDO_IBUF_inst/I
    AP5                  INBUF (Prop_INBUF_HDIOB_S_PAD_O)
                                                      1.052     1.052 r  BIAS_SDO_IBUF_inst/INBUF_INST/O
                         net (fo=1, routed)           0.000     1.052    BIAS_SDO_IBUF_inst/OUT
    AP5                  IBUFCTRL (Prop_IBUFCTRL_HDIOB_S_I_O)
                                                      0.000     1.052 r  BIAS_SDO_IBUF_inst/IBUFCTRL_INST/O
                         net (fo=1, routed)           0.101     1.153    d_1_i/dac_bias_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/io1_i
    HDIOLOGIC_S_X0Y11    FDRE                                         r  d_1_i/dac_bias_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/IO1_I_REG/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       2.179     2.361    d_1_i/dac_bias_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/ext_spi_clk
    HDIOLOGIC_S_X0Y11    FDRE                                         r  d_1_i/dac_bias_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/IO1_I_REG/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 BIAS_SDO
                            (input port)
  Destination:            d_1_i/dac_bias_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/IO1_I_REG/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.436ns  (logic 0.386ns (88.530%)  route 0.050ns (11.470%))
  Logic Levels:           2  (IBUFCTRL=1 INBUF=1)
  Clock Path Skew:        1.697ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.697ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Net Delay (Destination): 1.550ns (routing 0.405ns, distribution 1.145ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    AP5                                               0.000     0.000 r  BIAS_SDO (IN)
                         net (fo=0)                   0.000     0.000    BIAS_SDO_IBUF_inst/I
    AP5                  INBUF (Prop_INBUF_HDIOB_S_PAD_O)
                                                      0.386     0.386 r  BIAS_SDO_IBUF_inst/INBUF_INST/O
                         net (fo=1, routed)           0.000     0.386    BIAS_SDO_IBUF_inst/OUT
    AP5                  IBUFCTRL (Prop_IBUFCTRL_HDIOB_S_I_O)
                                                      0.000     0.386 r  BIAS_SDO_IBUF_inst/IBUFCTRL_INST/O
                         net (fo=1, routed)           0.050     0.436    d_1_i/dac_bias_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/io1_i
    HDIOLOGIC_S_X0Y11    FDRE                                         r  d_1_i/dac_bias_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/IO1_I_REG/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.550     1.697    d_1_i/dac_bias_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/ext_spi_clk
    HDIOLOGIC_S_X0Y11    FDRE                                         r  d_1_i/dac_bias_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/IO1_I_REG/C

Slack:                    inf
  Source:                 SDO
                            (input port)
  Destination:            d_1_i/psf_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/IO1_I_REG/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.494ns  (logic 0.444ns (89.880%)  route 0.050ns (10.120%))
  Logic Levels:           2  (IBUFCTRL=1 INBUF=1)
  Clock Path Skew:        1.640ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.640ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Net Delay (Destination): 1.493ns (routing 0.405ns, distribution 1.088ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    B9                                                0.000     0.000 r  SDO (IN)
                         net (fo=0)                   0.000     0.000    SDO_IBUF_inst/I
    B9                   INBUF (Prop_INBUF_HDIOB_S_PAD_O)
                                                      0.444     0.444 r  SDO_IBUF_inst/INBUF_INST/O
                         net (fo=1, routed)           0.000     0.444    SDO_IBUF_inst/OUT
    B9                   IBUFCTRL (Prop_IBUFCTRL_HDIOB_S_I_O)
                                                      0.000     0.444 r  SDO_IBUF_inst/IBUFCTRL_INST/O
                         net (fo=1, routed)           0.050     0.494    d_1_i/psf_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/io1_i
    HDIOLOGIC_S_X0Y19    FDRE                                         r  d_1_i/psf_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/IO1_I_REG/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.493     1.640    d_1_i/psf_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/ext_spi_clk
    HDIOLOGIC_S_X0Y19    FDRE                                         r  d_1_i/psf_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/IO1_I_REG/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_COMMON[7]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[7]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.781ns  (logic 0.154ns (19.718%)  route 0.627ns (80.282%))
  Logic Levels:           5  (LUT5=1 LUT6=4)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.501ns (routing 0.405ns, distribution 1.096ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y2           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_COMMON[7]
                         net (fo=1, routed)           0.302     0.302    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_22_1[7]
    SLICE_X110Y117       LUT5 (Prop_E6LUT_SLICEM_I3_O)
                                                      0.035     0.337 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[7]_i_36/O
                         net (fo=1, routed)           0.114     0.451    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[7]_i_36_n_0
    SLICE_X108Y116       LUT6 (Prop_G6LUT_SLICEL_I5_O)
                                                      0.040     0.491 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[7]_i_30/O
                         net (fo=1, routed)           0.048     0.539    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[7]_i_30_n_0
    SLICE_X108Y114       LUT6 (Prop_G6LUT_SLICEL_I4_O)
                                                      0.035     0.574 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[7]_i_17/O
                         net (fo=1, routed)           0.073     0.647    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[7]_i_17_n_0
    SLICE_X108Y111       LUT6 (Prop_G6LUT_SLICEL_I1_O)
                                                      0.022     0.669 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[7]_i_6/O
                         net (fo=1, routed)           0.073     0.742    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[7]_i_6_n_0
    SLICE_X108Y109       LUT6 (Prop_C6LUT_SLICEL_I4_O)
                                                      0.022     0.764 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[7]_i_1/O
                         net (fo=1, routed)           0.017     0.781    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_77
    SLICE_X108Y109       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[7]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.501     1.648    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X108Y109       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[7]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_COMMON[1]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[1]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.876ns  (logic 0.104ns (11.871%)  route 0.772ns (88.129%))
  Logic Levels:           4  (LUT6=4)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.500ns (routing 0.405ns, distribution 1.095ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y2           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_COMMON[1]
                         net (fo=2, routed)           0.288     0.288    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_22_1[1]
    SLICE_X112Y122       LUT6 (Prop_G6LUT_SLICEM_I0_O)
                                                      0.014     0.302 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[1]_i_27/O
                         net (fo=1, routed)           0.107     0.409    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[1]_i_27_n_0
    SLICE_X111Y117       LUT6 (Prop_G6LUT_SLICEL_I0_O)
                                                      0.035     0.444 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[1]_i_10/O
                         net (fo=1, routed)           0.269     0.713    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[1]_i_10_n_0
    SLICE_X110Y106       LUT6 (Prop_F6LUT_SLICEM_I1_O)
                                                      0.040     0.753 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[1]_i_4/O
                         net (fo=1, routed)           0.093     0.846    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[1]_i_4_n_0
    SLICE_X108Y107       LUT6 (Prop_B6LUT_SLICEL_I2_O)
                                                      0.015     0.861 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[1]_i_1/O
                         net (fo=1, routed)           0.015     0.876    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_83
    SLICE_X108Y107       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.500     1.647    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X108Y107       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[1]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_COMMON[3]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[3]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.879ns  (logic 0.109ns (12.400%)  route 0.770ns (87.600%))
  Logic Levels:           4  (LUT6=4)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.499ns (routing 0.405ns, distribution 1.094ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_COMMON[3]
                         net (fo=1, routed)           0.439     0.439    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_23_0[3]
    SLICE_X106Y104       LUT6 (Prop_G6LUT_SLICEL_I0_O)
                                                      0.014     0.453 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[3]_i_28/O
                         net (fo=1, routed)           0.025     0.478    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[3]_i_28_n_0
    SLICE_X106Y104       LUT6 (Prop_F6LUT_SLICEL_I5_O)
                                                      0.040     0.518 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[3]_i_8/O
                         net (fo=1, routed)           0.202     0.720    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[3]_i_8_n_0
    SLICE_X108Y104       LUT6 (Prop_H6LUT_SLICEL_I2_O)
                                                      0.041     0.761 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[3]_i_2/O
                         net (fo=1, routed)           0.088     0.849    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[3]_i_2_n_0
    SLICE_X108Y104       LUT6 (Prop_D6LUT_SLICEL_I0_O)
                                                      0.014     0.863 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[3]_i_1/O
                         net (fo=1, routed)           0.016     0.879    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_81
    SLICE_X108Y104       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[3]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.499     1.646    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X108Y104       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[3]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_COMMON[4]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[4]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.903ns  (logic 0.163ns (18.051%)  route 0.740ns (81.949%))
  Logic Levels:           4  (LUT4=1 LUT5=1 LUT6=2)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.489ns (routing 0.405ns, distribution 1.084ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_COMMON[4]
                         net (fo=1, routed)           0.320     0.320    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_23_0[4]
    SLICE_X108Y103       LUT5 (Prop_C6LUT_SLICEL_I4_O)
                                                      0.040     0.360 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[4]_i_42/O
                         net (fo=1, routed)           0.216     0.576    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[4]_i_42_n_0
    SLICE_X107Y106       LUT6 (Prop_C6LUT_SLICEM_I5_O)
                                                      0.014     0.590 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[4]_i_24/O
                         net (fo=1, routed)           0.031     0.621    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[4]_i_24_n_0
    SLICE_X107Y106       LUT4 (Prop_F6LUT_SLICEM_I3_O)
                                                      0.059     0.680 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[4]_i_5/O
                         net (fo=1, routed)           0.147     0.827    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[4]_i_5_n_0
    SLICE_X104Y109       LUT6 (Prop_D6LUT_SLICEM_I3_O)
                                                      0.050     0.877 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[4]_i_1/O
                         net (fo=1, routed)           0.026     0.903    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_80
    SLICE_X104Y109       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[4]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.489     1.636    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X104Y109       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[4]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_COMMON[0]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.005ns  (logic 0.081ns (8.060%)  route 0.924ns (91.940%))
  Logic Levels:           4  (LUT6=4)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.501ns (routing 0.405ns, distribution 1.096ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_COMMON[0]
                         net (fo=1, routed)           0.644     0.644    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_23_0[0]
    SLICE_X107Y105       LUT6 (Prop_G6LUT_SLICEM_I0_O)
                                                      0.014     0.658 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[0]_i_47/O
                         net (fo=1, routed)           0.027     0.685    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[0]_i_47_n_0
    SLICE_X107Y105       LUT6 (Prop_H6LUT_SLICEM_I0_O)
                                                      0.023     0.708 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[0]_i_17/O
                         net (fo=1, routed)           0.194     0.902    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[0]_i_17_n_0
    SLICE_X108Y109       LUT6 (Prop_G6LUT_SLICEL_I5_O)
                                                      0.022     0.924 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[0]_i_4/O
                         net (fo=1, routed)           0.043     0.967    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[0]_i_4_n_0
    SLICE_X108Y109       LUT6 (Prop_D6LUT_SLICEL_I2_O)
                                                      0.022     0.989 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[0]_i_1/O
                         net (fo=1, routed)           0.016     1.005    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_84
    SLICE_X108Y109       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.501     1.648    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X108Y109       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/STATUS_COMMON[2]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[2]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.070ns  (logic 0.148ns (13.835%)  route 0.922ns (86.165%))
  Logic Levels:           4  (LUT6=4)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.486ns (routing 0.405ns, distribution 1.081ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/STATUS_COMMON[2]
                         net (fo=2, routed)           0.714     0.714    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/STATUS_COMMON[2]
    SLICE_X107Y99        LUT6 (Prop_E6LUT_SLICEM_I3_O)
                                                      0.014     0.728 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[2]_i_47/O
                         net (fo=1, routed)           0.033     0.761    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[2]_i_47_n_0
    SLICE_X107Y99        LUT6 (Prop_F6LUT_SLICEM_I3_O)
                                                      0.059     0.820 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[2]_i_17/O
                         net (fo=1, routed)           0.047     0.867    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[2]_i_17_n_0
    SLICE_X106Y99        LUT6 (Prop_F6LUT_SLICEL_I4_O)
                                                      0.035     0.902 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[2]_i_4/O
                         net (fo=1, routed)           0.111     1.013    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[2]_i_4_n_0
    SLICE_X106Y104       LUT6 (Prop_C6LUT_SLICEL_I3_O)
                                                      0.040     1.053 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[2]_i_1/O
                         net (fo=1, routed)           0.017     1.070    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_82
    SLICE_X106Y104       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[2]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.486     1.633    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X106Y104       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[2]/C

Slack:                    inf
  Source:                 LO_MISO2
                            (input port)
  Destination:            d_1_i/lo_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/IO1_I_REG/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.300ns  (logic 0.442ns (34.019%)  route 0.858ns (65.981%))
  Logic Levels:           3  (IBUFCTRL=1 INBUF=1 LUT6=1)
  Clock Path Skew:        1.589ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.589ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Net Delay (Destination): 1.442ns (routing 0.405ns, distribution 1.037ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    AV7                                               0.000     0.000 r  LO_MISO2 (IN)
                         net (fo=0)                   0.000     0.000    LO_MISO2_IBUF_inst/I
    AV7                  INBUF (Prop_INBUF_HDIOB_S_PAD_O)
                                                      0.382     0.382 r  LO_MISO2_IBUF_inst/INBUF_INST/O
                         net (fo=1, routed)           0.000     0.382    LO_MISO2_IBUF_inst/OUT
    AV7                  IBUFCTRL (Prop_IBUFCTRL_HDIOB_S_I_O)
                                                      0.000     0.382 r  LO_MISO2_IBUF_inst/IBUFCTRL_INST/O
                         net (fo=1, routed)           0.841     1.223    d_1_i/lo_spi_mux_v2_0/inst/sdo2_in
    SLICE_X81Y50         LUT6 (Prop_H6LUT_SLICEL_I5_O)
                                                      0.060     1.283 r  d_1_i/lo_spi_mux_v2_0/inst/sdo_out__0/O
                         net (fo=1, routed)           0.017     1.300    d_1_i/lo_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/io1_i
    SLICE_X81Y50         FDRE                                         r  d_1_i/lo_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/IO1_I_REG/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.442     1.589    d_1_i/lo_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/ext_spi_clk
    SLICE_X81Y50         FDRE                                         r  d_1_i/lo_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/IO1_I_REG/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/STATUS_COMMON[5]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[5]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.807ns  (logic 0.170ns (9.408%)  route 1.637ns (90.592%))
  Logic Levels:           4  (LUT4=1 LUT6=3)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.499ns (routing 0.405ns, distribution 1.094ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/STATUS_COMMON[5]
                         net (fo=1, routed)           0.940     0.940    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_31_0[5]
    SLICE_X103Y128       LUT4 (Prop_G6LUT_SLICEM_I0_O)
                                                      0.035     0.975 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_22/O
                         net (fo=1, routed)           0.145     1.120    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_22_n_0
    SLICE_X101Y128       LUT6 (Prop_H6LUT_SLICEL_I1_O)
                                                      0.050     1.170 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_11/O
                         net (fo=1, routed)           0.254     1.424    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_11_n_0
    SLICE_X106Y121       LUT6 (Prop_H6LUT_SLICEL_I5_O)
                                                      0.035     1.459 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_2/O
                         net (fo=1, routed)           0.281     1.740    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_2_n_0
    SLICE_X108Y104       LUT6 (Prop_C6LUT_SLICEL_I0_O)
                                                      0.050     1.790 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_1/O
                         net (fo=1, routed)           0.017     1.807    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_79
    SLICE_X108Y104       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[5]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y48        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=48236, routed)       1.499     1.646    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X108Y104       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[5]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  
  To Clock:  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK

Max Delay             4 Endpoints
Min Delay             4 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TDI
                            (internal pin)
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/iTDI_reg_reg/D
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        6.319ns  (logic 4.300ns (68.053%)  route 2.019ns (31.947%))
  Logic Levels:           1  (BSCANE2=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.548ns (routing 0.470ns, distribution 1.078ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TDI
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TDI_TDI)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TDI
                         net (fo=4, routed)           2.019     6.319    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/out
    SLICE_X107Y327       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/iTDI_reg_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.219     1.684    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y81         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.708 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.548     3.256    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/m_bscan_tck[0]
    SLICE_X107Y327       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/iTDI_reg_reg/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TDI
                            (internal pin)
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/shiftreg_reg[31]/D
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        5.231ns  (logic 4.400ns (84.110%)  route 0.831ns (15.890%))
  Logic Levels:           2  (BSCANE2=1 LUT5=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.544ns (routing 0.470ns, distribution 1.074ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TDI
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TDI_TDI)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TDI
                         net (fo=4, routed)           0.776     5.076    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_tdi
    SLICE_X107Y66        LUT5 (Prop_E6LUT_SLICEM_I2_O)
                                                      0.100     5.176 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/shiftreg[31]_i_2/O
                         net (fo=1, routed)           0.055     5.231    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/shiftreg[31]_i_2_n_0
    SLICE_X107Y66        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/shiftreg_reg[31]/D
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.219     1.684    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y81         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.708 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.544     3.252    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_tck
    SLICE_X107Y66        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/shiftreg_reg[31]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TDI
                            (internal pin)
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscanid_reg[31]/D
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        5.111ns  (logic 4.400ns (86.085%)  route 0.711ns (13.915%))
  Logic Levels:           2  (BSCANE2=1 LUT4=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.544ns (routing 0.470ns, distribution 1.074ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TDI
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TDI_TDI)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TDI
                         net (fo=4, routed)           0.658     4.958    dbg_hub/inst/BSCANID.u_xsdbm_id/TDI
    SLICE_X107Y69        LUT4 (Prop_A6LUT_SLICEM_I3_O)
                                                      0.100     5.058 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscanid[31]_i_1/O
                         net (fo=1, routed)           0.053     5.111    dbg_hub/inst/BSCANID.u_xsdbm_id/p_2_in[31]
    SLICE_X107Y69        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscanid_reg[31]/D
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.219     1.684    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y81         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.708 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.544     3.252    dbg_hub/inst/BSCANID.u_xsdbm_id/itck_i
    SLICE_X107Y69        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscanid_reg[31]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TDI
                            (internal pin)
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/bscanid_reg[31]/D
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        5.007ns  (logic 4.400ns (87.880%)  route 0.607ns (12.120%))
  Logic Levels:           2  (BSCANE2=1 LUT2=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.546ns (routing 0.470ns, distribution 1.076ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TDI
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TDI_TDI)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TDI
                         net (fo=4, routed)           0.548     4.848    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_tdi
    SLICE_X107Y64        LUT2 (Prop_B6LUT_SLICEM_I1_O)
                                                      0.100     4.948 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/bscanid[31]_i_2/O
                         net (fo=1, routed)           0.059     5.007    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/bscanid[31]_i_2_n_0
    SLICE_X107Y64        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/bscanid_reg[31]/D
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.219     1.684    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y81         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.708 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.546     3.254    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_tck
    SLICE_X107Y64        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/bscanid_reg[31]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TDI
                            (internal pin)
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/bscanid_reg[31]/D
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.816ns  (logic 0.506ns (62.022%)  route 0.310ns (37.978%))
  Logic Levels:           2  (BSCANE2=1 LUT2=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.093ns (routing 0.313ns, distribution 0.780ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TDI
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TDI_TDI)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TDI
                         net (fo=4, routed)           0.289     0.754    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_tdi
    SLICE_X107Y64        LUT2 (Prop_B6LUT_SLICEM_I1_O)
                                                      0.041     0.795 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/bscanid[31]_i_2/O
                         net (fo=1, routed)           0.021     0.816    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/bscanid[31]_i_2_n_0
    SLICE_X107Y64        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/bscanid_reg[31]/D
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.264     5.564    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y81         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     5.583 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.093     6.676    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_tck
    SLICE_X107Y64        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/bscanid_reg[31]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TDI
                            (internal pin)
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscanid_reg[31]/D
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.872ns  (logic 0.506ns (58.014%)  route 0.366ns (41.986%))
  Logic Levels:           2  (BSCANE2=1 LUT4=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.092ns (routing 0.313ns, distribution 0.779ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TDI
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TDI_TDI)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TDI
                         net (fo=4, routed)           0.348     0.813    dbg_hub/inst/BSCANID.u_xsdbm_id/TDI
    SLICE_X107Y69        LUT4 (Prop_A6LUT_SLICEM_I3_O)
                                                      0.041     0.854 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscanid[31]_i_1/O
                         net (fo=1, routed)           0.018     0.872    dbg_hub/inst/BSCANID.u_xsdbm_id/p_2_in[31]
    SLICE_X107Y69        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscanid_reg[31]/D
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.264     5.564    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y81         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     5.583 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.092     6.675    dbg_hub/inst/BSCANID.u_xsdbm_id/itck_i
    SLICE_X107Y69        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscanid_reg[31]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TDI
                            (internal pin)
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/shiftreg_reg[31]/D
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.928ns  (logic 0.505ns (54.406%)  route 0.423ns (45.594%))
  Logic Levels:           2  (BSCANE2=1 LUT5=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.090ns (routing 0.313ns, distribution 0.777ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TDI
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TDI_TDI)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TDI
                         net (fo=4, routed)           0.404     0.869    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_tdi
    SLICE_X107Y66        LUT5 (Prop_E6LUT_SLICEM_I2_O)
                                                      0.040     0.909 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/shiftreg[31]_i_2/O
                         net (fo=1, routed)           0.019     0.928    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/shiftreg[31]_i_2_n_0
    SLICE_X107Y66        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/shiftreg_reg[31]/D
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.264     5.564    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y81         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     5.583 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.090     6.673    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_tck
    SLICE_X107Y66        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/shiftreg_reg[31]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TDI
                            (internal pin)
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/iTDI_reg_reg/D
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.486ns  (logic 0.465ns (31.297%)  route 1.021ns (68.703%))
  Logic Levels:           1  (BSCANE2=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.084ns (routing 0.313ns, distribution 0.771ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TDI
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TDI_TDI)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TDI
                         net (fo=4, routed)           1.021     1.486    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/out
    SLICE_X107Y327       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/iTDI_reg_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.264     5.564    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y81         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     5.583 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.084     6.667    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/m_bscan_tck[0]
    SLICE_X107Y327       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/iTDI_reg_reg/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  
  To Clock:  sys_clk_ddr4_clk_p

Max Delay             2 Endpoints
Min Delay             2 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[1].gen_plle4.PLLE4_BASE_INST_OTHER/LOCKED
                            (internal pin)
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_async_riu_div_reg/D
                            (rising edge-triggered cell FDRE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.932ns  (logic 0.197ns (6.719%)  route 2.735ns (93.281%))
  Logic Levels:           2  (LUT3=2)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.548ns (routing 0.635ns, distribution 0.913ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    PLL_X0Y8             PLLE4_ADV                    0.000     0.000 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[1].gen_plle4.PLLE4_BASE_INST_OTHER/LOCKED
                         net (fo=1, routed)           1.606     1.606    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/pll_lock_i[1]
    SLICE_X81Y289        LUT3 (Prop_E6LUT_SLICEL_I2_O)
                                                      0.147     1.753 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/pll_lock__0/O
                         net (fo=1, routed)           0.401     2.154    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/pll_lock
    SLICE_X91Y294        LUT3 (Prop_G6LUT_SLICEL_I2_O)
                                                      0.050     2.204 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_async_riu_div_i_1/O
                         net (fo=1, routed)           0.728     2.932    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_async_riu_div_reg0
    SLICE_X91Y355        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_async_riu_div_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y4 (CLOCK_ROOT)    net (fo=18, routed)          1.548     2.463    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X91Y355        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_async_riu_div_reg/C

Slack:                    inf
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/LOCKED
                            (internal pin)
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_async_mb_reg/D
                            (rising edge-triggered cell FDRE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.501ns  (logic 0.110ns (7.326%)  route 1.391ns (92.674%))
  Logic Levels:           1  (LUT2=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.543ns (routing 0.635ns, distribution 0.908ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    MMCM_X0Y4            MMCME4_ADV                   0.000     0.000 f  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/LOCKED
                         net (fo=3, routed)           0.476     0.476    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_lock
    SLICE_X91Y294        LUT2 (Prop_D5LUT_SLICEL_I1_O)
                                                      0.110     0.586 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_async_mb_i_1/O
                         net (fo=1, routed)           0.915     1.501    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_async_mb_reg0
    SLICE_X92Y341        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_async_mb_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y4 (CLOCK_ROOT)    net (fo=18, routed)          1.543     2.458    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X92Y341        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_async_mb_reg/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/LOCKED
                            (internal pin)
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_async_riu_div_reg/D
                            (rising edge-triggered cell FDRE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.667ns  (logic 0.060ns (9.000%)  route 0.607ns (91.000%))
  Logic Levels:           1  (LUT3=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.092ns (routing 0.434ns, distribution 0.658ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    MMCM_X0Y4            MMCME4_ADV                   0.000     0.000 f  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/LOCKED
                         net (fo=3, routed)           0.250     0.250    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_lock
    SLICE_X91Y294        LUT3 (Prop_G6LUT_SLICEL_I0_O)
                                                      0.060     0.310 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_async_riu_div_i_1/O
                         net (fo=1, routed)           0.357     0.667    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_async_riu_div_reg0
    SLICE_X91Y355        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_async_riu_div_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y4 (CLOCK_ROOT)    net (fo=18, routed)          1.092     1.879    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X91Y355        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_async_riu_div_reg/C

Slack:                    inf
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/LOCKED
                            (internal pin)
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_async_mb_reg/D
                            (rising edge-triggered cell FDRE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.735ns  (logic 0.039ns (5.308%)  route 0.696ns (94.692%))
  Logic Levels:           1  (LUT2=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.087ns (routing 0.434ns, distribution 0.653ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    MMCM_X0Y4            MMCME4_ADV                   0.000     0.000 f  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/LOCKED
                         net (fo=3, routed)           0.242     0.242    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_lock
    SLICE_X91Y294        LUT2 (Prop_D5LUT_SLICEL_I1_O)
                                                      0.039     0.281 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_async_mb_i_1/O
                         net (fo=1, routed)           0.454     0.735    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_async_mb_reg0
    SLICE_X92Y341        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_async_mb_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y4 (CLOCK_ROOT)    net (fo=18, routed)          1.087     1.874    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X92Y341        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_async_mb_reg/C





