Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version      : Vivado v.2023.1 (lin64) Build 3865809 Sun May  7 15:04:56 MDT 2023
| Date              : Thu Nov 21 17:44:31 2024
| Host              : linux-139028 running 64-bit Debian GNU/Linux 12 (bookworm)
| Command           : report_timing_summary -max_paths 10 -report_unconstrained -file d_1_wrapper_timing_summary_routed.rpt -pb d_1_wrapper_timing_summary_routed.pb -rpx d_1_wrapper_timing_summary_routed.rpx -warn_on_violation
| Design            : d_1_wrapper
| Device            : xczu28dr-ffvg1517
| Speed File        : -2  PRODUCTION 1.30 05-03-2022
| Design State      : Routed
| Temperature Grade : E
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------

Timing Summary Report

------------------------------------------------------------------------------------------------
| Timer Settings
| --------------
------------------------------------------------------------------------------------------------

  Enable Multi Corner Analysis               :  Yes
  Enable Pessimism Removal                   :  Yes
  Pessimism Removal Resolution               :  Nearest Common Node
  Enable Input Delay Default Clock           :  No
  Enable Preset / Clear Arcs                 :  No
  Disable Flight Delays                      :  No
  Ignore I/O Paths                           :  No
  Timing Early Launch at Borrowing Latches   :  No
  Borrow Time for Max Delay Exceptions       :  Yes
  Merge Timing Exceptions                    :  Yes

  Corner  Analyze    Analyze    
  Name    Max Paths  Min Paths  
  ------  ---------  ---------  
  Slow    Yes        Yes        
  Fast    Yes        Yes        


------------------------------------------------------------------------------------------------
| Report Methodology
| ------------------
------------------------------------------------------------------------------------------------

Rule       Severity  Description                                 Violations  
---------  --------  ------------------------------------------  ----------  
LUTAR-1    Warning   LUT drives async reset alert                3           
TIMING-9   Warning   Unknown CDC Logic                           1           
TIMING-10  Warning   Missing property on synchronizer            1           
TIMING-18  Warning   Missing input or output delay               8           
CLKC-56    Advisory  MMCME4 with global clock driver has no LOC  1           

Note: This report is based on the most recent report_methodology run and may not be up-to-date. Run report_methodology on the current design for the latest report.



check_timing report

Table of Contents
-----------------
1. checking no_clock (0)
2. checking constant_clock (0)
3. checking pulse_width_clock (0)
4. checking unconstrained_internal_endpoints (0)
5. checking no_input_delay (0)
6. checking no_output_delay (8)
7. checking multiple_clock (0)
8. checking generated_clocks (0)
9. checking loops (0)
10. checking partial_input_delay (0)
11. checking partial_output_delay (0)
12. checking latch_loops (0)

1. checking no_clock (0)
------------------------
 There are 0 register/latch pins with no clock.


2. checking constant_clock (0)
------------------------------
 There are 0 register/latch pins with constant_clock.


3. checking pulse_width_clock (0)
---------------------------------
 There are 0 register/latch pins which need pulse_width check


4. checking unconstrained_internal_endpoints (0)
------------------------------------------------
 There are 0 pins that are not constrained for maximum delay.

 There are 0 pins that are not constrained for maximum delay due to constant clock.


5. checking no_input_delay (0)
------------------------------
 There are 0 input ports with no input delay specified.

 There are 0 input ports with no input delay but user has a false path constraint.


6. checking no_output_delay (8)
-------------------------------
 There are 8 ports with no output delay specified. (HIGH)

 There are 0 ports with no output delay but user has a false path constraint

 There are 0 ports with no output delay but with a timing clock defined on it or propagating through it


7. checking multiple_clock (0)
------------------------------
 There are 0 register/latch pins with multiple clocks.


8. checking generated_clocks (0)
--------------------------------
 There are 0 generated clocks that are not connected to a clock source.


9. checking loops (0)
---------------------
 There are 0 combinational loops in the design.


10. checking partial_input_delay (0)
------------------------------------
 There are 0 input ports with partial input delay specified.


11. checking partial_output_delay (0)
-------------------------------------
 There are 0 ports with partial output delay specified.


12. checking latch_loops (0)
----------------------------
 There are 0 combinational latch loops in the design through latch input



------------------------------------------------------------------------------------------------
| Design Timing Summary
| ---------------------
------------------------------------------------------------------------------------------------

    WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints     WPWS(ns)     TPWS(ns)  TPWS Failing Endpoints  TPWS Total Endpoints  
    -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------     --------     --------  ----------------------  --------------------  
      0.393        0.000                      0               138935        0.011        0.000                      0               138935        0.420        0.000                       0                 35888  


All user specified timing constraints are met.


------------------------------------------------------------------------------------------------
| Clock Summary
| -------------
------------------------------------------------------------------------------------------------

Clock                         Waveform(ns)         Period(ns)      Frequency(MHz)
-----                         ------------         ----------      --------------
RFADC0_CLK                    {0.000 3.906}        7.812           128.008         
  clk_out1_d_1_clk_adc0_x2_0  {0.000 1.953}        3.906           256.016         
RFADC0_CLK_dummy              {0.000 3.906}        7.812           128.008         
RFADC1_CLK                    {0.000 5.000}        10.000          100.000         
RFADC1_CLK_dummy              {0.000 5.000}        10.000          100.000         
RFADC1_FABCLK0                {0.000 5.000}        10.000          100.000         
RFADC1_FABCLK1                {0.000 5.000}        10.000          100.000         
RFADC1_FABCLK2                {0.000 5.000}        10.000          100.000         
RFADC1_FABCLK3                {0.000 5.000}        10.000          100.000         
RFADC2_CLK                    {0.000 5.000}        10.000          100.000         
RFADC2_CLK_dummy              {0.000 5.000}        10.000          100.000         
RFADC2_FABCLK0                {0.000 5.000}        10.000          100.000         
RFADC2_FABCLK1                {0.000 5.000}        10.000          100.000         
RFADC2_FABCLK2                {0.000 5.000}        10.000          100.000         
RFADC2_FABCLK3                {0.000 5.000}        10.000          100.000         
RFADC3_CLK                    {0.000 5.000}        10.000          100.000         
RFADC3_CLK_dummy              {0.000 5.000}        10.000          100.000         
RFADC3_FABCLK0                {0.000 5.000}        10.000          100.000         
RFADC3_FABCLK1                {0.000 5.000}        10.000          100.000         
RFADC3_FABCLK2                {0.000 5.000}        10.000          100.000         
RFADC3_FABCLK3                {0.000 5.000}        10.000          100.000         
RFDAC0_CLK                    {0.000 1.221}        2.441           409.668         
RFDAC1_CLK                    {0.000 5.000}        10.000          100.000         
RFDAC1_FABCLK0                {0.000 5.000}        10.000          100.000         
RFDAC1_FABCLK1                {0.000 5.000}        10.000          100.000         
RFDAC1_FABCLK2                {0.000 5.000}        10.000          100.000         
RFDAC1_FABCLK3                {0.000 5.000}        10.000          100.000         
clk_pl_0                      {0.000 5.000}        10.000          100.000         


------------------------------------------------------------------------------------------------
| Intra Clock Table
| -----------------
------------------------------------------------------------------------------------------------

Clock                             WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints     WPWS(ns)     TPWS(ns)  TPWS Failing Endpoints  TPWS Total Endpoints  
-----                             -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------     --------     --------  ----------------------  --------------------  
RFADC0_CLK                                                                                                                                                                      1.562        0.000                       0                     3  
  clk_out1_d_1_clk_adc0_x2_0        0.562        0.000                      0                 3896        0.013        0.000                      0                 3896        1.153        0.000                       0                  1947  
RFDAC0_CLK                          0.393        0.000                      0                23014        0.019        0.000                      0                23014        0.420        0.000                       0                  4814  
clk_pl_0                            0.701        0.000                      0               107775        0.011        0.000                      0               107775        3.400        0.000                       0                 29124  


------------------------------------------------------------------------------------------------
| Inter Clock Table
| -----------------
------------------------------------------------------------------------------------------------

From Clock    To Clock          WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints  
----------    --------          -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------  


------------------------------------------------------------------------------------------------
| Other Path Groups Table
| -----------------------
------------------------------------------------------------------------------------------------

Path Group                  From Clock                  To Clock                        WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints  
----------                  ----------                  --------                        -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------  
**async_default**           RFDAC0_CLK                  RFDAC0_CLK                        0.734        0.000                      0                  274        0.107        0.000                      0                  274  
**async_default**           clk_out1_d_1_clk_adc0_x2_0  clk_out1_d_1_clk_adc0_x2_0        0.526        0.000                      0                  166        0.351        0.000                      0                  166  
**async_default**           clk_pl_0                    clk_pl_0                          6.916        0.000                      0                 3810        0.156        0.000                      0                 3810  


------------------------------------------------------------------------------------------------
| User Ignored Path Table
| -----------------------
------------------------------------------------------------------------------------------------

Path Group                  From Clock                  To Clock                  
----------                  ----------                  --------                  
(none)                                                  RFDAC0_CLK                  
(none)                      clk_pl_0                    RFDAC0_CLK                  
(none)                                                  clk_out1_d_1_clk_adc0_x2_0  
(none)                      clk_pl_0                    clk_out1_d_1_clk_adc0_x2_0  
(none)                                                  clk_pl_0                    
(none)                      RFADC0_CLK                  clk_pl_0                    
(none)                      RFADC1_CLK                  clk_pl_0                    
(none)                      RFADC2_CLK                  clk_pl_0                    
(none)                      RFADC3_CLK                  clk_pl_0                    
(none)                      RFDAC0_CLK                  clk_pl_0                    
(none)                      RFDAC1_CLK                  clk_pl_0                    
(none)                      clk_out1_d_1_clk_adc0_x2_0  clk_pl_0                    
(none)                      clk_pl_0                    clk_pl_0                    


------------------------------------------------------------------------------------------------
| Unconstrained Path Table
| ------------------------
------------------------------------------------------------------------------------------------

Path Group                  From Clock                  To Clock                  
----------                  ----------                  --------                  
(none)                      RFDAC0_CLK                                              
(none)                      clk_pl_0                                                
(none)                                                  clk_out1_d_1_clk_adc0_x2_0  
(none)                                                  clk_pl_0                    


------------------------------------------------------------------------------------------------
| Timing Details
| --------------
------------------------------------------------------------------------------------------------


---------------------------------------------------------------------------------------------------
From Clock:  RFADC0_CLK
  To Clock:  RFADC0_CLK

Setup :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
PW    :            0  Failing Endpoints,  Worst Slack        1.562ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         RFADC0_CLK
Waveform(ns):       { 0.000 3.906 }
Period(ns):         7.812
Sources:            { d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX }

Check Type        Corner  Lib Pin            Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location       Pin
Min Period        n/a     HSADC/CLK_ADC      n/a            1.923         7.812       5.889      HSADC_X0Y0     d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
Min Period        n/a     BUFG_GT/I          n/a            1.290         7.812       6.522      BUFG_GT_X1Y18  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/I
Min Period        n/a     MMCME4_ADV/CLKIN1  n/a            1.071         7.812       6.741      MMCM_X0Y7      d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKIN1
Max Period        n/a     MMCME4_ADV/CLKIN1  n/a            100.000       7.812       92.188     MMCM_X0Y7      d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKIN1
Low Pulse Width   Slow    MMCME4_ADV/CLKIN1  n/a            2.344         3.906       1.562      MMCM_X0Y7      d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKIN1
Low Pulse Width   Fast    MMCME4_ADV/CLKIN1  n/a            2.344         3.906       1.562      MMCM_X0Y7      d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKIN1
Low Pulse Width   Slow    HSADC/CLK_ADC      n/a            0.800         3.906       3.106      HSADC_X0Y0     d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
Low Pulse Width   Fast    HSADC/CLK_ADC      n/a            0.800         3.906       3.106      HSADC_X0Y0     d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
High Pulse Width  Slow    MMCME4_ADV/CLKIN1  n/a            2.344         3.906       1.562      MMCM_X0Y7      d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKIN1
High Pulse Width  Fast    MMCME4_ADV/CLKIN1  n/a            2.344         3.906       1.562      MMCM_X0Y7      d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKIN1
High Pulse Width  Slow    HSADC/CLK_ADC      n/a            0.800         3.906       3.106      HSADC_X0Y0     d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
High Pulse Width  Fast    HSADC/CLK_ADC      n/a            0.800         3.906       3.106      HSADC_X0Y0     d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC



---------------------------------------------------------------------------------------------------
From Clock:  clk_out1_d_1_clk_adc0_x2_0
  To Clock:  clk_out1_d_1_clk_adc0_x2_0

Setup :            0  Failing Endpoints,  Worst Slack        0.562ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.013ns,  Total Violation        0.000ns
PW    :            0  Failing Endpoints,  Worst Slack        1.153ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.562ns  (required time - arrival time)
  Source:                 d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[1].TAG_CALC/ENCODER/output_register.bin_dt_r_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[1].TAG_CALC/trig_time_ck_r_reg[22]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             clk_out1_d_1_clk_adc0_x2_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.906ns  (clk_out1_d_1_clk_adc0_x2_0 rise@3.906ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        2.944ns  (logic 0.178ns (6.046%)  route 2.766ns (93.954%))
  Logic Levels:           1  (LUT6=1)
  Clock Path Skew:        -0.366ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    6.249ns = ( 10.155 - 3.906 ) 
    Source Clock Delay      (SCD):    6.479ns
    Clock Pessimism Removal (CPR):    -0.136ns
  Clock Uncertainty:      0.059ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.095ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      3.241ns (routing 1.963ns, distribution 1.278ns)
  Clock Net Delay (Destination): 2.690ns (routing 1.778ns, distribution 0.912ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y18        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=1, routed)           2.565     3.092    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.965 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     3.210    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.238 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=1945, routed)        3.241     6.479    d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[1].TAG_CALC/ENCODER/adc_clk
    SLICE_X111Y52        FDRE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[1].TAG_CALC/ENCODER/output_register.bin_dt_r_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X111Y52        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.079     6.558 r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[1].TAG_CALC/ENCODER/output_register.bin_dt_r_reg[1]/Q
                         net (fo=63, routed)          2.715     9.273    d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[1].TAG_CALC/ENCODER/output_register.bin_dt_r_reg[1]_0[1]
    SLICE_X73Y170        LUT6 (Prop_H6LUT_SLICEL_I3_O)
                                                      0.099     9.372 r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[1].TAG_CALC/ENCODER/trig_time_ck_r[22]_i_1__0/O
                         net (fo=1, routed)           0.051     9.423    d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[1].TAG_CALC/time_ck_s[22]
    SLICE_X73Y170        FDRE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[1].TAG_CALC/trig_time_ck_r_reg[22]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      3.906     3.906 r  
    HSADC_X0Y0           HSADC                        0.000     3.906 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     4.028 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     4.178    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y18        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     4.292 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=1, routed)           2.303     6.595    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     7.225 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.216     7.441    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     7.465 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=1945, routed)        2.690    10.155    d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[1].TAG_CALC/adc_clk
    SLICE_X73Y170        FDRE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[1].TAG_CALC/trig_time_ck_r_reg[22]/C
                         clock pessimism             -0.136    10.019    
                         clock uncertainty           -0.059     9.960    
    SLICE_X73Y170        FDRE (Setup_HFF_SLICEL_C_D)
                                                      0.025     9.985    d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[1].TAG_CALC/trig_time_ck_r_reg[22]
  -------------------------------------------------------------------
                         required time                          9.985    
                         arrival time                          -9.423    
  -------------------------------------------------------------------
                         slack                                  0.562    

Slack (MET) :             0.566ns  (required time - arrival time)
  Source:                 d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[1].TAG_CALC/ENCODER/output_register.bin_dt_r_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[1].TAG_CALC/trig_time_ck_r_reg[28]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             clk_out1_d_1_clk_adc0_x2_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.906ns  (clk_out1_d_1_clk_adc0_x2_0 rise@3.906ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        2.938ns  (logic 0.203ns (6.910%)  route 2.735ns (93.090%))
  Logic Levels:           1  (LUT6=1)
  Clock Path Skew:        -0.368ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    6.247ns = ( 10.153 - 3.906 ) 
    Source Clock Delay      (SCD):    6.479ns
    Clock Pessimism Removal (CPR):    -0.136ns
  Clock Uncertainty:      0.059ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.095ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      3.241ns (routing 1.963ns, distribution 1.278ns)
  Clock Net Delay (Destination): 2.688ns (routing 1.778ns, distribution 0.910ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y18        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=1, routed)           2.565     3.092    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.965 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     3.210    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.238 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=1945, routed)        3.241     6.479    d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[1].TAG_CALC/ENCODER/adc_clk
    SLICE_X111Y52        FDRE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[1].TAG_CALC/ENCODER/output_register.bin_dt_r_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X111Y52        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.079     6.558 r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[1].TAG_CALC/ENCODER/output_register.bin_dt_r_reg[1]/Q
                         net (fo=63, routed)          2.687     9.245    d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[1].TAG_CALC/ENCODER/output_register.bin_dt_r_reg[1]_0[1]
    SLICE_X73Y169        LUT6 (Prop_A6LUT_SLICEL_I3_O)
                                                      0.124     9.369 r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[1].TAG_CALC/ENCODER/trig_time_ck_r[28]_i_1__0/O
                         net (fo=1, routed)           0.048     9.417    d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[1].TAG_CALC/time_ck_s[28]
    SLICE_X73Y169        FDRE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[1].TAG_CALC/trig_time_ck_r_reg[28]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      3.906     3.906 r  
    HSADC_X0Y0           HSADC                        0.000     3.906 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     4.028 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     4.178    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y18        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     4.292 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=1, routed)           2.303     6.595    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     7.225 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.216     7.441    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     7.465 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=1945, routed)        2.688    10.153    d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[1].TAG_CALC/adc_clk
    SLICE_X73Y169        FDRE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[1].TAG_CALC/trig_time_ck_r_reg[28]/C
                         clock pessimism             -0.136    10.017    
                         clock uncertainty           -0.059     9.958    
    SLICE_X73Y169        FDRE (Setup_AFF_SLICEL_C_D)
                                                      0.025     9.983    d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[1].TAG_CALC/trig_time_ck_r_reg[28]
  -------------------------------------------------------------------
                         required time                          9.983    
                         arrival time                          -9.417    
  -------------------------------------------------------------------
                         slack                                  0.566    

Slack (MET) :             0.567ns  (required time - arrival time)
  Source:                 d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[1].TAG_CALC/ENCODER/output_register.bin_dt_r_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[1].TAG_CALC/trig_time_ck_r_reg[23]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             clk_out1_d_1_clk_adc0_x2_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.906ns  (clk_out1_d_1_clk_adc0_x2_0 rise@3.906ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        2.939ns  (logic 0.176ns (5.988%)  route 2.763ns (94.012%))
  Logic Levels:           1  (LUT6=1)
  Clock Path Skew:        -0.366ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    6.249ns = ( 10.155 - 3.906 ) 
    Source Clock Delay      (SCD):    6.479ns
    Clock Pessimism Removal (CPR):    -0.136ns
  Clock Uncertainty:      0.059ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.095ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      3.241ns (routing 1.963ns, distribution 1.278ns)
  Clock Net Delay (Destination): 2.690ns (routing 1.778ns, distribution 0.912ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y18        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=1, routed)           2.565     3.092    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.965 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     3.210    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.238 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=1945, routed)        3.241     6.479    d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[1].TAG_CALC/ENCODER/adc_clk
    SLICE_X111Y52        FDRE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[1].TAG_CALC/ENCODER/output_register.bin_dt_r_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X111Y52        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.079     6.558 r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[1].TAG_CALC/ENCODER/output_register.bin_dt_r_reg[1]/Q
                         net (fo=63, routed)          2.715     9.273    d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[1].TAG_CALC/ENCODER/output_register.bin_dt_r_reg[1]_0[1]
    SLICE_X73Y170        LUT6 (Prop_G6LUT_SLICEL_I3_O)
                                                      0.097     9.370 r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[1].TAG_CALC/ENCODER/trig_time_ck_r[23]_i_1__0/O
                         net (fo=1, routed)           0.048     9.418    d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[1].TAG_CALC/time_ck_s[23]
    SLICE_X73Y170        FDRE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[1].TAG_CALC/trig_time_ck_r_reg[23]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      3.906     3.906 r  
    HSADC_X0Y0           HSADC                        0.000     3.906 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     4.028 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     4.178    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y18        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     4.292 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=1, routed)           2.303     6.595    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     7.225 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.216     7.441    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     7.465 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=1945, routed)        2.690    10.155    d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[1].TAG_CALC/adc_clk
    SLICE_X73Y170        FDRE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[1].TAG_CALC/trig_time_ck_r_reg[23]/C
                         clock pessimism             -0.136    10.019    
                         clock uncertainty           -0.059     9.960    
    SLICE_X73Y170        FDRE (Setup_GFF_SLICEL_C_D)
                                                      0.025     9.985    d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[1].TAG_CALC/trig_time_ck_r_reg[23]
  -------------------------------------------------------------------
                         required time                          9.985    
                         arrival time                          -9.418    
  -------------------------------------------------------------------
                         slack                                  0.567    

Slack (MET) :             0.574ns  (required time - arrival time)
  Source:                 d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[1].TAG_CALC/ENCODER/output_register.bin_dt_r_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[1].TAG_CALC/trig_time_ck_r_reg[18]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             clk_out1_d_1_clk_adc0_x2_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.906ns  (clk_out1_d_1_clk_adc0_x2_0 rise@3.906ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        2.933ns  (logic 0.178ns (6.069%)  route 2.755ns (93.931%))
  Logic Levels:           1  (LUT6=1)
  Clock Path Skew:        -0.365ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    6.250ns = ( 10.156 - 3.906 ) 
    Source Clock Delay      (SCD):    6.479ns
    Clock Pessimism Removal (CPR):    -0.136ns
  Clock Uncertainty:      0.059ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.095ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      3.241ns (routing 1.963ns, distribution 1.278ns)
  Clock Net Delay (Destination): 2.691ns (routing 1.778ns, distribution 0.913ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y18        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=1, routed)           2.565     3.092    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.965 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     3.210    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.238 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=1945, routed)        3.241     6.479    d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[1].TAG_CALC/ENCODER/adc_clk
    SLICE_X111Y52        FDRE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[1].TAG_CALC/ENCODER/output_register.bin_dt_r_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X111Y52        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.079     6.558 r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[1].TAG_CALC/ENCODER/output_register.bin_dt_r_reg[1]/Q
                         net (fo=63, routed)          2.704     9.262    d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[1].TAG_CALC/ENCODER/output_register.bin_dt_r_reg[1]_0[1]
    SLICE_X71Y168        LUT6 (Prop_H6LUT_SLICEL_I3_O)
                                                      0.099     9.361 r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[1].TAG_CALC/ENCODER/trig_time_ck_r[18]_i_1__0/O
                         net (fo=1, routed)           0.051     9.412    d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[1].TAG_CALC/time_ck_s[18]
    SLICE_X71Y168        FDRE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[1].TAG_CALC/trig_time_ck_r_reg[18]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      3.906     3.906 r  
    HSADC_X0Y0           HSADC                        0.000     3.906 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     4.028 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     4.178    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y18        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     4.292 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=1, routed)           2.303     6.595    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     7.225 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.216     7.441    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     7.465 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=1945, routed)        2.691    10.156    d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[1].TAG_CALC/adc_clk
    SLICE_X71Y168        FDRE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[1].TAG_CALC/trig_time_ck_r_reg[18]/C
                         clock pessimism             -0.136    10.020    
                         clock uncertainty           -0.059     9.961    
    SLICE_X71Y168        FDRE (Setup_HFF_SLICEL_C_D)
                                                      0.025     9.986    d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[1].TAG_CALC/trig_time_ck_r_reg[18]
  -------------------------------------------------------------------
                         required time                          9.986    
                         arrival time                          -9.412    
  -------------------------------------------------------------------
                         slack                                  0.574    

Slack (MET) :             0.577ns  (required time - arrival time)
  Source:                 d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[1].TAG_CALC/ENCODER/output_register.bin_dt_r_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[1].TAG_CALC/trig_time_ck_r_reg[2]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             clk_out1_d_1_clk_adc0_x2_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.906ns  (clk_out1_d_1_clk_adc0_x2_0 rise@3.906ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        2.945ns  (logic 0.169ns (5.739%)  route 2.776ns (94.261%))
  Logic Levels:           1  (LUT6=1)
  Clock Path Skew:        -0.350ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    6.243ns = ( 10.149 - 3.906 ) 
    Source Clock Delay      (SCD):    6.457ns
    Clock Pessimism Removal (CPR):    -0.136ns
  Clock Uncertainty:      0.059ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.095ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      3.219ns (routing 1.963ns, distribution 1.256ns)
  Clock Net Delay (Destination): 2.684ns (routing 1.778ns, distribution 0.906ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y18        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=1, routed)           2.565     3.092    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.965 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     3.210    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.238 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=1945, routed)        3.219     6.457    d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[1].TAG_CALC/ENCODER/adc_clk
    SLICE_X106Y52        FDRE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[1].TAG_CALC/ENCODER/output_register.bin_dt_r_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X106Y52        FDRE (Prop_CFF_SLICEL_C_Q)
                                                      0.079     6.536 r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[1].TAG_CALC/ENCODER/output_register.bin_dt_r_reg[2]/Q
                         net (fo=46, routed)          2.725     9.261    d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[1].TAG_CALC/ENCODER/enc_s[2]
    SLICE_X71Y165        LUT6 (Prop_H6LUT_SLICEL_I4_O)
                                                      0.090     9.351 r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[1].TAG_CALC/ENCODER/trig_time_ck_r[2]_i_1__0/O
                         net (fo=1, routed)           0.051     9.402    d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[1].TAG_CALC/time_ck_s[2]
    SLICE_X71Y165        FDRE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[1].TAG_CALC/trig_time_ck_r_reg[2]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      3.906     3.906 r  
    HSADC_X0Y0           HSADC                        0.000     3.906 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     4.028 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     4.178    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y18        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     4.292 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=1, routed)           2.303     6.595    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     7.225 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.216     7.441    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     7.465 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=1945, routed)        2.684    10.149    d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[1].TAG_CALC/adc_clk
    SLICE_X71Y165        FDRE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[1].TAG_CALC/trig_time_ck_r_reg[2]/C
                         clock pessimism             -0.136    10.013    
                         clock uncertainty           -0.059     9.954    
    SLICE_X71Y165        FDRE (Setup_HFF_SLICEL_C_D)
                                                      0.025     9.979    d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[1].TAG_CALC/trig_time_ck_r_reg[2]
  -------------------------------------------------------------------
                         required time                          9.979    
                         arrival time                          -9.402    
  -------------------------------------------------------------------
                         slack                                  0.577    

Slack (MET) :             0.594ns  (required time - arrival time)
  Source:                 d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[1].TAG_CALC/ENCODER/output_register.bin_dt_r_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[1].TAG_CALC/trig_time_ck_r_reg[20]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             clk_out1_d_1_clk_adc0_x2_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.906ns  (clk_out1_d_1_clk_adc0_x2_0 rise@3.906ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        2.916ns  (logic 0.180ns (6.172%)  route 2.736ns (93.828%))
  Logic Levels:           1  (LUT6=1)
  Clock Path Skew:        -0.361ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    6.254ns = ( 10.160 - 3.906 ) 
    Source Clock Delay      (SCD):    6.479ns
    Clock Pessimism Removal (CPR):    -0.136ns
  Clock Uncertainty:      0.059ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.095ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      3.241ns (routing 1.963ns, distribution 1.278ns)
  Clock Net Delay (Destination): 2.695ns (routing 1.778ns, distribution 0.917ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y18        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=1, routed)           2.565     3.092    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.965 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     3.210    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.238 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=1945, routed)        3.241     6.479    d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[1].TAG_CALC/ENCODER/adc_clk
    SLICE_X111Y52        FDRE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[1].TAG_CALC/ENCODER/output_register.bin_dt_r_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X111Y52        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.079     6.558 r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[1].TAG_CALC/ENCODER/output_register.bin_dt_r_reg[1]/Q
                         net (fo=63, routed)          2.678     9.236    d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[1].TAG_CALC/ENCODER/output_register.bin_dt_r_reg[1]_0[1]
    SLICE_X72Y168        LUT6 (Prop_H6LUT_SLICEM_I3_O)
                                                      0.101     9.337 r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[1].TAG_CALC/ENCODER/trig_time_ck_r[20]_i_1__0/O
                         net (fo=1, routed)           0.058     9.395    d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[1].TAG_CALC/time_ck_s[20]
    SLICE_X72Y168        FDRE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[1].TAG_CALC/trig_time_ck_r_reg[20]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      3.906     3.906 r  
    HSADC_X0Y0           HSADC                        0.000     3.906 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     4.028 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     4.178    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y18        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     4.292 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=1, routed)           2.303     6.595    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     7.225 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.216     7.441    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     7.465 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=1945, routed)        2.695    10.160    d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[1].TAG_CALC/adc_clk
    SLICE_X72Y168        FDRE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[1].TAG_CALC/trig_time_ck_r_reg[20]/C
                         clock pessimism             -0.136    10.024    
                         clock uncertainty           -0.059     9.965    
    SLICE_X72Y168        FDRE (Setup_HFF_SLICEM_C_D)
                                                      0.025     9.990    d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[1].TAG_CALC/trig_time_ck_r_reg[20]
  -------------------------------------------------------------------
                         required time                          9.990    
                         arrival time                          -9.395    
  -------------------------------------------------------------------
                         slack                                  0.594    

Slack (MET) :             0.597ns  (required time - arrival time)
  Source:                 d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[1].TAG_CALC/ENCODER/output_register.bin_dt_r_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[1].TAG_CALC/trig_time_ck_r_reg[24]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             clk_out1_d_1_clk_adc0_x2_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.906ns  (clk_out1_d_1_clk_adc0_x2_0 rise@3.906ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        2.913ns  (logic 0.179ns (6.144%)  route 2.734ns (93.856%))
  Logic Levels:           1  (LUT6=1)
  Clock Path Skew:        -0.361ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    6.254ns = ( 10.160 - 3.906 ) 
    Source Clock Delay      (SCD):    6.479ns
    Clock Pessimism Removal (CPR):    -0.136ns
  Clock Uncertainty:      0.059ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.095ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      3.241ns (routing 1.963ns, distribution 1.278ns)
  Clock Net Delay (Destination): 2.695ns (routing 1.778ns, distribution 0.917ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y18        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=1, routed)           2.565     3.092    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.965 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     3.210    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.238 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=1945, routed)        3.241     6.479    d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[1].TAG_CALC/ENCODER/adc_clk
    SLICE_X111Y52        FDRE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[1].TAG_CALC/ENCODER/output_register.bin_dt_r_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X111Y52        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.079     6.558 r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[1].TAG_CALC/ENCODER/output_register.bin_dt_r_reg[1]/Q
                         net (fo=63, routed)          2.675     9.233    d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[1].TAG_CALC/ENCODER/output_register.bin_dt_r_reg[1]_0[1]
    SLICE_X72Y168        LUT6 (Prop_G6LUT_SLICEM_I3_O)
                                                      0.100     9.333 r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[1].TAG_CALC/ENCODER/trig_time_ck_r[24]_i_1__0/O
                         net (fo=1, routed)           0.059     9.392    d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[1].TAG_CALC/time_ck_s[24]
    SLICE_X72Y168        FDRE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[1].TAG_CALC/trig_time_ck_r_reg[24]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      3.906     3.906 r  
    HSADC_X0Y0           HSADC                        0.000     3.906 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     4.028 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     4.178    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y18        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     4.292 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=1, routed)           2.303     6.595    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     7.225 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.216     7.441    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     7.465 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=1945, routed)        2.695    10.160    d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[1].TAG_CALC/adc_clk
    SLICE_X72Y168        FDRE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[1].TAG_CALC/trig_time_ck_r_reg[24]/C
                         clock pessimism             -0.136    10.024    
                         clock uncertainty           -0.059     9.965    
    SLICE_X72Y168        FDRE (Setup_GFF_SLICEM_C_D)
                                                      0.025     9.990    d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[1].TAG_CALC/trig_time_ck_r_reg[24]
  -------------------------------------------------------------------
                         required time                          9.990    
                         arrival time                          -9.392    
  -------------------------------------------------------------------
                         slack                                  0.597    

Slack (MET) :             0.630ns  (required time - arrival time)
  Source:                 d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[1].TAG_CALC/ENCODER/output_register.bin_dt_r_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[1].TAG_CALC/trig_time_ck_r_reg[3]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             clk_out1_d_1_clk_adc0_x2_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.906ns  (clk_out1_d_1_clk_adc0_x2_0 rise@3.906ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        2.892ns  (logic 0.227ns (7.850%)  route 2.665ns (92.150%))
  Logic Levels:           1  (LUT6=1)
  Clock Path Skew:        -0.350ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    6.243ns = ( 10.149 - 3.906 ) 
    Source Clock Delay      (SCD):    6.457ns
    Clock Pessimism Removal (CPR):    -0.136ns
  Clock Uncertainty:      0.059ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.095ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      3.219ns (routing 1.963ns, distribution 1.256ns)
  Clock Net Delay (Destination): 2.684ns (routing 1.778ns, distribution 0.906ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y18        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=1, routed)           2.565     3.092    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.965 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     3.210    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.238 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=1945, routed)        3.219     6.457    d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[1].TAG_CALC/ENCODER/adc_clk
    SLICE_X106Y52        FDRE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[1].TAG_CALC/ENCODER/output_register.bin_dt_r_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X106Y52        FDRE (Prop_CFF_SLICEL_C_Q)
                                                      0.079     6.536 r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[1].TAG_CALC/ENCODER/output_register.bin_dt_r_reg[2]/Q
                         net (fo=46, routed)          2.598     9.134    d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[1].TAG_CALC/ENCODER/enc_s[2]
    SLICE_X72Y165        LUT6 (Prop_F6LUT_SLICEM_I4_O)
                                                      0.148     9.282 r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[1].TAG_CALC/ENCODER/trig_time_ck_r[3]_i_1__0/O
                         net (fo=1, routed)           0.067     9.349    d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[1].TAG_CALC/time_ck_s[3]
    SLICE_X72Y165        FDRE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[1].TAG_CALC/trig_time_ck_r_reg[3]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      3.906     3.906 r  
    HSADC_X0Y0           HSADC                        0.000     3.906 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     4.028 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     4.178    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y18        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     4.292 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=1, routed)           2.303     6.595    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     7.225 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.216     7.441    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     7.465 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=1945, routed)        2.684    10.149    d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[1].TAG_CALC/adc_clk
    SLICE_X72Y165        FDRE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[1].TAG_CALC/trig_time_ck_r_reg[3]/C
                         clock pessimism             -0.136    10.013    
                         clock uncertainty           -0.059     9.953    
    SLICE_X72Y165        FDRE (Setup_FFF_SLICEM_C_D)
                                                      0.025     9.978    d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[1].TAG_CALC/trig_time_ck_r_reg[3]
  -------------------------------------------------------------------
                         required time                          9.978    
                         arrival time                          -9.349    
  -------------------------------------------------------------------
                         slack                                  0.630    

Slack (MET) :             0.633ns  (required time - arrival time)
  Source:                 d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[1].TAG_CALC/ENCODER/output_register.bin_dt_r_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[1].TAG_CALC/trig_time_ck_r_reg[10]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             clk_out1_d_1_clk_adc0_x2_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.906ns  (clk_out1_d_1_clk_adc0_x2_0 rise@3.906ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        2.898ns  (logic 0.231ns (7.970%)  route 2.667ns (92.030%))
  Logic Levels:           1  (LUT6=1)
  Clock Path Skew:        -0.340ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    6.253ns = ( 10.159 - 3.906 ) 
    Source Clock Delay      (SCD):    6.457ns
    Clock Pessimism Removal (CPR):    -0.136ns
  Clock Uncertainty:      0.059ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.095ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      3.219ns (routing 1.963ns, distribution 1.256ns)
  Clock Net Delay (Destination): 2.694ns (routing 1.778ns, distribution 0.916ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y18        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=1, routed)           2.565     3.092    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.965 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     3.210    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.238 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=1945, routed)        3.219     6.457    d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[1].TAG_CALC/ENCODER/adc_clk
    SLICE_X106Y52        FDRE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[1].TAG_CALC/ENCODER/output_register.bin_dt_r_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X106Y52        FDRE (Prop_CFF_SLICEL_C_Q)
                                                      0.079     6.536 r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[1].TAG_CALC/ENCODER/output_register.bin_dt_r_reg[2]/Q
                         net (fo=46, routed)          2.609     9.145    d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[1].TAG_CALC/ENCODER/enc_s[2]
    SLICE_X72Y167        LUT6 (Prop_H6LUT_SLICEM_I4_O)
                                                      0.152     9.297 r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[1].TAG_CALC/ENCODER/trig_time_ck_r[10]_i_1__0/O
                         net (fo=1, routed)           0.058     9.355    d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[1].TAG_CALC/time_ck_s[10]
    SLICE_X72Y167        FDRE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[1].TAG_CALC/trig_time_ck_r_reg[10]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      3.906     3.906 r  
    HSADC_X0Y0           HSADC                        0.000     3.906 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     4.028 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     4.178    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y18        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     4.292 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=1, routed)           2.303     6.595    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     7.225 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.216     7.441    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     7.465 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=1945, routed)        2.694    10.159    d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[1].TAG_CALC/adc_clk
    SLICE_X72Y167        FDRE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[1].TAG_CALC/trig_time_ck_r_reg[10]/C
                         clock pessimism             -0.136    10.023    
                         clock uncertainty           -0.059     9.964    
    SLICE_X72Y167        FDRE (Setup_HFF_SLICEM_C_D)
                                                      0.025     9.989    d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[1].TAG_CALC/trig_time_ck_r_reg[10]
  -------------------------------------------------------------------
                         required time                          9.989    
                         arrival time                          -9.355    
  -------------------------------------------------------------------
                         slack                                  0.633    

Slack (MET) :             0.634ns  (required time - arrival time)
  Source:                 d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[1].TAG_CALC/ENCODER/output_register.bin_dt_r_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[1].TAG_CALC/trig_time_ck_r_reg[4]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             clk_out1_d_1_clk_adc0_x2_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.906ns  (clk_out1_d_1_clk_adc0_x2_0 rise@3.906ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        2.892ns  (logic 0.168ns (5.810%)  route 2.724ns (94.190%))
  Logic Levels:           1  (LUT6=1)
  Clock Path Skew:        -0.346ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    6.247ns = ( 10.153 - 3.906 ) 
    Source Clock Delay      (SCD):    6.457ns
    Clock Pessimism Removal (CPR):    -0.136ns
  Clock Uncertainty:      0.059ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.095ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      3.219ns (routing 1.963ns, distribution 1.256ns)
  Clock Net Delay (Destination): 2.688ns (routing 1.778ns, distribution 0.910ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y18        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=1, routed)           2.565     3.092    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.965 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     3.210    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.238 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=1945, routed)        3.219     6.457    d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[1].TAG_CALC/ENCODER/adc_clk
    SLICE_X106Y52        FDRE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[1].TAG_CALC/ENCODER/output_register.bin_dt_r_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X106Y52        FDRE (Prop_CFF_SLICEL_C_Q)
                                                      0.079     6.536 r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[1].TAG_CALC/ENCODER/output_register.bin_dt_r_reg[2]/Q
                         net (fo=46, routed)          2.675     9.211    d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[1].TAG_CALC/ENCODER/enc_s[2]
    SLICE_X71Y167        LUT6 (Prop_D6LUT_SLICEL_I4_O)
                                                      0.089     9.300 r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[1].TAG_CALC/ENCODER/trig_time_ck_r[4]_i_1__0/O
                         net (fo=1, routed)           0.049     9.349    d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[1].TAG_CALC/time_ck_s[4]
    SLICE_X71Y167        FDRE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[1].TAG_CALC/trig_time_ck_r_reg[4]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      3.906     3.906 r  
    HSADC_X0Y0           HSADC                        0.000     3.906 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     4.028 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     4.178    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y18        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     4.292 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=1, routed)           2.303     6.595    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     7.225 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.216     7.441    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     7.465 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=1945, routed)        2.688    10.153    d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[1].TAG_CALC/adc_clk
    SLICE_X71Y167        FDRE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[1].TAG_CALC/trig_time_ck_r_reg[4]/C
                         clock pessimism             -0.136    10.017    
                         clock uncertainty           -0.059     9.958    
    SLICE_X71Y167        FDRE (Setup_DFF_SLICEL_C_D)
                                                      0.025     9.983    d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[1].TAG_CALC/trig_time_ck_r_reg[4]
  -------------------------------------------------------------------
                         required time                          9.983    
                         arrival time                          -9.349    
  -------------------------------------------------------------------
                         slack                                  0.634    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.013ns  (arrival time - required time)
  Source:                 d_1_i/qick_time_tagger_0/inst/QTT/time_cnt_reg[14]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/time_ck_r_reg[14]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             clk_out1_d_1_clk_adc0_x2_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        0.173ns  (logic 0.058ns (33.515%)  route 0.115ns (66.485%))
  Logic Levels:           0  
  Clock Path Skew:        0.098ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    6.265ns
    Source Clock Delay      (SCD):    6.250ns
    Clock Pessimism Removal (CPR):    -0.083ns
  Clock Net Delay (Source):      2.691ns (routing 1.778ns, distribution 0.913ns)
  Clock Net Delay (Destination): 3.027ns (routing 1.963ns, distribution 1.064ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y18        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=1, routed)           2.303     2.689    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     3.319 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.216     3.535    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.559 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=1945, routed)        2.691     6.250    d_1_i/qick_time_tagger_0/inst/QTT/adc_clk
    SLICE_X70Y167        FDRE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/time_cnt_reg[14]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X70Y167        FDRE (Prop_GFF_SLICEM_C_Q)
                                                      0.058     6.308 r  d_1_i/qick_time_tagger_0/inst/QTT/time_cnt_reg[14]/Q
                         net (fo=2, routed)           0.115     6.423    d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/time_ck_i[14]
    SLICE_X72Y166        FDRE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/time_ck_r_reg[14]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y18        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=1, routed)           2.565     3.092    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.965 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     3.210    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.238 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=1945, routed)        3.027     6.265    d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/adc_clk
    SLICE_X72Y166        FDRE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/time_ck_r_reg[14]/C
                         clock pessimism              0.083     6.348    
    SLICE_X72Y166        FDRE (Hold_HFF2_SLICEM_C_D)
                                                      0.062     6.410    d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/time_ck_r_reg[14]
  -------------------------------------------------------------------
                         required time                         -6.410    
                         arrival time                           6.423    
  -------------------------------------------------------------------
                         slack                                  0.013    

Slack (MET) :             0.022ns  (arrival time - required time)
  Source:                 d_1_i/axis_register_slice_5/inst/axisc_register_slice_0/storage_data1_reg[35]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/qick_time_tagger_0/inst/QTT/SMP.SMP_MEM/smp_wr_dt_reg[35]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             clk_out1_d_1_clk_adc0_x2_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        0.185ns  (logic 0.058ns (31.386%)  route 0.127ns (68.614%))
  Logic Levels:           0  
  Clock Path Skew:        0.100ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    6.360ns
    Source Clock Delay      (SCD):    6.338ns
    Clock Pessimism Removal (CPR):    -0.078ns
  Clock Net Delay (Source):      2.779ns (routing 1.778ns, distribution 1.001ns)
  Clock Net Delay (Destination): 3.122ns (routing 1.963ns, distribution 1.159ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y18        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=1, routed)           2.303     2.689    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     3.319 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.216     3.535    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.559 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=1945, routed)        2.779     6.338    d_1_i/axis_register_slice_5/inst/axisc_register_slice_0/aclk
    SLICE_X90Y78         FDRE                                         r  d_1_i/axis_register_slice_5/inst/axisc_register_slice_0/storage_data1_reg[35]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X90Y78         FDRE (Prop_DFF_SLICEM_C_Q)
                                                      0.058     6.396 r  d_1_i/axis_register_slice_5/inst/axisc_register_slice_0/storage_data1_reg[35]/Q
                         net (fo=9, routed)           0.127     6.522    d_1_i/qick_time_tagger_0/inst/QTT/SMP.SMP_MEM/adc0_s_axis_tdata_i[35]
    SLICE_X88Y78         FDRE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/SMP.SMP_MEM/smp_wr_dt_reg[35]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y18        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=1, routed)           2.565     3.092    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.965 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     3.210    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.238 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=1945, routed)        3.122     6.360    d_1_i/qick_time_tagger_0/inst/QTT/SMP.SMP_MEM/adc_clk
    SLICE_X88Y78         FDRE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/SMP.SMP_MEM/smp_wr_dt_reg[35]/C
                         clock pessimism              0.078     6.438    
    SLICE_X88Y78         FDRE (Hold_CFF2_SLICEL_C_D)
                                                      0.062     6.500    d_1_i/qick_time_tagger_0/inst/QTT/SMP.SMP_MEM/smp_wr_dt_reg[35]
  -------------------------------------------------------------------
                         required time                         -6.500    
                         arrival time                           6.522    
  -------------------------------------------------------------------
                         slack                                  0.022    

Slack (MET) :             0.029ns  (arrival time - required time)
  Source:                 d_1_i/axis_register_slice_6/inst/axisc_register_slice_0/storage_data2_reg[63]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/axis_register_slice_6/inst/axisc_register_slice_0/storage_data1_reg[63]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             clk_out1_d_1_clk_adc0_x2_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        0.181ns  (logic 0.097ns (53.591%)  route 0.084ns (46.409%))
  Logic Levels:           1  (LUT4=1)
  Clock Path Skew:        0.092ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    6.508ns
    Source Clock Delay      (SCD):    6.480ns
    Clock Pessimism Removal (CPR):    -0.064ns
  Clock Net Delay (Source):      2.921ns (routing 1.778ns, distribution 1.143ns)
  Clock Net Delay (Destination): 3.270ns (routing 1.963ns, distribution 1.307ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y18        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=1, routed)           2.303     2.689    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     3.319 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.216     3.535    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.559 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=1945, routed)        2.921     6.480    d_1_i/axis_register_slice_6/inst/axisc_register_slice_0/aclk
    SLICE_X115Y49        FDRE                                         r  d_1_i/axis_register_slice_6/inst/axisc_register_slice_0/storage_data2_reg[63]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X115Y49        FDRE (Prop_DFF2_SLICEM_C_Q)
                                                      0.061     6.541 r  d_1_i/axis_register_slice_6/inst/axisc_register_slice_0/storage_data2_reg[63]/Q
                         net (fo=1, routed)           0.060     6.601    d_1_i/axis_register_slice_6/inst/axisc_register_slice_0/storage_data2[63]
    SLICE_X114Y49        LUT4 (Prop_H6LUT_SLICEL_I0_O)
                                                      0.036     6.637 r  d_1_i/axis_register_slice_6/inst/axisc_register_slice_0/storage_data1[63]_i_1/O
                         net (fo=1, routed)           0.024     6.661    d_1_i/axis_register_slice_6/inst/axisc_register_slice_0/p_0_in[63]
    SLICE_X114Y49        FDRE                                         r  d_1_i/axis_register_slice_6/inst/axisc_register_slice_0/storage_data1_reg[63]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y18        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=1, routed)           2.565     3.092    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.965 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     3.210    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.238 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=1945, routed)        3.270     6.508    d_1_i/axis_register_slice_6/inst/axisc_register_slice_0/aclk
    SLICE_X114Y49        FDRE                                         r  d_1_i/axis_register_slice_6/inst/axisc_register_slice_0/storage_data1_reg[63]/C
                         clock pessimism              0.064     6.572    
    SLICE_X114Y49        FDRE (Hold_HFF_SLICEL_C_D)
                                                      0.060     6.632    d_1_i/axis_register_slice_6/inst/axisc_register_slice_0/storage_data1_reg[63]
  -------------------------------------------------------------------
                         required time                         -6.632    
                         arrival time                           6.661    
  -------------------------------------------------------------------
                         slack                                  0.029    

Slack (MET) :             0.030ns  (arrival time - required time)
  Source:                 d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/TAG[1].MEM/FIFO_PUSH/rd_gptr_rcd_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/TAG[1].MEM/FIFO_PUSH/rd_gptr_r_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             clk_out1_d_1_clk_adc0_x2_0
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        0.082ns  (logic 0.039ns (47.561%)  route 0.043ns (52.439%))
  Logic Levels:           0  
  Clock Path Skew:        0.006ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.675ns
    Source Clock Delay      (SCD):    3.707ns
    Clock Pessimism Removal (CPR):    -0.038ns
  Clock Net Delay (Source):      1.646ns (routing 1.074ns, distribution 0.572ns)
  Clock Net Delay (Destination): 1.858ns (routing 1.208ns, distribution 0.650ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y18        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=1, routed)           1.405     1.668    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.898 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     2.044    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.061 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=1945, routed)        1.646     3.707    d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/TAG[1].MEM/FIFO_PUSH/adc_clk
    SLICE_X71Y155        FDRE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/TAG[1].MEM/FIFO_PUSH/rd_gptr_rcd_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X71Y155        FDRE (Prop_GFF_SLICEL_C_Q)
                                                      0.039     3.746 r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/TAG[1].MEM/FIFO_PUSH/rd_gptr_rcd_reg[0]/Q
                         net (fo=1, routed)           0.043     3.789    d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/TAG[1].MEM/FIFO_PUSH/rd_gptr_rcd[0]
    SLICE_X71Y155        FDRE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/TAG[1].MEM/FIFO_PUSH/rd_gptr_r_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y18        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=1, routed)           1.575     1.927    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.632 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.798    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.817 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=1945, routed)        1.858     3.675    d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/TAG[1].MEM/FIFO_PUSH/adc_clk
    SLICE_X71Y155        FDRE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/TAG[1].MEM/FIFO_PUSH/rd_gptr_r_reg[0]/C
                         clock pessimism              0.038     3.713    
    SLICE_X71Y155        FDRE (Hold_EFF_SLICEL_C_D)
                                                      0.046     3.759    d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/TAG[1].MEM/FIFO_PUSH/rd_gptr_r_reg[0]
  -------------------------------------------------------------------
                         required time                         -3.759    
                         arrival time                           3.789    
  -------------------------------------------------------------------
                         slack                                  0.030    

Slack (MET) :             0.032ns  (arrival time - required time)
  Source:                 d_1_i/qick_time_tagger_0/inst/QTT/time_cnt_reg[5]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/time_ck_r_reg[5]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             clk_out1_d_1_clk_adc0_x2_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        0.131ns  (logic 0.057ns (43.534%)  route 0.074ns (56.466%))
  Logic Levels:           0  
  Clock Path Skew:        0.037ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    6.261ns
    Source Clock Delay      (SCD):    6.250ns
    Clock Pessimism Removal (CPR):    -0.026ns
  Clock Net Delay (Source):      2.691ns (routing 1.778ns, distribution 0.913ns)
  Clock Net Delay (Destination): 3.023ns (routing 1.963ns, distribution 1.060ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y18        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=1, routed)           2.303     2.689    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     3.319 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.216     3.535    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.559 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=1945, routed)        2.691     6.250    d_1_i/qick_time_tagger_0/inst/QTT/adc_clk
    SLICE_X70Y166        FDRE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/time_cnt_reg[5]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X70Y166        FDRE (Prop_FFF_SLICEM_C_Q)
                                                      0.057     6.307 r  d_1_i/qick_time_tagger_0/inst/QTT/time_cnt_reg[5]/Q
                         net (fo=2, routed)           0.074     6.381    d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/time_ck_i[5]
    SLICE_X71Y166        FDRE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/time_ck_r_reg[5]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y18        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=1, routed)           2.565     3.092    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.965 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     3.210    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.238 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=1945, routed)        3.023     6.261    d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/adc_clk
    SLICE_X71Y166        FDRE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/time_ck_r_reg[5]/C
                         clock pessimism              0.026     6.287    
    SLICE_X71Y166        FDRE (Hold_GFF2_SLICEL_C_D)
                                                      0.062     6.349    d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/time_ck_r_reg[5]
  -------------------------------------------------------------------
                         required time                         -6.349    
                         arrival time                           6.381    
  -------------------------------------------------------------------
                         slack                                  0.032    

Slack (MET) :             0.032ns  (arrival time - required time)
  Source:                 d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/time_ck_r_reg[4]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[1].TAG_CALC/time_ck_2r_reg[4]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             clk_out1_d_1_clk_adc0_x2_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        0.142ns  (logic 0.059ns (41.437%)  route 0.083ns (58.563%))
  Logic Levels:           0  
  Clock Path Skew:        0.050ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    6.262ns
    Source Clock Delay      (SCD):    6.249ns
    Clock Pessimism Removal (CPR):    -0.037ns
  Clock Net Delay (Source):      2.690ns (routing 1.778ns, distribution 0.912ns)
  Clock Net Delay (Destination): 3.024ns (routing 1.963ns, distribution 1.061ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y18        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=1, routed)           2.303     2.689    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     3.319 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.216     3.535    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.559 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=1945, routed)        2.690     6.249    d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/adc_clk
    SLICE_X71Y166        FDRE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/time_ck_r_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X71Y166        FDRE (Prop_HFF2_SLICEL_C_Q)
                                                      0.059     6.308 r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/time_ck_r_reg[4]/Q
                         net (fo=3, routed)           0.083     6.391    d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[1].TAG_CALC/time_ck_r[4]
    SLICE_X71Y167        FDRE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[1].TAG_CALC/time_ck_2r_reg[4]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y18        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=1, routed)           2.565     3.092    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.965 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     3.210    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.238 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=1945, routed)        3.024     6.262    d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[1].TAG_CALC/adc_clk
    SLICE_X71Y167        FDRE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[1].TAG_CALC/time_ck_2r_reg[4]/C
                         clock pessimism              0.037     6.299    
    SLICE_X71Y167        FDRE (Hold_EFF_SLICEL_C_D)
                                                      0.060     6.359    d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[1].TAG_CALC/time_ck_2r_reg[4]
  -------------------------------------------------------------------
                         required time                         -6.359    
                         arrival time                           6.391    
  -------------------------------------------------------------------
                         slack                                  0.032    

Slack (MET) :             0.034ns  (arrival time - required time)
  Source:                 d_1_i/qick_time_tagger_0/inst/QTT/SMP.SMP_MEM/smp_wr_dt_r_reg[117]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/qick_time_tagger_0/inst/QTT/SMP.SMP_MEM/smp_wr_dt_2r_reg[117]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             clk_out1_d_1_clk_adc0_x2_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        0.178ns  (logic 0.060ns (33.708%)  route 0.118ns (66.292%))
  Logic Levels:           0  
  Clock Path Skew:        0.084ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    6.325ns
    Source Clock Delay      (SCD):    6.319ns
    Clock Pessimism Removal (CPR):    -0.078ns
  Clock Net Delay (Source):      2.760ns (routing 1.778ns, distribution 0.982ns)
  Clock Net Delay (Destination): 3.087ns (routing 1.963ns, distribution 1.124ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y18        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=1, routed)           2.303     2.689    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     3.319 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.216     3.535    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.559 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=1945, routed)        2.760     6.319    d_1_i/qick_time_tagger_0/inst/QTT/SMP.SMP_MEM/adc_clk
    SLICE_X86Y88         FDRE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/SMP.SMP_MEM/smp_wr_dt_r_reg[117]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X86Y88         FDRE (Prop_EFF2_SLICEM_C_Q)
                                                      0.060     6.379 r  d_1_i/qick_time_tagger_0/inst/QTT/SMP.SMP_MEM/smp_wr_dt_r_reg[117]/Q
                         net (fo=1, routed)           0.118     6.497    d_1_i/qick_time_tagger_0/inst/QTT/SMP.SMP_MEM/smp_wr_dt_r[117]
    SLICE_X85Y87         FDRE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/SMP.SMP_MEM/smp_wr_dt_2r_reg[117]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y18        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=1, routed)           2.565     3.092    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.965 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     3.210    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.238 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=1945, routed)        3.087     6.325    d_1_i/qick_time_tagger_0/inst/QTT/SMP.SMP_MEM/adc_clk
    SLICE_X85Y87         FDRE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/SMP.SMP_MEM/smp_wr_dt_2r_reg[117]/C
                         clock pessimism              0.078     6.403    
    SLICE_X85Y87         FDRE (Hold_EFF_SLICEL_C_D)
                                                      0.060     6.463    d_1_i/qick_time_tagger_0/inst/QTT/SMP.SMP_MEM/smp_wr_dt_2r_reg[117]
  -------------------------------------------------------------------
                         required time                         -6.463    
                         arrival time                           6.497    
  -------------------------------------------------------------------
                         slack                                  0.034    

Slack (MET) :             0.035ns  (arrival time - required time)
  Source:                 d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/time_ck_r_reg[11]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[1].TAG_CALC/time_ck_2r_reg[11]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             clk_out1_d_1_clk_adc0_x2_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        0.146ns  (logic 0.060ns (41.101%)  route 0.086ns (58.898%))
  Logic Levels:           0  
  Clock Path Skew:        0.050ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    6.267ns
    Source Clock Delay      (SCD):    6.253ns
    Clock Pessimism Removal (CPR):    -0.036ns
  Clock Net Delay (Source):      2.694ns (routing 1.778ns, distribution 0.916ns)
  Clock Net Delay (Destination): 3.029ns (routing 1.963ns, distribution 1.066ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y18        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=1, routed)           2.303     2.689    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     3.319 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.216     3.535    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.559 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=1945, routed)        2.694     6.253    d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/adc_clk
    SLICE_X72Y167        FDRE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/time_ck_r_reg[11]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X72Y167        FDRE (Prop_GFF2_SLICEM_C_Q)
                                                      0.060     6.313 r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[0].TAG_CALC/time_ck_r_reg[11]/Q
                         net (fo=3, routed)           0.086     6.399    d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[1].TAG_CALC/time_ck_r[11]
    SLICE_X72Y166        FDRE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[1].TAG_CALC/time_ck_2r_reg[11]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y18        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=1, routed)           2.565     3.092    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.965 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     3.210    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.238 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=1945, routed)        3.029     6.267    d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[1].TAG_CALC/adc_clk
    SLICE_X72Y166        FDRE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[1].TAG_CALC/time_ck_2r_reg[11]/C
                         clock pessimism              0.036     6.303    
    SLICE_X72Y166        FDRE (Hold_DFF2_SLICEM_C_D)
                                                      0.061     6.364    d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[1].TAG_CALC/time_ck_2r_reg[11]
  -------------------------------------------------------------------
                         required time                         -6.364    
                         arrival time                           6.399    
  -------------------------------------------------------------------
                         slack                                  0.035    

Slack (MET) :             0.036ns  (arrival time - required time)
  Source:                 d_1_i/qick_time_tagger_0/inst/QTT/SMP.SMP_MEM/smp_wr_dt_3r_reg[57]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/qick_time_tagger_0/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/WR_SMP_FIFO/fifo_mem/mem_reg_0/DINBDIN[25]
                            (rising edge-triggered cell RAMB36E2 clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             clk_out1_d_1_clk_adc0_x2_0
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        0.146ns  (logic 0.039ns (26.712%)  route 0.107ns (73.288%))
  Logic Levels:           0  
  Clock Path Skew:        0.115ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.805ns
    Source Clock Delay      (SCD):    3.764ns
    Clock Pessimism Removal (CPR):    -0.073ns
  Clock Net Delay (Source):      1.703ns (routing 1.074ns, distribution 0.629ns)
  Clock Net Delay (Destination): 1.988ns (routing 1.208ns, distribution 0.780ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y18        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=1, routed)           1.405     1.668    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.898 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     2.044    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.061 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=1945, routed)        1.703     3.764    d_1_i/qick_time_tagger_0/inst/QTT/SMP.SMP_MEM/adc_clk
    SLICE_X89Y79         FDRE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/SMP.SMP_MEM/smp_wr_dt_3r_reg[57]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X89Y79         FDRE (Prop_GFF2_SLICEM_C_Q)
                                                      0.039     3.803 r  d_1_i/qick_time_tagger_0/inst/QTT/SMP.SMP_MEM/smp_wr_dt_3r_reg[57]/Q
                         net (fo=1, routed)           0.107     3.910    d_1_i/qick_time_tagger_0/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/WR_SMP_FIFO/fifo_mem/mem_reg_1_0[57]
    RAMB36_X8Y15         RAMB36E2                                     r  d_1_i/qick_time_tagger_0/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/WR_SMP_FIFO/fifo_mem/mem_reg_0/DINBDIN[25]
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y18        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=1, routed)           1.575     1.927    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.632 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.798    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.817 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=1945, routed)        1.988     3.805    d_1_i/qick_time_tagger_0/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/WR_SMP_FIFO/fifo_mem/adc_clk
    RAMB36_X8Y15         RAMB36E2                                     r  d_1_i/qick_time_tagger_0/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/WR_SMP_FIFO/fifo_mem/mem_reg_0/CLKBWRCLK
                         clock pessimism              0.073     3.879    
    RAMB36_X8Y15         RAMB36E2 (Hold_RAMB36E2_RAMB36_CLKBWRCLK_DINBDIN[25])
                                                     -0.005     3.874    d_1_i/qick_time_tagger_0/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/WR_SMP_FIFO/fifo_mem/mem_reg_0
  -------------------------------------------------------------------
                         required time                         -3.874    
                         arrival time                           3.910    
  -------------------------------------------------------------------
                         slack                                  0.036    

Slack (MET) :             0.036ns  (arrival time - required time)
  Source:                 d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/TAG[1].MEM/FIFO_PUSH/gcc_wr_ptr/count_bin_r_reg[4]/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/TAG[1].MEM/FIFO_PUSH/gcc_wr_ptr/count_bin_2r_reg[4]/D
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             clk_out1_d_1_clk_adc0_x2_0
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        0.089ns  (logic 0.059ns (66.292%)  route 0.030ns (33.708%))
  Logic Levels:           1  (LUT2=1)
  Clock Path Skew:        0.006ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.670ns
    Source Clock Delay      (SCD):    3.701ns
    Clock Pessimism Removal (CPR):    -0.037ns
  Clock Net Delay (Source):      1.640ns (routing 1.074ns, distribution 0.566ns)
  Clock Net Delay (Destination): 1.853ns (routing 1.208ns, distribution 0.645ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y18        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=1, routed)           1.405     1.668    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.898 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     2.044    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.061 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=1945, routed)        1.640     3.701    d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/TAG[1].MEM/FIFO_PUSH/gcc_wr_ptr/adc_clk
    SLICE_X73Y156        FDCE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/TAG[1].MEM/FIFO_PUSH/gcc_wr_ptr/count_bin_r_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X73Y156        FDCE (Prop_FFF_SLICEL_C_Q)
                                                      0.039     3.740 r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/TAG[1].MEM/FIFO_PUSH/gcc_wr_ptr/count_bin_r_reg[4]/Q
                         net (fo=1, routed)           0.024     3.764    d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/TAG[1].MEM/FIFO_PUSH/gcc_wr_ptr/count_bin_r[4]
    SLICE_X73Y156        LUT2 (Prop_H5LUT_SLICEL_I0_O)
                                                      0.020     3.784 r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/TAG[1].MEM/FIFO_PUSH/gcc_wr_ptr/count_bin_2r[4]_i_1__3/O
                         net (fo=1, routed)           0.006     3.790    d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/TAG[1].MEM/FIFO_PUSH/gcc_wr_ptr/count_bin_2r[4]_i_1__3_n_0
    SLICE_X73Y156        FDCE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/TAG[1].MEM/FIFO_PUSH/gcc_wr_ptr/count_bin_2r_reg[4]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y18        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=1, routed)           1.575     1.927    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.632 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.798    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.817 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=1945, routed)        1.853     3.670    d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/TAG[1].MEM/FIFO_PUSH/gcc_wr_ptr/adc_clk
    SLICE_X73Y156        FDCE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/TAG[1].MEM/FIFO_PUSH/gcc_wr_ptr/count_bin_2r_reg[4]/C
                         clock pessimism              0.037     3.707    
    SLICE_X73Y156        FDCE (Hold_HFF2_SLICEL_C_D)
                                                      0.047     3.754    d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/TAG[1].MEM/FIFO_PUSH/gcc_wr_ptr/count_bin_2r_reg[4]
  -------------------------------------------------------------------
                         required time                         -3.754    
                         arrival time                           3.790    
  -------------------------------------------------------------------
                         slack                                  0.036    





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         clk_out1_d_1_clk_adc0_x2_0
Waveform(ns):       { 0.000 1.953 }
Period(ns):         3.906
Sources:            { d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0 }

Check Type        Corner  Lib Pin             Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location       Pin
Min Period        n/a     HSADC/FABRIC_CLK    n/a            1.923         3.906       1.983      HSADC_X0Y0     d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/FABRIC_CLK
Min Period        n/a     RAMB18E2/CLKBWRCLK  n/a            1.355         3.906       2.551      RAMB18_X7Y78   d_1_i/qick_time_tagger_0/inst/QTT/ARM.ARM_MEM/FIFO_PUSH/fifo_mem/mem_reg/CLKBWRCLK
Min Period        n/a     RAMB36E2/CLKBWRCLK  n/a            1.355         3.906       2.551      RAMB36_X8Y15   d_1_i/qick_time_tagger_0/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/WR_SMP_FIFO/fifo_mem/mem_reg_0/CLKBWRCLK
Min Period        n/a     RAMB36E2/CLKBWRCLK  n/a            1.355         3.906       2.551      RAMB36_X8Y16   d_1_i/qick_time_tagger_0/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/WR_SMP_FIFO/fifo_mem/mem_reg_1/CLKBWRCLK
Min Period        n/a     RAMB36E2/CLKARDCLK  n/a            1.355         3.906       2.551      RAMB36_X5Y35   d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/fifo_mem/mem_reg_bram_0/CLKARDCLK
Min Period        n/a     RAMB18E2/CLKBWRCLK  n/a            1.355         3.906       2.551      RAMB18_X7Y62   d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/TAG[1].MEM/FIFO_PUSH/fifo_mem/mem_reg/CLKBWRCLK
Min Period        n/a     BUFGCE/I            n/a            1.290         3.906       2.616      BUFGCE_X0Y179  d_1_i/clk_adc0_x2/inst/clkout1_buf/I
Min Period        n/a     MMCME4_ADV/CLKOUT0  n/a            1.071         3.906       2.835      MMCM_X0Y7      d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
Min Period        n/a     SRL16E/CLK          n/a            1.064         3.906       2.842      SLICE_X79Y110  d_1_i/rst_adc0_x2/U0/EXT_LPF/POR_SRL_I/CLK
Min Period        n/a     FDRE/C              n/a            0.550         3.906       3.356      SLICE_X108Y63  d_1_i/axis_register_slice_5/inst/areset_r_reg/C
Low Pulse Width   Slow    HSADC/FABRIC_CLK    n/a            0.800         1.953       1.153      HSADC_X0Y0     d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/FABRIC_CLK
Low Pulse Width   Fast    HSADC/FABRIC_CLK    n/a            0.800         1.953       1.153      HSADC_X0Y0     d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/FABRIC_CLK
Low Pulse Width   Slow    RAMB18E2/CLKBWRCLK  n/a            0.542         1.953       1.411      RAMB18_X7Y78   d_1_i/qick_time_tagger_0/inst/QTT/ARM.ARM_MEM/FIFO_PUSH/fifo_mem/mem_reg/CLKBWRCLK
Low Pulse Width   Fast    RAMB18E2/CLKBWRCLK  n/a            0.542         1.953       1.411      RAMB18_X7Y78   d_1_i/qick_time_tagger_0/inst/QTT/ARM.ARM_MEM/FIFO_PUSH/fifo_mem/mem_reg/CLKBWRCLK
Low Pulse Width   Slow    RAMB36E2/CLKBWRCLK  n/a            0.542         1.953       1.411      RAMB36_X8Y15   d_1_i/qick_time_tagger_0/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/WR_SMP_FIFO/fifo_mem/mem_reg_0/CLKBWRCLK
Low Pulse Width   Fast    RAMB36E2/CLKBWRCLK  n/a            0.542         1.953       1.411      RAMB36_X8Y15   d_1_i/qick_time_tagger_0/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/WR_SMP_FIFO/fifo_mem/mem_reg_0/CLKBWRCLK
Low Pulse Width   Slow    RAMB36E2/CLKBWRCLK  n/a            0.542         1.953       1.411      RAMB36_X8Y16   d_1_i/qick_time_tagger_0/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/WR_SMP_FIFO/fifo_mem/mem_reg_1/CLKBWRCLK
Low Pulse Width   Fast    RAMB36E2/CLKBWRCLK  n/a            0.542         1.953       1.411      RAMB36_X8Y16   d_1_i/qick_time_tagger_0/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/WR_SMP_FIFO/fifo_mem/mem_reg_1/CLKBWRCLK
Low Pulse Width   Slow    RAMB36E2/CLKARDCLK  n/a            0.542         1.953       1.411      RAMB36_X5Y35   d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/fifo_mem/mem_reg_bram_0/CLKARDCLK
Low Pulse Width   Fast    RAMB36E2/CLKARDCLK  n/a            0.542         1.953       1.411      RAMB36_X5Y35   d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/fifo_mem/mem_reg_bram_0/CLKARDCLK
High Pulse Width  Slow    HSADC/FABRIC_CLK    n/a            0.800         1.953       1.153      HSADC_X0Y0     d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/FABRIC_CLK
High Pulse Width  Fast    HSADC/FABRIC_CLK    n/a            0.800         1.953       1.153      HSADC_X0Y0     d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/FABRIC_CLK
High Pulse Width  Slow    RAMB18E2/CLKBWRCLK  n/a            0.542         1.953       1.411      RAMB18_X7Y78   d_1_i/qick_time_tagger_0/inst/QTT/ARM.ARM_MEM/FIFO_PUSH/fifo_mem/mem_reg/CLKBWRCLK
High Pulse Width  Fast    RAMB18E2/CLKBWRCLK  n/a            0.542         1.953       1.411      RAMB18_X7Y78   d_1_i/qick_time_tagger_0/inst/QTT/ARM.ARM_MEM/FIFO_PUSH/fifo_mem/mem_reg/CLKBWRCLK
High Pulse Width  Slow    RAMB36E2/CLKBWRCLK  n/a            0.542         1.953       1.411      RAMB36_X8Y15   d_1_i/qick_time_tagger_0/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/WR_SMP_FIFO/fifo_mem/mem_reg_0/CLKBWRCLK
High Pulse Width  Fast    RAMB36E2/CLKBWRCLK  n/a            0.542         1.953       1.411      RAMB36_X8Y15   d_1_i/qick_time_tagger_0/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/WR_SMP_FIFO/fifo_mem/mem_reg_0/CLKBWRCLK
High Pulse Width  Slow    RAMB36E2/CLKBWRCLK  n/a            0.542         1.953       1.411      RAMB36_X8Y16   d_1_i/qick_time_tagger_0/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/WR_SMP_FIFO/fifo_mem/mem_reg_1/CLKBWRCLK
High Pulse Width  Fast    RAMB36E2/CLKBWRCLK  n/a            0.542         1.953       1.411      RAMB36_X8Y16   d_1_i/qick_time_tagger_0/inst/QTT/SMP.SMP_MEM/SMP_FIFO_DC/WR_SMP_FIFO/fifo_mem/mem_reg_1/CLKBWRCLK
High Pulse Width  Slow    RAMB36E2/CLKARDCLK  n/a            0.542         1.953       1.411      RAMB36_X5Y35   d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/fifo_mem/mem_reg_bram_0/CLKARDCLK
High Pulse Width  Fast    RAMB36E2/CLKARDCLK  n/a            0.542         1.953       1.411      RAMB36_X5Y35   d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/fifo_mem/mem_reg_bram_0/CLKARDCLK



---------------------------------------------------------------------------------------------------
From Clock:  RFDAC0_CLK
  To Clock:  RFDAC0_CLK

Setup :            0  Failing Endpoints,  Worst Slack        0.393ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.019ns,  Total Violation        0.000ns
PW    :            0  Failing Endpoints,  Worst Slack        0.420ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.393ns  (required time - arrival time)
  Source:                 d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_replica_3/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[2].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_1/ENARDEN
                            (rising edge-triggered cell RAMB36E2 clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             RFDAC0_CLK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            2.441ns  (RFDAC0_CLK rise@2.441ns - RFDAC0_CLK rise@0.000ns)
  Data Path Delay:        1.569ns  (logic 0.076ns (4.844%)  route 1.493ns (95.156%))
  Logic Levels:           0  
  Clock Path Skew:        -0.102ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.760ns = ( 5.201 - 2.441 ) 
    Source Clock Delay      (SCD):    3.207ns
    Clock Pessimism Removal (CPR):    0.345ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.534ns (routing 1.490ns, distribution 1.044ns)
  Clock Net Delay (Destination): 2.239ns (routing 1.352ns, distribution 0.887ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=5276, routed)        2.534     3.207    d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/aclk
    SLICE_X76Y110        FDRE                                         r  d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_replica_3/C
  -------------------------------------------------------------------    -------------------
    SLICE_X76Y110        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     3.283 r  d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_replica_3/Q
                         net (fo=187, routed)         1.493     4.776    d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[2].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/dds_tvalid_r_repN_3_alias
    RAMB36_X6Y18         RAMB36E2                                     r  d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[2].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_1/ENARDEN
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      2.441     2.441 r  
    HSDAC_X0Y0           HSDAC                        0.000     2.441 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     2.722 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     2.848    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     2.962 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=5276, routed)        2.239     5.201    d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[2].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/aclk
    RAMB36_X6Y18         RAMB36E2                                     r  d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[2].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_1/CLKARDCLK
                         clock pessimism              0.345     5.546    
                         clock uncertainty           -0.035     5.511    
    RAMB36_X6Y18         RAMB36E2 (Setup_RAMB36E2_RAMB36_CLKARDCLK_ENARDEN)
                                                     -0.342     5.169    d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[2].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_1
  -------------------------------------------------------------------
                         required time                          5.169    
                         arrival time                          -4.776    
  -------------------------------------------------------------------
                         slack                                  0.393    

Slack (MET) :             0.446ns  (required time - arrival time)
  Source:                 d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_1/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[0].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_OUTPUT_INST/RSTP
                            (rising edge-triggered cell DSP_OUTPUT clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             RFDAC0_CLK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            2.441ns  (RFDAC0_CLK rise@2.441ns - RFDAC0_CLK rise@0.000ns)
  Data Path Delay:        1.640ns  (logic 0.079ns (4.817%)  route 1.561ns (95.183%))
  Logic Levels:           0  
  Clock Path Skew:        -0.115ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.752ns = ( 5.193 - 2.441 ) 
    Source Clock Delay      (SCD):    3.206ns
    Clock Pessimism Removal (CPR):    0.339ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.533ns (routing 1.490ns, distribution 1.043ns)
  Clock Net Delay (Destination): 2.231ns (routing 1.352ns, distribution 0.879ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=5276, routed)        2.533     3.206    d_1_i/rst_dac0/U0/slowest_sync_clk
    SLICE_X76Y142        FDRE                                         r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_1/C
  -------------------------------------------------------------------    -------------------
    SLICE_X76Y142        FDRE (Prop_GFF2_SLICEM_C_Q)
                                                      0.079     3.285 f  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_1/Q
                         net (fo=169, routed)         1.561     4.846    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[0].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/RSTP
    DSP48E2_X12Y53       DSP_OUTPUT                                   r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[0].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_OUTPUT_INST/RSTP  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      2.441     2.441 r  
    HSDAC_X0Y0           HSDAC                        0.000     2.441 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     2.722 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     2.848    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     2.962 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=5276, routed)        2.231     5.193    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[0].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/CLK
    DSP48E2_X12Y53       DSP_OUTPUT                                   r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[0].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_OUTPUT_INST/CLK
                         clock pessimism              0.339     5.532    
                         clock uncertainty           -0.035     5.497    
    DSP48E2_X12Y53       DSP_OUTPUT (Setup_DSP_OUTPUT_DSP48E2_CLK_RSTP)
                                                     -0.205     5.292    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[0].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_OUTPUT_INST
  -------------------------------------------------------------------
                         required time                          5.292    
                         arrival time                          -4.846    
  -------------------------------------------------------------------
                         slack                                  0.446    

Slack (MET) :             0.469ns  (required time - arrival time)
  Source:                 d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[0].prodg_y_full_real_r_reg[0]/DSP_OUTPUT_INST/CLK
                            (rising edge-triggered cell DSP_OUTPUT clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/DATA_DAC0[6]
                            (rising edge-triggered cell HSDAC clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             RFDAC0_CLK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            2.441ns  (RFDAC0_CLK rise@2.441ns - RFDAC0_CLK rise@0.000ns)
  Data Path Delay:        1.541ns  (logic 0.373ns (24.205%)  route 1.168ns (75.795%))
  Logic Levels:           1  (LUT4=1)
  Clock Path Skew:        -0.064ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.146ns = ( 5.587 - 2.441 ) 
    Source Clock Delay      (SCD):    3.508ns
    Clock Pessimism Removal (CPR):    0.298ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.835ns (routing 1.490ns, distribution 1.345ns)
  Clock Net Delay (Destination): 2.528ns (routing 1.352ns, distribution 1.176ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=5276, routed)        2.835     3.508    d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[0].prodg_y_full_real_r_reg[0]/CLK
    DSP48E2_X21Y83       DSP_OUTPUT                                   r  d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[0].prodg_y_full_real_r_reg[0]/DSP_OUTPUT_INST/CLK
  -------------------------------------------------------------------    -------------------
    DSP48E2_X21Y83       DSP_OUTPUT (Prop_DSP_OUTPUT_DSP48E2_CLK_P[21])
                                                      0.225     3.733 r  d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[0].prodg_y_full_real_r_reg[0]/DSP_OUTPUT_INST/P[21]
                         net (fo=1, routed)           0.606     4.339    d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[0].round_r_reg[0][6]
    SLICE_X114Y240       LUT4 (Prop_B6LUT_SLICEL_I0_O)
                                                      0.148     4.487 r  d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/m_axis_tdata[6]_INST_0/O
                         net (fo=1, routed)           0.562     5.049    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/s00_axis_tdata[6]
    HSDAC_X0Y0           HSDAC                                        r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/DATA_DAC0[6]
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      2.441     2.441 r  
    HSDAC_X0Y0           HSDAC                        0.000     2.441 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     2.722 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     2.848    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     2.962 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=5276, routed)        2.528     5.490    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/s0_axis_aclk
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_FABRIC_CLK_INTERNAL_FABRIC_CLK0)
                                                      0.097     5.587 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FABRIC_CLK0
                         clock pessimism              0.298     5.885    
                         clock uncertainty           -0.035     5.850    
    HSDAC_X0Y0           HSDAC (Setup_HSDAC_INTERNAL_FABRIC_CLK0_DATA_DAC0[6])
                                                     -0.332     5.518    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac
  -------------------------------------------------------------------
                         required time                          5.518    
                         arrival time                          -5.049    
  -------------------------------------------------------------------
                         slack                                  0.469    

Slack (MET) :             0.470ns  (required time - arrival time)
  Source:                 d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_replica_3/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[2].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_1/REGCEAREGCE
                            (rising edge-triggered cell RAMB36E2 clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             RFDAC0_CLK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            2.441ns  (RFDAC0_CLK rise@2.441ns - RFDAC0_CLK rise@0.000ns)
  Data Path Delay:        1.601ns  (logic 0.076ns (4.748%)  route 1.525ns (95.252%))
  Logic Levels:           0  
  Clock Path Skew:        -0.102ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.760ns = ( 5.201 - 2.441 ) 
    Source Clock Delay      (SCD):    3.207ns
    Clock Pessimism Removal (CPR):    0.345ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.534ns (routing 1.490ns, distribution 1.044ns)
  Clock Net Delay (Destination): 2.239ns (routing 1.352ns, distribution 0.887ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=5276, routed)        2.534     3.207    d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/aclk
    SLICE_X76Y110        FDRE                                         r  d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_replica_3/C
  -------------------------------------------------------------------    -------------------
    SLICE_X76Y110        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     3.283 r  d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_replica_3/Q
                         net (fo=187, routed)         1.525     4.808    d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[2].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/dds_tvalid_r_repN_3_alias
    RAMB36_X6Y18         RAMB36E2                                     r  d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[2].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_1/REGCEAREGCE
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      2.441     2.441 r  
    HSDAC_X0Y0           HSDAC                        0.000     2.441 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     2.722 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     2.848    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     2.962 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=5276, routed)        2.239     5.201    d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[2].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/aclk
    RAMB36_X6Y18         RAMB36E2                                     r  d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[2].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_1/CLKARDCLK
                         clock pessimism              0.345     5.546    
                         clock uncertainty           -0.035     5.511    
    RAMB36_X6Y18         RAMB36E2 (Setup_RAMB36E2_RAMB36_CLKARDCLK_REGCEAREGCE)
                                                     -0.233     5.278    d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[2].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_1
  -------------------------------------------------------------------
                         required time                          5.278    
                         arrival time                          -4.808    
  -------------------------------------------------------------------
                         slack                                  0.470    

Slack (MET) :             0.490ns  (required time - arrival time)
  Source:                 d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/en_reg_r3_reg_r/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/pinc_N_r4_reg[26]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             RFDAC0_CLK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            2.441ns  (RFDAC0_CLK rise@2.441ns - RFDAC0_CLK rise@0.000ns)
  Data Path Delay:        1.720ns  (logic 0.201ns (11.684%)  route 1.519ns (88.316%))
  Logic Levels:           1  (LUT2=1)
  Clock Path Skew:        -0.220ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.757ns = ( 5.198 - 2.441 ) 
    Source Clock Delay      (SCD):    3.319ns
    Clock Pessimism Removal (CPR):    0.342ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.646ns (routing 1.490ns, distribution 1.156ns)
  Clock Net Delay (Destination): 2.236ns (routing 1.352ns, distribution 0.884ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=5276, routed)        2.646     3.319    d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/aclk
    SLICE_X94Y179        FDRE                                         r  d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/en_reg_r3_reg_r/C
  -------------------------------------------------------------------    -------------------
    SLICE_X94Y179        FDRE (Prop_GFF_SLICEM_C_Q)
                                                      0.078     3.397 r  d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/en_reg_r3_reg_r/Q
                         net (fo=129, routed)         1.452     4.849    d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/en_reg_r3_reg_r_0
    SLICE_X79Y154        LUT2 (Prop_F6LUT_SLICEM_I1_O)
                                                      0.123     4.972 r  d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/pinc_N_r3_reg_gate__23/O
                         net (fo=1, routed)           0.067     5.039    d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/pinc_N_r3_reg_gate__23_n_0
    SLICE_X79Y154        FDRE                                         r  d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/pinc_N_r4_reg[26]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      2.441     2.441 r  
    HSDAC_X0Y0           HSDAC                        0.000     2.441 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     2.722 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     2.848    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     2.962 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=5276, routed)        2.236     5.198    d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/aclk
    SLICE_X79Y154        FDRE                                         r  d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/pinc_N_r4_reg[26]/C
                         clock pessimism              0.342     5.540    
                         clock uncertainty           -0.035     5.505    
    SLICE_X79Y154        FDRE (Setup_FFF_SLICEM_C_D)
                                                      0.025     5.530    d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/pinc_N_r4_reg[26]
  -------------------------------------------------------------------
                         required time                          5.530    
                         arrival time                          -5.039    
  -------------------------------------------------------------------
                         slack                                  0.490    

Slack (MET) :             0.502ns  (required time - arrival time)
  Source:                 d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[0].prodg_y_full_real_r_reg[0]/DSP_OUTPUT_INST/CLK
                            (rising edge-triggered cell DSP_OUTPUT clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/DATA_DAC0[15]
                            (rising edge-triggered cell HSDAC clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             RFDAC0_CLK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            2.441ns  (RFDAC0_CLK rise@2.441ns - RFDAC0_CLK rise@0.000ns)
  Data Path Delay:        1.484ns  (logic 0.313ns (21.092%)  route 1.171ns (78.908%))
  Logic Levels:           1  (LUT4=1)
  Clock Path Skew:        -0.064ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.146ns = ( 5.587 - 2.441 ) 
    Source Clock Delay      (SCD):    3.508ns
    Clock Pessimism Removal (CPR):    0.298ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.835ns (routing 1.490ns, distribution 1.345ns)
  Clock Net Delay (Destination): 2.528ns (routing 1.352ns, distribution 1.176ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=5276, routed)        2.835     3.508    d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[0].prodg_y_full_real_r_reg[0]/CLK
    DSP48E2_X21Y83       DSP_OUTPUT                                   r  d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[0].prodg_y_full_real_r_reg[0]/DSP_OUTPUT_INST/CLK
  -------------------------------------------------------------------    -------------------
    DSP48E2_X21Y83       DSP_OUTPUT (Prop_DSP_OUTPUT_DSP48E2_CLK_P[30])
                                                      0.223     3.731 r  d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[0].prodg_y_full_real_r_reg[0]/DSP_OUTPUT_INST/P[30]
                         net (fo=1, routed)           0.675     4.406    d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[0].round_r_reg[0][15]
    SLICE_X116Y239       LUT4 (Prop_B6LUT_SLICEL_I0_O)
                                                      0.090     4.496 r  d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/m_axis_tdata[15]_INST_0/O
                         net (fo=1, routed)           0.496     4.992    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/s00_axis_tdata[15]
    HSDAC_X0Y0           HSDAC                                        r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/DATA_DAC0[15]
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      2.441     2.441 r  
    HSDAC_X0Y0           HSDAC                        0.000     2.441 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     2.722 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     2.848    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     2.962 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=5276, routed)        2.528     5.490    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/s0_axis_aclk
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_FABRIC_CLK_INTERNAL_FABRIC_CLK0)
                                                      0.097     5.587 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FABRIC_CLK0
                         clock pessimism              0.298     5.885    
                         clock uncertainty           -0.035     5.850    
    HSDAC_X0Y0           HSDAC (Setup_HSDAC_INTERNAL_FABRIC_CLK0_DATA_DAC0[15])
                                                     -0.356     5.494    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac
  -------------------------------------------------------------------
                         required time                          5.494    
                         arrival time                          -4.992    
  -------------------------------------------------------------------
                         slack                                  0.502    

Slack (MET) :             0.504ns  (required time - arrival time)
  Source:                 d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/en_reg_r3_reg_r/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/pinc_N_r4_reg[27]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             RFDAC0_CLK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            2.441ns  (RFDAC0_CLK rise@2.441ns - RFDAC0_CLK rise@0.000ns)
  Data Path Delay:        1.706ns  (logic 0.220ns (12.893%)  route 1.486ns (87.107%))
  Logic Levels:           1  (LUT2=1)
  Clock Path Skew:        -0.220ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.757ns = ( 5.198 - 2.441 ) 
    Source Clock Delay      (SCD):    3.319ns
    Clock Pessimism Removal (CPR):    0.342ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.646ns (routing 1.490ns, distribution 1.156ns)
  Clock Net Delay (Destination): 2.236ns (routing 1.352ns, distribution 0.884ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=5276, routed)        2.646     3.319    d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/aclk
    SLICE_X94Y179        FDRE                                         r  d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/en_reg_r3_reg_r/C
  -------------------------------------------------------------------    -------------------
    SLICE_X94Y179        FDRE (Prop_GFF_SLICEM_C_Q)
                                                      0.078     3.397 r  d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/en_reg_r3_reg_r/Q
                         net (fo=129, routed)         1.452     4.849    d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/en_reg_r3_reg_r_0
    SLICE_X79Y154        LUT2 (Prop_F5LUT_SLICEM_I1_O)
                                                      0.142     4.991 r  d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/pinc_N_r3_reg_gate__24/O
                         net (fo=1, routed)           0.034     5.025    d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/pinc_N_r3_reg_gate__24_n_0
    SLICE_X79Y154        FDRE                                         r  d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/pinc_N_r4_reg[27]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      2.441     2.441 r  
    HSDAC_X0Y0           HSDAC                        0.000     2.441 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     2.722 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     2.848    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     2.962 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=5276, routed)        2.236     5.198    d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/aclk
    SLICE_X79Y154        FDRE                                         r  d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/pinc_N_r4_reg[27]/C
                         clock pessimism              0.342     5.540    
                         clock uncertainty           -0.035     5.505    
    SLICE_X79Y154        FDRE (Setup_FFF2_SLICEM_C_D)
                                                      0.025     5.530    d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/pinc_N_r4_reg[27]
  -------------------------------------------------------------------
                         required time                          5.530    
                         arrival time                          -5.025    
  -------------------------------------------------------------------
                         slack                                  0.504    

Slack (MET) :             0.510ns  (required time - arrival time)
  Source:                 d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_1/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_ALU_INST/RSTALLCARRYIN
                            (rising edge-triggered cell DSP_ALU clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             RFDAC0_CLK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            2.441ns  (RFDAC0_CLK rise@2.441ns - RFDAC0_CLK rise@0.000ns)
  Data Path Delay:        1.629ns  (logic 0.079ns (4.849%)  route 1.550ns (95.151%))
  Logic Levels:           0  
  Clock Path Skew:        -0.114ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.753ns = ( 5.194 - 2.441 ) 
    Source Clock Delay      (SCD):    3.206ns
    Clock Pessimism Removal (CPR):    0.339ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.533ns (routing 1.490ns, distribution 1.043ns)
  Clock Net Delay (Destination): 2.232ns (routing 1.352ns, distribution 0.880ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=5276, routed)        2.533     3.206    d_1_i/rst_dac0/U0/slowest_sync_clk
    SLICE_X76Y142        FDRE                                         r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_1/C
  -------------------------------------------------------------------    -------------------
    SLICE_X76Y142        FDRE (Prop_GFF2_SLICEM_C_Q)
                                                      0.079     3.285 f  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_1/Q
                         net (fo=169, routed)         1.550     4.835    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/RSTALLCARRYIN
    DSP48E2_X12Y52       DSP_ALU                                      r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_ALU_INST/RSTALLCARRYIN  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      2.441     2.441 r  
    HSDAC_X0Y0           HSDAC                        0.000     2.441 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     2.722 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     2.848    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     2.962 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=5276, routed)        2.232     5.194    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/CLK
    DSP48E2_X12Y52       DSP_ALU                                      r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_ALU_INST/CLK
                         clock pessimism              0.339     5.533    
                         clock uncertainty           -0.035     5.498    
    DSP48E2_X12Y52       DSP_ALU (Setup_DSP_ALU_DSP48E2_CLK_RSTALLCARRYIN)
                                                     -0.153     5.345    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_ALU_INST
  -------------------------------------------------------------------
                         required time                          5.345    
                         arrival time                          -4.835    
  -------------------------------------------------------------------
                         slack                                  0.510    

Slack (MET) :             0.529ns  (required time - arrival time)
  Source:                 d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/en_reg_r3_reg_r/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/pinc_N_r4_reg[18]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             RFDAC0_CLK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            2.441ns  (RFDAC0_CLK rise@2.441ns - RFDAC0_CLK rise@0.000ns)
  Data Path Delay:        1.682ns  (logic 0.168ns (9.991%)  route 1.514ns (90.009%))
  Logic Levels:           1  (LUT2=1)
  Clock Path Skew:        -0.220ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.757ns = ( 5.198 - 2.441 ) 
    Source Clock Delay      (SCD):    3.319ns
    Clock Pessimism Removal (CPR):    0.342ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.646ns (routing 1.490ns, distribution 1.156ns)
  Clock Net Delay (Destination): 2.236ns (routing 1.352ns, distribution 0.884ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=5276, routed)        2.646     3.319    d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/aclk
    SLICE_X94Y179        FDRE                                         r  d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/en_reg_r3_reg_r/C
  -------------------------------------------------------------------    -------------------
    SLICE_X94Y179        FDRE (Prop_GFF_SLICEM_C_Q)
                                                      0.078     3.397 r  d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/en_reg_r3_reg_r/Q
                         net (fo=129, routed)         1.456     4.853    d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/en_reg_r3_reg_r_0
    SLICE_X79Y154        LUT2 (Prop_H6LUT_SLICEM_I1_O)
                                                      0.090     4.943 r  d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/pinc_N_r3_reg_gate__15/O
                         net (fo=1, routed)           0.058     5.001    d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/pinc_N_r3_reg_gate__15_n_0
    SLICE_X79Y154        FDRE                                         r  d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/pinc_N_r4_reg[18]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      2.441     2.441 r  
    HSDAC_X0Y0           HSDAC                        0.000     2.441 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     2.722 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     2.848    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     2.962 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=5276, routed)        2.236     5.198    d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/aclk
    SLICE_X79Y154        FDRE                                         r  d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/pinc_N_r4_reg[18]/C
                         clock pessimism              0.342     5.540    
                         clock uncertainty           -0.035     5.505    
    SLICE_X79Y154        FDRE (Setup_HFF_SLICEM_C_D)
                                                      0.025     5.530    d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/pinc_N_r4_reg[18]
  -------------------------------------------------------------------
                         required time                          5.530    
                         arrival time                          -5.001    
  -------------------------------------------------------------------
                         slack                                  0.529    

Slack (MET) :             0.530ns  (required time - arrival time)
  Source:                 d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/en_reg_r3_reg_r/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/pinc_N_r4_reg[24]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             RFDAC0_CLK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            2.441ns  (RFDAC0_CLK rise@2.441ns - RFDAC0_CLK rise@0.000ns)
  Data Path Delay:        1.681ns  (logic 0.168ns (9.997%)  route 1.513ns (90.003%))
  Logic Levels:           1  (LUT2=1)
  Clock Path Skew:        -0.220ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.757ns = ( 5.198 - 2.441 ) 
    Source Clock Delay      (SCD):    3.319ns
    Clock Pessimism Removal (CPR):    0.342ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.646ns (routing 1.490ns, distribution 1.156ns)
  Clock Net Delay (Destination): 2.236ns (routing 1.352ns, distribution 0.884ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=5276, routed)        2.646     3.319    d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/aclk
    SLICE_X94Y179        FDRE                                         r  d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/en_reg_r3_reg_r/C
  -------------------------------------------------------------------    -------------------
    SLICE_X94Y179        FDRE (Prop_GFF_SLICEM_C_Q)
                                                      0.078     3.397 r  d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/en_reg_r3_reg_r/Q
                         net (fo=129, routed)         1.454     4.851    d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/en_reg_r3_reg_r_0
    SLICE_X79Y154        LUT2 (Prop_G6LUT_SLICEM_I1_O)
                                                      0.090     4.941 r  d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/pinc_N_r3_reg_gate__21/O
                         net (fo=1, routed)           0.059     5.000    d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/pinc_N_r3_reg_gate__21_n_0
    SLICE_X79Y154        FDRE                                         r  d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/pinc_N_r4_reg[24]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      2.441     2.441 r  
    HSDAC_X0Y0           HSDAC                        0.000     2.441 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     2.722 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     2.848    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     2.962 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=5276, routed)        2.236     5.198    d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/aclk
    SLICE_X79Y154        FDRE                                         r  d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/pinc_N_r4_reg[24]/C
                         clock pessimism              0.342     5.540    
                         clock uncertainty           -0.035     5.505    
    SLICE_X79Y154        FDRE (Setup_GFF_SLICEM_C_D)
                                                      0.025     5.530    d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/pinc_N_r4_reg[24]
  -------------------------------------------------------------------
                         required time                          5.530    
                         arrival time                          -5.000    
  -------------------------------------------------------------------
                         slack                                  0.530    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.019ns  (arrival time - required time)
  Source:                 d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[2].env_imag_latency_reg_i/shift_r_reg[0][13]/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[2].env_imag_latency_reg_i/GEN_reg[1].shift_r_reg[1][13]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             RFDAC0_CLK
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (RFDAC0_CLK rise@0.000ns - RFDAC0_CLK rise@0.000ns)
  Data Path Delay:        0.319ns  (logic 0.058ns (18.182%)  route 0.261ns (81.818%))
  Logic Levels:           0  
  Clock Path Skew:        0.240ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.420ns
    Source Clock Delay      (SCD):    2.890ns
    Clock Pessimism Removal (CPR):    0.290ns
  Clock Net Delay (Source):      2.369ns (routing 1.352ns, distribution 1.017ns)
  Clock Net Delay (Destination): 2.747ns (routing 1.490ns, distribution 1.257ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=5276, routed)        2.369     2.890    d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[2].env_imag_latency_reg_i/aclk
    SLICE_X95Y178        FDRE                                         r  d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[2].env_imag_latency_reg_i/shift_r_reg[0][13]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X95Y178        FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.058     2.948 r  d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[2].env_imag_latency_reg_i/shift_r_reg[0][13]/Q
                         net (fo=1, routed)           0.261     3.209    d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[2].env_imag_latency_reg_i/shift_r_reg_n_0_[0][13]
    SLICE_X100Y191       FDRE                                         r  d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[2].env_imag_latency_reg_i/GEN_reg[1].shift_r_reg[1][13]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=5276, routed)        2.747     3.420    d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[2].env_imag_latency_reg_i/aclk
    SLICE_X100Y191       FDRE                                         r  d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[2].env_imag_latency_reg_i/GEN_reg[1].shift_r_reg[1][13]/C
                         clock pessimism             -0.290     3.130    
    SLICE_X100Y191       FDRE (Hold_FFF_SLICEL_C_D)
                                                      0.060     3.190    d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[2].env_imag_latency_reg_i/GEN_reg[1].shift_r_reg[1][13]
  -------------------------------------------------------------------
                         required time                         -3.190    
                         arrival time                           3.209    
  -------------------------------------------------------------------
                         slack                                  0.019    

Slack (MET) :             0.019ns  (arrival time - required time)
  Source:                 d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/fifo_i/mem_i/dob_reg[64]/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/fifo_dout_r_reg[64]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             RFDAC0_CLK
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (RFDAC0_CLK rise@0.000ns - RFDAC0_CLK rise@0.000ns)
  Data Path Delay:        0.168ns  (logic 0.060ns (35.714%)  route 0.108ns (64.286%))
  Logic Levels:           0  
  Clock Path Skew:        0.089ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.284ns
    Source Clock Delay      (SCD):    2.847ns
    Clock Pessimism Removal (CPR):    0.348ns
  Clock Net Delay (Source):      2.326ns (routing 1.352ns, distribution 0.974ns)
  Clock Net Delay (Destination): 2.611ns (routing 1.490ns, distribution 1.121ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=5276, routed)        2.326     2.847    d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/fifo_i/mem_i/aclk
    SLICE_X82Y160        FDRE                                         r  d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/fifo_i/mem_i/dob_reg[64]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X82Y160        FDRE (Prop_EFF2_SLICEM_C_Q)
                                                      0.060     2.907 r  d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/fifo_i/mem_i/dob_reg[64]/Q
                         net (fo=1, routed)           0.108     3.015    d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/fifo_dout_r_reg[148]_0[64]
    SLICE_X83Y160        FDRE                                         r  d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/fifo_dout_r_reg[64]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=5276, routed)        2.611     3.284    d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/aclk
    SLICE_X83Y160        FDRE                                         r  d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/fifo_dout_r_reg[64]/C
                         clock pessimism             -0.348     2.936    
    SLICE_X83Y160        FDRE (Hold_EFF_SLICEM_C_D)
                                                      0.060     2.996    d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/fifo_dout_r_reg[64]
  -------------------------------------------------------------------
                         required time                         -2.996    
                         arrival time                           3.015    
  -------------------------------------------------------------------
                         slack                                  0.019    

Slack (MET) :             0.021ns  (arrival time - required time)
  Source:                 d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_m_data_chan_no_fifo.m_axis_data_tdata_int_reg[73]/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[2].env_real_r1_reg[2][10]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             RFDAC0_CLK
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (RFDAC0_CLK rise@0.000ns - RFDAC0_CLK rise@0.000ns)
  Data Path Delay:        0.306ns  (logic 0.057ns (18.618%)  route 0.249ns (81.382%))
  Logic Levels:           0  
  Clock Path Skew:        0.226ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.388ns
    Source Clock Delay      (SCD):    2.872ns
    Clock Pessimism Removal (CPR):    0.290ns
  Clock Net Delay (Source):      2.351ns (routing 1.352ns, distribution 0.999ns)
  Clock Net Delay (Destination): 2.715ns (routing 1.490ns, distribution 1.225ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=5276, routed)        2.351     2.872    d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/aclk
    SLICE_X96Y161        FDRE                                         r  d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_m_data_chan_no_fifo.m_axis_data_tdata_int_reg[73]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X96Y161        FDRE (Prop_FFF_SLICEM_C_Q)
                                                      0.057     2.929 r  d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_m_data_chan_no_fifo.m_axis_data_tdata_int_reg[73]/Q
                         net (fo=3, routed)           0.249     3.178    d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/env_dout[73]
    SLICE_X94Y180        FDRE                                         r  d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[2].env_real_r1_reg[2][10]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=5276, routed)        2.715     3.388    d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/aclk
    SLICE_X94Y180        FDRE                                         r  d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[2].env_real_r1_reg[2][10]/C
                         clock pessimism             -0.290     3.098    
    SLICE_X94Y180        FDRE (Hold_BFF_SLICEM_C_D)
                                                      0.060     3.158    d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[2].env_real_r1_reg[2][10]
  -------------------------------------------------------------------
                         required time                         -3.158    
                         arrival time                           3.178    
  -------------------------------------------------------------------
                         slack                                  0.021    

Slack (MET) :             0.024ns  (arrival time - required time)
  Source:                 d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[2].dds_dout_latency_reg_i/GEN_reg[1].shift_r_reg[1][10]/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[2].dds_dout_latency_reg_i/GEN_reg[3].shift_r_reg[3][10]_srl2___inst_signal_gen_top_i_signal_gen_i_ctrl_i_en_reg_r2_reg_r/D
                            (rising edge-triggered cell SRL16E clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             RFDAC0_CLK
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (RFDAC0_CLK rise@0.000ns - RFDAC0_CLK rise@0.000ns)
  Data Path Delay:        0.351ns  (logic 0.058ns (16.506%)  route 0.293ns (83.494%))
  Logic Levels:           0  
  Clock Path Skew:        0.273ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.441ns
    Source Clock Delay      (SCD):    2.879ns
    Clock Pessimism Removal (CPR):    0.290ns
  Clock Net Delay (Source):      2.358ns (routing 1.352ns, distribution 1.006ns)
  Clock Net Delay (Destination): 2.768ns (routing 1.490ns, distribution 1.278ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=5276, routed)        2.358     2.879    d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[2].dds_dout_latency_reg_i/aclk
    SLICE_X92Y171        FDRE                                         r  d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[2].dds_dout_latency_reg_i/GEN_reg[1].shift_r_reg[1][10]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X92Y171        FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.058     2.937 r  d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[2].dds_dout_latency_reg_i/GEN_reg[1].shift_r_reg[1][10]/Q
                         net (fo=3, routed)           0.293     3.230    d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[2].dds_dout_latency_reg_i/Q[10]
    SLICE_X94Y184        SRL16E                                       r  d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[2].dds_dout_latency_reg_i/GEN_reg[3].shift_r_reg[3][10]_srl2___inst_signal_gen_top_i_signal_gen_i_ctrl_i_en_reg_r2_reg_r/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=5276, routed)        2.768     3.441    d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[2].dds_dout_latency_reg_i/aclk
    SLICE_X94Y184        SRL16E                                       r  d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[2].dds_dout_latency_reg_i/GEN_reg[3].shift_r_reg[3][10]_srl2___inst_signal_gen_top_i_signal_gen_i_ctrl_i_en_reg_r2_reg_r/CLK
                         clock pessimism             -0.290     3.151    
    SLICE_X94Y184        SRL16E (Hold_C5LUT_SLICEM_CLK_D)
                                                      0.055     3.206    d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[2].dds_dout_latency_reg_i/GEN_reg[3].shift_r_reg[3][10]_srl2___inst_signal_gen_top_i_signal_gen_i_ctrl_i_en_reg_r2_reg_r
  -------------------------------------------------------------------
                         required time                         -3.206    
                         arrival time                           3.230    
  -------------------------------------------------------------------
                         slack                                  0.024    

Slack (MET) :             0.025ns  (arrival time - required time)
  Source:                 d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[0].dds_dout_latency_reg_i/GEN_reg[1].shift_r_reg[1][2]/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[0].dds_dout_latency_reg_i/GEN_reg[3].shift_r_reg[3][2]_srl2___inst_signal_gen_top_i_signal_gen_i_ctrl_i_en_reg_r2_reg_r/D
                            (rising edge-triggered cell SRL16E clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             RFDAC0_CLK
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (RFDAC0_CLK rise@0.000ns - RFDAC0_CLK rise@0.000ns)
  Data Path Delay:        0.322ns  (logic 0.058ns (18.023%)  route 0.264ns (81.977%))
  Logic Levels:           0  
  Clock Path Skew:        0.269ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.440ns
    Source Clock Delay      (SCD):    2.882ns
    Clock Pessimism Removal (CPR):    0.290ns
  Clock Net Delay (Source):      2.361ns (routing 1.352ns, distribution 1.009ns)
  Clock Net Delay (Destination): 2.767ns (routing 1.490ns, distribution 1.277ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=5276, routed)        2.361     2.882    d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[0].dds_dout_latency_reg_i/aclk
    SLICE_X92Y174        FDRE                                         r  d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[0].dds_dout_latency_reg_i/GEN_reg[1].shift_r_reg[1][2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X92Y174        FDRE (Prop_HFF_SLICEL_C_Q)
                                                      0.058     2.940 r  d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[0].dds_dout_latency_reg_i/GEN_reg[1].shift_r_reg[1][2]/Q
                         net (fo=3, routed)           0.264     3.203    d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[0].dds_dout_latency_reg_i/Q[2]
    SLICE_X94Y186        SRL16E                                       r  d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[0].dds_dout_latency_reg_i/GEN_reg[3].shift_r_reg[3][2]_srl2___inst_signal_gen_top_i_signal_gen_i_ctrl_i_en_reg_r2_reg_r/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=5276, routed)        2.767     3.440    d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[0].dds_dout_latency_reg_i/aclk
    SLICE_X94Y186        SRL16E                                       r  d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[0].dds_dout_latency_reg_i/GEN_reg[3].shift_r_reg[3][2]_srl2___inst_signal_gen_top_i_signal_gen_i_ctrl_i_en_reg_r2_reg_r/CLK
                         clock pessimism             -0.290     3.150    
    SLICE_X94Y186        SRL16E (Hold_C6LUT_SLICEM_CLK_D)
                                                      0.028     3.178    d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[0].dds_dout_latency_reg_i/GEN_reg[3].shift_r_reg[3][2]_srl2___inst_signal_gen_top_i_signal_gen_i_ctrl_i_en_reg_r2_reg_r
  -------------------------------------------------------------------
                         required time                         -3.178    
                         arrival time                           3.203    
  -------------------------------------------------------------------
                         slack                                  0.025    

Slack (MET) :             0.025ns  (arrival time - required time)
  Source:                 d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[0].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_piped_map.i_original_cos_ls/opt_has_pipe.first_q_reg[4]/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[0].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_cos_ls/opt_has_pipe.first_q_reg[4]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             RFDAC0_CLK
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (RFDAC0_CLK rise@0.000ns - RFDAC0_CLK rise@0.000ns)
  Data Path Delay:        0.213ns  (logic 0.058ns (27.230%)  route 0.155ns (72.770%))
  Logic Levels:           0  
  Clock Path Skew:        0.126ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.288ns
    Source Clock Delay      (SCD):    2.869ns
    Clock Pessimism Removal (CPR):    0.294ns
  Clock Net Delay (Source):      2.348ns (routing 1.352ns, distribution 0.996ns)
  Clock Net Delay (Destination): 2.615ns (routing 1.490ns, distribution 1.125ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=5276, routed)        2.348     2.869    d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[0].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_piped_map.i_original_cos_ls/aclk
    SLICE_X81Y117        FDRE                                         r  d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[0].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_piped_map.i_original_cos_ls/opt_has_pipe.first_q_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y117        FDRE (Prop_HFF_SLICEL_C_Q)
                                                      0.058     2.927 r  d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[0].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_piped_map.i_original_cos_ls/opt_has_pipe.first_q_reg[4]/Q
                         net (fo=1, routed)           0.155     3.082    d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[0].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_cos_ls/D[4]
    SLICE_X81Y124        FDRE                                         r  d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[0].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_cos_ls/opt_has_pipe.first_q_reg[4]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=5276, routed)        2.615     3.288    d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[0].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_cos_ls/aclk
    SLICE_X81Y124        FDRE                                         r  d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[0].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_cos_ls/opt_has_pipe.first_q_reg[4]/C
                         clock pessimism             -0.294     2.994    
    SLICE_X81Y124        FDRE (Hold_HFF2_SLICEL_C_D)
                                                      0.062     3.056    d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[0].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_cos_ls/opt_has_pipe.first_q_reg[4]
  -------------------------------------------------------------------
                         required time                         -3.056    
                         arrival time                           3.082    
  -------------------------------------------------------------------
                         slack                                  0.025    

Slack (MET) :             0.026ns  (arrival time - required time)
  Source:                 d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[0].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_addr_reg_c/opt_has_pipe.first_q_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[0].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_addr_reg_c/opt_has_pipe.i_pipe[3].pipe_reg[3][1]_srl2/D
                            (rising edge-triggered cell SRL16E clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             RFDAC0_CLK
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (RFDAC0_CLK rise@0.000ns - RFDAC0_CLK rise@0.000ns)
  Data Path Delay:        0.200ns  (logic 0.058ns (29.000%)  route 0.142ns (71.000%))
  Logic Levels:           0  
  Clock Path Skew:        0.145ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.243ns
    Source Clock Delay      (SCD):    2.759ns
    Clock Pessimism Removal (CPR):    0.339ns
  Clock Net Delay (Source):      2.238ns (routing 1.352ns, distribution 0.886ns)
  Clock Net Delay (Destination): 2.570ns (routing 1.490ns, distribution 1.080ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=5276, routed)        2.238     2.759    d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[0].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_addr_reg_c/aclk
    SLICE_X75Y121        FDRE                                         r  d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[0].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_addr_reg_c/opt_has_pipe.first_q_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X75Y121        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.058     2.817 r  d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[0].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_addr_reg_c/opt_has_pipe.first_q_reg[1]/Q
                         net (fo=1, routed)           0.142     2.959    d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[0].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_addr_reg_c/opt_has_pipe.first_q[1]
    SLICE_X78Y121        SRL16E                                       r  d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[0].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_addr_reg_c/opt_has_pipe.i_pipe[3].pipe_reg[3][1]_srl2/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=5276, routed)        2.570     3.243    d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[0].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_addr_reg_c/aclk
    SLICE_X78Y121        SRL16E                                       r  d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[0].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_addr_reg_c/opt_has_pipe.i_pipe[3].pipe_reg[3][1]_srl2/CLK
                         clock pessimism             -0.339     2.904    
    SLICE_X78Y121        SRL16E (Hold_B6LUT_SLICEM_CLK_D)
                                                      0.029     2.933    d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[0].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_addr_reg_c/opt_has_pipe.i_pipe[3].pipe_reg[3][1]_srl2
  -------------------------------------------------------------------
                         required time                         -2.933    
                         arrival time                           2.959    
  -------------------------------------------------------------------
                         slack                                  0.026    

Slack (MET) :             0.029ns  (arrival time - required time)
  Source:                 d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[0].env_imag_latency_reg_i/shift_r_reg[0][4]/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[0].env_imag_latency_reg_i/GEN_reg[1].shift_r_reg[1][4]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             RFDAC0_CLK
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (RFDAC0_CLK rise@0.000ns - RFDAC0_CLK rise@0.000ns)
  Data Path Delay:        0.289ns  (logic 0.058ns (20.069%)  route 0.231ns (79.931%))
  Logic Levels:           0  
  Clock Path Skew:        0.198ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.371ns
    Source Clock Delay      (SCD):    2.884ns
    Clock Pessimism Removal (CPR):    0.290ns
  Clock Net Delay (Source):      2.363ns (routing 1.352ns, distribution 1.011ns)
  Clock Net Delay (Destination): 2.698ns (routing 1.490ns, distribution 1.208ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=5276, routed)        2.363     2.884    d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[0].env_imag_latency_reg_i/aclk
    SLICE_X93Y176        FDRE                                         r  d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[0].env_imag_latency_reg_i/shift_r_reg[0][4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X93Y176        FDRE (Prop_AFF_SLICEM_C_Q)
                                                      0.058     2.942 r  d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[0].env_imag_latency_reg_i/shift_r_reg[0][4]/Q
                         net (fo=1, routed)           0.231     3.173    d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[0].env_imag_latency_reg_i/shift_r_reg_n_0_[0][4]
    SLICE_X94Y193        FDRE                                         r  d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[0].env_imag_latency_reg_i/GEN_reg[1].shift_r_reg[1][4]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=5276, routed)        2.698     3.371    d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[0].env_imag_latency_reg_i/aclk
    SLICE_X94Y193        FDRE                                         r  d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[0].env_imag_latency_reg_i/GEN_reg[1].shift_r_reg[1][4]/C
                         clock pessimism             -0.290     3.081    
    SLICE_X94Y193        FDRE (Hold_EFF2_SLICEM_C_D)
                                                      0.062     3.143    d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[0].env_imag_latency_reg_i/GEN_reg[1].shift_r_reg[1][4]
  -------------------------------------------------------------------
                         required time                         -3.143    
                         arrival time                           3.173    
  -------------------------------------------------------------------
                         slack                                  0.029    

Slack (MET) :             0.031ns  (arrival time - required time)
  Source:                 d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[0].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_piped_map.i_original_cos_ls/opt_has_pipe.first_q_reg[6]/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[0].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_cos_ls/opt_has_pipe.first_q_reg[6]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             RFDAC0_CLK
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (RFDAC0_CLK rise@0.000ns - RFDAC0_CLK rise@0.000ns)
  Data Path Delay:        0.209ns  (logic 0.058ns (27.751%)  route 0.151ns (72.249%))
  Logic Levels:           0  
  Clock Path Skew:        0.116ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.277ns
    Source Clock Delay      (SCD):    2.867ns
    Clock Pessimism Removal (CPR):    0.294ns
  Clock Net Delay (Source):      2.346ns (routing 1.352ns, distribution 0.994ns)
  Clock Net Delay (Destination): 2.604ns (routing 1.490ns, distribution 1.114ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=5276, routed)        2.346     2.867    d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[0].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_piped_map.i_original_cos_ls/aclk
    SLICE_X81Y117        FDRE                                         r  d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[0].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_piped_map.i_original_cos_ls/opt_has_pipe.first_q_reg[6]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y117        FDRE (Prop_CFF_SLICEL_C_Q)
                                                      0.058     2.925 r  d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[0].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_piped_map.i_original_cos_ls/opt_has_pipe.first_q_reg[6]/Q
                         net (fo=1, routed)           0.151     3.076    d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[0].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_cos_ls/D[6]
    SLICE_X81Y123        FDRE                                         r  d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[0].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_cos_ls/opt_has_pipe.first_q_reg[6]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=5276, routed)        2.604     3.277    d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[0].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_cos_ls/aclk
    SLICE_X81Y123        FDRE                                         r  d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[0].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_cos_ls/opt_has_pipe.first_q_reg[6]/C
                         clock pessimism             -0.294     2.983    
    SLICE_X81Y123        FDRE (Hold_GFF2_SLICEL_C_D)
                                                      0.062     3.045    d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[0].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_cos_ls/opt_has_pipe.first_q_reg[6]
  -------------------------------------------------------------------
                         required time                         -3.045    
                         arrival time                           3.076    
  -------------------------------------------------------------------
                         slack                                  0.031    

Slack (MET) :             0.031ns  (arrival time - required time)
  Source:                 d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[2].env_real_r1_reg[2][5]/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[2].env_real_latency_reg_i/shift_r_reg[0][5]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             RFDAC0_CLK
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (RFDAC0_CLK rise@0.000ns - RFDAC0_CLK rise@0.000ns)
  Data Path Delay:        0.083ns  (logic 0.039ns (46.988%)  route 0.044ns (53.012%))
  Logic Levels:           0  
  Clock Path Skew:        0.006ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.071ns
    Source Clock Delay      (SCD):    1.791ns
    Clock Pessimism Removal (CPR):    0.275ns
  Clock Net Delay (Source):      1.442ns (routing 0.805ns, distribution 0.637ns)
  Clock Net Delay (Destination): 1.623ns (routing 0.900ns, distribution 0.723ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=5276, routed)        1.442     1.791    d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/aclk
    SLICE_X95Y167        FDRE                                         r  d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[2].env_real_r1_reg[2][5]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X95Y167        FDRE (Prop_GFF_SLICEL_C_Q)
                                                      0.039     1.830 r  d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[2].env_real_r1_reg[2][5]/Q
                         net (fo=1, routed)           0.044     1.874    d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[2].env_real_latency_reg_i/Q[4]
    SLICE_X95Y167        FDRE                                         r  d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[2].env_real_latency_reg_i/shift_r_reg[0][5]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=5276, routed)        1.623     2.071    d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[2].env_real_latency_reg_i/aclk
    SLICE_X95Y167        FDRE                                         r  d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[2].env_real_latency_reg_i/shift_r_reg[0][5]/C
                         clock pessimism             -0.275     1.797    
    SLICE_X95Y167        FDRE (Hold_FFF_SLICEL_C_D)
                                                      0.046     1.843    d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[2].env_real_latency_reg_i/shift_r_reg[0][5]
  -------------------------------------------------------------------
                         required time                         -1.843    
                         arrival time                           1.874    
  -------------------------------------------------------------------
                         slack                                  0.031    





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         RFDAC0_CLK
Waveform(ns):       { 0.000 1.220 }
Period(ns):         2.441
Sources:            { d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX }

Check Type        Corner  Lib Pin             Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location      Pin
Min Period        n/a     HSDAC/CLK_DAC       n/a            2.000         2.441       0.441      HSDAC_X0Y0    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
Min Period        n/a     HSDAC/FABRIC_CLK    n/a            2.000         2.441       0.441      HSDAC_X0Y0    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/FABRIC_CLK
Min Period        n/a     RAMB18E2/CLKBWRCLK  n/a            1.355         2.441       1.086      RAMB18_X7Y36  d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/mem_imag_i/RAM_reg_bram_0/CLKBWRCLK
Min Period        n/a     RAMB18E2/CLKBWRCLK  n/a            1.355         2.441       1.086      RAMB18_X7Y37  d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/mem_real_i/RAM_reg_bram_0/CLKBWRCLK
Min Period        n/a     RAMB36E2/CLKARDCLK  n/a            1.355         2.441       1.086      RAMB36_X7Y17  d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[0].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_0/CLKARDCLK
Min Period        n/a     RAMB36E2/CLKBWRCLK  n/a            1.355         2.441       1.086      RAMB36_X7Y17  d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[0].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_0/CLKBWRCLK
Min Period        n/a     RAMB36E2/CLKARDCLK  n/a            1.355         2.441       1.086      RAMB36_X7Y16  d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[0].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_1/CLKARDCLK
Min Period        n/a     RAMB36E2/CLKBWRCLK  n/a            1.355         2.441       1.086      RAMB36_X7Y16  d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[0].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_1/CLKBWRCLK
Min Period        n/a     RAMB36E2/CLKARDCLK  n/a            1.355         2.441       1.086      RAMB36_X6Y17  d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[1].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_0/CLKARDCLK
Min Period        n/a     RAMB36E2/CLKBWRCLK  n/a            1.355         2.441       1.086      RAMB36_X6Y17  d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[1].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_0/CLKBWRCLK
Low Pulse Width   Slow    HSDAC/CLK_DAC       n/a            0.800         1.220       0.420      HSDAC_X0Y0    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
Low Pulse Width   Fast    HSDAC/CLK_DAC       n/a            0.800         1.220       0.420      HSDAC_X0Y0    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
Low Pulse Width   Slow    HSDAC/FABRIC_CLK    n/a            0.800         1.220       0.420      HSDAC_X0Y0    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/FABRIC_CLK
Low Pulse Width   Fast    HSDAC/FABRIC_CLK    n/a            0.800         1.221       0.421      HSDAC_X0Y0    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/FABRIC_CLK
Low Pulse Width   Slow    RAMB18E2/CLKBWRCLK  n/a            0.542         1.220       0.678      RAMB18_X7Y36  d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/mem_imag_i/RAM_reg_bram_0/CLKBWRCLK
Low Pulse Width   Fast    RAMB18E2/CLKBWRCLK  n/a            0.542         1.220       0.678      RAMB18_X7Y36  d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/mem_imag_i/RAM_reg_bram_0/CLKBWRCLK
Low Pulse Width   Slow    RAMB18E2/CLKBWRCLK  n/a            0.542         1.220       0.678      RAMB18_X7Y37  d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/mem_real_i/RAM_reg_bram_0/CLKBWRCLK
Low Pulse Width   Fast    RAMB18E2/CLKBWRCLK  n/a            0.542         1.221       0.679      RAMB18_X7Y37  d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/mem_real_i/RAM_reg_bram_0/CLKBWRCLK
Low Pulse Width   Slow    RAMB36E2/CLKARDCLK  n/a            0.542         1.221       0.679      RAMB36_X7Y17  d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[0].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_0/CLKARDCLK
Low Pulse Width   Fast    RAMB36E2/CLKARDCLK  n/a            0.542         1.220       0.678      RAMB36_X7Y17  d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[0].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_0/CLKARDCLK
High Pulse Width  Slow    HSDAC/CLK_DAC       n/a            0.800         1.221       0.421      HSDAC_X0Y0    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
High Pulse Width  Fast    HSDAC/CLK_DAC       n/a            0.800         1.221       0.421      HSDAC_X0Y0    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
High Pulse Width  Slow    HSDAC/FABRIC_CLK    n/a            0.800         1.221       0.421      HSDAC_X0Y0    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/FABRIC_CLK
High Pulse Width  Fast    HSDAC/FABRIC_CLK    n/a            0.800         1.220       0.420      HSDAC_X0Y0    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/FABRIC_CLK
High Pulse Width  Slow    RAMB18E2/CLKBWRCLK  n/a            0.542         1.221       0.679      RAMB18_X7Y36  d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/mem_imag_i/RAM_reg_bram_0/CLKBWRCLK
High Pulse Width  Fast    RAMB18E2/CLKBWRCLK  n/a            0.542         1.220       0.678      RAMB18_X7Y36  d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/mem_imag_i/RAM_reg_bram_0/CLKBWRCLK
High Pulse Width  Slow    RAMB18E2/CLKBWRCLK  n/a            0.542         1.221       0.679      RAMB18_X7Y37  d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/mem_real_i/RAM_reg_bram_0/CLKBWRCLK
High Pulse Width  Fast    RAMB18E2/CLKBWRCLK  n/a            0.542         1.220       0.678      RAMB18_X7Y37  d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/mem_real_i/RAM_reg_bram_0/CLKBWRCLK
High Pulse Width  Slow    RAMB36E2/CLKARDCLK  n/a            0.542         1.220       0.678      RAMB36_X7Y17  d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[0].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_0/CLKARDCLK
High Pulse Width  Fast    RAMB36E2/CLKARDCLK  n/a            0.542         1.221       0.679      RAMB36_X7Y17  d_1_i/axis_sg_int4_v2_0/inst/signal_gen_top_i/signal_gen_i/GEN_dds[0].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_0/CLKARDCLK



---------------------------------------------------------------------------------------------------
From Clock:  clk_pl_0
  To Clock:  clk_pl_0

Setup :            0  Failing Endpoints,  Worst Slack        0.701ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.011ns,  Total Violation        0.000ns
PW    :            0  Failing Endpoints,  Worst Slack        3.400ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.701ns  (required time - arrival time)
  Source:                 d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/fifo_mem/mem_reg_bram_0/CLKBWRCLK
                            (rising edge-triggered cell RAMB36E2 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/qick_time_tagger_0/MEM0/FIFO_TAG/mem_reg_bram_4/DINADIN[1]
                            (rising edge-triggered cell RAMB36E2 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk_pl_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk_pl_0 rise@10.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        8.716ns  (logic 0.916ns (10.510%)  route 7.800ns (89.490%))
  Logic Levels:           0  
  Clock Path Skew:        -0.159ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.167ns = ( 12.167 - 10.000 ) 
    Source Clock Delay      (SCD):    2.443ns
    Clock Pessimism Removal (CPR):    0.117ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.217ns (routing 0.763ns, distribution 1.454ns)
  Clock Net Delay (Destination): 1.985ns (routing 0.690ns, distribution 1.295ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       2.217     2.443    d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/fifo_mem/ps_clk
    RAMB36_X5Y35         RAMB36E2                                     r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/fifo_mem/mem_reg_bram_0/CLKBWRCLK
  -------------------------------------------------------------------    -------------------
    RAMB36_X5Y35         RAMB36E2 (Prop_RAMB36E2_RAMB36_CLKBWRCLK_DOUTBDOUT[1])
                                                      0.916     3.359 r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/fifo_mem/mem_reg_bram_0/DOUTBDOUT[1]
                         net (fo=128, routed)         7.800    11.159    d_1_i/qick_time_tagger_0/QTT/TAG_MEM/MEM0/data_s[1]
    RAMB36_X5Y82         RAMB36E2                                     r  d_1_i/qick_time_tagger_0/MEM0/FIFO_TAG/mem_reg_bram_4/DINADIN[1]
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                     10.000    10.000 r  
    PS8_X0Y0             PS8                          0.000    10.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157    10.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025    10.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       1.985    12.167    d_1_i/qick_time_tagger_0/ps_clk
    RAMB36_X5Y82         RAMB36E2                                     r  d_1_i/qick_time_tagger_0/MEM0/FIFO_TAG/mem_reg_bram_4/CLKARDCLK
                         clock pessimism              0.117    12.284    
                         clock uncertainty           -0.130    12.154    
    RAMB36_X5Y82         RAMB36E2 (Setup_RAMB36E2_RAMB36_CLKARDCLK_DINADIN[1])
                                                     -0.294    11.860    d_1_i/qick_time_tagger_0/MEM0/FIFO_TAG/mem_reg_bram_4
  -------------------------------------------------------------------
                         required time                         11.860    
                         arrival time                         -11.159    
  -------------------------------------------------------------------
                         slack                                  0.701    

Slack (MET) :             0.728ns  (required time - arrival time)
  Source:                 d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/fifo_mem/mem_reg_bram_0/CLKBWRCLK
                            (rising edge-triggered cell RAMB36E2 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/qick_time_tagger_0/MEM0/FIFO_TAG/mem_reg_bram_5/DINADIN[1]
                            (rising edge-triggered cell RAMB36E2 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk_pl_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk_pl_0 rise@10.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        8.690ns  (logic 0.916ns (10.541%)  route 7.774ns (89.459%))
  Logic Levels:           0  
  Clock Path Skew:        -0.158ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.168ns = ( 12.168 - 10.000 ) 
    Source Clock Delay      (SCD):    2.443ns
    Clock Pessimism Removal (CPR):    0.117ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.217ns (routing 0.763ns, distribution 1.454ns)
  Clock Net Delay (Destination): 1.986ns (routing 0.690ns, distribution 1.296ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       2.217     2.443    d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/fifo_mem/ps_clk
    RAMB36_X5Y35         RAMB36E2                                     r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/fifo_mem/mem_reg_bram_0/CLKBWRCLK
  -------------------------------------------------------------------    -------------------
    RAMB36_X5Y35         RAMB36E2 (Prop_RAMB36E2_RAMB36_CLKBWRCLK_DOUTBDOUT[1])
                                                      0.916     3.359 r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/fifo_mem/mem_reg_bram_0/DOUTBDOUT[1]
                         net (fo=128, routed)         7.774    11.133    d_1_i/qick_time_tagger_0/QTT/TAG_MEM/MEM0/data_s[1]
    RAMB36_X5Y83         RAMB36E2                                     r  d_1_i/qick_time_tagger_0/MEM0/FIFO_TAG/mem_reg_bram_5/DINADIN[1]
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                     10.000    10.000 r  
    PS8_X0Y0             PS8                          0.000    10.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157    10.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025    10.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       1.986    12.168    d_1_i/qick_time_tagger_0/ps_clk
    RAMB36_X5Y83         RAMB36E2                                     r  d_1_i/qick_time_tagger_0/MEM0/FIFO_TAG/mem_reg_bram_5/CLKARDCLK
                         clock pessimism              0.117    12.285    
                         clock uncertainty           -0.130    12.155    
    RAMB36_X5Y83         RAMB36E2 (Setup_RAMB36E2_RAMB36_CLKARDCLK_DINADIN[1])
                                                     -0.294    11.861    d_1_i/qick_time_tagger_0/MEM0/FIFO_TAG/mem_reg_bram_5
  -------------------------------------------------------------------
                         required time                         11.861    
                         arrival time                         -11.133    
  -------------------------------------------------------------------
                         slack                                  0.728    

Slack (MET) :             0.734ns  (required time - arrival time)
  Source:                 d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/fifo_mem/mem_reg_bram_0/CLKBWRCLK
                            (rising edge-triggered cell RAMB36E2 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/qick_time_tagger_0/MEM0/FIFO_TAG/mem_reg_bram_48/DINADIN[1]
                            (rising edge-triggered cell RAMB36E2 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk_pl_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk_pl_0 rise@10.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        8.755ns  (logic 0.916ns (10.463%)  route 7.839ns (89.537%))
  Logic Levels:           0  
  Clock Path Skew:        -0.087ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.239ns = ( 12.239 - 10.000 ) 
    Source Clock Delay      (SCD):    2.443ns
    Clock Pessimism Removal (CPR):    0.117ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.217ns (routing 0.763ns, distribution 1.454ns)
  Clock Net Delay (Destination): 2.057ns (routing 0.690ns, distribution 1.367ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       2.217     2.443    d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/fifo_mem/ps_clk
    RAMB36_X5Y35         RAMB36E2                                     r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/fifo_mem/mem_reg_bram_0/CLKBWRCLK
  -------------------------------------------------------------------    -------------------
    RAMB36_X5Y35         RAMB36E2 (Prop_RAMB36E2_RAMB36_CLKBWRCLK_DOUTBDOUT[1])
                                                      0.916     3.359 r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/fifo_mem/mem_reg_bram_0/DOUTBDOUT[1]
                         net (fo=128, routed)         7.839    11.198    d_1_i/qick_time_tagger_0/QTT/TAG_MEM/MEM0/data_s[1]
    RAMB36_X6Y80         RAMB36E2                                     r  d_1_i/qick_time_tagger_0/MEM0/FIFO_TAG/mem_reg_bram_48/DINADIN[1]
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                     10.000    10.000 r  
    PS8_X0Y0             PS8                          0.000    10.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157    10.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025    10.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       2.057    12.239    d_1_i/qick_time_tagger_0/ps_clk
    RAMB36_X6Y80         RAMB36E2                                     r  d_1_i/qick_time_tagger_0/MEM0/FIFO_TAG/mem_reg_bram_48/CLKARDCLK
                         clock pessimism              0.117    12.356    
                         clock uncertainty           -0.130    12.226    
    RAMB36_X6Y80         RAMB36E2 (Setup_RAMB36E2_RAMB36_CLKARDCLK_DINADIN[1])
                                                     -0.294    11.932    d_1_i/qick_time_tagger_0/MEM0/FIFO_TAG/mem_reg_bram_48
  -------------------------------------------------------------------
                         required time                         11.932    
                         arrival time                         -11.198    
  -------------------------------------------------------------------
                         slack                                  0.734    

Slack (MET) :             0.784ns  (required time - arrival time)
  Source:                 d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/fifo_mem/mem_reg_bram_0/CLKBWRCLK
                            (rising edge-triggered cell RAMB36E2 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/qick_time_tagger_0/MEM0/FIFO_TAG/mem_reg_bram_87/DINADIN[6]
                            (rising edge-triggered cell RAMB36E2 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk_pl_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk_pl_0 rise@10.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        8.698ns  (logic 0.899ns (10.336%)  route 7.799ns (89.664%))
  Logic Levels:           0  
  Clock Path Skew:        -0.144ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.182ns = ( 12.182 - 10.000 ) 
    Source Clock Delay      (SCD):    2.443ns
    Clock Pessimism Removal (CPR):    0.117ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.217ns (routing 0.763ns, distribution 1.454ns)
  Clock Net Delay (Destination): 2.000ns (routing 0.690ns, distribution 1.310ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       2.217     2.443    d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/fifo_mem/ps_clk
    RAMB36_X5Y35         RAMB36E2                                     r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/fifo_mem/mem_reg_bram_0/CLKBWRCLK
  -------------------------------------------------------------------    -------------------
    RAMB36_X5Y35         RAMB36E2 (Prop_RAMB36E2_RAMB36_CLKBWRCLK_DOUTBDOUT[6])
                                                      0.899     3.342 r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/fifo_mem/mem_reg_bram_0/DOUTBDOUT[6]
                         net (fo=128, routed)         7.799    11.141    d_1_i/qick_time_tagger_0/QTT/TAG_MEM/MEM0/data_s[6]
    RAMB36_X5Y93         RAMB36E2                                     r  d_1_i/qick_time_tagger_0/MEM0/FIFO_TAG/mem_reg_bram_87/DINADIN[6]
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                     10.000    10.000 r  
    PS8_X0Y0             PS8                          0.000    10.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157    10.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025    10.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       2.000    12.182    d_1_i/qick_time_tagger_0/ps_clk
    RAMB36_X5Y93         RAMB36E2                                     r  d_1_i/qick_time_tagger_0/MEM0/FIFO_TAG/mem_reg_bram_87/CLKARDCLK
                         clock pessimism              0.117    12.299    
                         clock uncertainty           -0.130    12.169    
    RAMB36_X5Y93         RAMB36E2 (Setup_RAMB36E2_RAMB36_CLKARDCLK_DINADIN[6])
                                                     -0.244    11.925    d_1_i/qick_time_tagger_0/MEM0/FIFO_TAG/mem_reg_bram_87
  -------------------------------------------------------------------
                         required time                         11.925    
                         arrival time                         -11.141    
  -------------------------------------------------------------------
                         slack                                  0.784    

Slack (MET) :             0.851ns  (required time - arrival time)
  Source:                 d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/fifo_mem/mem_reg_bram_0/CLKBWRCLK
                            (rising edge-triggered cell RAMB36E2 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/qick_time_tagger_0/MEM0/FIFO_TAG/mem_reg_bram_94/DINADIN[1]
                            (rising edge-triggered cell RAMB36E2 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk_pl_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk_pl_0 rise@10.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        8.669ns  (logic 0.916ns (10.566%)  route 7.753ns (89.434%))
  Logic Levels:           0  
  Clock Path Skew:        -0.055ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.271ns = ( 12.271 - 10.000 ) 
    Source Clock Delay      (SCD):    2.443ns
    Clock Pessimism Removal (CPR):    0.117ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.217ns (routing 0.763ns, distribution 1.454ns)
  Clock Net Delay (Destination): 2.089ns (routing 0.690ns, distribution 1.399ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       2.217     2.443    d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/fifo_mem/ps_clk
    RAMB36_X5Y35         RAMB36E2                                     r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/fifo_mem/mem_reg_bram_0/CLKBWRCLK
  -------------------------------------------------------------------    -------------------
    RAMB36_X5Y35         RAMB36E2 (Prop_RAMB36E2_RAMB36_CLKBWRCLK_DOUTBDOUT[1])
                                                      0.916     3.359 r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/fifo_mem/mem_reg_bram_0/DOUTBDOUT[1]
                         net (fo=128, routed)         7.753    11.112    d_1_i/qick_time_tagger_0/QTT/TAG_MEM/MEM0/data_s[1]
    RAMB36_X7Y79         RAMB36E2                                     r  d_1_i/qick_time_tagger_0/MEM0/FIFO_TAG/mem_reg_bram_94/DINADIN[1]
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                     10.000    10.000 r  
    PS8_X0Y0             PS8                          0.000    10.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157    10.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025    10.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       2.089    12.271    d_1_i/qick_time_tagger_0/ps_clk
    RAMB36_X7Y79         RAMB36E2                                     r  d_1_i/qick_time_tagger_0/MEM0/FIFO_TAG/mem_reg_bram_94/CLKARDCLK
                         clock pessimism              0.117    12.388    
                         clock uncertainty           -0.130    12.258    
    RAMB36_X7Y79         RAMB36E2 (Setup_RAMB36E2_RAMB36_CLKARDCLK_DINADIN[1])
                                                     -0.294    11.964    d_1_i/qick_time_tagger_0/MEM0/FIFO_TAG/mem_reg_bram_94
  -------------------------------------------------------------------
                         required time                         11.964    
                         arrival time                         -11.112    
  -------------------------------------------------------------------
                         slack                                  0.851    

Slack (MET) :             0.881ns  (required time - arrival time)
  Source:                 d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/fifo_mem/mem_reg_bram_0/CLKBWRCLK
                            (rising edge-triggered cell RAMB36E2 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/qick_time_tagger_0/MEM0/FIFO_TAG/mem_reg_bram_86/DINADIN[6]
                            (rising edge-triggered cell RAMB36E2 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk_pl_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk_pl_0 rise@10.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        8.597ns  (logic 0.899ns (10.457%)  route 7.698ns (89.543%))
  Logic Levels:           0  
  Clock Path Skew:        -0.148ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.178ns = ( 12.178 - 10.000 ) 
    Source Clock Delay      (SCD):    2.443ns
    Clock Pessimism Removal (CPR):    0.117ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.217ns (routing 0.763ns, distribution 1.454ns)
  Clock Net Delay (Destination): 1.996ns (routing 0.690ns, distribution 1.306ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       2.217     2.443    d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/fifo_mem/ps_clk
    RAMB36_X5Y35         RAMB36E2                                     r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/fifo_mem/mem_reg_bram_0/CLKBWRCLK
  -------------------------------------------------------------------    -------------------
    RAMB36_X5Y35         RAMB36E2 (Prop_RAMB36E2_RAMB36_CLKBWRCLK_DOUTBDOUT[6])
                                                      0.899     3.342 r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/fifo_mem/mem_reg_bram_0/DOUTBDOUT[6]
                         net (fo=128, routed)         7.698    11.040    d_1_i/qick_time_tagger_0/QTT/TAG_MEM/MEM0/data_s[6]
    RAMB36_X5Y92         RAMB36E2                                     r  d_1_i/qick_time_tagger_0/MEM0/FIFO_TAG/mem_reg_bram_86/DINADIN[6]
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                     10.000    10.000 r  
    PS8_X0Y0             PS8                          0.000    10.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157    10.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025    10.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       1.996    12.178    d_1_i/qick_time_tagger_0/ps_clk
    RAMB36_X5Y92         RAMB36E2                                     r  d_1_i/qick_time_tagger_0/MEM0/FIFO_TAG/mem_reg_bram_86/CLKARDCLK
                         clock pessimism              0.117    12.295    
                         clock uncertainty           -0.130    12.165    
    RAMB36_X5Y92         RAMB36E2 (Setup_RAMB36E2_RAMB36_CLKARDCLK_DINADIN[6])
                                                     -0.244    11.921    d_1_i/qick_time_tagger_0/MEM0/FIFO_TAG/mem_reg_bram_86
  -------------------------------------------------------------------
                         required time                         11.921    
                         arrival time                         -11.040    
  -------------------------------------------------------------------
                         slack                                  0.881    

Slack (MET) :             0.923ns  (required time - arrival time)
  Source:                 d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/fifo_mem/mem_reg_bram_0/CLKBWRCLK
                            (rising edge-triggered cell RAMB36E2 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/qick_time_tagger_0/MEM0/FIFO_TAG/mem_reg_bram_6/DINADIN[1]
                            (rising edge-triggered cell RAMB36E2 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk_pl_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk_pl_0 rise@10.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        8.520ns  (logic 0.916ns (10.751%)  route 7.604ns (89.249%))
  Logic Levels:           0  
  Clock Path Skew:        -0.133ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.193ns = ( 12.193 - 10.000 ) 
    Source Clock Delay      (SCD):    2.443ns
    Clock Pessimism Removal (CPR):    0.117ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.217ns (routing 0.763ns, distribution 1.454ns)
  Clock Net Delay (Destination): 2.011ns (routing 0.690ns, distribution 1.321ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       2.217     2.443    d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/fifo_mem/ps_clk
    RAMB36_X5Y35         RAMB36E2                                     r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/fifo_mem/mem_reg_bram_0/CLKBWRCLK
  -------------------------------------------------------------------    -------------------
    RAMB36_X5Y35         RAMB36E2 (Prop_RAMB36E2_RAMB36_CLKBWRCLK_DOUTBDOUT[1])
                                                      0.916     3.359 r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/fifo_mem/mem_reg_bram_0/DOUTBDOUT[1]
                         net (fo=128, routed)         7.604    10.963    d_1_i/qick_time_tagger_0/QTT/TAG_MEM/MEM0/data_s[1]
    RAMB36_X5Y84         RAMB36E2                                     r  d_1_i/qick_time_tagger_0/MEM0/FIFO_TAG/mem_reg_bram_6/DINADIN[1]
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                     10.000    10.000 r  
    PS8_X0Y0             PS8                          0.000    10.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157    10.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025    10.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       2.011    12.193    d_1_i/qick_time_tagger_0/ps_clk
    RAMB36_X5Y84         RAMB36E2                                     r  d_1_i/qick_time_tagger_0/MEM0/FIFO_TAG/mem_reg_bram_6/CLKARDCLK
                         clock pessimism              0.117    12.310    
                         clock uncertainty           -0.130    12.180    
    RAMB36_X5Y84         RAMB36E2 (Setup_RAMB36E2_RAMB36_CLKARDCLK_DINADIN[1])
                                                     -0.294    11.886    d_1_i/qick_time_tagger_0/MEM0/FIFO_TAG/mem_reg_bram_6
  -------------------------------------------------------------------
                         required time                         11.886    
                         arrival time                         -10.963    
  -------------------------------------------------------------------
                         slack                                  0.923    

Slack (MET) :             0.958ns  (required time - arrival time)
  Source:                 d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/fifo_mem/mem_reg_bram_0/CLKBWRCLK
                            (rising edge-triggered cell RAMB36E2 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/qick_time_tagger_0/MEM0/FIFO_TAG/mem_reg_bram_95/DINADIN[1]
                            (rising edge-triggered cell RAMB36E2 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk_pl_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk_pl_0 rise@10.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        8.569ns  (logic 0.916ns (10.690%)  route 7.653ns (89.310%))
  Logic Levels:           0  
  Clock Path Skew:        -0.049ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.277ns = ( 12.277 - 10.000 ) 
    Source Clock Delay      (SCD):    2.443ns
    Clock Pessimism Removal (CPR):    0.117ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.217ns (routing 0.763ns, distribution 1.454ns)
  Clock Net Delay (Destination): 2.095ns (routing 0.690ns, distribution 1.405ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       2.217     2.443    d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/fifo_mem/ps_clk
    RAMB36_X5Y35         RAMB36E2                                     r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/fifo_mem/mem_reg_bram_0/CLKBWRCLK
  -------------------------------------------------------------------    -------------------
    RAMB36_X5Y35         RAMB36E2 (Prop_RAMB36E2_RAMB36_CLKBWRCLK_DOUTBDOUT[1])
                                                      0.916     3.359 r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/fifo_mem/mem_reg_bram_0/DOUTBDOUT[1]
                         net (fo=128, routed)         7.653    11.012    d_1_i/qick_time_tagger_0/QTT/TAG_MEM/MEM0/data_s[1]
    RAMB36_X7Y80         RAMB36E2                                     r  d_1_i/qick_time_tagger_0/MEM0/FIFO_TAG/mem_reg_bram_95/DINADIN[1]
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                     10.000    10.000 r  
    PS8_X0Y0             PS8                          0.000    10.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157    10.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025    10.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       2.095    12.277    d_1_i/qick_time_tagger_0/ps_clk
    RAMB36_X7Y80         RAMB36E2                                     r  d_1_i/qick_time_tagger_0/MEM0/FIFO_TAG/mem_reg_bram_95/CLKARDCLK
                         clock pessimism              0.117    12.394    
                         clock uncertainty           -0.130    12.264    
    RAMB36_X7Y80         RAMB36E2 (Setup_RAMB36E2_RAMB36_CLKARDCLK_DINADIN[1])
                                                     -0.294    11.970    d_1_i/qick_time_tagger_0/MEM0/FIFO_TAG/mem_reg_bram_95
  -------------------------------------------------------------------
                         required time                         11.970    
                         arrival time                         -11.012    
  -------------------------------------------------------------------
                         slack                                  0.958    

Slack (MET) :             0.959ns  (required time - arrival time)
  Source:                 d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/fifo_mem/mem_reg_bram_0/CLKBWRCLK
                            (rising edge-triggered cell RAMB36E2 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/qick_time_tagger_0/MEM0/FIFO_TAG/mem_reg_bram_85/DINADIN[6]
                            (rising edge-triggered cell RAMB36E2 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk_pl_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk_pl_0 rise@10.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        8.513ns  (logic 0.899ns (10.560%)  route 7.614ns (89.440%))
  Logic Levels:           0  
  Clock Path Skew:        -0.154ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.172ns = ( 12.172 - 10.000 ) 
    Source Clock Delay      (SCD):    2.443ns
    Clock Pessimism Removal (CPR):    0.117ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.217ns (routing 0.763ns, distribution 1.454ns)
  Clock Net Delay (Destination): 1.990ns (routing 0.690ns, distribution 1.300ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       2.217     2.443    d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/fifo_mem/ps_clk
    RAMB36_X5Y35         RAMB36E2                                     r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/fifo_mem/mem_reg_bram_0/CLKBWRCLK
  -------------------------------------------------------------------    -------------------
    RAMB36_X5Y35         RAMB36E2 (Prop_RAMB36E2_RAMB36_CLKBWRCLK_DOUTBDOUT[6])
                                                      0.899     3.342 r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/fifo_mem/mem_reg_bram_0/DOUTBDOUT[6]
                         net (fo=128, routed)         7.614    10.956    d_1_i/qick_time_tagger_0/QTT/TAG_MEM/MEM0/data_s[6]
    RAMB36_X5Y91         RAMB36E2                                     r  d_1_i/qick_time_tagger_0/MEM0/FIFO_TAG/mem_reg_bram_85/DINADIN[6]
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                     10.000    10.000 r  
    PS8_X0Y0             PS8                          0.000    10.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157    10.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025    10.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       1.990    12.172    d_1_i/qick_time_tagger_0/ps_clk
    RAMB36_X5Y91         RAMB36E2                                     r  d_1_i/qick_time_tagger_0/MEM0/FIFO_TAG/mem_reg_bram_85/CLKARDCLK
                         clock pessimism              0.117    12.289    
                         clock uncertainty           -0.130    12.159    
    RAMB36_X5Y91         RAMB36E2 (Setup_RAMB36E2_RAMB36_CLKARDCLK_DINADIN[6])
                                                     -0.244    11.915    d_1_i/qick_time_tagger_0/MEM0/FIFO_TAG/mem_reg_bram_85
  -------------------------------------------------------------------
                         required time                         11.915    
                         arrival time                         -10.956    
  -------------------------------------------------------------------
                         slack                                  0.959    

Slack (MET) :             1.035ns  (required time - arrival time)
  Source:                 d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/fifo_mem/mem_reg_bram_0/CLKBWRCLK
                            (rising edge-triggered cell RAMB36E2 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/qick_time_tagger_0/MEM0/FIFO_TAG/mem_reg_bram_54/DINADIN[1]
                            (rising edge-triggered cell RAMB36E2 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk_pl_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk_pl_0 rise@10.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        8.484ns  (logic 0.916ns (10.797%)  route 7.568ns (89.203%))
  Logic Levels:           0  
  Clock Path Skew:        -0.057ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.269ns = ( 12.269 - 10.000 ) 
    Source Clock Delay      (SCD):    2.443ns
    Clock Pessimism Removal (CPR):    0.117ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.217ns (routing 0.763ns, distribution 1.454ns)
  Clock Net Delay (Destination): 2.087ns (routing 0.690ns, distribution 1.397ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       2.217     2.443    d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/fifo_mem/ps_clk
    RAMB36_X5Y35         RAMB36E2                                     r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/fifo_mem/mem_reg_bram_0/CLKBWRCLK
  -------------------------------------------------------------------    -------------------
    RAMB36_X5Y35         RAMB36E2 (Prop_RAMB36E2_RAMB36_CLKBWRCLK_DOUTBDOUT[1])
                                                      0.916     3.359 r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/fifo_mem/mem_reg_bram_0/DOUTBDOUT[1]
                         net (fo=128, routed)         7.568    10.927    d_1_i/qick_time_tagger_0/QTT/TAG_MEM/MEM0/data_s[1]
    RAMB36_X6Y86         RAMB36E2                                     r  d_1_i/qick_time_tagger_0/MEM0/FIFO_TAG/mem_reg_bram_54/DINADIN[1]
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                     10.000    10.000 r  
    PS8_X0Y0             PS8                          0.000    10.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157    10.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025    10.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       2.087    12.269    d_1_i/qick_time_tagger_0/ps_clk
    RAMB36_X6Y86         RAMB36E2                                     r  d_1_i/qick_time_tagger_0/MEM0/FIFO_TAG/mem_reg_bram_54/CLKARDCLK
                         clock pessimism              0.117    12.386    
                         clock uncertainty           -0.130    12.256    
    RAMB36_X6Y86         RAMB36E2 (Setup_RAMB36E2_RAMB36_CLKARDCLK_DINADIN[1])
                                                     -0.294    11.962    d_1_i/qick_time_tagger_0/MEM0/FIFO_TAG/mem_reg_bram_54
  -------------------------------------------------------------------
                         required time                         11.962    
                         arrival time                         -10.927    
  -------------------------------------------------------------------
                         slack                                  1.035    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.011ns  (arrival time - required time)
  Source:                 d_1_i/axi_dma_tproc/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_S2MM_MMAP_SKID_BUF/sig_data_reg_out_reg[65]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axi_smc/inst/s03_entry_pipeline/s03_mmu/inst/w_sreg/skid_buffer_reg[1090]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk_pl_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_pl_0 rise@0.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        0.176ns  (logic 0.058ns (33.024%)  route 0.118ns (66.976%))
  Logic Levels:           0  
  Clock Path Skew:        0.102ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.435ns
    Source Clock Delay      (SCD):    2.129ns
    Clock Pessimism Removal (CPR):    0.203ns
  Clock Net Delay (Source):      1.947ns (routing 0.690ns, distribution 1.257ns)
  Clock Net Delay (Destination): 2.209ns (routing 0.763ns, distribution 1.446ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       1.947     2.129    d_1_i/axi_dma_tproc/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_S2MM_MMAP_SKID_BUF/m_axi_s2mm_aclk
    SLICE_X48Y21         FDRE                                         r  d_1_i/axi_dma_tproc/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_S2MM_MMAP_SKID_BUF/sig_data_reg_out_reg[65]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X48Y21         FDRE (Prop_CFF_SLICEM_C_Q)
                                                      0.058     2.187 r  d_1_i/axi_dma_tproc/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_S2MM_MMAP_SKID_BUF/sig_data_reg_out_reg[65]/Q
                         net (fo=2, routed)           0.118     2.305    d_1_i/axi_smc/inst/s03_entry_pipeline/s03_mmu/inst/w_sreg/D[66]
    SLICE_X46Y20         FDRE                                         r  d_1_i/axi_smc/inst/s03_entry_pipeline/s03_mmu/inst/w_sreg/skid_buffer_reg[1090]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       2.209     2.435    d_1_i/axi_smc/inst/s03_entry_pipeline/s03_mmu/inst/w_sreg/aclk
    SLICE_X46Y20         FDRE                                         r  d_1_i/axi_smc/inst/s03_entry_pipeline/s03_mmu/inst/w_sreg/skid_buffer_reg[1090]/C
                         clock pessimism             -0.203     2.232    
    SLICE_X46Y20         FDRE (Hold_GFF2_SLICEM_C_D)
                                                      0.062     2.294    d_1_i/axi_smc/inst/s03_entry_pipeline/s03_mmu/inst/w_sreg/skid_buffer_reg[1090]
  -------------------------------------------------------------------
                         required time                         -2.294    
                         arrival time                           2.305    
  -------------------------------------------------------------------
                         slack                                  0.011    

Slack (MET) :             0.012ns  (arrival time - required time)
  Source:                 d_1_i/axi_dma_qtt/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_input_addr_reg_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axi_dma_qtt/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_child_addr_reg_reg[2]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk_pl_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_pl_0 rise@0.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        0.183ns  (logic 0.057ns (31.170%)  route 0.126ns (68.830%))
  Logic Levels:           0  
  Clock Path Skew:        0.109ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.456ns
    Source Clock Delay      (SCD):    2.144ns
    Clock Pessimism Removal (CPR):    0.203ns
  Clock Net Delay (Source):      1.962ns (routing 0.690ns, distribution 1.272ns)
  Clock Net Delay (Destination): 2.230ns (routing 0.763ns, distribution 1.467ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       1.962     2.144    d_1_i/axi_dma_qtt/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/m_axi_s2mm_aclk
    SLICE_X41Y52         FDRE                                         r  d_1_i/axi_dma_qtt/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_input_addr_reg_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X41Y52         FDRE (Prop_FFF_SLICEM_C_Q)
                                                      0.057     2.201 r  d_1_i/axi_dma_qtt/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_input_addr_reg_reg[2]/Q
                         net (fo=8, routed)           0.126     2.326    d_1_i/axi_dma_qtt/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_input_addr_reg[2]
    SLICE_X39Y51         FDRE                                         r  d_1_i/axi_dma_qtt/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_child_addr_reg_reg[2]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       2.230     2.456    d_1_i/axi_dma_qtt/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/m_axi_s2mm_aclk
    SLICE_X39Y51         FDRE                                         r  d_1_i/axi_dma_qtt/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_child_addr_reg_reg[2]/C
                         clock pessimism             -0.203     2.253    
    SLICE_X39Y51         FDRE (Hold_EFF2_SLICEM_C_D)
                                                      0.062     2.315    d_1_i/axi_dma_qtt/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_child_addr_reg_reg[2]
  -------------------------------------------------------------------
                         required time                         -2.315    
                         arrival time                           2.326    
  -------------------------------------------------------------------
                         slack                                  0.012    

Slack (MET) :             0.012ns  (arrival time - required time)
  Source:                 d_1_i/axi_smc/inst/m00_nodes/m00_r_node/inst/inst_mi_handler/gen_normal_area.gen_upsizer.inst_upsizer/gen_r_ch.accum_reg[bytes][18][userdata][2]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axi_smc/inst/m00_nodes/m00_r_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[1].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41/RAMB/I
                            (rising edge-triggered cell RAMD32 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk_pl_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_pl_0 rise@0.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        0.209ns  (logic 0.058ns (27.751%)  route 0.151ns (72.249%))
  Logic Levels:           0  
  Clock Path Skew:        0.119ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.456ns
    Source Clock Delay      (SCD):    2.133ns
    Clock Pessimism Removal (CPR):    0.203ns
  Clock Net Delay (Source):      1.951ns (routing 0.690ns, distribution 1.261ns)
  Clock Net Delay (Destination): 2.230ns (routing 0.763ns, distribution 1.467ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       1.951     2.133    d_1_i/axi_smc/inst/m00_nodes/m00_r_node/inst/inst_mi_handler/gen_normal_area.gen_upsizer.inst_upsizer/s_sc_aclk
    SLICE_X55Y11         FDRE                                         r  d_1_i/axi_smc/inst/m00_nodes/m00_r_node/inst/inst_mi_handler/gen_normal_area.gen_upsizer.inst_upsizer/gen_r_ch.accum_reg[bytes][18][userdata][2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X55Y11         FDRE (Prop_HFF_SLICEL_C_Q)
                                                      0.058     2.191 r  d_1_i/axi_smc/inst/m00_nodes/m00_r_node/inst/inst_mi_handler/gen_normal_area.gen_upsizer.inst_upsizer/gen_r_ch.accum_reg[bytes][18][userdata][2]/Q
                         net (fo=1, routed)           0.151     2.342    d_1_i/axi_smc/inst/m00_nodes/m00_r_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[1].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41/DIB0
    SLICE_X60Y12         RAMD32                                       r  d_1_i/axi_smc/inst/m00_nodes/m00_r_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[1].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41/RAMB/I
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       2.230     2.456    d_1_i/axi_smc/inst/m00_nodes/m00_r_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[1].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41/WCLK
    SLICE_X60Y12         RAMD32                                       r  d_1_i/axi_smc/inst/m00_nodes/m00_r_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[1].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41/RAMB/CLK
                         clock pessimism             -0.203     2.252    
    SLICE_X60Y12         RAMD32 (Hold_B5LUT_SLICEM_CLK_I)
                                                      0.078     2.330    d_1_i/axi_smc/inst/m00_nodes/m00_r_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[1].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41/RAMB
  -------------------------------------------------------------------
                         required time                         -2.330    
                         arrival time                           2.342    
  -------------------------------------------------------------------
                         slack                                  0.012    

Slack (MET) :             0.012ns  (arrival time - required time)
  Source:                 d_1_i/axi_smc/inst/switchboards/aw_switchboard/inst/gen_mi[0].inst_opipe_payld/gen_pipe[1].pipe_reg[1][126]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axi_smc/inst/m00_nodes/m00_aw_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_126_139/RAMA/I
                            (rising edge-triggered cell RAMD32 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk_pl_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_pl_0 rise@0.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        0.172ns  (logic 0.058ns (33.721%)  route 0.114ns (66.279%))
  Logic Levels:           0  
  Clock Path Skew:        0.085ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.569ns
    Source Clock Delay      (SCD):    2.215ns
    Clock Pessimism Removal (CPR):    0.270ns
  Clock Net Delay (Source):      2.033ns (routing 0.690ns, distribution 1.343ns)
  Clock Net Delay (Destination): 2.343ns (routing 0.763ns, distribution 1.580ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       2.033     2.215    d_1_i/axi_smc/inst/switchboards/aw_switchboard/inst/gen_mi[0].inst_opipe_payld/aclk
    SLICE_X32Y20         FDRE                                         r  d_1_i/axi_smc/inst/switchboards/aw_switchboard/inst/gen_mi[0].inst_opipe_payld/gen_pipe[1].pipe_reg[1][126]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X32Y20         FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.058     2.273 r  d_1_i/axi_smc/inst/switchboards/aw_switchboard/inst/gen_mi[0].inst_opipe_payld/gen_pipe[1].pipe_reg[1][126]/Q
                         net (fo=1, routed)           0.114     2.387    d_1_i/axi_smc/inst/m00_nodes/m00_aw_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_126_139/DIA0
    SLICE_X31Y20         RAMD32                                       r  d_1_i/axi_smc/inst/m00_nodes/m00_aw_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_126_139/RAMA/I
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       2.343     2.569    d_1_i/axi_smc/inst/m00_nodes/m00_aw_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_126_139/WCLK
    SLICE_X31Y20         RAMD32                                       r  d_1_i/axi_smc/inst/m00_nodes/m00_aw_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_126_139/RAMA/CLK
                         clock pessimism             -0.270     2.300    
    SLICE_X31Y20         RAMD32 (Hold_A5LUT_SLICEM_CLK_I)
                                                      0.075     2.375    d_1_i/axi_smc/inst/m00_nodes/m00_aw_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_126_139/RAMA
  -------------------------------------------------------------------
                         required time                         -2.375    
                         arrival time                           2.387    
  -------------------------------------------------------------------
                         slack                                  0.012    

Slack (MET) :             0.013ns  (arrival time - required time)
  Source:                 d_1_i/axi_smc/inst/s03_nodes/s03_w_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_wr_addra/count_r_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axi_smc/inst/s03_nodes/s03_w_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13/RAMA/WADR0
                            (rising edge-triggered cell RAMD32 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk_pl_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_pl_0 rise@0.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        0.170ns  (logic 0.059ns (34.744%)  route 0.111ns (65.256%))
  Logic Levels:           0  
  Clock Path Skew:        0.072ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.472ns
    Source Clock Delay      (SCD):    2.144ns
    Clock Pessimism Removal (CPR):    0.255ns
  Clock Net Delay (Source):      1.962ns (routing 0.690ns, distribution 1.272ns)
  Clock Net Delay (Destination): 2.246ns (routing 0.763ns, distribution 1.483ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       1.962     2.144    d_1_i/axi_smc/inst/s03_nodes/s03_w_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_wr_addra/s_sc_aclk
    SLICE_X43Y20         FDRE                                         r  d_1_i/axi_smc/inst/s03_nodes/s03_w_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_wr_addra/count_r_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X43Y20         FDRE (Prop_HFF2_SLICEL_C_Q)
                                                      0.059     2.203 r  d_1_i/axi_smc/inst/s03_nodes/s03_w_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_wr_addra/count_r_reg[0]/Q
                         net (fo=23, routed)          0.111     2.314    d_1_i/axi_smc/inst/s03_nodes/s03_w_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13/ADDRH0
    SLICE_X42Y21         RAMD32                                       r  d_1_i/axi_smc/inst/s03_nodes/s03_w_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13/RAMA/WADR0
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       2.246     2.472    d_1_i/axi_smc/inst/s03_nodes/s03_w_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13/WCLK
    SLICE_X42Y21         RAMD32                                       r  d_1_i/axi_smc/inst/s03_nodes/s03_w_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13/RAMA/CLK
                         clock pessimism             -0.255     2.216    
    SLICE_X42Y21         RAMD32 (Hold_A5LUT_SLICEM_CLK_WADR0)
                                                      0.085     2.301    d_1_i/axi_smc/inst/s03_nodes/s03_w_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13/RAMA
  -------------------------------------------------------------------
                         required time                         -2.301    
                         arrival time                           2.314    
  -------------------------------------------------------------------
                         slack                                  0.013    

Slack (MET) :             0.013ns  (arrival time - required time)
  Source:                 d_1_i/axi_smc/inst/s03_nodes/s03_w_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_wr_addra/count_r_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axi_smc/inst/s03_nodes/s03_w_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13/RAMA_D1/WADR0
                            (rising edge-triggered cell RAMD32 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk_pl_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_pl_0 rise@0.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        0.170ns  (logic 0.059ns (34.744%)  route 0.111ns (65.256%))
  Logic Levels:           0  
  Clock Path Skew:        0.072ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.472ns
    Source Clock Delay      (SCD):    2.144ns
    Clock Pessimism Removal (CPR):    0.255ns
  Clock Net Delay (Source):      1.962ns (routing 0.690ns, distribution 1.272ns)
  Clock Net Delay (Destination): 2.246ns (routing 0.763ns, distribution 1.483ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       1.962     2.144    d_1_i/axi_smc/inst/s03_nodes/s03_w_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_wr_addra/s_sc_aclk
    SLICE_X43Y20         FDRE                                         r  d_1_i/axi_smc/inst/s03_nodes/s03_w_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_wr_addra/count_r_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X43Y20         FDRE (Prop_HFF2_SLICEL_C_Q)
                                                      0.059     2.203 r  d_1_i/axi_smc/inst/s03_nodes/s03_w_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_wr_addra/count_r_reg[0]/Q
                         net (fo=23, routed)          0.111     2.314    d_1_i/axi_smc/inst/s03_nodes/s03_w_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13/ADDRH0
    SLICE_X42Y21         RAMD32                                       r  d_1_i/axi_smc/inst/s03_nodes/s03_w_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13/RAMA_D1/WADR0
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       2.246     2.472    d_1_i/axi_smc/inst/s03_nodes/s03_w_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13/WCLK
    SLICE_X42Y21         RAMD32                                       r  d_1_i/axi_smc/inst/s03_nodes/s03_w_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13/RAMA_D1/CLK
                         clock pessimism             -0.255     2.216    
    SLICE_X42Y21         RAMD32 (Hold_A6LUT_SLICEM_CLK_WADR0)
                                                      0.085     2.301    d_1_i/axi_smc/inst/s03_nodes/s03_w_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13/RAMA_D1
  -------------------------------------------------------------------
                         required time                         -2.301    
                         arrival time                           2.314    
  -------------------------------------------------------------------
                         slack                                  0.013    

Slack (MET) :             0.013ns  (arrival time - required time)
  Source:                 d_1_i/axi_smc/inst/s03_nodes/s03_w_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_wr_addra/count_r_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axi_smc/inst/s03_nodes/s03_w_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13/RAMB/WADR0
                            (rising edge-triggered cell RAMD32 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk_pl_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_pl_0 rise@0.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        0.170ns  (logic 0.059ns (34.744%)  route 0.111ns (65.256%))
  Logic Levels:           0  
  Clock Path Skew:        0.072ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.472ns
    Source Clock Delay      (SCD):    2.144ns
    Clock Pessimism Removal (CPR):    0.255ns
  Clock Net Delay (Source):      1.962ns (routing 0.690ns, distribution 1.272ns)
  Clock Net Delay (Destination): 2.246ns (routing 0.763ns, distribution 1.483ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       1.962     2.144    d_1_i/axi_smc/inst/s03_nodes/s03_w_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_wr_addra/s_sc_aclk
    SLICE_X43Y20         FDRE                                         r  d_1_i/axi_smc/inst/s03_nodes/s03_w_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_wr_addra/count_r_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X43Y20         FDRE (Prop_HFF2_SLICEL_C_Q)
                                                      0.059     2.203 r  d_1_i/axi_smc/inst/s03_nodes/s03_w_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_wr_addra/count_r_reg[0]/Q
                         net (fo=23, routed)          0.111     2.314    d_1_i/axi_smc/inst/s03_nodes/s03_w_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13/ADDRH0
    SLICE_X42Y21         RAMD32                                       r  d_1_i/axi_smc/inst/s03_nodes/s03_w_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13/RAMB/WADR0
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       2.246     2.472    d_1_i/axi_smc/inst/s03_nodes/s03_w_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13/WCLK
    SLICE_X42Y21         RAMD32                                       r  d_1_i/axi_smc/inst/s03_nodes/s03_w_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13/RAMB/CLK
                         clock pessimism             -0.255     2.216    
    SLICE_X42Y21         RAMD32 (Hold_B5LUT_SLICEM_CLK_WADR0)
                                                      0.085     2.301    d_1_i/axi_smc/inst/s03_nodes/s03_w_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13/RAMB
  -------------------------------------------------------------------
                         required time                         -2.301    
                         arrival time                           2.314    
  -------------------------------------------------------------------
                         slack                                  0.013    

Slack (MET) :             0.013ns  (arrival time - required time)
  Source:                 d_1_i/axi_smc/inst/s03_nodes/s03_w_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_wr_addra/count_r_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axi_smc/inst/s03_nodes/s03_w_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13/RAMB_D1/WADR0
                            (rising edge-triggered cell RAMD32 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk_pl_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_pl_0 rise@0.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        0.170ns  (logic 0.059ns (34.744%)  route 0.111ns (65.256%))
  Logic Levels:           0  
  Clock Path Skew:        0.072ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.472ns
    Source Clock Delay      (SCD):    2.144ns
    Clock Pessimism Removal (CPR):    0.255ns
  Clock Net Delay (Source):      1.962ns (routing 0.690ns, distribution 1.272ns)
  Clock Net Delay (Destination): 2.246ns (routing 0.763ns, distribution 1.483ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       1.962     2.144    d_1_i/axi_smc/inst/s03_nodes/s03_w_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_wr_addra/s_sc_aclk
    SLICE_X43Y20         FDRE                                         r  d_1_i/axi_smc/inst/s03_nodes/s03_w_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_wr_addra/count_r_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X43Y20         FDRE (Prop_HFF2_SLICEL_C_Q)
                                                      0.059     2.203 r  d_1_i/axi_smc/inst/s03_nodes/s03_w_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_wr_addra/count_r_reg[0]/Q
                         net (fo=23, routed)          0.111     2.314    d_1_i/axi_smc/inst/s03_nodes/s03_w_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13/ADDRH0
    SLICE_X42Y21         RAMD32                                       r  d_1_i/axi_smc/inst/s03_nodes/s03_w_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13/RAMB_D1/WADR0
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       2.246     2.472    d_1_i/axi_smc/inst/s03_nodes/s03_w_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13/WCLK
    SLICE_X42Y21         RAMD32                                       r  d_1_i/axi_smc/inst/s03_nodes/s03_w_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13/RAMB_D1/CLK
                         clock pessimism             -0.255     2.216    
    SLICE_X42Y21         RAMD32 (Hold_B6LUT_SLICEM_CLK_WADR0)
                                                      0.085     2.301    d_1_i/axi_smc/inst/s03_nodes/s03_w_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13/RAMB_D1
  -------------------------------------------------------------------
                         required time                         -2.301    
                         arrival time                           2.314    
  -------------------------------------------------------------------
                         slack                                  0.013    

Slack (MET) :             0.013ns  (arrival time - required time)
  Source:                 d_1_i/axi_smc/inst/s03_nodes/s03_w_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_wr_addra/count_r_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axi_smc/inst/s03_nodes/s03_w_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13/RAMC/WADR0
                            (rising edge-triggered cell RAMD32 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk_pl_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_pl_0 rise@0.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        0.170ns  (logic 0.059ns (34.744%)  route 0.111ns (65.256%))
  Logic Levels:           0  
  Clock Path Skew:        0.072ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.472ns
    Source Clock Delay      (SCD):    2.144ns
    Clock Pessimism Removal (CPR):    0.255ns
  Clock Net Delay (Source):      1.962ns (routing 0.690ns, distribution 1.272ns)
  Clock Net Delay (Destination): 2.246ns (routing 0.763ns, distribution 1.483ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       1.962     2.144    d_1_i/axi_smc/inst/s03_nodes/s03_w_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_wr_addra/s_sc_aclk
    SLICE_X43Y20         FDRE                                         r  d_1_i/axi_smc/inst/s03_nodes/s03_w_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_wr_addra/count_r_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X43Y20         FDRE (Prop_HFF2_SLICEL_C_Q)
                                                      0.059     2.203 r  d_1_i/axi_smc/inst/s03_nodes/s03_w_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_wr_addra/count_r_reg[0]/Q
                         net (fo=23, routed)          0.111     2.314    d_1_i/axi_smc/inst/s03_nodes/s03_w_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13/ADDRH0
    SLICE_X42Y21         RAMD32                                       r  d_1_i/axi_smc/inst/s03_nodes/s03_w_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13/RAMC/WADR0
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       2.246     2.472    d_1_i/axi_smc/inst/s03_nodes/s03_w_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13/WCLK
    SLICE_X42Y21         RAMD32                                       r  d_1_i/axi_smc/inst/s03_nodes/s03_w_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13/RAMC/CLK
                         clock pessimism             -0.255     2.216    
    SLICE_X42Y21         RAMD32 (Hold_C5LUT_SLICEM_CLK_WADR0)
                                                      0.085     2.301    d_1_i/axi_smc/inst/s03_nodes/s03_w_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13/RAMC
  -------------------------------------------------------------------
                         required time                         -2.301    
                         arrival time                           2.314    
  -------------------------------------------------------------------
                         slack                                  0.013    

Slack (MET) :             0.013ns  (arrival time - required time)
  Source:                 d_1_i/axi_smc/inst/s03_nodes/s03_w_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_wr_addra/count_r_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axi_smc/inst/s03_nodes/s03_w_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13/RAMC_D1/WADR0
                            (rising edge-triggered cell RAMD32 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk_pl_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_pl_0 rise@0.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        0.170ns  (logic 0.059ns (34.744%)  route 0.111ns (65.256%))
  Logic Levels:           0  
  Clock Path Skew:        0.072ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.472ns
    Source Clock Delay      (SCD):    2.144ns
    Clock Pessimism Removal (CPR):    0.255ns
  Clock Net Delay (Source):      1.962ns (routing 0.690ns, distribution 1.272ns)
  Clock Net Delay (Destination): 2.246ns (routing 0.763ns, distribution 1.483ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       1.962     2.144    d_1_i/axi_smc/inst/s03_nodes/s03_w_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_wr_addra/s_sc_aclk
    SLICE_X43Y20         FDRE                                         r  d_1_i/axi_smc/inst/s03_nodes/s03_w_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_wr_addra/count_r_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X43Y20         FDRE (Prop_HFF2_SLICEL_C_Q)
                                                      0.059     2.203 r  d_1_i/axi_smc/inst/s03_nodes/s03_w_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_wr_addra/count_r_reg[0]/Q
                         net (fo=23, routed)          0.111     2.314    d_1_i/axi_smc/inst/s03_nodes/s03_w_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13/ADDRH0
    SLICE_X42Y21         RAMD32                                       r  d_1_i/axi_smc/inst/s03_nodes/s03_w_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13/RAMC_D1/WADR0
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       2.246     2.472    d_1_i/axi_smc/inst/s03_nodes/s03_w_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13/WCLK
    SLICE_X42Y21         RAMD32                                       r  d_1_i/axi_smc/inst/s03_nodes/s03_w_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13/RAMC_D1/CLK
                         clock pessimism             -0.255     2.216    
    SLICE_X42Y21         RAMD32 (Hold_C6LUT_SLICEM_CLK_WADR0)
                                                      0.085     2.301    d_1_i/axi_smc/inst/s03_nodes/s03_w_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13/RAMC_D1
  -------------------------------------------------------------------
                         required time                         -2.301    
                         arrival time                           2.314    
  -------------------------------------------------------------------
                         slack                                  0.013    





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         clk_pl_0
Waveform(ns):       { 0.000 5.000 }
Period(ns):         10.000
Sources:            { d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0] }

Check Type        Corner  Lib Pin           Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location    Pin
Min Period        n/a     HSADC/DCLK        n/a            4.000         10.000      6.000      HSADC_X0Y0  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/DCLK
Min Period        n/a     HSADC/DCLK        n/a            4.000         10.000      6.000      HSADC_X0Y1  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/DCLK
Min Period        n/a     HSADC/DCLK        n/a            4.000         10.000      6.000      HSADC_X0Y2  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/DCLK
Min Period        n/a     HSADC/DCLK        n/a            4.000         10.000      6.000      HSADC_X0Y3  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/DCLK
Min Period        n/a     HSDAC/DCLK        n/a            4.000         10.000      6.000      HSDAC_X0Y0  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/DCLK
Min Period        n/a     HSDAC/DCLK        n/a            4.000         10.000      6.000      HSDAC_X0Y1  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/DCLK
Min Period        n/a     PS8/MAXIGP0ACLK   n/a            3.000         10.000      7.000      PS8_X0Y0    d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/MAXIGP0ACLK
Min Period        n/a     PS8/SAXIGP0RCLK   n/a            3.000         10.000      7.000      PS8_X0Y0    d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/SAXIGP0RCLK
Min Period        n/a     PS8/SAXIGP0WCLK   n/a            3.000         10.000      7.000      PS8_X0Y0    d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/SAXIGP0WCLK
Min Period        n/a     HSADC/PLL_MONCLK  n/a            2.500         10.000      7.500      HSADC_X0Y0  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/PLL_MONCLK
Low Pulse Width   Slow    HSADC/DCLK        n/a            1.600         5.000       3.400      HSADC_X0Y0  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/DCLK
Low Pulse Width   Fast    HSADC/DCLK        n/a            1.600         5.000       3.400      HSADC_X0Y0  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/DCLK
Low Pulse Width   Slow    HSADC/DCLK        n/a            1.600         5.000       3.400      HSADC_X0Y1  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/DCLK
Low Pulse Width   Fast    HSADC/DCLK        n/a            1.600         5.000       3.400      HSADC_X0Y1  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/DCLK
Low Pulse Width   Slow    HSADC/DCLK        n/a            1.600         5.000       3.400      HSADC_X0Y2  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/DCLK
Low Pulse Width   Fast    HSADC/DCLK        n/a            1.600         5.000       3.400      HSADC_X0Y2  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/DCLK
Low Pulse Width   Slow    HSADC/DCLK        n/a            1.600         5.000       3.400      HSADC_X0Y3  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/DCLK
Low Pulse Width   Fast    HSADC/DCLK        n/a            1.600         5.000       3.400      HSADC_X0Y3  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/DCLK
Low Pulse Width   Slow    HSDAC/DCLK        n/a            1.600         5.000       3.400      HSDAC_X0Y0  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/DCLK
Low Pulse Width   Fast    HSDAC/DCLK        n/a            1.600         5.000       3.400      HSDAC_X0Y0  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/DCLK
High Pulse Width  Slow    HSADC/DCLK        n/a            1.600         5.000       3.400      HSADC_X0Y0  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/DCLK
High Pulse Width  Fast    HSADC/DCLK        n/a            1.600         5.000       3.400      HSADC_X0Y0  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/DCLK
High Pulse Width  Slow    HSADC/DCLK        n/a            1.600         5.000       3.400      HSADC_X0Y1  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/DCLK
High Pulse Width  Fast    HSADC/DCLK        n/a            1.600         5.000       3.400      HSADC_X0Y1  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/DCLK
High Pulse Width  Slow    HSADC/DCLK        n/a            1.600         5.000       3.400      HSADC_X0Y2  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/DCLK
High Pulse Width  Fast    HSADC/DCLK        n/a            1.600         5.000       3.400      HSADC_X0Y2  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/DCLK
High Pulse Width  Slow    HSADC/DCLK        n/a            1.600         5.000       3.400      HSADC_X0Y3  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/DCLK
High Pulse Width  Fast    HSADC/DCLK        n/a            1.600         5.000       3.400      HSADC_X0Y3  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/DCLK
High Pulse Width  Slow    HSDAC/DCLK        n/a            1.600         5.000       3.400      HSDAC_X0Y0  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/DCLK
High Pulse Width  Fast    HSDAC/DCLK        n/a            1.600         5.000       3.400      HSDAC_X0Y0  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/DCLK



---------------------------------------------------------------------------------------------------
Path Group:  **async_default**
From Clock:  RFDAC0_CLK
  To Clock:  RFDAC0_CLK

Setup :            0  Failing Endpoints,  Worst Slack        0.734ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.107ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.734ns  (required time - arrival time)
  Source:                 d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_6/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/m_axis_tdata_r_reg[0][100]/CLR
                            (recovery check against rising-edge clock RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            2.441ns  (RFDAC0_CLK rise@2.441ns - RFDAC0_CLK rise@0.000ns)
  Data Path Delay:        1.415ns  (logic 0.077ns (5.443%)  route 1.338ns (94.557%))
  Logic Levels:           0  
  Clock Path Skew:        -0.191ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.763ns = ( 5.204 - 2.441 ) 
    Source Clock Delay      (SCD):    3.296ns
    Clock Pessimism Removal (CPR):    0.342ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.623ns (routing 1.490ns, distribution 1.133ns)
  Clock Net Delay (Destination): 2.242ns (routing 1.352ns, distribution 0.890ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=5276, routed)        2.623     3.296    d_1_i/rst_dac0/U0/slowest_sync_clk
    SLICE_X83Y159        FDRE                                         r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_6/C
  -------------------------------------------------------------------    -------------------
    SLICE_X83Y159        FDRE (Prop_AFF_SLICEM_C_Q)
                                                      0.077     3.373 r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_6/Q
                         net (fo=131, routed)         1.338     4.711    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/peripheral_aresetn[0]_repN_6_alias
    SLICE_X78Y141        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/m_axis_tdata_r_reg[0][100]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      2.441     2.441 r  
    HSDAC_X0Y0           HSDAC                        0.000     2.441 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     2.722 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     2.848    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     2.962 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=5276, routed)        2.242     5.204    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
    SLICE_X78Y141        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/m_axis_tdata_r_reg[0][100]/C
                         clock pessimism              0.342     5.546    
                         clock uncertainty           -0.035     5.510    
    SLICE_X78Y141        FDCE (Recov_DFF_SLICEM_C_CLR)
                                                     -0.066     5.444    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/m_axis_tdata_r_reg[0][100]
  -------------------------------------------------------------------
                         required time                          5.444    
                         arrival time                          -4.711    
  -------------------------------------------------------------------
                         slack                                  0.734    

Slack (MET) :             0.734ns  (required time - arrival time)
  Source:                 d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_6/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/m_axis_tdata_r_reg[0][101]/CLR
                            (recovery check against rising-edge clock RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            2.441ns  (RFDAC0_CLK rise@2.441ns - RFDAC0_CLK rise@0.000ns)
  Data Path Delay:        1.415ns  (logic 0.077ns (5.443%)  route 1.338ns (94.557%))
  Logic Levels:           0  
  Clock Path Skew:        -0.191ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.763ns = ( 5.204 - 2.441 ) 
    Source Clock Delay      (SCD):    3.296ns
    Clock Pessimism Removal (CPR):    0.342ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.623ns (routing 1.490ns, distribution 1.133ns)
  Clock Net Delay (Destination): 2.242ns (routing 1.352ns, distribution 0.890ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=5276, routed)        2.623     3.296    d_1_i/rst_dac0/U0/slowest_sync_clk
    SLICE_X83Y159        FDRE                                         r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_6/C
  -------------------------------------------------------------------    -------------------
    SLICE_X83Y159        FDRE (Prop_AFF_SLICEM_C_Q)
                                                      0.077     3.373 r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_6/Q
                         net (fo=131, routed)         1.338     4.711    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/peripheral_aresetn[0]_repN_6_alias
    SLICE_X78Y141        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/m_axis_tdata_r_reg[0][101]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      2.441     2.441 r  
    HSDAC_X0Y0           HSDAC                        0.000     2.441 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     2.722 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     2.848    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     2.962 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=5276, routed)        2.242     5.204    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
    SLICE_X78Y141        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/m_axis_tdata_r_reg[0][101]/C
                         clock pessimism              0.342     5.546    
                         clock uncertainty           -0.035     5.510    
    SLICE_X78Y141        FDCE (Recov_DFF2_SLICEM_C_CLR)
                                                     -0.066     5.444    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/m_axis_tdata_r_reg[0][101]
  -------------------------------------------------------------------
                         required time                          5.444    
                         arrival time                          -4.711    
  -------------------------------------------------------------------
                         slack                                  0.734    

Slack (MET) :             0.734ns  (required time - arrival time)
  Source:                 d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_6/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/m_axis_tdata_r_reg[0][102]/CLR
                            (recovery check against rising-edge clock RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            2.441ns  (RFDAC0_CLK rise@2.441ns - RFDAC0_CLK rise@0.000ns)
  Data Path Delay:        1.415ns  (logic 0.077ns (5.443%)  route 1.338ns (94.557%))
  Logic Levels:           0  
  Clock Path Skew:        -0.191ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.763ns = ( 5.204 - 2.441 ) 
    Source Clock Delay      (SCD):    3.296ns
    Clock Pessimism Removal (CPR):    0.342ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.623ns (routing 1.490ns, distribution 1.133ns)
  Clock Net Delay (Destination): 2.242ns (routing 1.352ns, distribution 0.890ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=5276, routed)        2.623     3.296    d_1_i/rst_dac0/U0/slowest_sync_clk
    SLICE_X83Y159        FDRE                                         r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_6/C
  -------------------------------------------------------------------    -------------------
    SLICE_X83Y159        FDRE (Prop_AFF_SLICEM_C_Q)
                                                      0.077     3.373 r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_6/Q
                         net (fo=131, routed)         1.338     4.711    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/peripheral_aresetn[0]_repN_6_alias
    SLICE_X78Y141        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/m_axis_tdata_r_reg[0][102]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      2.441     2.441 r  
    HSDAC_X0Y0           HSDAC                        0.000     2.441 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     2.722 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     2.848    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     2.962 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=5276, routed)        2.242     5.204    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
    SLICE_X78Y141        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/m_axis_tdata_r_reg[0][102]/C
                         clock pessimism              0.342     5.546    
                         clock uncertainty           -0.035     5.510    
    SLICE_X78Y141        FDCE (Recov_CFF_SLICEM_C_CLR)
                                                     -0.066     5.444    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/m_axis_tdata_r_reg[0][102]
  -------------------------------------------------------------------
                         required time                          5.444    
                         arrival time                          -4.711    
  -------------------------------------------------------------------
                         slack                                  0.734    

Slack (MET) :             0.734ns  (required time - arrival time)
  Source:                 d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_6/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/m_axis_tdata_r_reg[0][103]/CLR
                            (recovery check against rising-edge clock RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            2.441ns  (RFDAC0_CLK rise@2.441ns - RFDAC0_CLK rise@0.000ns)
  Data Path Delay:        1.415ns  (logic 0.077ns (5.443%)  route 1.338ns (94.557%))
  Logic Levels:           0  
  Clock Path Skew:        -0.191ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.763ns = ( 5.204 - 2.441 ) 
    Source Clock Delay      (SCD):    3.296ns
    Clock Pessimism Removal (CPR):    0.342ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.623ns (routing 1.490ns, distribution 1.133ns)
  Clock Net Delay (Destination): 2.242ns (routing 1.352ns, distribution 0.890ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=5276, routed)        2.623     3.296    d_1_i/rst_dac0/U0/slowest_sync_clk
    SLICE_X83Y159        FDRE                                         r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_6/C
  -------------------------------------------------------------------    -------------------
    SLICE_X83Y159        FDRE (Prop_AFF_SLICEM_C_Q)
                                                      0.077     3.373 r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_6/Q
                         net (fo=131, routed)         1.338     4.711    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/peripheral_aresetn[0]_repN_6_alias
    SLICE_X78Y141        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/m_axis_tdata_r_reg[0][103]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      2.441     2.441 r  
    HSDAC_X0Y0           HSDAC                        0.000     2.441 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     2.722 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     2.848    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     2.962 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=5276, routed)        2.242     5.204    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
    SLICE_X78Y141        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/m_axis_tdata_r_reg[0][103]/C
                         clock pessimism              0.342     5.546    
                         clock uncertainty           -0.035     5.510    
    SLICE_X78Y141        FDCE (Recov_CFF2_SLICEM_C_CLR)
                                                     -0.066     5.444    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/m_axis_tdata_r_reg[0][103]
  -------------------------------------------------------------------
                         required time                          5.444    
                         arrival time                          -4.711    
  -------------------------------------------------------------------
                         slack                                  0.734    

Slack (MET) :             0.734ns  (required time - arrival time)
  Source:                 d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_6/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/m_axis_tdata_r_reg[0][132]/CLR
                            (recovery check against rising-edge clock RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            2.441ns  (RFDAC0_CLK rise@2.441ns - RFDAC0_CLK rise@0.000ns)
  Data Path Delay:        1.415ns  (logic 0.077ns (5.443%)  route 1.338ns (94.557%))
  Logic Levels:           0  
  Clock Path Skew:        -0.191ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.763ns = ( 5.204 - 2.441 ) 
    Source Clock Delay      (SCD):    3.296ns
    Clock Pessimism Removal (CPR):    0.342ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.623ns (routing 1.490ns, distribution 1.133ns)
  Clock Net Delay (Destination): 2.242ns (routing 1.352ns, distribution 0.890ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=5276, routed)        2.623     3.296    d_1_i/rst_dac0/U0/slowest_sync_clk
    SLICE_X83Y159        FDRE                                         r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_6/C
  -------------------------------------------------------------------    -------------------
    SLICE_X83Y159        FDRE (Prop_AFF_SLICEM_C_Q)
                                                      0.077     3.373 r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_6/Q
                         net (fo=131, routed)         1.338     4.711    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/peripheral_aresetn[0]_repN_6_alias
    SLICE_X78Y141        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/m_axis_tdata_r_reg[0][132]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      2.441     2.441 r  
    HSDAC_X0Y0           HSDAC                        0.000     2.441 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     2.722 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     2.848    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     2.962 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=5276, routed)        2.242     5.204    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
    SLICE_X78Y141        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/m_axis_tdata_r_reg[0][132]/C
                         clock pessimism              0.342     5.546    
                         clock uncertainty           -0.035     5.510    
    SLICE_X78Y141        FDCE (Recov_BFF_SLICEM_C_CLR)
                                                     -0.066     5.444    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/m_axis_tdata_r_reg[0][132]
  -------------------------------------------------------------------
                         required time                          5.444    
                         arrival time                          -4.711    
  -------------------------------------------------------------------
                         slack                                  0.734    

Slack (MET) :             0.734ns  (required time - arrival time)
  Source:                 d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_6/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/m_axis_tdata_r_reg[0][133]/CLR
                            (recovery check against rising-edge clock RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            2.441ns  (RFDAC0_CLK rise@2.441ns - RFDAC0_CLK rise@0.000ns)
  Data Path Delay:        1.415ns  (logic 0.077ns (5.443%)  route 1.338ns (94.557%))
  Logic Levels:           0  
  Clock Path Skew:        -0.191ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.763ns = ( 5.204 - 2.441 ) 
    Source Clock Delay      (SCD):    3.296ns
    Clock Pessimism Removal (CPR):    0.342ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.623ns (routing 1.490ns, distribution 1.133ns)
  Clock Net Delay (Destination): 2.242ns (routing 1.352ns, distribution 0.890ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=5276, routed)        2.623     3.296    d_1_i/rst_dac0/U0/slowest_sync_clk
    SLICE_X83Y159        FDRE                                         r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_6/C
  -------------------------------------------------------------------    -------------------
    SLICE_X83Y159        FDRE (Prop_AFF_SLICEM_C_Q)
                                                      0.077     3.373 r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_6/Q
                         net (fo=131, routed)         1.338     4.711    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/peripheral_aresetn[0]_repN_6_alias
    SLICE_X78Y141        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/m_axis_tdata_r_reg[0][133]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      2.441     2.441 r  
    HSDAC_X0Y0           HSDAC                        0.000     2.441 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     2.722 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     2.848    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     2.962 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=5276, routed)        2.242     5.204    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
    SLICE_X78Y141        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/m_axis_tdata_r_reg[0][133]/C
                         clock pessimism              0.342     5.546    
                         clock uncertainty           -0.035     5.510    
    SLICE_X78Y141        FDCE (Recov_BFF2_SLICEM_C_CLR)
                                                     -0.066     5.444    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/m_axis_tdata_r_reg[0][133]
  -------------------------------------------------------------------
                         required time                          5.444    
                         arrival time                          -4.711    
  -------------------------------------------------------------------
                         slack                                  0.734    

Slack (MET) :             0.734ns  (required time - arrival time)
  Source:                 d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_6/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/m_axis_tdata_r_reg[0][96]/CLR
                            (recovery check against rising-edge clock RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            2.441ns  (RFDAC0_CLK rise@2.441ns - RFDAC0_CLK rise@0.000ns)
  Data Path Delay:        1.415ns  (logic 0.077ns (5.443%)  route 1.338ns (94.557%))
  Logic Levels:           0  
  Clock Path Skew:        -0.191ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.763ns = ( 5.204 - 2.441 ) 
    Source Clock Delay      (SCD):    3.296ns
    Clock Pessimism Removal (CPR):    0.342ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.623ns (routing 1.490ns, distribution 1.133ns)
  Clock Net Delay (Destination): 2.242ns (routing 1.352ns, distribution 0.890ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=5276, routed)        2.623     3.296    d_1_i/rst_dac0/U0/slowest_sync_clk
    SLICE_X83Y159        FDRE                                         r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_6/C
  -------------------------------------------------------------------    -------------------
    SLICE_X83Y159        FDRE (Prop_AFF_SLICEM_C_Q)
                                                      0.077     3.373 r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_6/Q
                         net (fo=131, routed)         1.338     4.711    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/peripheral_aresetn[0]_repN_6_alias
    SLICE_X78Y141        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/m_axis_tdata_r_reg[0][96]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      2.441     2.441 r  
    HSDAC_X0Y0           HSDAC                        0.000     2.441 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     2.722 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     2.848    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     2.962 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=5276, routed)        2.242     5.204    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
    SLICE_X78Y141        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/m_axis_tdata_r_reg[0][96]/C
                         clock pessimism              0.342     5.546    
                         clock uncertainty           -0.035     5.510    
    SLICE_X78Y141        FDCE (Recov_AFF_SLICEM_C_CLR)
                                                     -0.066     5.444    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/m_axis_tdata_r_reg[0][96]
  -------------------------------------------------------------------
                         required time                          5.444    
                         arrival time                          -4.711    
  -------------------------------------------------------------------
                         slack                                  0.734    

Slack (MET) :             0.734ns  (required time - arrival time)
  Source:                 d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_6/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/m_axis_tdata_r_reg[0][97]/CLR
                            (recovery check against rising-edge clock RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            2.441ns  (RFDAC0_CLK rise@2.441ns - RFDAC0_CLK rise@0.000ns)
  Data Path Delay:        1.415ns  (logic 0.077ns (5.443%)  route 1.338ns (94.557%))
  Logic Levels:           0  
  Clock Path Skew:        -0.191ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.763ns = ( 5.204 - 2.441 ) 
    Source Clock Delay      (SCD):    3.296ns
    Clock Pessimism Removal (CPR):    0.342ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.623ns (routing 1.490ns, distribution 1.133ns)
  Clock Net Delay (Destination): 2.242ns (routing 1.352ns, distribution 0.890ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=5276, routed)        2.623     3.296    d_1_i/rst_dac0/U0/slowest_sync_clk
    SLICE_X83Y159        FDRE                                         r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_6/C
  -------------------------------------------------------------------    -------------------
    SLICE_X83Y159        FDRE (Prop_AFF_SLICEM_C_Q)
                                                      0.077     3.373 r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_6/Q
                         net (fo=131, routed)         1.338     4.711    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/peripheral_aresetn[0]_repN_6_alias
    SLICE_X78Y141        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/m_axis_tdata_r_reg[0][97]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      2.441     2.441 r  
    HSDAC_X0Y0           HSDAC                        0.000     2.441 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     2.722 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     2.848    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     2.962 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=5276, routed)        2.242     5.204    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
    SLICE_X78Y141        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/m_axis_tdata_r_reg[0][97]/C
                         clock pessimism              0.342     5.546    
                         clock uncertainty           -0.035     5.510    
    SLICE_X78Y141        FDCE (Recov_AFF2_SLICEM_C_CLR)
                                                     -0.066     5.444    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/m_axis_tdata_r_reg[0][97]
  -------------------------------------------------------------------
                         required time                          5.444    
                         arrival time                          -4.711    
  -------------------------------------------------------------------
                         slack                                  0.734    

Slack (MET) :             0.736ns  (required time - arrival time)
  Source:                 d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_6/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/m_axis_tdata_r_reg[0][98]/CLR
                            (recovery check against rising-edge clock RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            2.441ns  (RFDAC0_CLK rise@2.441ns - RFDAC0_CLK rise@0.000ns)
  Data Path Delay:        1.412ns  (logic 0.077ns (5.455%)  route 1.335ns (94.545%))
  Logic Levels:           0  
  Clock Path Skew:        -0.192ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.762ns = ( 5.203 - 2.441 ) 
    Source Clock Delay      (SCD):    3.296ns
    Clock Pessimism Removal (CPR):    0.342ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.623ns (routing 1.490ns, distribution 1.133ns)
  Clock Net Delay (Destination): 2.241ns (routing 1.352ns, distribution 0.889ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=5276, routed)        2.623     3.296    d_1_i/rst_dac0/U0/slowest_sync_clk
    SLICE_X83Y159        FDRE                                         r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_6/C
  -------------------------------------------------------------------    -------------------
    SLICE_X83Y159        FDRE (Prop_AFF_SLICEM_C_Q)
                                                      0.077     3.373 r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_6/Q
                         net (fo=131, routed)         1.335     4.708    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/peripheral_aresetn[0]_repN_6_alias
    SLICE_X78Y141        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/m_axis_tdata_r_reg[0][98]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      2.441     2.441 r  
    HSDAC_X0Y0           HSDAC                        0.000     2.441 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     2.722 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     2.848    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     2.962 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=5276, routed)        2.241     5.203    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
    SLICE_X78Y141        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/m_axis_tdata_r_reg[0][98]/C
                         clock pessimism              0.342     5.545    
                         clock uncertainty           -0.035     5.509    
    SLICE_X78Y141        FDCE (Recov_HFF_SLICEM_C_CLR)
                                                     -0.066     5.443    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/m_axis_tdata_r_reg[0][98]
  -------------------------------------------------------------------
                         required time                          5.443    
                         arrival time                          -4.708    
  -------------------------------------------------------------------
                         slack                                  0.736    

Slack (MET) :             0.736ns  (required time - arrival time)
  Source:                 d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_6/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/m_axis_tdata_r_reg[0][99]/CLR
                            (recovery check against rising-edge clock RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            2.441ns  (RFDAC0_CLK rise@2.441ns - RFDAC0_CLK rise@0.000ns)
  Data Path Delay:        1.412ns  (logic 0.077ns (5.455%)  route 1.335ns (94.545%))
  Logic Levels:           0  
  Clock Path Skew:        -0.192ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.762ns = ( 5.203 - 2.441 ) 
    Source Clock Delay      (SCD):    3.296ns
    Clock Pessimism Removal (CPR):    0.342ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.623ns (routing 1.490ns, distribution 1.133ns)
  Clock Net Delay (Destination): 2.241ns (routing 1.352ns, distribution 0.889ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=5276, routed)        2.623     3.296    d_1_i/rst_dac0/U0/slowest_sync_clk
    SLICE_X83Y159        FDRE                                         r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_6/C
  -------------------------------------------------------------------    -------------------
    SLICE_X83Y159        FDRE (Prop_AFF_SLICEM_C_Q)
                                                      0.077     3.373 r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_6/Q
                         net (fo=131, routed)         1.335     4.708    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/peripheral_aresetn[0]_repN_6_alias
    SLICE_X78Y141        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/m_axis_tdata_r_reg[0][99]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      2.441     2.441 r  
    HSDAC_X0Y0           HSDAC                        0.000     2.441 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     2.722 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     2.848    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     2.962 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=5276, routed)        2.241     5.203    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
    SLICE_X78Y141        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/m_axis_tdata_r_reg[0][99]/C
                         clock pessimism              0.342     5.545    
                         clock uncertainty           -0.035     5.509    
    SLICE_X78Y141        FDCE (Recov_HFF2_SLICEM_C_CLR)
                                                     -0.066     5.443    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/m_axis_tdata_r_reg[0][99]
  -------------------------------------------------------------------
                         required time                          5.443    
                         arrival time                          -4.708    
  -------------------------------------------------------------------
                         slack                                  0.736    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.107ns  (arrival time - required time)
  Source:                 d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_2/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[3]/CLR
                            (removal check against rising-edge clock RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (RFDAC0_CLK rise@0.000ns - RFDAC0_CLK rise@0.000ns)
  Data Path Delay:        0.134ns  (logic 0.038ns (28.425%)  route 0.096ns (71.575%))
  Logic Levels:           0  
  Clock Path Skew:        0.047ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.991ns
    Source Clock Delay      (SCD):    1.719ns
    Clock Pessimism Removal (CPR):    0.225ns
  Clock Net Delay (Source):      1.370ns (routing 0.805ns, distribution 0.565ns)
  Clock Net Delay (Destination): 1.543ns (routing 0.900ns, distribution 0.643ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=5276, routed)        1.370     1.719    d_1_i/rst_dac0/U0/slowest_sync_clk
    SLICE_X79Y144        FDRE                                         r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_2/C
  -------------------------------------------------------------------    -------------------
    SLICE_X79Y144        FDRE (Prop_AFF_SLICEM_C_Q)
                                                      0.038     1.757 r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_2/Q
                         net (fo=170, routed)         0.096     1.852    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_rd_ptr/peripheral_aresetn[0]_repN_2_alias
    SLICE_X77Y144        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[3]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=5276, routed)        1.543     1.991    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_rd_ptr/t_clk_i
    SLICE_X77Y144        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[3]/C
                         clock pessimism             -0.225     1.766    
    SLICE_X77Y144        FDCE (Remov_DFF_SLICEL_C_CLR)
                                                     -0.020     1.746    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[3]
  -------------------------------------------------------------------
                         required time                         -1.746    
                         arrival time                           1.852    
  -------------------------------------------------------------------
                         slack                                  0.107    

Slack (MET) :             0.107ns  (arrival time - required time)
  Source:                 d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_2/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[5]/CLR
                            (removal check against rising-edge clock RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (RFDAC0_CLK rise@0.000ns - RFDAC0_CLK rise@0.000ns)
  Data Path Delay:        0.134ns  (logic 0.038ns (28.425%)  route 0.096ns (71.575%))
  Logic Levels:           0  
  Clock Path Skew:        0.047ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.991ns
    Source Clock Delay      (SCD):    1.719ns
    Clock Pessimism Removal (CPR):    0.225ns
  Clock Net Delay (Source):      1.370ns (routing 0.805ns, distribution 0.565ns)
  Clock Net Delay (Destination): 1.543ns (routing 0.900ns, distribution 0.643ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=5276, routed)        1.370     1.719    d_1_i/rst_dac0/U0/slowest_sync_clk
    SLICE_X79Y144        FDRE                                         r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_2/C
  -------------------------------------------------------------------    -------------------
    SLICE_X79Y144        FDRE (Prop_AFF_SLICEM_C_Q)
                                                      0.038     1.757 r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_2/Q
                         net (fo=170, routed)         0.096     1.852    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_rd_ptr/peripheral_aresetn[0]_repN_2_alias
    SLICE_X77Y144        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[5]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=5276, routed)        1.543     1.991    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_rd_ptr/t_clk_i
    SLICE_X77Y144        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[5]/C
                         clock pessimism             -0.225     1.766    
    SLICE_X77Y144        FDCE (Remov_CFF_SLICEL_C_CLR)
                                                     -0.020     1.746    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[5]
  -------------------------------------------------------------------
                         required time                         -1.746    
                         arrival time                           1.852    
  -------------------------------------------------------------------
                         slack                                  0.107    

Slack (MET) :             0.107ns  (arrival time - required time)
  Source:                 d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_2/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[6]/CLR
                            (removal check against rising-edge clock RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (RFDAC0_CLK rise@0.000ns - RFDAC0_CLK rise@0.000ns)
  Data Path Delay:        0.134ns  (logic 0.038ns (28.425%)  route 0.096ns (71.575%))
  Logic Levels:           0  
  Clock Path Skew:        0.047ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.991ns
    Source Clock Delay      (SCD):    1.719ns
    Clock Pessimism Removal (CPR):    0.225ns
  Clock Net Delay (Source):      1.370ns (routing 0.805ns, distribution 0.565ns)
  Clock Net Delay (Destination): 1.543ns (routing 0.900ns, distribution 0.643ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=5276, routed)        1.370     1.719    d_1_i/rst_dac0/U0/slowest_sync_clk
    SLICE_X79Y144        FDRE                                         r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_2/C
  -------------------------------------------------------------------    -------------------
    SLICE_X79Y144        FDRE (Prop_AFF_SLICEM_C_Q)
                                                      0.038     1.757 r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_2/Q
                         net (fo=170, routed)         0.096     1.852    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_rd_ptr/peripheral_aresetn[0]_repN_2_alias
    SLICE_X77Y144        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[6]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=5276, routed)        1.543     1.991    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_rd_ptr/t_clk_i
    SLICE_X77Y144        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[6]/C
                         clock pessimism             -0.225     1.766    
    SLICE_X77Y144        FDCE (Remov_BFF_SLICEL_C_CLR)
                                                     -0.020     1.746    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[6]
  -------------------------------------------------------------------
                         required time                         -1.746    
                         arrival time                           1.852    
  -------------------------------------------------------------------
                         slack                                  0.107    

Slack (MET) :             0.107ns  (arrival time - required time)
  Source:                 d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_2/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[7]/CLR
                            (removal check against rising-edge clock RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (RFDAC0_CLK rise@0.000ns - RFDAC0_CLK rise@0.000ns)
  Data Path Delay:        0.134ns  (logic 0.038ns (28.425%)  route 0.096ns (71.575%))
  Logic Levels:           0  
  Clock Path Skew:        0.047ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.991ns
    Source Clock Delay      (SCD):    1.719ns
    Clock Pessimism Removal (CPR):    0.225ns
  Clock Net Delay (Source):      1.370ns (routing 0.805ns, distribution 0.565ns)
  Clock Net Delay (Destination): 1.543ns (routing 0.900ns, distribution 0.643ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=5276, routed)        1.370     1.719    d_1_i/rst_dac0/U0/slowest_sync_clk
    SLICE_X79Y144        FDRE                                         r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_2/C
  -------------------------------------------------------------------    -------------------
    SLICE_X79Y144        FDRE (Prop_AFF_SLICEM_C_Q)
                                                      0.038     1.757 r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_2/Q
                         net (fo=170, routed)         0.096     1.852    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_rd_ptr/peripheral_aresetn[0]_repN_2_alias
    SLICE_X77Y144        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[7]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=5276, routed)        1.543     1.991    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_rd_ptr/t_clk_i
    SLICE_X77Y144        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[7]/C
                         clock pessimism             -0.225     1.766    
    SLICE_X77Y144        FDCE (Remov_AFF_SLICEL_C_CLR)
                                                     -0.020     1.746    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[7]
  -------------------------------------------------------------------
                         required time                         -1.746    
                         arrival time                           1.852    
  -------------------------------------------------------------------
                         slack                                  0.107    

Slack (MET) :             0.110ns  (arrival time - required time)
  Source:                 d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_4/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[0]/CLR
                            (removal check against rising-edge clock RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (RFDAC0_CLK rise@0.000ns - RFDAC0_CLK rise@0.000ns)
  Data Path Delay:        0.141ns  (logic 0.039ns (27.646%)  route 0.102ns (72.354%))
  Logic Levels:           0  
  Clock Path Skew:        0.051ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.995ns
    Source Clock Delay      (SCD):    1.719ns
    Clock Pessimism Removal (CPR):    0.225ns
  Clock Net Delay (Source):      1.370ns (routing 0.805ns, distribution 0.565ns)
  Clock Net Delay (Destination): 1.547ns (routing 0.900ns, distribution 0.647ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=5276, routed)        1.370     1.719    d_1_i/rst_dac0/U0/slowest_sync_clk
    SLICE_X79Y144        FDRE                                         r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_4/C
  -------------------------------------------------------------------    -------------------
    SLICE_X79Y144        FDRE (Prop_AFF2_SLICEM_C_Q)
                                                      0.039     1.758 r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_4/Q
                         net (fo=238, routed)         0.102     1.860    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_rd_ptr/peripheral_aresetn[0]_repN_4_alias
    SLICE_X77Y144        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[0]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=5276, routed)        1.547     1.995    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_rd_ptr/t_clk_i
    SLICE_X77Y144        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[0]/C
                         clock pessimism             -0.225     1.770    
    SLICE_X77Y144        FDCE (Remov_HFF2_SLICEL_C_CLR)
                                                     -0.020     1.750    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[0]
  -------------------------------------------------------------------
                         required time                         -1.750    
                         arrival time                           1.860    
  -------------------------------------------------------------------
                         slack                                  0.110    

Slack (MET) :             0.110ns  (arrival time - required time)
  Source:                 d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_4/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[4]/CLR
                            (removal check against rising-edge clock RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (RFDAC0_CLK rise@0.000ns - RFDAC0_CLK rise@0.000ns)
  Data Path Delay:        0.141ns  (logic 0.039ns (27.646%)  route 0.102ns (72.354%))
  Logic Levels:           0  
  Clock Path Skew:        0.051ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.995ns
    Source Clock Delay      (SCD):    1.719ns
    Clock Pessimism Removal (CPR):    0.225ns
  Clock Net Delay (Source):      1.370ns (routing 0.805ns, distribution 0.565ns)
  Clock Net Delay (Destination): 1.547ns (routing 0.900ns, distribution 0.647ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=5276, routed)        1.370     1.719    d_1_i/rst_dac0/U0/slowest_sync_clk
    SLICE_X79Y144        FDRE                                         r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_4/C
  -------------------------------------------------------------------    -------------------
    SLICE_X79Y144        FDRE (Prop_AFF2_SLICEM_C_Q)
                                                      0.039     1.758 r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_4/Q
                         net (fo=238, routed)         0.102     1.860    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_rd_ptr/peripheral_aresetn[0]_repN_4_alias
    SLICE_X77Y144        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[4]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=5276, routed)        1.547     1.995    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_rd_ptr/t_clk_i
    SLICE_X77Y144        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[4]/C
                         clock pessimism             -0.225     1.770    
    SLICE_X77Y144        FDCE (Remov_HFF_SLICEL_C_CLR)
                                                     -0.020     1.750    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[4]
  -------------------------------------------------------------------
                         required time                         -1.750    
                         arrival time                           1.860    
  -------------------------------------------------------------------
                         slack                                  0.110    

Slack (MET) :             0.110ns  (arrival time - required time)
  Source:                 d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_4/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[8]/CLR
                            (removal check against rising-edge clock RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (RFDAC0_CLK rise@0.000ns - RFDAC0_CLK rise@0.000ns)
  Data Path Delay:        0.141ns  (logic 0.039ns (27.646%)  route 0.102ns (72.354%))
  Logic Levels:           0  
  Clock Path Skew:        0.051ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.995ns
    Source Clock Delay      (SCD):    1.719ns
    Clock Pessimism Removal (CPR):    0.225ns
  Clock Net Delay (Source):      1.370ns (routing 0.805ns, distribution 0.565ns)
  Clock Net Delay (Destination): 1.547ns (routing 0.900ns, distribution 0.647ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=5276, routed)        1.370     1.719    d_1_i/rst_dac0/U0/slowest_sync_clk
    SLICE_X79Y144        FDRE                                         r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_4/C
  -------------------------------------------------------------------    -------------------
    SLICE_X79Y144        FDRE (Prop_AFF2_SLICEM_C_Q)
                                                      0.039     1.758 r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_4/Q
                         net (fo=238, routed)         0.102     1.860    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_rd_ptr/peripheral_aresetn[0]_repN_4_alias
    SLICE_X77Y144        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[8]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=5276, routed)        1.547     1.995    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_rd_ptr/t_clk_i
    SLICE_X77Y144        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[8]/C
                         clock pessimism             -0.225     1.770    
    SLICE_X77Y144        FDCE (Remov_GFF_SLICEL_C_CLR)
                                                     -0.020     1.750    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[8]
  -------------------------------------------------------------------
                         required time                         -1.750    
                         arrival time                           1.860    
  -------------------------------------------------------------------
                         slack                                  0.110    

Slack (MET) :             0.161ns  (arrival time - required time)
  Source:                 d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_5/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[1]/CLR
                            (removal check against rising-edge clock RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (RFDAC0_CLK rise@0.000ns - RFDAC0_CLK rise@0.000ns)
  Data Path Delay:        0.185ns  (logic 0.038ns (20.568%)  route 0.147ns (79.432%))
  Logic Levels:           0  
  Clock Path Skew:        0.044ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.985ns
    Source Clock Delay      (SCD):    1.717ns
    Clock Pessimism Removal (CPR):    0.225ns
  Clock Net Delay (Source):      1.368ns (routing 0.805ns, distribution 0.563ns)
  Clock Net Delay (Destination): 1.537ns (routing 0.900ns, distribution 0.637ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=5276, routed)        1.368     1.717    d_1_i/rst_dac0/U0/slowest_sync_clk
    SLICE_X78Y145        FDRE                                         r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_5/C
  -------------------------------------------------------------------    -------------------
    SLICE_X78Y145        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.038     1.755 r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_5/Q
                         net (fo=129, routed)         0.147     1.901    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/peripheral_aresetn[0]_repN_5_alias
    SLICE_X75Y145        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[1]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=5276, routed)        1.537     1.985    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
    SLICE_X75Y145        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[1]/C
                         clock pessimism             -0.225     1.760    
    SLICE_X75Y145        FDCE (Remov_DFF2_SLICEM_C_CLR)
                                                     -0.020     1.740    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[1]
  -------------------------------------------------------------------
                         required time                         -1.740    
                         arrival time                           1.901    
  -------------------------------------------------------------------
                         slack                                  0.161    

Slack (MET) :             0.161ns  (arrival time - required time)
  Source:                 d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_5/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/trig_pop_r2_reg[1]/CLR
                            (removal check against rising-edge clock RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (RFDAC0_CLK rise@0.000ns - RFDAC0_CLK rise@0.000ns)
  Data Path Delay:        0.185ns  (logic 0.038ns (20.568%)  route 0.147ns (79.432%))
  Logic Levels:           0  
  Clock Path Skew:        0.044ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.985ns
    Source Clock Delay      (SCD):    1.717ns
    Clock Pessimism Removal (CPR):    0.225ns
  Clock Net Delay (Source):      1.368ns (routing 0.805ns, distribution 0.563ns)
  Clock Net Delay (Destination): 1.537ns (routing 0.900ns, distribution 0.637ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=5276, routed)        1.368     1.717    d_1_i/rst_dac0/U0/slowest_sync_clk
    SLICE_X78Y145        FDRE                                         r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_5/C
  -------------------------------------------------------------------    -------------------
    SLICE_X78Y145        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.038     1.755 r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_5/Q
                         net (fo=129, routed)         0.147     1.901    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/peripheral_aresetn[0]_repN_5_alias
    SLICE_X75Y145        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/trig_pop_r2_reg[1]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=5276, routed)        1.537     1.985    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
    SLICE_X75Y145        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/trig_pop_r2_reg[1]/C
                         clock pessimism             -0.225     1.760    
    SLICE_X75Y145        FDCE (Remov_AFF_SLICEM_C_CLR)
                                                     -0.020     1.740    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/trig_pop_r2_reg[1]
  -------------------------------------------------------------------
                         required time                         -1.740    
                         arrival time                           1.901    
  -------------------------------------------------------------------
                         slack                                  0.161    

Slack (MET) :             0.161ns  (arrival time - required time)
  Source:                 d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_5/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/trig_pop_r3_reg[1]/CLR
                            (removal check against rising-edge clock RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (RFDAC0_CLK rise@0.000ns - RFDAC0_CLK rise@0.000ns)
  Data Path Delay:        0.185ns  (logic 0.038ns (20.568%)  route 0.147ns (79.432%))
  Logic Levels:           0  
  Clock Path Skew:        0.044ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.985ns
    Source Clock Delay      (SCD):    1.717ns
    Clock Pessimism Removal (CPR):    0.225ns
  Clock Net Delay (Source):      1.368ns (routing 0.805ns, distribution 0.563ns)
  Clock Net Delay (Destination): 1.537ns (routing 0.900ns, distribution 0.637ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=5276, routed)        1.368     1.717    d_1_i/rst_dac0/U0/slowest_sync_clk
    SLICE_X78Y145        FDRE                                         r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_5/C
  -------------------------------------------------------------------    -------------------
    SLICE_X78Y145        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.038     1.755 r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_5/Q
                         net (fo=129, routed)         0.147     1.901    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/peripheral_aresetn[0]_repN_5_alias
    SLICE_X75Y145        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/trig_pop_r3_reg[1]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=5276, routed)        1.537     1.985    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
    SLICE_X75Y145        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/trig_pop_r3_reg[1]/C
                         clock pessimism             -0.225     1.760    
    SLICE_X75Y145        FDCE (Remov_AFF2_SLICEM_C_CLR)
                                                     -0.020     1.740    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/trig_pop_r3_reg[1]
  -------------------------------------------------------------------
                         required time                         -1.740    
                         arrival time                           1.901    
  -------------------------------------------------------------------
                         slack                                  0.161    





---------------------------------------------------------------------------------------------------
Path Group:  **async_default**
From Clock:  clk_out1_d_1_clk_adc0_x2_0
  To Clock:  clk_out1_d_1_clk_adc0_x2_0

Setup :            0  Failing Endpoints,  Worst Slack        0.526ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.351ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.526ns  (required time - arrival time)
  Source:                 d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/gcc_wr_ptr/count_bin_2r_reg[5]/CLR
                            (recovery check against rising-edge clock clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            3.906ns  (clk_out1_d_1_clk_adc0_x2_0 rise@3.906ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        3.221ns  (logic 0.079ns (2.453%)  route 3.142ns (97.547%))
  Logic Levels:           0  
  Clock Path Skew:        -0.034ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    6.325ns = ( 10.231 - 3.906 ) 
    Source Clock Delay      (SCD):    6.223ns
    Clock Pessimism Removal (CPR):    -0.136ns
  Clock Uncertainty:      0.059ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.095ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.985ns (routing 1.963ns, distribution 1.022ns)
  Clock Net Delay (Destination): 2.766ns (routing 1.778ns, distribution 0.988ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y18        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=1, routed)           2.565     3.092    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.965 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     3.210    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.238 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=1945, routed)        2.985     6.223    d_1_i/rst_adc0_x2/U0/slowest_sync_clk
    SLICE_X80Y109        FDRE                                         r  d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X80Y109        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     6.302 r  d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=932, routed)         3.142     9.444    d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/gcc_wr_ptr/count_bin_r_reg[0]_0
    SLICE_X53Y218        FDCE                                         f  d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/gcc_wr_ptr/count_bin_2r_reg[5]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      3.906     3.906 r  
    HSADC_X0Y0           HSADC                        0.000     3.906 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     4.028 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     4.178    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y18        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     4.292 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=1, routed)           2.303     6.595    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     7.225 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.216     7.441    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     7.465 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=1945, routed)        2.766    10.231    d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/gcc_wr_ptr/adc_clk
    SLICE_X53Y218        FDCE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/gcc_wr_ptr/count_bin_2r_reg[5]/C
                         clock pessimism             -0.136    10.095    
                         clock uncertainty           -0.059    10.036    
    SLICE_X53Y218        FDCE (Recov_DFF_SLICEM_C_CLR)
                                                     -0.066     9.970    d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/gcc_wr_ptr/count_bin_2r_reg[5]
  -------------------------------------------------------------------
                         required time                          9.970    
                         arrival time                          -9.444    
  -------------------------------------------------------------------
                         slack                                  0.526    

Slack (MET) :             0.526ns  (required time - arrival time)
  Source:                 d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/gcc_wr_ptr/count_bin_2r_reg[6]/CLR
                            (recovery check against rising-edge clock clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            3.906ns  (clk_out1_d_1_clk_adc0_x2_0 rise@3.906ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        3.221ns  (logic 0.079ns (2.453%)  route 3.142ns (97.547%))
  Logic Levels:           0  
  Clock Path Skew:        -0.034ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    6.325ns = ( 10.231 - 3.906 ) 
    Source Clock Delay      (SCD):    6.223ns
    Clock Pessimism Removal (CPR):    -0.136ns
  Clock Uncertainty:      0.059ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.095ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.985ns (routing 1.963ns, distribution 1.022ns)
  Clock Net Delay (Destination): 2.766ns (routing 1.778ns, distribution 0.988ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y18        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=1, routed)           2.565     3.092    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.965 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     3.210    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.238 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=1945, routed)        2.985     6.223    d_1_i/rst_adc0_x2/U0/slowest_sync_clk
    SLICE_X80Y109        FDRE                                         r  d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X80Y109        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     6.302 r  d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=932, routed)         3.142     9.444    d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/gcc_wr_ptr/count_bin_r_reg[0]_0
    SLICE_X53Y218        FDCE                                         f  d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/gcc_wr_ptr/count_bin_2r_reg[6]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      3.906     3.906 r  
    HSADC_X0Y0           HSADC                        0.000     3.906 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     4.028 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     4.178    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y18        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     4.292 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=1, routed)           2.303     6.595    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     7.225 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.216     7.441    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     7.465 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=1945, routed)        2.766    10.231    d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/gcc_wr_ptr/adc_clk
    SLICE_X53Y218        FDCE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/gcc_wr_ptr/count_bin_2r_reg[6]/C
                         clock pessimism             -0.136    10.095    
                         clock uncertainty           -0.059    10.036    
    SLICE_X53Y218        FDCE (Recov_DFF2_SLICEM_C_CLR)
                                                     -0.066     9.970    d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/gcc_wr_ptr/count_bin_2r_reg[6]
  -------------------------------------------------------------------
                         required time                          9.970    
                         arrival time                          -9.444    
  -------------------------------------------------------------------
                         slack                                  0.526    

Slack (MET) :             0.526ns  (required time - arrival time)
  Source:                 d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/gcc_wr_ptr/count_bin_r_reg[5]/CLR
                            (recovery check against rising-edge clock clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            3.906ns  (clk_out1_d_1_clk_adc0_x2_0 rise@3.906ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        3.221ns  (logic 0.079ns (2.453%)  route 3.142ns (97.547%))
  Logic Levels:           0  
  Clock Path Skew:        -0.034ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    6.325ns = ( 10.231 - 3.906 ) 
    Source Clock Delay      (SCD):    6.223ns
    Clock Pessimism Removal (CPR):    -0.136ns
  Clock Uncertainty:      0.059ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.095ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.985ns (routing 1.963ns, distribution 1.022ns)
  Clock Net Delay (Destination): 2.766ns (routing 1.778ns, distribution 0.988ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y18        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=1, routed)           2.565     3.092    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.965 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     3.210    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.238 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=1945, routed)        2.985     6.223    d_1_i/rst_adc0_x2/U0/slowest_sync_clk
    SLICE_X80Y109        FDRE                                         r  d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X80Y109        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     6.302 r  d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=932, routed)         3.142     9.444    d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/gcc_wr_ptr/count_bin_r_reg[0]_0
    SLICE_X53Y218        FDCE                                         f  d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/gcc_wr_ptr/count_bin_r_reg[5]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      3.906     3.906 r  
    HSADC_X0Y0           HSADC                        0.000     3.906 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     4.028 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     4.178    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y18        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     4.292 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=1, routed)           2.303     6.595    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     7.225 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.216     7.441    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     7.465 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=1945, routed)        2.766    10.231    d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/gcc_wr_ptr/adc_clk
    SLICE_X53Y218        FDCE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/gcc_wr_ptr/count_bin_r_reg[5]/C
                         clock pessimism             -0.136    10.095    
                         clock uncertainty           -0.059    10.036    
    SLICE_X53Y218        FDCE (Recov_CFF_SLICEM_C_CLR)
                                                     -0.066     9.970    d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/gcc_wr_ptr/count_bin_r_reg[5]
  -------------------------------------------------------------------
                         required time                          9.970    
                         arrival time                          -9.444    
  -------------------------------------------------------------------
                         slack                                  0.526    

Slack (MET) :             0.526ns  (required time - arrival time)
  Source:                 d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/gcc_wr_ptr/count_gray_r_reg[4]/CLR
                            (recovery check against rising-edge clock clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            3.906ns  (clk_out1_d_1_clk_adc0_x2_0 rise@3.906ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        3.221ns  (logic 0.079ns (2.453%)  route 3.142ns (97.547%))
  Logic Levels:           0  
  Clock Path Skew:        -0.034ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    6.325ns = ( 10.231 - 3.906 ) 
    Source Clock Delay      (SCD):    6.223ns
    Clock Pessimism Removal (CPR):    -0.136ns
  Clock Uncertainty:      0.059ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.095ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.985ns (routing 1.963ns, distribution 1.022ns)
  Clock Net Delay (Destination): 2.766ns (routing 1.778ns, distribution 0.988ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y18        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=1, routed)           2.565     3.092    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.965 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     3.210    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.238 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=1945, routed)        2.985     6.223    d_1_i/rst_adc0_x2/U0/slowest_sync_clk
    SLICE_X80Y109        FDRE                                         r  d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X80Y109        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     6.302 r  d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=932, routed)         3.142     9.444    d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/gcc_wr_ptr/count_bin_r_reg[0]_0
    SLICE_X53Y218        FDCE                                         f  d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/gcc_wr_ptr/count_gray_r_reg[4]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      3.906     3.906 r  
    HSADC_X0Y0           HSADC                        0.000     3.906 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     4.028 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     4.178    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y18        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     4.292 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=1, routed)           2.303     6.595    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     7.225 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.216     7.441    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     7.465 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=1945, routed)        2.766    10.231    d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/gcc_wr_ptr/adc_clk
    SLICE_X53Y218        FDCE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/gcc_wr_ptr/count_gray_r_reg[4]/C
                         clock pessimism             -0.136    10.095    
                         clock uncertainty           -0.059    10.036    
    SLICE_X53Y218        FDCE (Recov_CFF2_SLICEM_C_CLR)
                                                     -0.066     9.970    d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/gcc_wr_ptr/count_gray_r_reg[4]
  -------------------------------------------------------------------
                         required time                          9.970    
                         arrival time                          -9.444    
  -------------------------------------------------------------------
                         slack                                  0.526    

Slack (MET) :             0.576ns  (required time - arrival time)
  Source:                 d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/gcc_wr_ptr/count_bin_2r_reg[1]/CLR
                            (recovery check against rising-edge clock clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            3.906ns  (clk_out1_d_1_clk_adc0_x2_0 rise@3.906ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        3.168ns  (logic 0.079ns (2.494%)  route 3.089ns (97.506%))
  Logic Levels:           0  
  Clock Path Skew:        -0.037ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    6.322ns = ( 10.228 - 3.906 ) 
    Source Clock Delay      (SCD):    6.223ns
    Clock Pessimism Removal (CPR):    -0.136ns
  Clock Uncertainty:      0.059ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.095ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.985ns (routing 1.963ns, distribution 1.022ns)
  Clock Net Delay (Destination): 2.763ns (routing 1.778ns, distribution 0.985ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y18        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=1, routed)           2.565     3.092    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.965 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     3.210    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.238 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=1945, routed)        2.985     6.223    d_1_i/rst_adc0_x2/U0/slowest_sync_clk
    SLICE_X80Y109        FDRE                                         r  d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X80Y109        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     6.302 r  d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=932, routed)         3.089     9.391    d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/gcc_wr_ptr/count_bin_r_reg[0]_0
    SLICE_X53Y216        FDCE                                         f  d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/gcc_wr_ptr/count_bin_2r_reg[1]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      3.906     3.906 r  
    HSADC_X0Y0           HSADC                        0.000     3.906 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     4.028 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     4.178    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y18        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     4.292 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=1, routed)           2.303     6.595    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     7.225 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.216     7.441    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     7.465 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=1945, routed)        2.763    10.228    d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/gcc_wr_ptr/adc_clk
    SLICE_X53Y216        FDCE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/gcc_wr_ptr/count_bin_2r_reg[1]/C
                         clock pessimism             -0.136    10.092    
                         clock uncertainty           -0.059    10.033    
    SLICE_X53Y216        FDCE (Recov_DFF_SLICEM_C_CLR)
                                                     -0.066     9.967    d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/gcc_wr_ptr/count_bin_2r_reg[1]
  -------------------------------------------------------------------
                         required time                          9.967    
                         arrival time                          -9.391    
  -------------------------------------------------------------------
                         slack                                  0.576    

Slack (MET) :             0.576ns  (required time - arrival time)
  Source:                 d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/gcc_wr_ptr/count_bin_2r_reg[2]/CLR
                            (recovery check against rising-edge clock clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            3.906ns  (clk_out1_d_1_clk_adc0_x2_0 rise@3.906ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        3.168ns  (logic 0.079ns (2.494%)  route 3.089ns (97.506%))
  Logic Levels:           0  
  Clock Path Skew:        -0.037ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    6.322ns = ( 10.228 - 3.906 ) 
    Source Clock Delay      (SCD):    6.223ns
    Clock Pessimism Removal (CPR):    -0.136ns
  Clock Uncertainty:      0.059ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.095ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.985ns (routing 1.963ns, distribution 1.022ns)
  Clock Net Delay (Destination): 2.763ns (routing 1.778ns, distribution 0.985ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y18        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=1, routed)           2.565     3.092    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.965 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     3.210    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.238 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=1945, routed)        2.985     6.223    d_1_i/rst_adc0_x2/U0/slowest_sync_clk
    SLICE_X80Y109        FDRE                                         r  d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X80Y109        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     6.302 r  d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=932, routed)         3.089     9.391    d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/gcc_wr_ptr/count_bin_r_reg[0]_0
    SLICE_X53Y216        FDCE                                         f  d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/gcc_wr_ptr/count_bin_2r_reg[2]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      3.906     3.906 r  
    HSADC_X0Y0           HSADC                        0.000     3.906 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     4.028 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     4.178    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y18        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     4.292 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=1, routed)           2.303     6.595    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     7.225 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.216     7.441    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     7.465 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=1945, routed)        2.763    10.228    d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/gcc_wr_ptr/adc_clk
    SLICE_X53Y216        FDCE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/gcc_wr_ptr/count_bin_2r_reg[2]/C
                         clock pessimism             -0.136    10.092    
                         clock uncertainty           -0.059    10.033    
    SLICE_X53Y216        FDCE (Recov_DFF2_SLICEM_C_CLR)
                                                     -0.066     9.967    d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/gcc_wr_ptr/count_bin_2r_reg[2]
  -------------------------------------------------------------------
                         required time                          9.967    
                         arrival time                          -9.391    
  -------------------------------------------------------------------
                         slack                                  0.576    

Slack (MET) :             0.604ns  (required time - arrival time)
  Source:                 d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/gcc_wr_ptr/count_gray_2r_reg[3]/CLR
                            (recovery check against rising-edge clock clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            3.906ns  (clk_out1_d_1_clk_adc0_x2_0 rise@3.906ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        3.140ns  (logic 0.079ns (2.516%)  route 3.061ns (97.484%))
  Logic Levels:           0  
  Clock Path Skew:        -0.036ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    6.323ns = ( 10.229 - 3.906 ) 
    Source Clock Delay      (SCD):    6.223ns
    Clock Pessimism Removal (CPR):    -0.136ns
  Clock Uncertainty:      0.059ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.095ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.985ns (routing 1.963ns, distribution 1.022ns)
  Clock Net Delay (Destination): 2.764ns (routing 1.778ns, distribution 0.986ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y18        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=1, routed)           2.565     3.092    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.965 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     3.210    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.238 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=1945, routed)        2.985     6.223    d_1_i/rst_adc0_x2/U0/slowest_sync_clk
    SLICE_X80Y109        FDRE                                         r  d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X80Y109        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     6.302 r  d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=932, routed)         3.061     9.363    d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/gcc_wr_ptr/count_bin_r_reg[0]_0
    SLICE_X54Y218        FDCE                                         f  d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/gcc_wr_ptr/count_gray_2r_reg[3]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      3.906     3.906 r  
    HSADC_X0Y0           HSADC                        0.000     3.906 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     4.028 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     4.178    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y18        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     4.292 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=1, routed)           2.303     6.595    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     7.225 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.216     7.441    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     7.465 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=1945, routed)        2.764    10.229    d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/gcc_wr_ptr/adc_clk
    SLICE_X54Y218        FDCE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/gcc_wr_ptr/count_gray_2r_reg[3]/C
                         clock pessimism             -0.136    10.093    
                         clock uncertainty           -0.059    10.033    
    SLICE_X54Y218        FDCE (Recov_DFF_SLICEM_C_CLR)
                                                     -0.066     9.967    d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/gcc_wr_ptr/count_gray_2r_reg[3]
  -------------------------------------------------------------------
                         required time                          9.967    
                         arrival time                          -9.363    
  -------------------------------------------------------------------
                         slack                                  0.604    

Slack (MET) :             0.604ns  (required time - arrival time)
  Source:                 d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/gcc_wr_ptr/count_gray_2r_reg[4]/CLR
                            (recovery check against rising-edge clock clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            3.906ns  (clk_out1_d_1_clk_adc0_x2_0 rise@3.906ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        3.140ns  (logic 0.079ns (2.516%)  route 3.061ns (97.484%))
  Logic Levels:           0  
  Clock Path Skew:        -0.036ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    6.323ns = ( 10.229 - 3.906 ) 
    Source Clock Delay      (SCD):    6.223ns
    Clock Pessimism Removal (CPR):    -0.136ns
  Clock Uncertainty:      0.059ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.095ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.985ns (routing 1.963ns, distribution 1.022ns)
  Clock Net Delay (Destination): 2.764ns (routing 1.778ns, distribution 0.986ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y18        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=1, routed)           2.565     3.092    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.965 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     3.210    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.238 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=1945, routed)        2.985     6.223    d_1_i/rst_adc0_x2/U0/slowest_sync_clk
    SLICE_X80Y109        FDRE                                         r  d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X80Y109        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     6.302 r  d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=932, routed)         3.061     9.363    d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/gcc_wr_ptr/count_bin_r_reg[0]_0
    SLICE_X54Y218        FDCE                                         f  d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/gcc_wr_ptr/count_gray_2r_reg[4]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      3.906     3.906 r  
    HSADC_X0Y0           HSADC                        0.000     3.906 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     4.028 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     4.178    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y18        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     4.292 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=1, routed)           2.303     6.595    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     7.225 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.216     7.441    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     7.465 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=1945, routed)        2.764    10.229    d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/gcc_wr_ptr/adc_clk
    SLICE_X54Y218        FDCE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/gcc_wr_ptr/count_gray_2r_reg[4]/C
                         clock pessimism             -0.136    10.093    
                         clock uncertainty           -0.059    10.033    
    SLICE_X54Y218        FDCE (Recov_DFF2_SLICEM_C_CLR)
                                                     -0.066     9.967    d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/gcc_wr_ptr/count_gray_2r_reg[4]
  -------------------------------------------------------------------
                         required time                          9.967    
                         arrival time                          -9.363    
  -------------------------------------------------------------------
                         slack                                  0.604    

Slack (MET) :             0.604ns  (required time - arrival time)
  Source:                 d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/gcc_wr_ptr/count_gray_2r_reg[5]/CLR
                            (recovery check against rising-edge clock clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            3.906ns  (clk_out1_d_1_clk_adc0_x2_0 rise@3.906ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        3.140ns  (logic 0.079ns (2.516%)  route 3.061ns (97.484%))
  Logic Levels:           0  
  Clock Path Skew:        -0.036ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    6.323ns = ( 10.229 - 3.906 ) 
    Source Clock Delay      (SCD):    6.223ns
    Clock Pessimism Removal (CPR):    -0.136ns
  Clock Uncertainty:      0.059ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.095ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.985ns (routing 1.963ns, distribution 1.022ns)
  Clock Net Delay (Destination): 2.764ns (routing 1.778ns, distribution 0.986ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y18        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=1, routed)           2.565     3.092    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.965 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     3.210    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.238 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=1945, routed)        2.985     6.223    d_1_i/rst_adc0_x2/U0/slowest_sync_clk
    SLICE_X80Y109        FDRE                                         r  d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X80Y109        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     6.302 r  d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=932, routed)         3.061     9.363    d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/gcc_wr_ptr/count_bin_r_reg[0]_0
    SLICE_X54Y218        FDCE                                         f  d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/gcc_wr_ptr/count_gray_2r_reg[5]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      3.906     3.906 r  
    HSADC_X0Y0           HSADC                        0.000     3.906 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     4.028 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     4.178    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y18        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     4.292 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=1, routed)           2.303     6.595    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     7.225 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.216     7.441    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     7.465 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=1945, routed)        2.764    10.229    d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/gcc_wr_ptr/adc_clk
    SLICE_X54Y218        FDCE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/gcc_wr_ptr/count_gray_2r_reg[5]/C
                         clock pessimism             -0.136    10.093    
                         clock uncertainty           -0.059    10.033    
    SLICE_X54Y218        FDCE (Recov_CFF_SLICEM_C_CLR)
                                                     -0.066     9.967    d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/gcc_wr_ptr/count_gray_2r_reg[5]
  -------------------------------------------------------------------
                         required time                          9.967    
                         arrival time                          -9.363    
  -------------------------------------------------------------------
                         slack                                  0.604    

Slack (MET) :             0.604ns  (required time - arrival time)
  Source:                 d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/gcc_wr_ptr/count_gray_r_reg[5]/CLR
                            (recovery check against rising-edge clock clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            3.906ns  (clk_out1_d_1_clk_adc0_x2_0 rise@3.906ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        3.140ns  (logic 0.079ns (2.516%)  route 3.061ns (97.484%))
  Logic Levels:           0  
  Clock Path Skew:        -0.036ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    6.323ns = ( 10.229 - 3.906 ) 
    Source Clock Delay      (SCD):    6.223ns
    Clock Pessimism Removal (CPR):    -0.136ns
  Clock Uncertainty:      0.059ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.095ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.985ns (routing 1.963ns, distribution 1.022ns)
  Clock Net Delay (Destination): 2.764ns (routing 1.778ns, distribution 0.986ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y18        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=1, routed)           2.565     3.092    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.965 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     3.210    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.238 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=1945, routed)        2.985     6.223    d_1_i/rst_adc0_x2/U0/slowest_sync_clk
    SLICE_X80Y109        FDRE                                         r  d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X80Y109        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     6.302 r  d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=932, routed)         3.061     9.363    d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/gcc_wr_ptr/count_bin_r_reg[0]_0
    SLICE_X54Y218        FDCE                                         f  d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/gcc_wr_ptr/count_gray_r_reg[5]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      3.906     3.906 r  
    HSADC_X0Y0           HSADC                        0.000     3.906 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     4.028 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     4.178    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y18        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     4.292 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=1, routed)           2.303     6.595    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     7.225 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.216     7.441    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     7.465 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=1945, routed)        2.764    10.229    d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/gcc_wr_ptr/adc_clk
    SLICE_X54Y218        FDCE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/gcc_wr_ptr/count_gray_r_reg[5]/C
                         clock pessimism             -0.136    10.093    
                         clock uncertainty           -0.059    10.033    
    SLICE_X54Y218        FDCE (Recov_CFF2_SLICEM_C_CLR)
                                                     -0.066     9.967    d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/gcc_wr_ptr/count_gray_r_reg[5]
  -------------------------------------------------------------------
                         required time                          9.967    
                         arrival time                          -9.363    
  -------------------------------------------------------------------
                         slack                                  0.604    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.351ns  (arrival time - required time)
  Source:                 d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/qick_time_tagger_0/inst/QTT/SMP.SMP_MEM/FSM_onehot_smp_wr_st_reg[0]/PRE
                            (removal check against rising-edge clock clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        0.348ns  (logic 0.039ns (11.203%)  route 0.309ns (88.797%))
  Logic Levels:           0  
  Clock Path Skew:        0.017ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.637ns
    Source Clock Delay      (SCD):    3.700ns
    Clock Pessimism Removal (CPR):    -0.080ns
  Clock Net Delay (Source):      1.639ns (routing 1.074ns, distribution 0.565ns)
  Clock Net Delay (Destination): 1.820ns (routing 1.208ns, distribution 0.612ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y18        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=1, routed)           1.405     1.668    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.898 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     2.044    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.061 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=1945, routed)        1.639     3.700    d_1_i/rst_adc0_x2/U0/slowest_sync_clk
    SLICE_X80Y109        FDRE                                         r  d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X80Y109        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.039     3.739 r  d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=932, routed)         0.309     4.048    d_1_i/qick_time_tagger_0/inst/QTT/SMP.SMP_MEM/adc_aresetn_0
    SLICE_X69Y93         FDPE                                         f  d_1_i/qick_time_tagger_0/inst/QTT/SMP.SMP_MEM/FSM_onehot_smp_wr_st_reg[0]/PRE  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y18        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=1, routed)           1.575     1.927    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.632 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.798    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.817 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=1945, routed)        1.820     3.637    d_1_i/qick_time_tagger_0/inst/QTT/SMP.SMP_MEM/adc_clk
    SLICE_X69Y93         FDPE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/SMP.SMP_MEM/FSM_onehot_smp_wr_st_reg[0]/C
                         clock pessimism              0.080     3.717    
    SLICE_X69Y93         FDPE (Remov_EFF_SLICEM_C_PRE)
                                                     -0.020     3.697    d_1_i/qick_time_tagger_0/inst/QTT/SMP.SMP_MEM/FSM_onehot_smp_wr_st_reg[0]
  -------------------------------------------------------------------
                         required time                         -3.697    
                         arrival time                           4.048    
  -------------------------------------------------------------------
                         slack                                  0.351    

Slack (MET) :             0.351ns  (arrival time - required time)
  Source:                 d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/qick_time_tagger_0/inst/QTT/SMP.SMP_MEM/FSM_onehot_smp_wr_st_reg[1]/CLR
                            (removal check against rising-edge clock clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        0.348ns  (logic 0.039ns (11.203%)  route 0.309ns (88.797%))
  Logic Levels:           0  
  Clock Path Skew:        0.017ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.637ns
    Source Clock Delay      (SCD):    3.700ns
    Clock Pessimism Removal (CPR):    -0.080ns
  Clock Net Delay (Source):      1.639ns (routing 1.074ns, distribution 0.565ns)
  Clock Net Delay (Destination): 1.820ns (routing 1.208ns, distribution 0.612ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y18        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=1, routed)           1.405     1.668    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.898 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     2.044    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.061 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=1945, routed)        1.639     3.700    d_1_i/rst_adc0_x2/U0/slowest_sync_clk
    SLICE_X80Y109        FDRE                                         r  d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X80Y109        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.039     3.739 r  d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=932, routed)         0.309     4.048    d_1_i/qick_time_tagger_0/inst/QTT/SMP.SMP_MEM/adc_aresetn_0
    SLICE_X69Y93         FDCE                                         f  d_1_i/qick_time_tagger_0/inst/QTT/SMP.SMP_MEM/FSM_onehot_smp_wr_st_reg[1]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y18        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=1, routed)           1.575     1.927    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.632 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.798    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.817 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=1945, routed)        1.820     3.637    d_1_i/qick_time_tagger_0/inst/QTT/SMP.SMP_MEM/adc_clk
    SLICE_X69Y93         FDCE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/SMP.SMP_MEM/FSM_onehot_smp_wr_st_reg[1]/C
                         clock pessimism              0.080     3.717    
    SLICE_X69Y93         FDCE (Remov_EFF2_SLICEM_C_CLR)
                                                     -0.020     3.697    d_1_i/qick_time_tagger_0/inst/QTT/SMP.SMP_MEM/FSM_onehot_smp_wr_st_reg[1]
  -------------------------------------------------------------------
                         required time                         -3.697    
                         arrival time                           4.048    
  -------------------------------------------------------------------
                         slack                                  0.351    

Slack (MET) :             0.415ns  (arrival time - required time)
  Source:                 d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/qick_time_tagger_0/inst/QTT/FSM_onehot_time_trig_st_reg[0]/PRE
                            (removal check against rising-edge clock clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        0.416ns  (logic 0.039ns (9.378%)  route 0.377ns (90.622%))
  Logic Levels:           0  
  Clock Path Skew:        0.020ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.640ns
    Source Clock Delay      (SCD):    3.700ns
    Clock Pessimism Removal (CPR):    -0.080ns
  Clock Net Delay (Source):      1.639ns (routing 1.074ns, distribution 0.565ns)
  Clock Net Delay (Destination): 1.823ns (routing 1.208ns, distribution 0.615ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y18        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=1, routed)           1.405     1.668    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.898 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     2.044    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.061 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=1945, routed)        1.639     3.700    d_1_i/rst_adc0_x2/U0/slowest_sync_clk
    SLICE_X80Y109        FDRE                                         r  d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X80Y109        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.039     3.739 r  d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=932, routed)         0.377     4.115    d_1_i/qick_time_tagger_0/inst/QTT/SMP.SMP_MEM_n_0
    SLICE_X71Y99         FDPE                                         f  d_1_i/qick_time_tagger_0/inst/QTT/FSM_onehot_time_trig_st_reg[0]/PRE  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y18        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=1, routed)           1.575     1.927    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.632 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.798    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.817 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=1945, routed)        1.823     3.640    d_1_i/qick_time_tagger_0/inst/QTT/adc_clk
    SLICE_X71Y99         FDPE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/FSM_onehot_time_trig_st_reg[0]/C
                         clock pessimism              0.080     3.720    
    SLICE_X71Y99         FDPE (Remov_CFF2_SLICEL_C_PRE)
                                                     -0.020     3.700    d_1_i/qick_time_tagger_0/inst/QTT/FSM_onehot_time_trig_st_reg[0]
  -------------------------------------------------------------------
                         required time                         -3.700    
                         arrival time                           4.115    
  -------------------------------------------------------------------
                         slack                                  0.415    

Slack (MET) :             0.415ns  (arrival time - required time)
  Source:                 d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/qick_time_tagger_0/inst/QTT/FSM_onehot_time_trig_st_reg[1]/CLR
                            (removal check against rising-edge clock clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        0.416ns  (logic 0.039ns (9.378%)  route 0.377ns (90.622%))
  Logic Levels:           0  
  Clock Path Skew:        0.020ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.640ns
    Source Clock Delay      (SCD):    3.700ns
    Clock Pessimism Removal (CPR):    -0.080ns
  Clock Net Delay (Source):      1.639ns (routing 1.074ns, distribution 0.565ns)
  Clock Net Delay (Destination): 1.823ns (routing 1.208ns, distribution 0.615ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y18        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=1, routed)           1.405     1.668    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.898 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     2.044    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.061 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=1945, routed)        1.639     3.700    d_1_i/rst_adc0_x2/U0/slowest_sync_clk
    SLICE_X80Y109        FDRE                                         r  d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X80Y109        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.039     3.739 r  d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=932, routed)         0.377     4.115    d_1_i/qick_time_tagger_0/inst/QTT/SMP.SMP_MEM_n_0
    SLICE_X71Y99         FDCE                                         f  d_1_i/qick_time_tagger_0/inst/QTT/FSM_onehot_time_trig_st_reg[1]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y18        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=1, routed)           1.575     1.927    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.632 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.798    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.817 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=1945, routed)        1.823     3.640    d_1_i/qick_time_tagger_0/inst/QTT/adc_clk
    SLICE_X71Y99         FDCE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/FSM_onehot_time_trig_st_reg[1]/C
                         clock pessimism              0.080     3.720    
    SLICE_X71Y99         FDCE (Remov_DFF_SLICEL_C_CLR)
                                                     -0.020     3.700    d_1_i/qick_time_tagger_0/inst/QTT/FSM_onehot_time_trig_st_reg[1]
  -------------------------------------------------------------------
                         required time                         -3.700    
                         arrival time                           4.115    
  -------------------------------------------------------------------
                         slack                                  0.415    

Slack (MET) :             0.415ns  (arrival time - required time)
  Source:                 d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/qick_time_tagger_0/inst/QTT/FSM_onehot_time_trig_st_reg[2]/CLR
                            (removal check against rising-edge clock clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        0.416ns  (logic 0.039ns (9.378%)  route 0.377ns (90.622%))
  Logic Levels:           0  
  Clock Path Skew:        0.020ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.640ns
    Source Clock Delay      (SCD):    3.700ns
    Clock Pessimism Removal (CPR):    -0.080ns
  Clock Net Delay (Source):      1.639ns (routing 1.074ns, distribution 0.565ns)
  Clock Net Delay (Destination): 1.823ns (routing 1.208ns, distribution 0.615ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y18        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=1, routed)           1.405     1.668    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.898 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     2.044    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.061 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=1945, routed)        1.639     3.700    d_1_i/rst_adc0_x2/U0/slowest_sync_clk
    SLICE_X80Y109        FDRE                                         r  d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X80Y109        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.039     3.739 r  d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=932, routed)         0.377     4.115    d_1_i/qick_time_tagger_0/inst/QTT/SMP.SMP_MEM_n_0
    SLICE_X71Y99         FDCE                                         f  d_1_i/qick_time_tagger_0/inst/QTT/FSM_onehot_time_trig_st_reg[2]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y18        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=1, routed)           1.575     1.927    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.632 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.798    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.817 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=1945, routed)        1.823     3.640    d_1_i/qick_time_tagger_0/inst/QTT/adc_clk
    SLICE_X71Y99         FDCE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/FSM_onehot_time_trig_st_reg[2]/C
                         clock pessimism              0.080     3.720    
    SLICE_X71Y99         FDCE (Remov_DFF2_SLICEL_C_CLR)
                                                     -0.020     3.700    d_1_i/qick_time_tagger_0/inst/QTT/FSM_onehot_time_trig_st_reg[2]
  -------------------------------------------------------------------
                         required time                         -3.700    
                         arrival time                           4.115    
  -------------------------------------------------------------------
                         slack                                  0.415    

Slack (MET) :             0.415ns  (arrival time - required time)
  Source:                 d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/qick_time_tagger_0/inst/QTT/time_trig_st_reg[0]/PRE
                            (removal check against rising-edge clock clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        0.416ns  (logic 0.039ns (9.378%)  route 0.377ns (90.622%))
  Logic Levels:           0  
  Clock Path Skew:        0.020ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.640ns
    Source Clock Delay      (SCD):    3.700ns
    Clock Pessimism Removal (CPR):    -0.080ns
  Clock Net Delay (Source):      1.639ns (routing 1.074ns, distribution 0.565ns)
  Clock Net Delay (Destination): 1.823ns (routing 1.208ns, distribution 0.615ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y18        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=1, routed)           1.405     1.668    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.898 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     2.044    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.061 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=1945, routed)        1.639     3.700    d_1_i/rst_adc0_x2/U0/slowest_sync_clk
    SLICE_X80Y109        FDRE                                         r  d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X80Y109        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.039     3.739 r  d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=932, routed)         0.377     4.115    d_1_i/qick_time_tagger_0/inst/QTT/SMP.SMP_MEM_n_0
    SLICE_X71Y99         FDPE                                         f  d_1_i/qick_time_tagger_0/inst/QTT/time_trig_st_reg[0]/PRE  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y18        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=1, routed)           1.575     1.927    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.632 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.798    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.817 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=1945, routed)        1.823     3.640    d_1_i/qick_time_tagger_0/inst/QTT/adc_clk
    SLICE_X71Y99         FDPE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/time_trig_st_reg[0]/C
                         clock pessimism              0.080     3.720    
    SLICE_X71Y99         FDPE (Remov_BFF2_SLICEL_C_PRE)
                                                     -0.020     3.700    d_1_i/qick_time_tagger_0/inst/QTT/time_trig_st_reg[0]
  -------------------------------------------------------------------
                         required time                         -3.700    
                         arrival time                           4.115    
  -------------------------------------------------------------------
                         slack                                  0.415    

Slack (MET) :             0.415ns  (arrival time - required time)
  Source:                 d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/qick_time_tagger_0/inst/QTT/time_trig_st_reg[1]/CLR
                            (removal check against rising-edge clock clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        0.416ns  (logic 0.039ns (9.378%)  route 0.377ns (90.622%))
  Logic Levels:           0  
  Clock Path Skew:        0.020ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.640ns
    Source Clock Delay      (SCD):    3.700ns
    Clock Pessimism Removal (CPR):    -0.080ns
  Clock Net Delay (Source):      1.639ns (routing 1.074ns, distribution 0.565ns)
  Clock Net Delay (Destination): 1.823ns (routing 1.208ns, distribution 0.615ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y18        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=1, routed)           1.405     1.668    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.898 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     2.044    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.061 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=1945, routed)        1.639     3.700    d_1_i/rst_adc0_x2/U0/slowest_sync_clk
    SLICE_X80Y109        FDRE                                         r  d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X80Y109        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.039     3.739 r  d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=932, routed)         0.377     4.115    d_1_i/qick_time_tagger_0/inst/QTT/SMP.SMP_MEM_n_0
    SLICE_X71Y99         FDCE                                         f  d_1_i/qick_time_tagger_0/inst/QTT/time_trig_st_reg[1]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y18        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=1, routed)           1.575     1.927    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.632 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.798    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.817 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=1945, routed)        1.823     3.640    d_1_i/qick_time_tagger_0/inst/QTT/adc_clk
    SLICE_X71Y99         FDCE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/time_trig_st_reg[1]/C
                         clock pessimism              0.080     3.720    
    SLICE_X71Y99         FDCE (Remov_AFF2_SLICEL_C_CLR)
                                                     -0.020     3.700    d_1_i/qick_time_tagger_0/inst/QTT/time_trig_st_reg[1]
  -------------------------------------------------------------------
                         required time                         -3.700    
                         arrival time                           4.115    
  -------------------------------------------------------------------
                         slack                                  0.415    

Slack (MET) :             0.524ns  (arrival time - required time)
  Source:                 d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/TAG[1].MEM/FIFO_PUSH/gcc_wr_ptr/count_bin_r_reg[0]/PRE
                            (removal check against rising-edge clock clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        0.586ns  (logic 0.039ns (6.655%)  route 0.547ns (93.345%))
  Logic Levels:           0  
  Clock Path Skew:        0.082ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.671ns
    Source Clock Delay      (SCD):    3.700ns
    Clock Pessimism Removal (CPR):    -0.110ns
  Clock Net Delay (Source):      1.639ns (routing 1.074ns, distribution 0.565ns)
  Clock Net Delay (Destination): 1.854ns (routing 1.208ns, distribution 0.646ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y18        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=1, routed)           1.405     1.668    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.898 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     2.044    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.061 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=1945, routed)        1.639     3.700    d_1_i/rst_adc0_x2/U0/slowest_sync_clk
    SLICE_X80Y109        FDRE                                         r  d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X80Y109        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.039     3.739 r  d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=932, routed)         0.547     4.286    d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/TAG[1].MEM/FIFO_PUSH/gcc_wr_ptr/count_bin_r_reg[0]_0
    SLICE_X71Y155        FDPE                                         f  d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/TAG[1].MEM/FIFO_PUSH/gcc_wr_ptr/count_bin_r_reg[0]/PRE  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y18        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=1, routed)           1.575     1.927    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.632 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.798    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.817 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=1945, routed)        1.854     3.671    d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/TAG[1].MEM/FIFO_PUSH/gcc_wr_ptr/adc_clk
    SLICE_X71Y155        FDPE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/TAG[1].MEM/FIFO_PUSH/gcc_wr_ptr/count_bin_r_reg[0]/C
                         clock pessimism              0.110     3.781    
    SLICE_X71Y155        FDPE (Remov_DFF_SLICEL_C_PRE)
                                                     -0.020     3.761    d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/TAG[1].MEM/FIFO_PUSH/gcc_wr_ptr/count_bin_r_reg[0]
  -------------------------------------------------------------------
                         required time                         -3.761    
                         arrival time                           4.286    
  -------------------------------------------------------------------
                         slack                                  0.524    

Slack (MET) :             0.524ns  (arrival time - required time)
  Source:                 d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/TAG[1].MEM/FIFO_PUSH/gcc_wr_ptr/count_gray_r_reg[0]/PRE
                            (removal check against rising-edge clock clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        0.586ns  (logic 0.039ns (6.655%)  route 0.547ns (93.345%))
  Logic Levels:           0  
  Clock Path Skew:        0.082ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.671ns
    Source Clock Delay      (SCD):    3.700ns
    Clock Pessimism Removal (CPR):    -0.110ns
  Clock Net Delay (Source):      1.639ns (routing 1.074ns, distribution 0.565ns)
  Clock Net Delay (Destination): 1.854ns (routing 1.208ns, distribution 0.646ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y18        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=1, routed)           1.405     1.668    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.898 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     2.044    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.061 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=1945, routed)        1.639     3.700    d_1_i/rst_adc0_x2/U0/slowest_sync_clk
    SLICE_X80Y109        FDRE                                         r  d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X80Y109        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.039     3.739 r  d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=932, routed)         0.547     4.286    d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/TAG[1].MEM/FIFO_PUSH/gcc_wr_ptr/count_bin_r_reg[0]_0
    SLICE_X71Y155        FDPE                                         f  d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/TAG[1].MEM/FIFO_PUSH/gcc_wr_ptr/count_gray_r_reg[0]/PRE  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y18        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=1, routed)           1.575     1.927    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.632 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.798    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.817 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=1945, routed)        1.854     3.671    d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/TAG[1].MEM/FIFO_PUSH/gcc_wr_ptr/adc_clk
    SLICE_X71Y155        FDPE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/TAG[1].MEM/FIFO_PUSH/gcc_wr_ptr/count_gray_r_reg[0]/C
                         clock pessimism              0.110     3.781    
    SLICE_X71Y155        FDPE (Remov_DFF2_SLICEL_C_PRE)
                                                     -0.020     3.761    d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/TAG[1].MEM/FIFO_PUSH/gcc_wr_ptr/count_gray_r_reg[0]
  -------------------------------------------------------------------
                         required time                         -3.761    
                         arrival time                           4.286    
  -------------------------------------------------------------------
                         slack                                  0.524    

Slack (MET) :             0.527ns  (arrival time - required time)
  Source:                 d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/TAG[1].MEM/FIFO_PUSH/gcc_wr_ptr/count_bin_r_reg[2]/CLR
                            (removal check against rising-edge clock clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        0.599ns  (logic 0.039ns (6.509%)  route 0.560ns (93.491%))
  Logic Levels:           0  
  Clock Path Skew:        0.092ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.682ns
    Source Clock Delay      (SCD):    3.700ns
    Clock Pessimism Removal (CPR):    -0.110ns
  Clock Net Delay (Source):      1.639ns (routing 1.074ns, distribution 0.565ns)
  Clock Net Delay (Destination): 1.865ns (routing 1.208ns, distribution 0.657ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y18        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=1, routed)           1.405     1.668    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.898 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     2.044    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.061 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=1945, routed)        1.639     3.700    d_1_i/rst_adc0_x2/U0/slowest_sync_clk
    SLICE_X80Y109        FDRE                                         r  d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X80Y109        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.039     3.739 r  d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=932, routed)         0.560     4.299    d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/TAG[1].MEM/FIFO_PUSH/gcc_wr_ptr/count_bin_r_reg[0]_0
    SLICE_X73Y155        FDCE                                         f  d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/TAG[1].MEM/FIFO_PUSH/gcc_wr_ptr/count_bin_r_reg[2]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y18        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=1, routed)           1.575     1.927    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.632 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.798    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.817 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=1945, routed)        1.865     3.682    d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/TAG[1].MEM/FIFO_PUSH/gcc_wr_ptr/adc_clk
    SLICE_X73Y155        FDCE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/TAG[1].MEM/FIFO_PUSH/gcc_wr_ptr/count_bin_r_reg[2]/C
                         clock pessimism              0.110     3.792    
    SLICE_X73Y155        FDCE (Remov_HFF_SLICEL_C_CLR)
                                                     -0.020     3.772    d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/TAG[1].MEM/FIFO_PUSH/gcc_wr_ptr/count_bin_r_reg[2]
  -------------------------------------------------------------------
                         required time                         -3.772    
                         arrival time                           4.299    
  -------------------------------------------------------------------
                         slack                                  0.527    





---------------------------------------------------------------------------------------------------
Path Group:  **async_default**
From Clock:  clk_pl_0
  To Clock:  clk_pl_0

Setup :            0  Failing Endpoints,  Worst Slack        6.916ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.156ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             6.916ns  (required time - arrival time)
  Source:                 d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/wr_ptr_reg[11]_rep__2/CLR
                            (recovery check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk_pl_0 rise@10.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        2.555ns  (logic 0.106ns (4.149%)  route 2.449ns (95.851%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        -0.333ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.150ns = ( 12.150 - 10.000 ) 
    Source Clock Delay      (SCD):    2.600ns
    Clock Pessimism Removal (CPR):    0.117ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.374ns (routing 0.763ns, distribution 1.611ns)
  Clock Net Delay (Destination): 1.968ns (routing 0.690ns, distribution 1.278ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       2.374     2.600    d_1_i/rst_100/U0/slowest_sync_clk
    SLICE_X83Y83         FDRE                                         r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X83Y83         FDRE (Prop_BFF_SLICEM_C_Q)
                                                      0.078     2.678 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           0.699     3.377    d_1_i/rst_100/U0/peripheral_aresetn[0]_bufg_place
    BUFGCE_X0Y44         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.405 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_bufg_place/O
                         net (fo=7045, routed)        1.750     5.155    d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/count_gray_r_reg[7]
    SLICE_X42Y345        FDCE                                         f  d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/wr_ptr_reg[11]_rep__2/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                     10.000    10.000 r  
    PS8_X0Y0             PS8                          0.000    10.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157    10.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025    10.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       1.968    12.150    d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/ps_clk
    SLICE_X42Y345        FDCE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/wr_ptr_reg[11]_rep__2/C
                         clock pessimism              0.117    12.267    
                         clock uncertainty           -0.130    12.137    
    SLICE_X42Y345        FDCE (Recov_EFF_SLICEM_C_CLR)
                                                     -0.066    12.071    d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/wr_ptr_reg[11]_rep__2
  -------------------------------------------------------------------
                         required time                         12.071    
                         arrival time                          -5.155    
  -------------------------------------------------------------------
                         slack                                  6.916    

Slack (MET) :             6.922ns  (required time - arrival time)
  Source:                 d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/rd_proc_ptr_reg[0]/CLR
                            (recovery check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk_pl_0 rise@10.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        2.617ns  (logic 0.106ns (4.050%)  route 2.511ns (95.950%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        -0.265ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.218ns = ( 12.218 - 10.000 ) 
    Source Clock Delay      (SCD):    2.600ns
    Clock Pessimism Removal (CPR):    0.117ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.374ns (routing 0.763ns, distribution 1.611ns)
  Clock Net Delay (Destination): 2.036ns (routing 0.690ns, distribution 1.346ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       2.374     2.600    d_1_i/rst_100/U0/slowest_sync_clk
    SLICE_X83Y83         FDRE                                         r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X83Y83         FDRE (Prop_BFF_SLICEM_C_Q)
                                                      0.078     2.678 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           0.699     3.377    d_1_i/rst_100/U0/peripheral_aresetn[0]_bufg_place
    BUFGCE_X0Y44         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.405 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_bufg_place/O
                         net (fo=7045, routed)        1.812     5.217    d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/count_gray_r_reg[7]
    SLICE_X34Y315        FDCE                                         f  d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/rd_proc_ptr_reg[0]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                     10.000    10.000 r  
    PS8_X0Y0             PS8                          0.000    10.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157    10.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025    10.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       2.036    12.218    d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/ps_clk
    SLICE_X34Y315        FDCE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/rd_proc_ptr_reg[0]/C
                         clock pessimism              0.117    12.335    
                         clock uncertainty           -0.130    12.205    
    SLICE_X34Y315        FDCE (Recov_AFF_SLICEM_C_CLR)
                                                     -0.066    12.139    d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/rd_proc_ptr_reg[0]
  -------------------------------------------------------------------
                         required time                         12.139    
                         arrival time                          -5.217    
  -------------------------------------------------------------------
                         slack                                  6.922    

Slack (MET) :             6.922ns  (required time - arrival time)
  Source:                 d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/rd_proc_ptr_reg[10]/CLR
                            (recovery check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk_pl_0 rise@10.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        2.616ns  (logic 0.106ns (4.052%)  route 2.510ns (95.948%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        -0.266ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.217ns = ( 12.217 - 10.000 ) 
    Source Clock Delay      (SCD):    2.600ns
    Clock Pessimism Removal (CPR):    0.117ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.374ns (routing 0.763ns, distribution 1.611ns)
  Clock Net Delay (Destination): 2.035ns (routing 0.690ns, distribution 1.345ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       2.374     2.600    d_1_i/rst_100/U0/slowest_sync_clk
    SLICE_X83Y83         FDRE                                         r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X83Y83         FDRE (Prop_BFF_SLICEM_C_Q)
                                                      0.078     2.678 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           0.699     3.377    d_1_i/rst_100/U0/peripheral_aresetn[0]_bufg_place
    BUFGCE_X0Y44         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.405 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_bufg_place/O
                         net (fo=7045, routed)        1.811     5.216    d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/count_gray_r_reg[7]
    SLICE_X34Y316        FDCE                                         f  d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/rd_proc_ptr_reg[10]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                     10.000    10.000 r  
    PS8_X0Y0             PS8                          0.000    10.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157    10.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025    10.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       2.035    12.217    d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/ps_clk
    SLICE_X34Y316        FDCE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/rd_proc_ptr_reg[10]/C
                         clock pessimism              0.117    12.334    
                         clock uncertainty           -0.130    12.204    
    SLICE_X34Y316        FDCE (Recov_CFF_SLICEM_C_CLR)
                                                     -0.066    12.138    d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/rd_proc_ptr_reg[10]
  -------------------------------------------------------------------
                         required time                         12.138    
                         arrival time                          -5.216    
  -------------------------------------------------------------------
                         slack                                  6.922    

Slack (MET) :             6.922ns  (required time - arrival time)
  Source:                 d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/rd_proc_ptr_reg[11]/CLR
                            (recovery check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk_pl_0 rise@10.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        2.616ns  (logic 0.106ns (4.052%)  route 2.510ns (95.948%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        -0.266ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.217ns = ( 12.217 - 10.000 ) 
    Source Clock Delay      (SCD):    2.600ns
    Clock Pessimism Removal (CPR):    0.117ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.374ns (routing 0.763ns, distribution 1.611ns)
  Clock Net Delay (Destination): 2.035ns (routing 0.690ns, distribution 1.345ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       2.374     2.600    d_1_i/rst_100/U0/slowest_sync_clk
    SLICE_X83Y83         FDRE                                         r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X83Y83         FDRE (Prop_BFF_SLICEM_C_Q)
                                                      0.078     2.678 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           0.699     3.377    d_1_i/rst_100/U0/peripheral_aresetn[0]_bufg_place
    BUFGCE_X0Y44         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.405 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_bufg_place/O
                         net (fo=7045, routed)        1.811     5.216    d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/count_gray_r_reg[7]
    SLICE_X34Y316        FDCE                                         f  d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/rd_proc_ptr_reg[11]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                     10.000    10.000 r  
    PS8_X0Y0             PS8                          0.000    10.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157    10.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025    10.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       2.035    12.217    d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/ps_clk
    SLICE_X34Y316        FDCE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/rd_proc_ptr_reg[11]/C
                         clock pessimism              0.117    12.334    
                         clock uncertainty           -0.130    12.204    
    SLICE_X34Y316        FDCE (Recov_DFF_SLICEM_C_CLR)
                                                     -0.066    12.138    d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/rd_proc_ptr_reg[11]
  -------------------------------------------------------------------
                         required time                         12.138    
                         arrival time                          -5.216    
  -------------------------------------------------------------------
                         slack                                  6.922    

Slack (MET) :             6.922ns  (required time - arrival time)
  Source:                 d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/rd_proc_ptr_reg[1]/CLR
                            (recovery check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk_pl_0 rise@10.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        2.617ns  (logic 0.106ns (4.050%)  route 2.511ns (95.950%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        -0.265ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.218ns = ( 12.218 - 10.000 ) 
    Source Clock Delay      (SCD):    2.600ns
    Clock Pessimism Removal (CPR):    0.117ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.374ns (routing 0.763ns, distribution 1.611ns)
  Clock Net Delay (Destination): 2.036ns (routing 0.690ns, distribution 1.346ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       2.374     2.600    d_1_i/rst_100/U0/slowest_sync_clk
    SLICE_X83Y83         FDRE                                         r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X83Y83         FDRE (Prop_BFF_SLICEM_C_Q)
                                                      0.078     2.678 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           0.699     3.377    d_1_i/rst_100/U0/peripheral_aresetn[0]_bufg_place
    BUFGCE_X0Y44         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.405 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_bufg_place/O
                         net (fo=7045, routed)        1.812     5.217    d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/count_gray_r_reg[7]
    SLICE_X34Y315        FDCE                                         f  d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/rd_proc_ptr_reg[1]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                     10.000    10.000 r  
    PS8_X0Y0             PS8                          0.000    10.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157    10.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025    10.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       2.036    12.218    d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/ps_clk
    SLICE_X34Y315        FDCE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/rd_proc_ptr_reg[1]/C
                         clock pessimism              0.117    12.335    
                         clock uncertainty           -0.130    12.205    
    SLICE_X34Y315        FDCE (Recov_BFF_SLICEM_C_CLR)
                                                     -0.066    12.139    d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/rd_proc_ptr_reg[1]
  -------------------------------------------------------------------
                         required time                         12.139    
                         arrival time                          -5.217    
  -------------------------------------------------------------------
                         slack                                  6.922    

Slack (MET) :             6.922ns  (required time - arrival time)
  Source:                 d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/rd_proc_ptr_reg[2]/CLR
                            (recovery check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk_pl_0 rise@10.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        2.617ns  (logic 0.106ns (4.050%)  route 2.511ns (95.950%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        -0.265ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.218ns = ( 12.218 - 10.000 ) 
    Source Clock Delay      (SCD):    2.600ns
    Clock Pessimism Removal (CPR):    0.117ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.374ns (routing 0.763ns, distribution 1.611ns)
  Clock Net Delay (Destination): 2.036ns (routing 0.690ns, distribution 1.346ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       2.374     2.600    d_1_i/rst_100/U0/slowest_sync_clk
    SLICE_X83Y83         FDRE                                         r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X83Y83         FDRE (Prop_BFF_SLICEM_C_Q)
                                                      0.078     2.678 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           0.699     3.377    d_1_i/rst_100/U0/peripheral_aresetn[0]_bufg_place
    BUFGCE_X0Y44         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.405 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_bufg_place/O
                         net (fo=7045, routed)        1.812     5.217    d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/count_gray_r_reg[7]
    SLICE_X34Y315        FDCE                                         f  d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/rd_proc_ptr_reg[2]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                     10.000    10.000 r  
    PS8_X0Y0             PS8                          0.000    10.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157    10.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025    10.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       2.036    12.218    d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/ps_clk
    SLICE_X34Y315        FDCE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/rd_proc_ptr_reg[2]/C
                         clock pessimism              0.117    12.335    
                         clock uncertainty           -0.130    12.205    
    SLICE_X34Y315        FDCE (Recov_CFF_SLICEM_C_CLR)
                                                     -0.066    12.139    d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/rd_proc_ptr_reg[2]
  -------------------------------------------------------------------
                         required time                         12.139    
                         arrival time                          -5.217    
  -------------------------------------------------------------------
                         slack                                  6.922    

Slack (MET) :             6.922ns  (required time - arrival time)
  Source:                 d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/rd_proc_ptr_reg[3]/CLR
                            (recovery check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk_pl_0 rise@10.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        2.617ns  (logic 0.106ns (4.050%)  route 2.511ns (95.950%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        -0.265ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.218ns = ( 12.218 - 10.000 ) 
    Source Clock Delay      (SCD):    2.600ns
    Clock Pessimism Removal (CPR):    0.117ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.374ns (routing 0.763ns, distribution 1.611ns)
  Clock Net Delay (Destination): 2.036ns (routing 0.690ns, distribution 1.346ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       2.374     2.600    d_1_i/rst_100/U0/slowest_sync_clk
    SLICE_X83Y83         FDRE                                         r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X83Y83         FDRE (Prop_BFF_SLICEM_C_Q)
                                                      0.078     2.678 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           0.699     3.377    d_1_i/rst_100/U0/peripheral_aresetn[0]_bufg_place
    BUFGCE_X0Y44         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.405 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_bufg_place/O
                         net (fo=7045, routed)        1.812     5.217    d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/count_gray_r_reg[7]
    SLICE_X34Y315        FDCE                                         f  d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/rd_proc_ptr_reg[3]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                     10.000    10.000 r  
    PS8_X0Y0             PS8                          0.000    10.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157    10.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025    10.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       2.036    12.218    d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/ps_clk
    SLICE_X34Y315        FDCE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/rd_proc_ptr_reg[3]/C
                         clock pessimism              0.117    12.335    
                         clock uncertainty           -0.130    12.205    
    SLICE_X34Y315        FDCE (Recov_DFF_SLICEM_C_CLR)
                                                     -0.066    12.139    d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/rd_proc_ptr_reg[3]
  -------------------------------------------------------------------
                         required time                         12.139    
                         arrival time                          -5.217    
  -------------------------------------------------------------------
                         slack                                  6.922    

Slack (MET) :             6.922ns  (required time - arrival time)
  Source:                 d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/rd_proc_ptr_reg[8]/CLR
                            (recovery check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk_pl_0 rise@10.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        2.616ns  (logic 0.106ns (4.052%)  route 2.510ns (95.948%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        -0.266ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.217ns = ( 12.217 - 10.000 ) 
    Source Clock Delay      (SCD):    2.600ns
    Clock Pessimism Removal (CPR):    0.117ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.374ns (routing 0.763ns, distribution 1.611ns)
  Clock Net Delay (Destination): 2.035ns (routing 0.690ns, distribution 1.345ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       2.374     2.600    d_1_i/rst_100/U0/slowest_sync_clk
    SLICE_X83Y83         FDRE                                         r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X83Y83         FDRE (Prop_BFF_SLICEM_C_Q)
                                                      0.078     2.678 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           0.699     3.377    d_1_i/rst_100/U0/peripheral_aresetn[0]_bufg_place
    BUFGCE_X0Y44         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.405 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_bufg_place/O
                         net (fo=7045, routed)        1.811     5.216    d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/count_gray_r_reg[7]
    SLICE_X34Y316        FDCE                                         f  d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/rd_proc_ptr_reg[8]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                     10.000    10.000 r  
    PS8_X0Y0             PS8                          0.000    10.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157    10.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025    10.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       2.035    12.217    d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/ps_clk
    SLICE_X34Y316        FDCE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/rd_proc_ptr_reg[8]/C
                         clock pessimism              0.117    12.334    
                         clock uncertainty           -0.130    12.204    
    SLICE_X34Y316        FDCE (Recov_AFF_SLICEM_C_CLR)
                                                     -0.066    12.138    d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/rd_proc_ptr_reg[8]
  -------------------------------------------------------------------
                         required time                         12.138    
                         arrival time                          -5.216    
  -------------------------------------------------------------------
                         slack                                  6.922    

Slack (MET) :             6.922ns  (required time - arrival time)
  Source:                 d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/rd_proc_ptr_reg[9]/CLR
                            (recovery check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk_pl_0 rise@10.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        2.616ns  (logic 0.106ns (4.052%)  route 2.510ns (95.948%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        -0.266ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.217ns = ( 12.217 - 10.000 ) 
    Source Clock Delay      (SCD):    2.600ns
    Clock Pessimism Removal (CPR):    0.117ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.374ns (routing 0.763ns, distribution 1.611ns)
  Clock Net Delay (Destination): 2.035ns (routing 0.690ns, distribution 1.345ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       2.374     2.600    d_1_i/rst_100/U0/slowest_sync_clk
    SLICE_X83Y83         FDRE                                         r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X83Y83         FDRE (Prop_BFF_SLICEM_C_Q)
                                                      0.078     2.678 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           0.699     3.377    d_1_i/rst_100/U0/peripheral_aresetn[0]_bufg_place
    BUFGCE_X0Y44         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.405 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_bufg_place/O
                         net (fo=7045, routed)        1.811     5.216    d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/count_gray_r_reg[7]
    SLICE_X34Y316        FDCE                                         f  d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/rd_proc_ptr_reg[9]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                     10.000    10.000 r  
    PS8_X0Y0             PS8                          0.000    10.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157    10.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025    10.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       2.035    12.217    d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/ps_clk
    SLICE_X34Y316        FDCE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/rd_proc_ptr_reg[9]/C
                         clock pessimism              0.117    12.334    
                         clock uncertainty           -0.130    12.204    
    SLICE_X34Y316        FDCE (Recov_BFF_SLICEM_C_CLR)
                                                     -0.066    12.138    d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/rd_proc_ptr_reg[9]
  -------------------------------------------------------------------
                         required time                         12.138    
                         arrival time                          -5.216    
  -------------------------------------------------------------------
                         slack                                  6.922    

Slack (MET) :             6.924ns  (required time - arrival time)
  Source:                 d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/rd_proc_ptr_reg[12]/CLR
                            (recovery check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk_pl_0 rise@10.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        2.613ns  (logic 0.106ns (4.057%)  route 2.507ns (95.943%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        -0.267ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.216ns = ( 12.216 - 10.000 ) 
    Source Clock Delay      (SCD):    2.600ns
    Clock Pessimism Removal (CPR):    0.117ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.374ns (routing 0.763ns, distribution 1.611ns)
  Clock Net Delay (Destination): 2.034ns (routing 0.690ns, distribution 1.344ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       2.374     2.600    d_1_i/rst_100/U0/slowest_sync_clk
    SLICE_X83Y83         FDRE                                         r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X83Y83         FDRE (Prop_BFF_SLICEM_C_Q)
                                                      0.078     2.678 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           0.699     3.377    d_1_i/rst_100/U0/peripheral_aresetn[0]_bufg_place
    BUFGCE_X0Y44         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.405 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_bufg_place/O
                         net (fo=7045, routed)        1.808     5.213    d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/count_gray_r_reg[7]
    SLICE_X34Y316        FDCE                                         f  d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/rd_proc_ptr_reg[12]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                     10.000    10.000 r  
    PS8_X0Y0             PS8                          0.000    10.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157    10.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025    10.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       2.034    12.216    d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/ps_clk
    SLICE_X34Y316        FDCE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/rd_proc_ptr_reg[12]/C
                         clock pessimism              0.117    12.333    
                         clock uncertainty           -0.130    12.203    
    SLICE_X34Y316        FDCE (Recov_EFF_SLICEM_C_CLR)
                                                     -0.066    12.137    d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/rd_proc_ptr_reg[12]
  -------------------------------------------------------------------
                         required time                         12.137    
                         arrival time                          -5.213    
  -------------------------------------------------------------------
                         slack                                  6.924    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.156ns  (arrival time - required time)
  Source:                 d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_i_reg/CLR
                            (removal check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_pl_0 rise@0.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        0.192ns  (logic 0.061ns (31.817%)  route 0.131ns (68.183%))
  Logic Levels:           1  (LUT3=1)
  Clock Path Skew:        0.056ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.571ns
    Source Clock Delay      (SCD):    1.373ns
    Clock Pessimism Removal (CPR):    0.142ns
  Clock Net Delay (Source):      1.253ns (routing 0.414ns, distribution 0.839ns)
  Clock Net Delay (Destination): 1.424ns (routing 0.463ns, distribution 0.961ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       1.253     1.373    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/clk
    SLICE_X30Y37         FDRE                                         r  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X30Y37         FDRE (Prop_AFF_SLICEM_C_Q)
                                                      0.038     1.411 f  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[0]/Q
                         net (fo=3, routed)           0.029     1.439    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc[0]
    SLICE_X30Y37         LUT3 (Prop_A6LUT_SLICEM_I1_O)
                                                      0.023     1.462 f  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/gpregsm1.curr_fwft_state[1]_i_2/O
                         net (fo=32, routed)          0.102     1.564    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/AR[0]
    SLICE_X29Y36         FDCE                                         f  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_i_reg/CLR
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       1.424     1.571    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/clk
    SLICE_X29Y36         FDCE                                         r  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_i_reg/C
                         clock pessimism             -0.142     1.429    
    SLICE_X29Y36         FDCE (Remov_HFF2_SLICEL_C_CLR)
                                                     -0.020     1.409    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_i_reg
  -------------------------------------------------------------------
                         required time                         -1.409    
                         arrival time                           1.564    
  -------------------------------------------------------------------
                         slack                                  0.156    

Slack (MET) :             0.156ns  (arrival time - required time)
  Source:                 d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_reg[2]/CLR
                            (removal check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_pl_0 rise@0.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        0.192ns  (logic 0.061ns (31.817%)  route 0.131ns (68.183%))
  Logic Levels:           1  (LUT3=1)
  Clock Path Skew:        0.056ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.571ns
    Source Clock Delay      (SCD):    1.373ns
    Clock Pessimism Removal (CPR):    0.142ns
  Clock Net Delay (Source):      1.253ns (routing 0.414ns, distribution 0.839ns)
  Clock Net Delay (Destination): 1.424ns (routing 0.463ns, distribution 0.961ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       1.253     1.373    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/clk
    SLICE_X30Y37         FDRE                                         r  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X30Y37         FDRE (Prop_AFF_SLICEM_C_Q)
                                                      0.038     1.411 f  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[0]/Q
                         net (fo=3, routed)           0.029     1.439    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc[0]
    SLICE_X30Y37         LUT3 (Prop_A6LUT_SLICEM_I1_O)
                                                      0.023     1.462 f  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/gpregsm1.curr_fwft_state[1]_i_2/O
                         net (fo=32, routed)          0.102     1.564    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/AR[0]
    SLICE_X29Y36         FDCE                                         f  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_reg[2]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       1.424     1.571    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/clk
    SLICE_X29Y36         FDCE                                         r  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_reg[2]/C
                         clock pessimism             -0.142     1.429    
    SLICE_X29Y36         FDCE (Remov_HFF_SLICEL_C_CLR)
                                                     -0.020     1.409    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_reg[2]
  -------------------------------------------------------------------
                         required time                         -1.409    
                         arrival time                           1.564    
  -------------------------------------------------------------------
                         slack                                  0.156    

Slack (MET) :             0.156ns  (arrival time - required time)
  Source:                 d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_reg[3]/CLR
                            (removal check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_pl_0 rise@0.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        0.192ns  (logic 0.061ns (31.817%)  route 0.131ns (68.183%))
  Logic Levels:           1  (LUT3=1)
  Clock Path Skew:        0.056ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.571ns
    Source Clock Delay      (SCD):    1.373ns
    Clock Pessimism Removal (CPR):    0.142ns
  Clock Net Delay (Source):      1.253ns (routing 0.414ns, distribution 0.839ns)
  Clock Net Delay (Destination): 1.424ns (routing 0.463ns, distribution 0.961ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       1.253     1.373    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/clk
    SLICE_X30Y37         FDRE                                         r  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X30Y37         FDRE (Prop_AFF_SLICEM_C_Q)
                                                      0.038     1.411 f  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[0]/Q
                         net (fo=3, routed)           0.029     1.439    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc[0]
    SLICE_X30Y37         LUT3 (Prop_A6LUT_SLICEM_I1_O)
                                                      0.023     1.462 f  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/gpregsm1.curr_fwft_state[1]_i_2/O
                         net (fo=32, routed)          0.102     1.564    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/AR[0]
    SLICE_X29Y36         FDCE                                         f  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_reg[3]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       1.424     1.571    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/clk
    SLICE_X29Y36         FDCE                                         r  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_reg[3]/C
                         clock pessimism             -0.142     1.429    
    SLICE_X29Y36         FDCE (Remov_GFF_SLICEL_C_CLR)
                                                     -0.020     1.409    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_reg[3]
  -------------------------------------------------------------------
                         required time                         -1.409    
                         arrival time                           1.564    
  -------------------------------------------------------------------
                         slack                                  0.156    

Slack (MET) :             0.156ns  (arrival time - required time)
  Source:                 d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_reg[4]/CLR
                            (removal check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_pl_0 rise@0.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        0.192ns  (logic 0.061ns (31.817%)  route 0.131ns (68.183%))
  Logic Levels:           1  (LUT3=1)
  Clock Path Skew:        0.056ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.571ns
    Source Clock Delay      (SCD):    1.373ns
    Clock Pessimism Removal (CPR):    0.142ns
  Clock Net Delay (Source):      1.253ns (routing 0.414ns, distribution 0.839ns)
  Clock Net Delay (Destination): 1.424ns (routing 0.463ns, distribution 0.961ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       1.253     1.373    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/clk
    SLICE_X30Y37         FDRE                                         r  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X30Y37         FDRE (Prop_AFF_SLICEM_C_Q)
                                                      0.038     1.411 f  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[0]/Q
                         net (fo=3, routed)           0.029     1.439    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc[0]
    SLICE_X30Y37         LUT3 (Prop_A6LUT_SLICEM_I1_O)
                                                      0.023     1.462 f  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/gpregsm1.curr_fwft_state[1]_i_2/O
                         net (fo=32, routed)          0.102     1.564    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/AR[0]
    SLICE_X29Y36         FDCE                                         f  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_reg[4]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       1.424     1.571    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/clk
    SLICE_X29Y36         FDCE                                         r  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_reg[4]/C
                         clock pessimism             -0.142     1.429    
    SLICE_X29Y36         FDCE (Remov_FFF_SLICEL_C_CLR)
                                                     -0.020     1.409    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_reg[4]
  -------------------------------------------------------------------
                         required time                         -1.409    
                         arrival time                           1.564    
  -------------------------------------------------------------------
                         slack                                  0.156    

Slack (MET) :             0.156ns  (arrival time - required time)
  Source:                 d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_reg[1]/CLR
                            (removal check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_pl_0 rise@0.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        0.192ns  (logic 0.061ns (31.817%)  route 0.131ns (68.183%))
  Logic Levels:           1  (LUT3=1)
  Clock Path Skew:        0.056ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.571ns
    Source Clock Delay      (SCD):    1.373ns
    Clock Pessimism Removal (CPR):    0.142ns
  Clock Net Delay (Source):      1.253ns (routing 0.414ns, distribution 0.839ns)
  Clock Net Delay (Destination): 1.424ns (routing 0.463ns, distribution 0.961ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       1.253     1.373    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/clk
    SLICE_X30Y37         FDRE                                         r  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X30Y37         FDRE (Prop_AFF_SLICEM_C_Q)
                                                      0.038     1.411 f  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[0]/Q
                         net (fo=3, routed)           0.029     1.439    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc[0]
    SLICE_X30Y37         LUT3 (Prop_A6LUT_SLICEM_I1_O)
                                                      0.023     1.462 f  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/gpregsm1.curr_fwft_state[1]_i_2/O
                         net (fo=32, routed)          0.102     1.564    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/AR[0]
    SLICE_X29Y36         FDCE                                         f  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_reg[1]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       1.424     1.571    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/clk
    SLICE_X29Y36         FDCE                                         r  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_reg[1]/C
                         clock pessimism             -0.142     1.429    
    SLICE_X29Y36         FDCE (Remov_EFF_SLICEL_C_CLR)
                                                     -0.020     1.409    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_reg[1]
  -------------------------------------------------------------------
                         required time                         -1.409    
                         arrival time                           1.564    
  -------------------------------------------------------------------
                         slack                                  0.156    

Slack (MET) :             0.160ns  (arrival time - required time)
  Source:                 d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_reg[1]/CLR
                            (removal check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_pl_0 rise@0.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        0.192ns  (logic 0.061ns (31.817%)  route 0.131ns (68.183%))
  Logic Levels:           1  (LUT3=1)
  Clock Path Skew:        0.052ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.567ns
    Source Clock Delay      (SCD):    1.373ns
    Clock Pessimism Removal (CPR):    0.142ns
  Clock Net Delay (Source):      1.253ns (routing 0.414ns, distribution 0.839ns)
  Clock Net Delay (Destination): 1.420ns (routing 0.463ns, distribution 0.957ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       1.253     1.373    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/clk
    SLICE_X30Y37         FDRE                                         r  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X30Y37         FDRE (Prop_AFF_SLICEM_C_Q)
                                                      0.038     1.411 f  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[0]/Q
                         net (fo=3, routed)           0.029     1.439    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc[0]
    SLICE_X30Y37         LUT3 (Prop_A6LUT_SLICEM_I1_O)
                                                      0.023     1.462 f  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/gpregsm1.curr_fwft_state[1]_i_2/O
                         net (fo=32, routed)          0.102     1.564    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/AR[0]
    SLICE_X29Y36         FDCE                                         f  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_reg[1]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       1.420     1.567    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/clk
    SLICE_X29Y36         FDCE                                         r  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_reg[1]/C
                         clock pessimism             -0.142     1.425    
    SLICE_X29Y36         FDCE (Remov_AFF_SLICEL_C_CLR)
                                                     -0.020     1.405    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_reg[1]
  -------------------------------------------------------------------
                         required time                         -1.405    
                         arrival time                           1.564    
  -------------------------------------------------------------------
                         slack                                  0.160    

Slack (MET) :             0.160ns  (arrival time - required time)
  Source:                 d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_reg[2]/CLR
                            (removal check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_pl_0 rise@0.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        0.192ns  (logic 0.061ns (31.817%)  route 0.131ns (68.183%))
  Logic Levels:           1  (LUT3=1)
  Clock Path Skew:        0.052ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.567ns
    Source Clock Delay      (SCD):    1.373ns
    Clock Pessimism Removal (CPR):    0.142ns
  Clock Net Delay (Source):      1.253ns (routing 0.414ns, distribution 0.839ns)
  Clock Net Delay (Destination): 1.420ns (routing 0.463ns, distribution 0.957ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       1.253     1.373    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/clk
    SLICE_X30Y37         FDRE                                         r  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X30Y37         FDRE (Prop_AFF_SLICEM_C_Q)
                                                      0.038     1.411 f  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[0]/Q
                         net (fo=3, routed)           0.029     1.439    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc[0]
    SLICE_X30Y37         LUT3 (Prop_A6LUT_SLICEM_I1_O)
                                                      0.023     1.462 f  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/gpregsm1.curr_fwft_state[1]_i_2/O
                         net (fo=32, routed)          0.102     1.564    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/AR[0]
    SLICE_X29Y36         FDCE                                         f  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_reg[2]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       1.420     1.567    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/clk
    SLICE_X29Y36         FDCE                                         r  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_reg[2]/C
                         clock pessimism             -0.142     1.425    
    SLICE_X29Y36         FDCE (Remov_BFF2_SLICEL_C_CLR)
                                                     -0.020     1.405    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_reg[2]
  -------------------------------------------------------------------
                         required time                         -1.405    
                         arrival time                           1.564    
  -------------------------------------------------------------------
                         slack                                  0.160    

Slack (MET) :             0.160ns  (arrival time - required time)
  Source:                 d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_reg[3]/CLR
                            (removal check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_pl_0 rise@0.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        0.192ns  (logic 0.061ns (31.817%)  route 0.131ns (68.183%))
  Logic Levels:           1  (LUT3=1)
  Clock Path Skew:        0.052ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.567ns
    Source Clock Delay      (SCD):    1.373ns
    Clock Pessimism Removal (CPR):    0.142ns
  Clock Net Delay (Source):      1.253ns (routing 0.414ns, distribution 0.839ns)
  Clock Net Delay (Destination): 1.420ns (routing 0.463ns, distribution 0.957ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       1.253     1.373    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/clk
    SLICE_X30Y37         FDRE                                         r  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X30Y37         FDRE (Prop_AFF_SLICEM_C_Q)
                                                      0.038     1.411 f  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[0]/Q
                         net (fo=3, routed)           0.029     1.439    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc[0]
    SLICE_X30Y37         LUT3 (Prop_A6LUT_SLICEM_I1_O)
                                                      0.023     1.462 f  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/gpregsm1.curr_fwft_state[1]_i_2/O
                         net (fo=32, routed)          0.102     1.564    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/AR[0]
    SLICE_X29Y36         FDCE                                         f  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_reg[3]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       1.420     1.567    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/clk
    SLICE_X29Y36         FDCE                                         r  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_reg[3]/C
                         clock pessimism             -0.142     1.425    
    SLICE_X29Y36         FDCE (Remov_CFF_SLICEL_C_CLR)
                                                     -0.020     1.405    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_reg[3]
  -------------------------------------------------------------------
                         required time                         -1.405    
                         arrival time                           1.564    
  -------------------------------------------------------------------
                         slack                                  0.160    

Slack (MET) :             0.160ns  (arrival time - required time)
  Source:                 d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_reg[4]/CLR
                            (removal check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_pl_0 rise@0.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        0.192ns  (logic 0.061ns (31.817%)  route 0.131ns (68.183%))
  Logic Levels:           1  (LUT3=1)
  Clock Path Skew:        0.052ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.567ns
    Source Clock Delay      (SCD):    1.373ns
    Clock Pessimism Removal (CPR):    0.142ns
  Clock Net Delay (Source):      1.253ns (routing 0.414ns, distribution 0.839ns)
  Clock Net Delay (Destination): 1.420ns (routing 0.463ns, distribution 0.957ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       1.253     1.373    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/clk
    SLICE_X30Y37         FDRE                                         r  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X30Y37         FDRE (Prop_AFF_SLICEM_C_Q)
                                                      0.038     1.411 f  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[0]/Q
                         net (fo=3, routed)           0.029     1.439    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc[0]
    SLICE_X30Y37         LUT3 (Prop_A6LUT_SLICEM_I1_O)
                                                      0.023     1.462 f  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/gpregsm1.curr_fwft_state[1]_i_2/O
                         net (fo=32, routed)          0.102     1.564    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/AR[0]
    SLICE_X29Y36         FDCE                                         f  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_reg[4]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       1.420     1.567    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/clk
    SLICE_X29Y36         FDCE                                         r  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_reg[4]/C
                         clock pessimism             -0.142     1.425    
    SLICE_X29Y36         FDCE (Remov_CFF2_SLICEL_C_CLR)
                                                     -0.020     1.405    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_reg[4]
  -------------------------------------------------------------------
                         required time                         -1.405    
                         arrival time                           1.564    
  -------------------------------------------------------------------
                         slack                                  0.160    

Slack (MET) :             0.187ns  (arrival time - required time)
  Source:                 d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[0]/CLR
                            (removal check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_pl_0 rise@0.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        0.224ns  (logic 0.061ns (27.219%)  route 0.163ns (72.781%))
  Logic Levels:           1  (LUT3=1)
  Clock Path Skew:        0.057ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.572ns
    Source Clock Delay      (SCD):    1.373ns
    Clock Pessimism Removal (CPR):    0.142ns
  Clock Net Delay (Source):      1.253ns (routing 0.414ns, distribution 0.839ns)
  Clock Net Delay (Destination): 1.425ns (routing 0.463ns, distribution 0.962ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       1.253     1.373    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/clk
    SLICE_X30Y37         FDRE                                         r  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X30Y37         FDRE (Prop_AFF_SLICEM_C_Q)
                                                      0.038     1.411 f  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[0]/Q
                         net (fo=3, routed)           0.029     1.439    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc[0]
    SLICE_X30Y37         LUT3 (Prop_A6LUT_SLICEM_I1_O)
                                                      0.023     1.462 f  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/gpregsm1.curr_fwft_state[1]_i_2/O
                         net (fo=32, routed)          0.134     1.597    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[4]_1
    SLICE_X29Y37         FDCE                                         f  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[0]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       1.425     1.572    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/clk
    SLICE_X29Y37         FDCE                                         r  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[0]/C
                         clock pessimism             -0.142     1.430    
    SLICE_X29Y37         FDCE (Remov_HFF2_SLICEL_C_CLR)
                                                     -0.020     1.410    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[0]
  -------------------------------------------------------------------
                         required time                         -1.410    
                         arrival time                           1.597    
  -------------------------------------------------------------------
                         slack                                  0.187    





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  
  To Clock:  RFDAC0_CLK

Max Delay             1 Endpoint
Min Delay             1 Endpoint
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/EMIOGPIOO[95]
                            (internal pin)
  Destination:            d_1_i/rst_dac0/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.493ns  (logic 0.149ns (5.976%)  route 2.344ns (94.024%))
  Logic Levels:           1  (LUT1=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.262ns (routing 1.352ns, distribution 0.910ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    PS8_X0Y0             PS8                          0.000     0.000 f  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/EMIOGPIOO[95]
                         net (fo=4, routed)           2.049     2.049    d_1_i/rst_dac0/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/ext_reset_in
    SLICE_X80Y112        LUT1 (Prop_G6LUT_SLICEL_I0_O)
                                                      0.149     2.198 r  d_1_i/rst_dac0/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1/O
                         net (fo=1, routed)           0.295     2.493    d_1_i/rst_dac0/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/exr_d1
    SLICE_X80Y112        FDRE                                         r  d_1_i/rst_dac0/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=5276, routed)        2.262     2.783    d_1_i/rst_dac0/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/slowest_sync_clk
    SLICE_X80Y112        FDRE                                         r  d_1_i/rst_dac0/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/EMIOGPIOO[95]
                            (internal pin)
  Destination:            d_1_i/rst_dac0/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.203ns  (logic 0.060ns (4.987%)  route 1.143ns (95.013%))
  Logic Levels:           1  (LUT1=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.563ns (routing 0.900ns, distribution 0.663ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    PS8_X0Y0             PS8                          0.000     0.000 f  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/EMIOGPIOO[95]
                         net (fo=4, routed)           1.040     1.040    d_1_i/rst_dac0/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/ext_reset_in
    SLICE_X80Y112        LUT1 (Prop_G6LUT_SLICEL_I0_O)
                                                      0.060     1.100 r  d_1_i/rst_dac0/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1/O
                         net (fo=1, routed)           0.103     1.203    d_1_i/rst_dac0/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/exr_d1
    SLICE_X80Y112        FDRE                                         r  d_1_i/rst_dac0/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=5276, routed)        1.563     2.011    d_1_i/rst_dac0/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/slowest_sync_clk
    SLICE_X80Y112        FDRE                                         r  d_1_i/rst_dac0/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  clk_pl_0
  To Clock:  RFDAC0_CLK

Max Delay           214 Endpoints
Min Delay           214 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/dac0_done_i_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac0_done_i/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.524ns  (logic 0.078ns (5.118%)  route 1.446ns (94.882%))
  Logic Levels:           0  
  Clock Path Skew:        0.259ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.032ns
    Source Clock Delay      (SCD):    2.773ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.547ns (routing 0.763ns, distribution 1.784ns)
  Clock Net Delay (Destination): 2.511ns (routing 1.352ns, distribution 1.159ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       2.547     2.773    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/s_axi_aclk
    SLICE_X113Y129       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/dac0_done_i_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X113Y129       FDRE (Prop_BFF_SLICEM_C_Q)
                                                      0.078     2.851 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/dac0_done_i_reg/Q
                         net (fo=1, routed)           1.446     4.297    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac0_done_i/src_in
    SLICE_X117Y270       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac0_done_i/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=5276, routed)        2.511     3.032    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac0_done_i/dest_clk
    SLICE_X117Y270       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac0_done_i/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].trig_fifo_inst/rd_gptr_r_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/sync_ctrl_ps_t/data_cdc_reg[3]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        4.107ns  (logic 0.790ns (19.237%)  route 3.317ns (80.763%))
  Logic Levels:           7  (LUT3=2 LUT4=1 LUT5=1 LUT6=3)
  Clock Path Skew:        0.272ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.733ns
    Source Clock Delay      (SCD):    2.460ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.234ns (routing 0.763ns, distribution 1.471ns)
  Clock Net Delay (Destination): 2.212ns (routing 1.352ns, distribution 0.860ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       2.234     2.460    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].trig_fifo_inst/c_clk_i
    SLICE_X72Y152        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].trig_fifo_inst/rd_gptr_r_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X72Y152        FDRE (Prop_EFF2_SLICEM_C_Q)
                                                      0.079     2.539 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].trig_fifo_inst/rd_gptr_r_reg[0]/Q
                         net (fo=1, routed)           0.210     2.749    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].trig_fifo_inst/gcc_wr_ptr/TRIG_FIFO[3].trig_fifo_inst/fifo_mem/RAM_reg_0[0]
    SLICE_X72Y152        LUT6 (Prop_H6LUT_SLICEM_I0_O)
                                                      0.152     2.901 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].trig_fifo_inst/gcc_wr_ptr/RAM_reg_i_2__2/O
                         net (fo=3, routed)           0.167     3.068    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].trig_fifo_inst/gcc_wr_ptr/RAM_reg_i_2__2_n_0
    SLICE_X72Y151        LUT5 (Prop_E6LUT_SLICEM_I2_O)
                                                      0.124     3.192 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].trig_fifo_inst/gcc_wr_ptr/qp1_en_o_INST_0_i_4/O
                         net (fo=3, routed)           0.594     3.786    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].trig_fifo_inst/gcc_wr_ptr/c_fifo_trig_push_r_reg[0][0]
    SLICE_X68Y133        LUT6 (Prop_C6LUT_SLICEL_I1_O)
                                                      0.123     3.909 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].trig_fifo_inst/gcc_wr_ptr/qp1_en_o_INST_0_i_2/O
                         net (fo=5, routed)           0.311     4.221    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].trig_fifo_inst/gcc_wr_ptr/some_fifo_full
    SLICE_X65Y119        LUT4 (Prop_F6LUT_SLICEL_I2_O)
                                                      0.123     4.344 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].trig_fifo_inst/gcc_wr_ptr/qp1_en_o_INST_0_i_1/O
                         net (fo=406, routed)         0.677     5.021    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/D[0]
    SLICE_X61Y93         LUT6 (Prop_H6LUT_SLICEM_I4_O)
                                                      0.039     5.060 f  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/data_cdc[4]_i_2/O
                         net (fo=4, routed)           0.221     5.280    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/x1_ctrl_reg[usr_ctrl][5]_1
    SLICE_X62Y100        LUT3 (Prop_D6LUT_SLICEL_I0_O)
                                                      0.099     5.379 f  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/data_cdc[3]_i_2/O
                         net (fo=33, routed)          0.563     5.943    d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/data_cdc_reg[3]
    SLICE_X63Y127        LUT3 (Prop_C6LUT_SLICEM_I2_O)
                                                      0.051     5.994 r  d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/data_cdc[3]_i_1/O
                         net (fo=33, routed)          0.573     6.567    d_1_i/qick_processor_0/inst/QPROC/sync_ctrl_ps_t/data_cdc_reg[6]_0[3]
    SLICE_X68Y131        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/sync_ctrl_ps_t/data_cdc_reg[3]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=5276, routed)        2.212     2.733    d_1_i/qick_processor_0/inst/QPROC/sync_ctrl_ps_t/t_clk_i
    SLICE_X68Y131        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/sync_ctrl_ps_t/data_cdc_reg[3]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].trig_fifo_inst/rd_gptr_r_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/sync_ctrl_ps_t/data_cdc_reg[4]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.728ns  (logic 0.849ns (22.776%)  route 2.879ns (77.224%))
  Logic Levels:           6  (LUT2=1 LUT4=1 LUT5=1 LUT6=3)
  Clock Path Skew:        0.278ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.739ns
    Source Clock Delay      (SCD):    2.460ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.234ns (routing 0.763ns, distribution 1.471ns)
  Clock Net Delay (Destination): 2.218ns (routing 1.352ns, distribution 0.866ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       2.234     2.460    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].trig_fifo_inst/c_clk_i
    SLICE_X72Y152        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].trig_fifo_inst/rd_gptr_r_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X72Y152        FDRE (Prop_EFF2_SLICEM_C_Q)
                                                      0.079     2.539 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].trig_fifo_inst/rd_gptr_r_reg[0]/Q
                         net (fo=1, routed)           0.210     2.749    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].trig_fifo_inst/gcc_wr_ptr/TRIG_FIFO[3].trig_fifo_inst/fifo_mem/RAM_reg_0[0]
    SLICE_X72Y152        LUT6 (Prop_H6LUT_SLICEM_I0_O)
                                                      0.152     2.901 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].trig_fifo_inst/gcc_wr_ptr/RAM_reg_i_2__2/O
                         net (fo=3, routed)           0.167     3.068    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].trig_fifo_inst/gcc_wr_ptr/RAM_reg_i_2__2_n_0
    SLICE_X72Y151        LUT5 (Prop_E6LUT_SLICEM_I2_O)
                                                      0.124     3.192 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].trig_fifo_inst/gcc_wr_ptr/qp1_en_o_INST_0_i_4/O
                         net (fo=3, routed)           0.594     3.786    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].trig_fifo_inst/gcc_wr_ptr/c_fifo_trig_push_r_reg[0][0]
    SLICE_X68Y133        LUT6 (Prop_C6LUT_SLICEL_I1_O)
                                                      0.123     3.909 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].trig_fifo_inst/gcc_wr_ptr/qp1_en_o_INST_0_i_2/O
                         net (fo=5, routed)           0.311     4.221    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].trig_fifo_inst/gcc_wr_ptr/some_fifo_full
    SLICE_X65Y119        LUT4 (Prop_F6LUT_SLICEL_I2_O)
                                                      0.123     4.344 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].trig_fifo_inst/gcc_wr_ptr/qp1_en_o_INST_0_i_1/O
                         net (fo=406, routed)         0.687     5.031    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/D[0]
    SLICE_X61Y95         LUT2 (Prop_C6LUT_SLICEM_I1_O)
                                                      0.098     5.129 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/qp1_op_o[0]_INST_0/O
                         net (fo=2, routed)           0.494     5.623    d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/qp1_op_o[0]
    SLICE_X65Y116        LUT6 (Prop_H6LUT_SLICEL_I0_O)
                                                      0.150     5.773 r  d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/data_cdc[4]_i_1/O
                         net (fo=1, routed)           0.415     6.188    d_1_i/qick_processor_0/inst/QPROC/sync_ctrl_ps_t/data_cdc_reg[6]_0[4]
    SLICE_X67Y124        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/sync_ctrl_ps_t/data_cdc_reg[4]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=5276, routed)        2.218     2.739    d_1_i/qick_processor_0/inst/QPROC/sync_ctrl_ps_t/t_clk_i
    SLICE_X67Y124        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/sync_ctrl_ps_t/data_cdc_reg[4]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/clr_fifo_req_reg/C
                            (rising edge-triggered cell FDCE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/gcc_rd_ptr/count_gray_r_reg[0]/CE
                            (rising edge-triggered cell FDPE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.738ns  (logic 0.344ns (19.787%)  route 1.394ns (80.213%))
  Logic Levels:           4  (LUT3=1 LUT5=3)
  Clock Path Skew:        0.281ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.760ns
    Source Clock Delay      (SCD):    2.479ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.253ns (routing 0.763ns, distribution 1.490ns)
  Clock Net Delay (Destination): 2.239ns (routing 1.352ns, distribution 0.887ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       2.253     2.479    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/c_clk_i
    SLICE_X74Y141        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/clr_fifo_req_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X74Y141        FDCE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     2.558 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/clr_fifo_req_reg/Q
                         net (fo=5, routed)           0.391     2.949    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/clr_fifo_req
    SLICE_X74Y141        LUT3 (Prop_C5LUT_SLICEL_I1_O)
                                                      0.110     3.059 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/t_fifo_trig_empty_inferred_i_4/O
                         net (fo=2, routed)           0.253     3.312    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/gcc_rd_ptr/trig_pop_r_reg[0][0]
    SLICE_X76Y143        LUT5 (Prop_D6LUT_SLICEM_I0_O)
                                                      0.037     3.349 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/gcc_rd_ptr/trig_pop_r[0]_i_2/O
                         net (fo=1, routed)           0.195     3.544    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].ADDSUB_MACRO_inst/trig_pop_r_reg[0]_0
    SLICE_X75Y140        LUT5 (Prop_D5LUT_SLICEM_I4_O)
                                                      0.066     3.610 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].ADDSUB_MACRO_inst/trig_pop_r[0]_i_1/O
                         net (fo=2, routed)           0.186     3.796    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/gcc_rd_ptr/trig_pop
    SLICE_X75Y141        LUT5 (Prop_G6LUT_SLICEM_I4_O)
                                                      0.052     3.848 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/gcc_rd_ptr/count_gray_r[8]_i_1__3/O
                         net (fo=18, routed)          0.370     4.218    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/gcc_rd_ptr/count_bin_2r
    SLICE_X78Y139        FDPE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/gcc_rd_ptr/count_gray_r_reg[0]/CE
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=5276, routed)        2.239     2.760    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/gcc_rd_ptr/t_clk_i
    SLICE_X78Y139        FDPE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/gcc_rd_ptr/count_gray_r_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/clr_fifo_req_reg/C
                            (rising edge-triggered cell FDCE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/gcc_rd_ptr/count_gray_r_reg[2]/CE
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.738ns  (logic 0.344ns (19.787%)  route 1.394ns (80.213%))
  Logic Levels:           4  (LUT3=1 LUT5=3)
  Clock Path Skew:        0.281ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.760ns
    Source Clock Delay      (SCD):    2.479ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.253ns (routing 0.763ns, distribution 1.490ns)
  Clock Net Delay (Destination): 2.239ns (routing 1.352ns, distribution 0.887ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       2.253     2.479    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/c_clk_i
    SLICE_X74Y141        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/clr_fifo_req_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X74Y141        FDCE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     2.558 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/clr_fifo_req_reg/Q
                         net (fo=5, routed)           0.391     2.949    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/clr_fifo_req
    SLICE_X74Y141        LUT3 (Prop_C5LUT_SLICEL_I1_O)
                                                      0.110     3.059 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/t_fifo_trig_empty_inferred_i_4/O
                         net (fo=2, routed)           0.253     3.312    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/gcc_rd_ptr/trig_pop_r_reg[0][0]
    SLICE_X76Y143        LUT5 (Prop_D6LUT_SLICEM_I0_O)
                                                      0.037     3.349 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/gcc_rd_ptr/trig_pop_r[0]_i_2/O
                         net (fo=1, routed)           0.195     3.544    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].ADDSUB_MACRO_inst/trig_pop_r_reg[0]_0
    SLICE_X75Y140        LUT5 (Prop_D5LUT_SLICEM_I4_O)
                                                      0.066     3.610 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].ADDSUB_MACRO_inst/trig_pop_r[0]_i_1/O
                         net (fo=2, routed)           0.186     3.796    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/gcc_rd_ptr/trig_pop
    SLICE_X75Y141        LUT5 (Prop_G6LUT_SLICEM_I4_O)
                                                      0.052     3.848 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/gcc_rd_ptr/count_gray_r[8]_i_1__3/O
                         net (fo=18, routed)          0.370     4.218    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/gcc_rd_ptr/count_bin_2r
    SLICE_X78Y139        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/gcc_rd_ptr/count_gray_r_reg[2]/CE
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=5276, routed)        2.239     2.760    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/gcc_rd_ptr/t_clk_i
    SLICE_X78Y139        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/gcc_rd_ptr/count_gray_r_reg[2]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/clr_fifo_req_reg/C
                            (rising edge-triggered cell FDCE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/gcc_rd_ptr/count_gray_r_reg[5]/CE
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.738ns  (logic 0.344ns (19.787%)  route 1.394ns (80.213%))
  Logic Levels:           4  (LUT3=1 LUT5=3)
  Clock Path Skew:        0.281ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.760ns
    Source Clock Delay      (SCD):    2.479ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.253ns (routing 0.763ns, distribution 1.490ns)
  Clock Net Delay (Destination): 2.239ns (routing 1.352ns, distribution 0.887ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       2.253     2.479    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/c_clk_i
    SLICE_X74Y141        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/clr_fifo_req_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X74Y141        FDCE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     2.558 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/clr_fifo_req_reg/Q
                         net (fo=5, routed)           0.391     2.949    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/clr_fifo_req
    SLICE_X74Y141        LUT3 (Prop_C5LUT_SLICEL_I1_O)
                                                      0.110     3.059 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/t_fifo_trig_empty_inferred_i_4/O
                         net (fo=2, routed)           0.253     3.312    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/gcc_rd_ptr/trig_pop_r_reg[0][0]
    SLICE_X76Y143        LUT5 (Prop_D6LUT_SLICEM_I0_O)
                                                      0.037     3.349 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/gcc_rd_ptr/trig_pop_r[0]_i_2/O
                         net (fo=1, routed)           0.195     3.544    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].ADDSUB_MACRO_inst/trig_pop_r_reg[0]_0
    SLICE_X75Y140        LUT5 (Prop_D5LUT_SLICEM_I4_O)
                                                      0.066     3.610 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].ADDSUB_MACRO_inst/trig_pop_r[0]_i_1/O
                         net (fo=2, routed)           0.186     3.796    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/gcc_rd_ptr/trig_pop
    SLICE_X75Y141        LUT5 (Prop_G6LUT_SLICEM_I4_O)
                                                      0.052     3.848 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/gcc_rd_ptr/count_gray_r[8]_i_1__3/O
                         net (fo=18, routed)          0.370     4.218    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/gcc_rd_ptr/count_bin_2r
    SLICE_X78Y139        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/gcc_rd_ptr/count_gray_r_reg[5]/CE
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=5276, routed)        2.239     2.760    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/gcc_rd_ptr/t_clk_i
    SLICE_X78Y139        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/gcc_rd_ptr/count_gray_r_reg[5]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/clr_fifo_req_reg/C
                            (rising edge-triggered cell FDCE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[1]/CE
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.707ns  (logic 0.344ns (20.148%)  route 1.363ns (79.852%))
  Logic Levels:           4  (LUT3=1 LUT5=3)
  Clock Path Skew:        0.293ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.772ns
    Source Clock Delay      (SCD):    2.479ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.253ns (routing 0.763ns, distribution 1.490ns)
  Clock Net Delay (Destination): 2.251ns (routing 1.352ns, distribution 0.899ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       2.253     2.479    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/c_clk_i
    SLICE_X74Y141        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/clr_fifo_req_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X74Y141        FDCE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     2.558 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/clr_fifo_req_reg/Q
                         net (fo=5, routed)           0.391     2.949    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/clr_fifo_req
    SLICE_X74Y141        LUT3 (Prop_C5LUT_SLICEL_I1_O)
                                                      0.110     3.059 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/t_fifo_trig_empty_inferred_i_4/O
                         net (fo=2, routed)           0.253     3.312    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/gcc_rd_ptr/trig_pop_r_reg[0][0]
    SLICE_X76Y143        LUT5 (Prop_D6LUT_SLICEM_I0_O)
                                                      0.037     3.349 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/gcc_rd_ptr/trig_pop_r[0]_i_2/O
                         net (fo=1, routed)           0.195     3.544    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].ADDSUB_MACRO_inst/trig_pop_r_reg[0]_0
    SLICE_X75Y140        LUT5 (Prop_D5LUT_SLICEM_I4_O)
                                                      0.066     3.610 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].ADDSUB_MACRO_inst/trig_pop_r[0]_i_1/O
                         net (fo=2, routed)           0.186     3.796    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/gcc_rd_ptr/trig_pop
    SLICE_X75Y141        LUT5 (Prop_G6LUT_SLICEM_I4_O)
                                                      0.052     3.848 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/gcc_rd_ptr/count_gray_r[8]_i_1__3/O
                         net (fo=18, routed)          0.338     4.187    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/gcc_rd_ptr/count_bin_2r
    SLICE_X76Y138        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[1]/CE
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=5276, routed)        2.251     2.772    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/gcc_rd_ptr/t_clk_i
    SLICE_X76Y138        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[1]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/clr_fifo_req_reg/C
                            (rising edge-triggered cell FDCE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[2]/CE
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.707ns  (logic 0.344ns (20.148%)  route 1.363ns (79.852%))
  Logic Levels:           4  (LUT3=1 LUT5=3)
  Clock Path Skew:        0.293ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.772ns
    Source Clock Delay      (SCD):    2.479ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.253ns (routing 0.763ns, distribution 1.490ns)
  Clock Net Delay (Destination): 2.251ns (routing 1.352ns, distribution 0.899ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       2.253     2.479    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/c_clk_i
    SLICE_X74Y141        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/clr_fifo_req_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X74Y141        FDCE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     2.558 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/clr_fifo_req_reg/Q
                         net (fo=5, routed)           0.391     2.949    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/clr_fifo_req
    SLICE_X74Y141        LUT3 (Prop_C5LUT_SLICEL_I1_O)
                                                      0.110     3.059 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/t_fifo_trig_empty_inferred_i_4/O
                         net (fo=2, routed)           0.253     3.312    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/gcc_rd_ptr/trig_pop_r_reg[0][0]
    SLICE_X76Y143        LUT5 (Prop_D6LUT_SLICEM_I0_O)
                                                      0.037     3.349 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/gcc_rd_ptr/trig_pop_r[0]_i_2/O
                         net (fo=1, routed)           0.195     3.544    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].ADDSUB_MACRO_inst/trig_pop_r_reg[0]_0
    SLICE_X75Y140        LUT5 (Prop_D5LUT_SLICEM_I4_O)
                                                      0.066     3.610 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].ADDSUB_MACRO_inst/trig_pop_r[0]_i_1/O
                         net (fo=2, routed)           0.186     3.796    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/gcc_rd_ptr/trig_pop
    SLICE_X75Y141        LUT5 (Prop_G6LUT_SLICEM_I4_O)
                                                      0.052     3.848 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/gcc_rd_ptr/count_gray_r[8]_i_1__3/O
                         net (fo=18, routed)          0.338     4.187    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/gcc_rd_ptr/count_bin_2r
    SLICE_X76Y138        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[2]/CE
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=5276, routed)        2.251     2.772    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/gcc_rd_ptr/t_clk_i
    SLICE_X76Y138        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[2]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/clr_fifo_req_reg/C
                            (rising edge-triggered cell FDCE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/gcc_rd_ptr/count_gray_r_reg[3]/CE
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.707ns  (logic 0.344ns (20.148%)  route 1.363ns (79.852%))
  Logic Levels:           4  (LUT3=1 LUT5=3)
  Clock Path Skew:        0.293ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.772ns
    Source Clock Delay      (SCD):    2.479ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.253ns (routing 0.763ns, distribution 1.490ns)
  Clock Net Delay (Destination): 2.251ns (routing 1.352ns, distribution 0.899ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       2.253     2.479    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/c_clk_i
    SLICE_X74Y141        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/clr_fifo_req_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X74Y141        FDCE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     2.558 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/clr_fifo_req_reg/Q
                         net (fo=5, routed)           0.391     2.949    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/clr_fifo_req
    SLICE_X74Y141        LUT3 (Prop_C5LUT_SLICEL_I1_O)
                                                      0.110     3.059 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/t_fifo_trig_empty_inferred_i_4/O
                         net (fo=2, routed)           0.253     3.312    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/gcc_rd_ptr/trig_pop_r_reg[0][0]
    SLICE_X76Y143        LUT5 (Prop_D6LUT_SLICEM_I0_O)
                                                      0.037     3.349 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/gcc_rd_ptr/trig_pop_r[0]_i_2/O
                         net (fo=1, routed)           0.195     3.544    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].ADDSUB_MACRO_inst/trig_pop_r_reg[0]_0
    SLICE_X75Y140        LUT5 (Prop_D5LUT_SLICEM_I4_O)
                                                      0.066     3.610 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].ADDSUB_MACRO_inst/trig_pop_r[0]_i_1/O
                         net (fo=2, routed)           0.186     3.796    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/gcc_rd_ptr/trig_pop
    SLICE_X75Y141        LUT5 (Prop_G6LUT_SLICEM_I4_O)
                                                      0.052     3.848 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/gcc_rd_ptr/count_gray_r[8]_i_1__3/O
                         net (fo=18, routed)          0.338     4.187    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/gcc_rd_ptr/count_bin_2r
    SLICE_X76Y138        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/gcc_rd_ptr/count_gray_r_reg[3]/CE
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=5276, routed)        2.251     2.772    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/gcc_rd_ptr/t_clk_i
    SLICE_X76Y138        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/gcc_rd_ptr/count_gray_r_reg[3]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/clr_fifo_req_reg/C
                            (rising edge-triggered cell FDCE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/gcc_rd_ptr/count_gray_r_reg[1]/CE
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.703ns  (logic 0.344ns (20.195%)  route 1.359ns (79.805%))
  Logic Levels:           4  (LUT3=1 LUT5=3)
  Clock Path Skew:        0.286ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.765ns
    Source Clock Delay      (SCD):    2.479ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.253ns (routing 0.763ns, distribution 1.490ns)
  Clock Net Delay (Destination): 2.244ns (routing 1.352ns, distribution 0.892ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       2.253     2.479    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/c_clk_i
    SLICE_X74Y141        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/clr_fifo_req_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X74Y141        FDCE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     2.558 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/clr_fifo_req_reg/Q
                         net (fo=5, routed)           0.391     2.949    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/clr_fifo_req
    SLICE_X74Y141        LUT3 (Prop_C5LUT_SLICEL_I1_O)
                                                      0.110     3.059 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/t_fifo_trig_empty_inferred_i_4/O
                         net (fo=2, routed)           0.253     3.312    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/gcc_rd_ptr/trig_pop_r_reg[0][0]
    SLICE_X76Y143        LUT5 (Prop_D6LUT_SLICEM_I0_O)
                                                      0.037     3.349 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/gcc_rd_ptr/trig_pop_r[0]_i_2/O
                         net (fo=1, routed)           0.195     3.544    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].ADDSUB_MACRO_inst/trig_pop_r_reg[0]_0
    SLICE_X75Y140        LUT5 (Prop_D5LUT_SLICEM_I4_O)
                                                      0.066     3.610 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].ADDSUB_MACRO_inst/trig_pop_r[0]_i_1/O
                         net (fo=2, routed)           0.186     3.796    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/gcc_rd_ptr/trig_pop
    SLICE_X75Y141        LUT5 (Prop_G6LUT_SLICEM_I4_O)
                                                      0.052     3.848 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/gcc_rd_ptr/count_gray_r[8]_i_1__3/O
                         net (fo=18, routed)          0.334     4.183    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/gcc_rd_ptr/count_bin_2r
    SLICE_X77Y138        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/gcc_rd_ptr/count_gray_r_reg[1]/CE
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=5276, routed)        2.244     2.765    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/gcc_rd_ptr/t_clk_i
    SLICE_X77Y138        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/gcc_rd_ptr/count_gray_r_reg[1]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/dac0_done_i_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac0_done_i/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.759ns  (logic 0.038ns (5.007%)  route 0.721ns (94.993%))
  Logic Levels:           0  
  Clock Path Skew:        0.668ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.178ns
    Source Clock Delay      (SCD):    1.510ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.390ns (routing 0.414ns, distribution 0.976ns)
  Clock Net Delay (Destination): 1.730ns (routing 0.900ns, distribution 0.830ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       1.390     1.510    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/s_axi_aclk
    SLICE_X113Y129       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/dac0_done_i_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X113Y129       FDRE (Prop_BFF_SLICEM_C_Q)
                                                      0.038     1.548 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/dac0_done_i_reg/Q
                         net (fo=1, routed)           0.721     2.269    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac0_done_i/src_in
    SLICE_X117Y270       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac0_done_i/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=5276, routed)        1.730     2.178    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac0_done_i/dest_clk
    SLICE_X117Y270       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac0_done_i/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[4]/C
                            (rising edge-triggered cell FDCE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/wr_gptr_cdc_reg[4]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.100ns  (logic 0.039ns (38.817%)  route 0.061ns (61.183%))
  Logic Levels:           0  
  Clock Path Skew:        0.632ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.981ns
    Source Clock Delay      (SCD):    1.350ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.230ns (routing 0.414ns, distribution 0.816ns)
  Clock Net Delay (Destination): 1.533ns (routing 0.900ns, distribution 0.633ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       1.230     1.350    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_wr_ptr/c_clk_i
    SLICE_X74Y144        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X74Y144        FDCE (Prop_DFF_SLICEL_C_Q)
                                                      0.039     1.389 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[4]/Q
                         net (fo=2, routed)           0.061     1.450    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/wr_gptr[4]
    SLICE_X74Y146        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/wr_gptr_cdc_reg[4]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=5276, routed)        1.533     1.981    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/t_clk_i
    SLICE_X74Y146        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/wr_gptr_cdc_reg[4]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].trig_fifo_inst/clr_fifo_req_reg/C
                            (rising edge-triggered cell FDCE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].trig_fifo_inst/gcc_rd_ptr/clear_cdc_reg/D
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.107ns  (logic 0.038ns (35.499%)  route 0.069ns (64.501%))
  Logic Levels:           0  
  Clock Path Skew:        0.631ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.974ns
    Source Clock Delay      (SCD):    1.343ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.223ns (routing 0.414ns, distribution 0.809ns)
  Clock Net Delay (Destination): 1.526ns (routing 0.900ns, distribution 0.626ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       1.223     1.343    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].trig_fifo_inst/c_clk_i
    SLICE_X72Y148        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].trig_fifo_inst/clr_fifo_req_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X72Y148        FDCE (Prop_AFF_SLICEM_C_Q)
                                                      0.038     1.381 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].trig_fifo_inst/clr_fifo_req_reg/Q
                         net (fo=5, routed)           0.069     1.450    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].trig_fifo_inst/gcc_rd_ptr/clr_fifo_req
    SLICE_X72Y148        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].trig_fifo_inst/gcc_rd_ptr/clear_cdc_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=5276, routed)        1.526     1.974    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].trig_fifo_inst/gcc_rd_ptr/t_clk_i
    SLICE_X72Y148        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].trig_fifo_inst/gcc_rd_ptr/clear_cdc_reg/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[2]/C
                            (rising edge-triggered cell FDCE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/wr_gptr_cdc_reg[2]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.106ns  (logic 0.039ns (36.903%)  route 0.067ns (63.097%))
  Logic Levels:           0  
  Clock Path Skew:        0.627ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.984ns
    Source Clock Delay      (SCD):    1.358ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.238ns (routing 0.414ns, distribution 0.824ns)
  Clock Net Delay (Destination): 1.536ns (routing 0.900ns, distribution 0.636ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       1.238     1.358    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_wr_ptr/c_clk_i
    SLICE_X75Y143        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X75Y143        FDCE (Prop_HFF_SLICEM_C_Q)
                                                      0.039     1.397 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[2]/Q
                         net (fo=2, routed)           0.067     1.463    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/wr_gptr[2]
    SLICE_X75Y144        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/wr_gptr_cdc_reg[2]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=5276, routed)        1.536     1.984    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/t_clk_i
    SLICE_X75Y144        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/wr_gptr_cdc_reg[2]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[0]/C
                            (rising edge-triggered cell FDCE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/wr_gptr_cdc_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.110ns  (logic 0.039ns (35.557%)  route 0.071ns (64.443%))
  Logic Levels:           0  
  Clock Path Skew:        0.629ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.986ns
    Source Clock Delay      (SCD):    1.358ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.238ns (routing 0.414ns, distribution 0.824ns)
  Clock Net Delay (Destination): 1.538ns (routing 0.900ns, distribution 0.638ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       1.238     1.358    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_wr_ptr/c_clk_i
    SLICE_X75Y143        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X75Y143        FDCE (Prop_HFF2_SLICEM_C_Q)
                                                      0.039     1.397 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[0]/Q
                         net (fo=2, routed)           0.071     1.467    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/wr_gptr[0]
    SLICE_X75Y144        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/wr_gptr_cdc_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=5276, routed)        1.538     1.986    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/t_clk_i
    SLICE_X75Y144        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/wr_gptr_cdc_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[0].wave_fifo_inst/clr_fifo_req_reg/C
                            (rising edge-triggered cell FDCE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[0].wave_fifo_inst/gcc_rd_ptr/clear_cdc_reg/D
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.128ns  (logic 0.039ns (30.382%)  route 0.089ns (69.618%))
  Logic Levels:           0  
  Clock Path Skew:        0.635ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.982ns
    Source Clock Delay      (SCD):    1.347ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.227ns (routing 0.414ns, distribution 0.813ns)
  Clock Net Delay (Destination): 1.534ns (routing 0.900ns, distribution 0.634ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       1.227     1.347    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[0].wave_fifo_inst/c_clk_i
    SLICE_X71Y133        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[0].wave_fifo_inst/clr_fifo_req_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X71Y133        FDCE (Prop_HFF2_SLICEL_C_Q)
                                                      0.039     1.386 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[0].wave_fifo_inst/clr_fifo_req_reg/Q
                         net (fo=5, routed)           0.089     1.475    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[0].wave_fifo_inst/gcc_rd_ptr/clr_fifo_req
    SLICE_X71Y135        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[0].wave_fifo_inst/gcc_rd_ptr/clear_cdc_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=5276, routed)        1.534     1.982    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[0].wave_fifo_inst/gcc_rd_ptr/t_clk_i
    SLICE_X71Y135        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[0].wave_fifo_inst/gcc_rd_ptr/clear_cdc_reg/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/clr_fifo_req_reg/C
                            (rising edge-triggered cell FDCE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_rd_ptr/clear_cdc_reg/D
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.123ns  (logic 0.039ns (31.785%)  route 0.084ns (68.215%))
  Logic Levels:           0  
  Clock Path Skew:        0.625ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.980ns
    Source Clock Delay      (SCD):    1.355ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.235ns (routing 0.414ns, distribution 0.821ns)
  Clock Net Delay (Destination): 1.532ns (routing 0.900ns, distribution 0.632ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       1.235     1.355    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/c_clk_i
    SLICE_X74Y141        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/clr_fifo_req_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X74Y141        FDCE (Prop_FFF_SLICEL_C_Q)
                                                      0.039     1.394 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/clr_fifo_req_reg/Q
                         net (fo=5, routed)           0.084     1.477    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_rd_ptr/clr_fifo_req
    SLICE_X74Y142        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_rd_ptr/clear_cdc_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=5276, routed)        1.532     1.980    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_rd_ptr/t_clk_i
    SLICE_X74Y142        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_rd_ptr/clear_cdc_reg/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[4]/C
                            (rising edge-triggered cell FDCE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].trig_fifo_inst/wr_gptr_cdc_reg[4]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.147ns  (logic 0.039ns (26.588%)  route 0.108ns (73.412%))
  Logic Levels:           0  
  Clock Path Skew:        0.631ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.969ns
    Source Clock Delay      (SCD):    1.338ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.218ns (routing 0.414ns, distribution 0.804ns)
  Clock Net Delay (Destination): 1.521ns (routing 0.900ns, distribution 0.621ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       1.218     1.338    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].trig_fifo_inst/gcc_wr_ptr/c_clk_i
    SLICE_X71Y153        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X71Y153        FDCE (Prop_DFF_SLICEL_C_Q)
                                                      0.039     1.377 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[4]/Q
                         net (fo=2, routed)           0.108     1.484    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].trig_fifo_inst/wr_gptr[4]
    SLICE_X73Y153        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].trig_fifo_inst/wr_gptr_cdc_reg[4]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=5276, routed)        1.521     1.969    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].trig_fifo_inst/t_clk_i
    SLICE_X73Y153        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].trig_fifo_inst/wr_gptr_cdc_reg[4]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].trig_fifo_inst/clr_fifo_req_reg/C
                            (rising edge-triggered cell FDCE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].trig_fifo_inst/gcc_rd_ptr/clear_cdc_reg/D
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.146ns  (logic 0.038ns (26.011%)  route 0.108ns (73.989%))
  Logic Levels:           0  
  Clock Path Skew:        0.631ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.971ns
    Source Clock Delay      (SCD):    1.340ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.220ns (routing 0.414ns, distribution 0.806ns)
  Clock Net Delay (Destination): 1.523ns (routing 0.900ns, distribution 0.623ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       1.220     1.340    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].trig_fifo_inst/c_clk_i
    SLICE_X72Y151        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].trig_fifo_inst/clr_fifo_req_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X72Y151        FDCE (Prop_EFF_SLICEM_C_Q)
                                                      0.038     1.378 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].trig_fifo_inst/clr_fifo_req_reg/Q
                         net (fo=5, routed)           0.108     1.486    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].trig_fifo_inst/gcc_rd_ptr/clr_fifo_req
    SLICE_X73Y151        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].trig_fifo_inst/gcc_rd_ptr/clear_cdc_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=5276, routed)        1.523     1.971    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].trig_fifo_inst/gcc_rd_ptr/t_clk_i
    SLICE_X73Y151        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].trig_fifo_inst/gcc_rd_ptr/clear_cdc_reg/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[3]/C
                            (rising edge-triggered cell FDCE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/wr_gptr_cdc_reg[3]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.148ns  (logic 0.039ns (26.408%)  route 0.109ns (73.592%))
  Logic Levels:           0  
  Clock Path Skew:        0.631ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.985ns
    Source Clock Delay      (SCD):    1.354ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.234ns (routing 0.414ns, distribution 0.820ns)
  Clock Net Delay (Destination): 1.537ns (routing 0.900ns, distribution 0.637ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       1.234     1.354    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_wr_ptr/c_clk_i
    SLICE_X74Y143        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X74Y143        FDCE (Prop_DFF_SLICEL_C_Q)
                                                      0.039     1.393 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[3]/Q
                         net (fo=2, routed)           0.109     1.502    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/wr_gptr[3]
    SLICE_X74Y146        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/wr_gptr_cdc_reg[3]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=5276, routed)        1.537     1.985    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/t_clk_i
    SLICE_X74Y146        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/wr_gptr_cdc_reg[3]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  
  To Clock:  clk_out1_d_1_clk_adc0_x2_0

Max Delay             1 Endpoint
Min Delay             1 Endpoint
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/EMIOGPIOO[95]
                            (internal pin)
  Destination:            d_1_i/rst_adc0_x2/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.223ns  (logic 0.158ns (7.107%)  route 2.065ns (92.894%))
  Logic Levels:           1  (LUT1=1)
  Clock Uncertainty:      0.139ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.094ns
    Phase Error              (PE):    0.086ns
  Clock Net Delay (Destination): 2.662ns (routing 1.778ns, distribution 0.884ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    PS8_X0Y0             PS8                          0.000     0.000 f  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/EMIOGPIOO[95]
                         net (fo=4, routed)           2.050     2.050    d_1_i/rst_adc0_x2/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/ext_reset_in
    SLICE_X80Y112        LUT1 (Prop_H5LUT_SLICEL_I0_O)
                                                      0.158     2.208 r  d_1_i/rst_adc0_x2/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1/O
                         net (fo=1, routed)           0.015     2.223    d_1_i/rst_adc0_x2/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/exr_d1
    SLICE_X80Y112        FDRE                                         r  d_1_i/rst_adc0_x2/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y18        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=1, routed)           2.303     2.689    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     3.319 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.216     3.535    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.559 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=1945, routed)        2.662     6.221    d_1_i/rst_adc0_x2/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/slowest_sync_clk
    SLICE_X80Y112        FDRE                                         r  d_1_i/rst_adc0_x2/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/EMIOGPIOO[95]
                            (internal pin)
  Destination:            d_1_i/rst_adc0_x2/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.104ns  (logic 0.058ns (5.253%)  route 1.046ns (94.747%))
  Logic Levels:           1  (LUT1=1)
  Clock Uncertainty:      0.139ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.094ns
    Phase Error              (PE):    0.086ns
  Clock Net Delay (Destination): 1.846ns (routing 1.208ns, distribution 0.638ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    PS8_X0Y0             PS8                          0.000     0.000 f  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/EMIOGPIOO[95]
                         net (fo=4, routed)           1.040     1.040    d_1_i/rst_adc0_x2/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/ext_reset_in
    SLICE_X80Y112        LUT1 (Prop_H5LUT_SLICEL_I0_O)
                                                      0.058     1.098 r  d_1_i/rst_adc0_x2/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1/O
                         net (fo=1, routed)           0.006     1.104    d_1_i/rst_adc0_x2/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/exr_d1
    SLICE_X80Y112        FDRE                                         r  d_1_i/rst_adc0_x2/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y18        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=1, routed)           1.575     1.927    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.632 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.798    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.817 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=1945, routed)        1.846     3.663    d_1_i/rst_adc0_x2/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/slowest_sync_clk
    SLICE_X80Y112        FDRE                                         r  d_1_i/rst_adc0_x2/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  clk_pl_0
  To Clock:  clk_out1_d_1_clk_adc0_x2_0

Max Delay           582 Endpoints
Min Delay           582 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/adc0_done_i_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_adc0_done_i/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.541ns  (logic 0.078ns (14.418%)  route 0.463ns (85.582%))
  Logic Levels:           0  
  Clock Path Skew:        3.711ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    6.453ns
    Source Clock Delay      (SCD):    2.742ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.261ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.343ns
    Phase Error              (PE):    0.086ns
  Clock Net Delay (Source):      2.516ns (routing 0.763ns, distribution 1.753ns)
  Clock Net Delay (Destination): 2.894ns (routing 1.778ns, distribution 1.116ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       2.516     2.742    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/s_axi_aclk
    SLICE_X109Y95        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/adc0_done_i_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X109Y95        FDRE (Prop_DFF_SLICEM_C_Q)
                                                      0.078     2.820 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/adc0_done_i_reg/Q
                         net (fo=1, routed)           0.463     3.283    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_adc0_done_i/src_in
    SLICE_X109Y64        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_adc0_done_i/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y18        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=1, routed)           2.303     2.689    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     3.319 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.216     3.535    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.559 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=1945, routed)        2.894     6.453    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_adc0_done_i/dest_clk
    SLICE_X109Y64        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_adc0_done_i/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/qick_time_tagger_0/inst/AXI_REG/slv_reg1_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[1].TAG_CALC/FSM_onehot_trig_cal_st_reg[3]/D
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        4.922ns  (logic 0.360ns (7.314%)  route 4.562ns (92.686%))
  Logic Levels:           2  (LUT3=1 LUT5=1)
  Clock Path Skew:        3.794ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    6.409ns
    Source Clock Delay      (SCD):    2.615ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.261ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.343ns
    Phase Error              (PE):    0.086ns
  Clock Net Delay (Source):      2.389ns (routing 0.763ns, distribution 1.626ns)
  Clock Net Delay (Destination): 2.850ns (routing 1.778ns, distribution 1.072ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       2.389     2.615    d_1_i/qick_time_tagger_0/inst/AXI_REG/ps_clk
    SLICE_X95Y96         FDRE                                         r  d_1_i/qick_time_tagger_0/inst/AXI_REG/slv_reg1_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X95Y96         FDRE (Prop_HFF2_SLICEL_C_Q)
                                                      0.080     2.695 f  d_1_i/qick_time_tagger_0/inst/AXI_REG/slv_reg1_reg[2]/Q
                         net (fo=190, routed)         2.552     5.247    d_1_i/qick_time_tagger_0/inst/AXI_REG/slv_reg1_reg[9]_0[1]
    SLICE_X70Y170        LUT3 (Prop_D6LUT_SLICEM_I0_O)
                                                      0.122     5.369 f  d_1_i/qick_time_tagger_0/inst/AXI_REG/FSM_onehot_trig_cal_st[3]_i_4__0/O
                         net (fo=2, routed)           1.980     7.349    d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[1].TAG_CALC/p_0_in
    SLICE_X104Y74        LUT5 (Prop_D5LUT_SLICEM_I2_O)
                                                      0.158     7.507 r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[1].TAG_CALC/FSM_onehot_trig_cal_st[3]_i_2__0/O
                         net (fo=1, routed)           0.030     7.537    d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[1].TAG_CALC/trig_calc_st_nxt[3]
    SLICE_X104Y74        FDCE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[1].TAG_CALC/FSM_onehot_trig_cal_st_reg[3]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y18        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=1, routed)           2.303     2.689    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     3.319 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.216     3.535    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.559 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=1945, routed)        2.850     6.409    d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[1].TAG_CALC/adc_clk
    SLICE_X104Y74        FDCE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[1].TAG_CALC/FSM_onehot_trig_cal_st_reg[3]/C

Slack:                    inf
  Source:                 d_1_i/qick_time_tagger_0/inst/AXI_REG/slv_reg1_reg[0]_rep__2/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[1].TAG_CALC/SMP[5].ftr_smp_reg[5][15]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        4.412ns  (logic 0.410ns (9.294%)  route 4.002ns (90.706%))
  Logic Levels:           3  (CARRY8=2 LUT4=1)
  Clock Path Skew:        3.895ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    6.477ns
    Source Clock Delay      (SCD):    2.582ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.261ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.343ns
    Phase Error              (PE):    0.086ns
  Clock Net Delay (Source):      2.356ns (routing 0.763ns, distribution 1.593ns)
  Clock Net Delay (Destination): 2.918ns (routing 1.778ns, distribution 1.140ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       2.356     2.582    d_1_i/qick_time_tagger_0/inst/AXI_REG/ps_clk
    SLICE_X82Y92         FDRE                                         r  d_1_i/qick_time_tagger_0/inst/AXI_REG/slv_reg1_reg[0]_rep__2/C
  -------------------------------------------------------------------    -------------------
    SLICE_X82Y92         FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     2.658 r  d_1_i/qick_time_tagger_0/inst/AXI_REG/slv_reg1_reg[0]_rep__2/Q
                         net (fo=131, routed)         3.801     6.459    d_1_i/qick_time_tagger_0/inst/AXI_REG/slv_reg1_reg[0]_rep__2_n_0
    SLICE_X114Y40        LUT4 (Prop_C5LUT_SLICEL_I3_O)
                                                      0.158     6.617 r  d_1_i/qick_time_tagger_0/inst/AXI_REG/SMP[5].ftr_smp[5][7]_i_3__0/O
                         net (fo=1, routed)           0.149     6.766    d_1_i/qick_time_tagger_0/inst/AXI_REG/SMP[5].ftr_smp[5][7]_i_3__0_n_0
    SLICE_X113Y40        CARRY8 (Prop_CARRY8_SLICEM_DI[6]_CO[7])
                                                      0.060     6.826 r  d_1_i/qick_time_tagger_0/inst/AXI_REG/SMP[5].ftr_smp_reg[5][7]_i_1__0/CO[7]
                         net (fo=1, routed)           0.026     6.852    d_1_i/qick_time_tagger_0/inst/AXI_REG/SMP[5].ftr_smp_reg[5][7]_i_1__0_n_0
    SLICE_X113Y41        CARRY8 (Prop_CARRY8_SLICEM_CI_O[7])
                                                      0.116     6.968 r  d_1_i/qick_time_tagger_0/inst/AXI_REG/SMP[5].ftr_smp_reg[5][15]_i_1__0/O[7]
                         net (fo=1, routed)           0.026     6.994    d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[1].TAG_CALC/SMP[5].ftr_smp_reg[5][16]_0[15]
    SLICE_X113Y41        FDRE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[1].TAG_CALC/SMP[5].ftr_smp_reg[5][15]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y18        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=1, routed)           2.303     2.689    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     3.319 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.216     3.535    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.559 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=1945, routed)        2.918     6.477    d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[1].TAG_CALC/adc_clk
    SLICE_X113Y41        FDRE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[1].TAG_CALC/SMP[5].ftr_smp_reg[5][15]/C

Slack:                    inf
  Source:                 d_1_i/qick_time_tagger_0/inst/AXI_REG/slv_reg1_reg[0]_rep__2/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[1].TAG_CALC/SMP[5].ftr_smp_reg[5][13]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        4.411ns  (logic 0.410ns (9.296%)  route 4.001ns (90.704%))
  Logic Levels:           3  (CARRY8=2 LUT4=1)
  Clock Path Skew:        3.895ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    6.477ns
    Source Clock Delay      (SCD):    2.582ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.261ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.343ns
    Phase Error              (PE):    0.086ns
  Clock Net Delay (Source):      2.356ns (routing 0.763ns, distribution 1.593ns)
  Clock Net Delay (Destination): 2.918ns (routing 1.778ns, distribution 1.140ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       2.356     2.582    d_1_i/qick_time_tagger_0/inst/AXI_REG/ps_clk
    SLICE_X82Y92         FDRE                                         r  d_1_i/qick_time_tagger_0/inst/AXI_REG/slv_reg1_reg[0]_rep__2/C
  -------------------------------------------------------------------    -------------------
    SLICE_X82Y92         FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     2.658 r  d_1_i/qick_time_tagger_0/inst/AXI_REG/slv_reg1_reg[0]_rep__2/Q
                         net (fo=131, routed)         3.801     6.459    d_1_i/qick_time_tagger_0/inst/AXI_REG/slv_reg1_reg[0]_rep__2_n_0
    SLICE_X114Y40        LUT4 (Prop_C5LUT_SLICEL_I3_O)
                                                      0.158     6.617 r  d_1_i/qick_time_tagger_0/inst/AXI_REG/SMP[5].ftr_smp[5][7]_i_3__0/O
                         net (fo=1, routed)           0.149     6.766    d_1_i/qick_time_tagger_0/inst/AXI_REG/SMP[5].ftr_smp[5][7]_i_3__0_n_0
    SLICE_X113Y40        CARRY8 (Prop_CARRY8_SLICEM_DI[6]_CO[7])
                                                      0.060     6.826 r  d_1_i/qick_time_tagger_0/inst/AXI_REG/SMP[5].ftr_smp_reg[5][7]_i_1__0/CO[7]
                         net (fo=1, routed)           0.026     6.852    d_1_i/qick_time_tagger_0/inst/AXI_REG/SMP[5].ftr_smp_reg[5][7]_i_1__0_n_0
    SLICE_X113Y41        CARRY8 (Prop_CARRY8_SLICEM_CI_O[5])
                                                      0.116     6.968 r  d_1_i/qick_time_tagger_0/inst/AXI_REG/SMP[5].ftr_smp_reg[5][15]_i_1__0/O[5]
                         net (fo=1, routed)           0.025     6.993    d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[1].TAG_CALC/SMP[5].ftr_smp_reg[5][16]_0[13]
    SLICE_X113Y41        FDRE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[1].TAG_CALC/SMP[5].ftr_smp_reg[5][13]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y18        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=1, routed)           2.303     2.689    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     3.319 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.216     3.535    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.559 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=1945, routed)        2.918     6.477    d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[1].TAG_CALC/adc_clk
    SLICE_X113Y41        FDRE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[1].TAG_CALC/SMP[5].ftr_smp_reg[5][13]/C

Slack:                    inf
  Source:                 d_1_i/qick_time_tagger_0/inst/AXI_REG/slv_reg1_reg[0]_rep__2/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[1].TAG_CALC/SMP[5].ftr_smp_reg[5][14]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        4.399ns  (logic 0.397ns (9.026%)  route 4.002ns (90.974%))
  Logic Levels:           3  (CARRY8=2 LUT4=1)
  Clock Path Skew:        3.895ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    6.477ns
    Source Clock Delay      (SCD):    2.582ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.261ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.343ns
    Phase Error              (PE):    0.086ns
  Clock Net Delay (Source):      2.356ns (routing 0.763ns, distribution 1.593ns)
  Clock Net Delay (Destination): 2.918ns (routing 1.778ns, distribution 1.140ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       2.356     2.582    d_1_i/qick_time_tagger_0/inst/AXI_REG/ps_clk
    SLICE_X82Y92         FDRE                                         r  d_1_i/qick_time_tagger_0/inst/AXI_REG/slv_reg1_reg[0]_rep__2/C
  -------------------------------------------------------------------    -------------------
    SLICE_X82Y92         FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     2.658 r  d_1_i/qick_time_tagger_0/inst/AXI_REG/slv_reg1_reg[0]_rep__2/Q
                         net (fo=131, routed)         3.801     6.459    d_1_i/qick_time_tagger_0/inst/AXI_REG/slv_reg1_reg[0]_rep__2_n_0
    SLICE_X114Y40        LUT4 (Prop_C5LUT_SLICEL_I3_O)
                                                      0.158     6.617 r  d_1_i/qick_time_tagger_0/inst/AXI_REG/SMP[5].ftr_smp[5][7]_i_3__0/O
                         net (fo=1, routed)           0.149     6.766    d_1_i/qick_time_tagger_0/inst/AXI_REG/SMP[5].ftr_smp[5][7]_i_3__0_n_0
    SLICE_X113Y40        CARRY8 (Prop_CARRY8_SLICEM_DI[6]_CO[7])
                                                      0.060     6.826 r  d_1_i/qick_time_tagger_0/inst/AXI_REG/SMP[5].ftr_smp_reg[5][7]_i_1__0/CO[7]
                         net (fo=1, routed)           0.026     6.852    d_1_i/qick_time_tagger_0/inst/AXI_REG/SMP[5].ftr_smp_reg[5][7]_i_1__0_n_0
    SLICE_X113Y41        CARRY8 (Prop_CARRY8_SLICEM_CI_O[6])
                                                      0.103     6.955 r  d_1_i/qick_time_tagger_0/inst/AXI_REG/SMP[5].ftr_smp_reg[5][15]_i_1__0/O[6]
                         net (fo=1, routed)           0.026     6.981    d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[1].TAG_CALC/SMP[5].ftr_smp_reg[5][16]_0[14]
    SLICE_X113Y41        FDRE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[1].TAG_CALC/SMP[5].ftr_smp_reg[5][14]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y18        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=1, routed)           2.303     2.689    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     3.319 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.216     3.535    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.559 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=1945, routed)        2.918     6.477    d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[1].TAG_CALC/adc_clk
    SLICE_X113Y41        FDRE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[1].TAG_CALC/SMP[5].ftr_smp_reg[5][14]/C

Slack:                    inf
  Source:                 d_1_i/qick_time_tagger_0/inst/AXI_REG/slv_reg1_reg[0]_rep__2/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[1].TAG_CALC/SMP[5].ftr_smp_reg[5][16]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        4.392ns  (logic 0.365ns (8.311%)  route 4.027ns (91.689%))
  Logic Levels:           4  (CARRY8=3 LUT4=1)
  Clock Path Skew:        3.892ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    6.474ns
    Source Clock Delay      (SCD):    2.582ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.261ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.343ns
    Phase Error              (PE):    0.086ns
  Clock Net Delay (Source):      2.356ns (routing 0.763ns, distribution 1.593ns)
  Clock Net Delay (Destination): 2.915ns (routing 1.778ns, distribution 1.137ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       2.356     2.582    d_1_i/qick_time_tagger_0/inst/AXI_REG/ps_clk
    SLICE_X82Y92         FDRE                                         r  d_1_i/qick_time_tagger_0/inst/AXI_REG/slv_reg1_reg[0]_rep__2/C
  -------------------------------------------------------------------    -------------------
    SLICE_X82Y92         FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     2.658 r  d_1_i/qick_time_tagger_0/inst/AXI_REG/slv_reg1_reg[0]_rep__2/Q
                         net (fo=131, routed)         3.801     6.459    d_1_i/qick_time_tagger_0/inst/AXI_REG/slv_reg1_reg[0]_rep__2_n_0
    SLICE_X114Y40        LUT4 (Prop_C5LUT_SLICEL_I3_O)
                                                      0.158     6.617 r  d_1_i/qick_time_tagger_0/inst/AXI_REG/SMP[5].ftr_smp[5][7]_i_3__0/O
                         net (fo=1, routed)           0.149     6.766    d_1_i/qick_time_tagger_0/inst/AXI_REG/SMP[5].ftr_smp[5][7]_i_3__0_n_0
    SLICE_X113Y40        CARRY8 (Prop_CARRY8_SLICEM_DI[6]_CO[7])
                                                      0.060     6.826 r  d_1_i/qick_time_tagger_0/inst/AXI_REG/SMP[5].ftr_smp_reg[5][7]_i_1__0/CO[7]
                         net (fo=1, routed)           0.026     6.852    d_1_i/qick_time_tagger_0/inst/AXI_REG/SMP[5].ftr_smp_reg[5][7]_i_1__0_n_0
    SLICE_X113Y41        CARRY8 (Prop_CARRY8_SLICEM_CI_CO[7])
                                                      0.015     6.867 r  d_1_i/qick_time_tagger_0/inst/AXI_REG/SMP[5].ftr_smp_reg[5][15]_i_1__0/CO[7]
                         net (fo=1, routed)           0.026     6.893    d_1_i/qick_time_tagger_0/inst/AXI_REG/SMP[5].ftr_smp_reg[5][15]_i_1__0_n_0
    SLICE_X113Y42        CARRY8 (Prop_CARRY8_SLICEM_CI_O[0])
                                                      0.056     6.949 r  d_1_i/qick_time_tagger_0/inst/AXI_REG/SMP[5].ftr_smp_reg[5][16]_i_1__0/O[0]
                         net (fo=1, routed)           0.025     6.974    d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[1].TAG_CALC/SMP[5].ftr_smp_reg[5][16]_0[16]
    SLICE_X113Y42        FDRE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[1].TAG_CALC/SMP[5].ftr_smp_reg[5][16]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y18        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=1, routed)           2.303     2.689    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     3.319 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.216     3.535    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.559 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=1945, routed)        2.915     6.474    d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[1].TAG_CALC/adc_clk
    SLICE_X113Y42        FDRE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[1].TAG_CALC/SMP[5].ftr_smp_reg[5][16]/C

Slack:                    inf
  Source:                 d_1_i/qick_time_tagger_0/inst/AXI_REG/slv_reg1_reg[0]_rep__2/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[1].TAG_CALC/SMP[5].ftr_smp_reg[5][12]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        4.381ns  (logic 0.380ns (8.675%)  route 4.001ns (91.325%))
  Logic Levels:           3  (CARRY8=2 LUT4=1)
  Clock Path Skew:        3.895ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    6.477ns
    Source Clock Delay      (SCD):    2.582ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.261ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.343ns
    Phase Error              (PE):    0.086ns
  Clock Net Delay (Source):      2.356ns (routing 0.763ns, distribution 1.593ns)
  Clock Net Delay (Destination): 2.918ns (routing 1.778ns, distribution 1.140ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       2.356     2.582    d_1_i/qick_time_tagger_0/inst/AXI_REG/ps_clk
    SLICE_X82Y92         FDRE                                         r  d_1_i/qick_time_tagger_0/inst/AXI_REG/slv_reg1_reg[0]_rep__2/C
  -------------------------------------------------------------------    -------------------
    SLICE_X82Y92         FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     2.658 r  d_1_i/qick_time_tagger_0/inst/AXI_REG/slv_reg1_reg[0]_rep__2/Q
                         net (fo=131, routed)         3.801     6.459    d_1_i/qick_time_tagger_0/inst/AXI_REG/slv_reg1_reg[0]_rep__2_n_0
    SLICE_X114Y40        LUT4 (Prop_C5LUT_SLICEL_I3_O)
                                                      0.158     6.617 r  d_1_i/qick_time_tagger_0/inst/AXI_REG/SMP[5].ftr_smp[5][7]_i_3__0/O
                         net (fo=1, routed)           0.149     6.766    d_1_i/qick_time_tagger_0/inst/AXI_REG/SMP[5].ftr_smp[5][7]_i_3__0_n_0
    SLICE_X113Y40        CARRY8 (Prop_CARRY8_SLICEM_DI[6]_CO[7])
                                                      0.060     6.826 r  d_1_i/qick_time_tagger_0/inst/AXI_REG/SMP[5].ftr_smp_reg[5][7]_i_1__0/CO[7]
                         net (fo=1, routed)           0.026     6.852    d_1_i/qick_time_tagger_0/inst/AXI_REG/SMP[5].ftr_smp_reg[5][7]_i_1__0_n_0
    SLICE_X113Y41        CARRY8 (Prop_CARRY8_SLICEM_CI_O[4])
                                                      0.086     6.938 r  d_1_i/qick_time_tagger_0/inst/AXI_REG/SMP[5].ftr_smp_reg[5][15]_i_1__0/O[4]
                         net (fo=1, routed)           0.025     6.963    d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[1].TAG_CALC/SMP[5].ftr_smp_reg[5][16]_0[12]
    SLICE_X113Y41        FDRE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[1].TAG_CALC/SMP[5].ftr_smp_reg[5][12]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y18        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=1, routed)           2.303     2.689    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     3.319 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.216     3.535    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.559 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=1945, routed)        2.918     6.477    d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[1].TAG_CALC/adc_clk
    SLICE_X113Y41        FDRE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[1].TAG_CALC/SMP[5].ftr_smp_reg[5][12]/C

Slack:                    inf
  Source:                 d_1_i/qick_time_tagger_0/inst/AXI_REG/slv_reg1_reg[0]_rep__2/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[1].TAG_CALC/SMP[5].ftr_smp_reg[5][11]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        4.378ns  (logic 0.376ns (8.589%)  route 4.002ns (91.411%))
  Logic Levels:           3  (CARRY8=2 LUT4=1)
  Clock Path Skew:        3.896ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    6.478ns
    Source Clock Delay      (SCD):    2.582ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.261ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.343ns
    Phase Error              (PE):    0.086ns
  Clock Net Delay (Source):      2.356ns (routing 0.763ns, distribution 1.593ns)
  Clock Net Delay (Destination): 2.919ns (routing 1.778ns, distribution 1.141ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       2.356     2.582    d_1_i/qick_time_tagger_0/inst/AXI_REG/ps_clk
    SLICE_X82Y92         FDRE                                         r  d_1_i/qick_time_tagger_0/inst/AXI_REG/slv_reg1_reg[0]_rep__2/C
  -------------------------------------------------------------------    -------------------
    SLICE_X82Y92         FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     2.658 r  d_1_i/qick_time_tagger_0/inst/AXI_REG/slv_reg1_reg[0]_rep__2/Q
                         net (fo=131, routed)         3.801     6.459    d_1_i/qick_time_tagger_0/inst/AXI_REG/slv_reg1_reg[0]_rep__2_n_0
    SLICE_X114Y40        LUT4 (Prop_C5LUT_SLICEL_I3_O)
                                                      0.158     6.617 r  d_1_i/qick_time_tagger_0/inst/AXI_REG/SMP[5].ftr_smp[5][7]_i_3__0/O
                         net (fo=1, routed)           0.149     6.766    d_1_i/qick_time_tagger_0/inst/AXI_REG/SMP[5].ftr_smp[5][7]_i_3__0_n_0
    SLICE_X113Y40        CARRY8 (Prop_CARRY8_SLICEM_DI[6]_CO[7])
                                                      0.060     6.826 r  d_1_i/qick_time_tagger_0/inst/AXI_REG/SMP[5].ftr_smp_reg[5][7]_i_1__0/CO[7]
                         net (fo=1, routed)           0.026     6.852    d_1_i/qick_time_tagger_0/inst/AXI_REG/SMP[5].ftr_smp_reg[5][7]_i_1__0_n_0
    SLICE_X113Y41        CARRY8 (Prop_CARRY8_SLICEM_CI_O[3])
                                                      0.082     6.934 r  d_1_i/qick_time_tagger_0/inst/AXI_REG/SMP[5].ftr_smp_reg[5][15]_i_1__0/O[3]
                         net (fo=1, routed)           0.026     6.960    d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[1].TAG_CALC/SMP[5].ftr_smp_reg[5][16]_0[11]
    SLICE_X113Y41        FDRE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[1].TAG_CALC/SMP[5].ftr_smp_reg[5][11]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y18        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=1, routed)           2.303     2.689    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     3.319 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.216     3.535    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.559 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=1945, routed)        2.919     6.478    d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[1].TAG_CALC/adc_clk
    SLICE_X113Y41        FDRE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[1].TAG_CALC/SMP[5].ftr_smp_reg[5][11]/C

Slack:                    inf
  Source:                 d_1_i/qick_time_tagger_0/inst/AXI_REG/slv_reg1_reg[0]_rep__2/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[1].TAG_CALC/SMP[5].ftr_smp_reg[5][9]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        4.371ns  (logic 0.370ns (8.466%)  route 4.001ns (91.534%))
  Logic Levels:           3  (CARRY8=2 LUT4=1)
  Clock Path Skew:        3.896ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    6.478ns
    Source Clock Delay      (SCD):    2.582ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.261ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.343ns
    Phase Error              (PE):    0.086ns
  Clock Net Delay (Source):      2.356ns (routing 0.763ns, distribution 1.593ns)
  Clock Net Delay (Destination): 2.919ns (routing 1.778ns, distribution 1.141ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       2.356     2.582    d_1_i/qick_time_tagger_0/inst/AXI_REG/ps_clk
    SLICE_X82Y92         FDRE                                         r  d_1_i/qick_time_tagger_0/inst/AXI_REG/slv_reg1_reg[0]_rep__2/C
  -------------------------------------------------------------------    -------------------
    SLICE_X82Y92         FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     2.658 r  d_1_i/qick_time_tagger_0/inst/AXI_REG/slv_reg1_reg[0]_rep__2/Q
                         net (fo=131, routed)         3.801     6.459    d_1_i/qick_time_tagger_0/inst/AXI_REG/slv_reg1_reg[0]_rep__2_n_0
    SLICE_X114Y40        LUT4 (Prop_C5LUT_SLICEL_I3_O)
                                                      0.158     6.617 r  d_1_i/qick_time_tagger_0/inst/AXI_REG/SMP[5].ftr_smp[5][7]_i_3__0/O
                         net (fo=1, routed)           0.149     6.766    d_1_i/qick_time_tagger_0/inst/AXI_REG/SMP[5].ftr_smp[5][7]_i_3__0_n_0
    SLICE_X113Y40        CARRY8 (Prop_CARRY8_SLICEM_DI[6]_CO[7])
                                                      0.060     6.826 r  d_1_i/qick_time_tagger_0/inst/AXI_REG/SMP[5].ftr_smp_reg[5][7]_i_1__0/CO[7]
                         net (fo=1, routed)           0.026     6.852    d_1_i/qick_time_tagger_0/inst/AXI_REG/SMP[5].ftr_smp_reg[5][7]_i_1__0_n_0
    SLICE_X113Y41        CARRY8 (Prop_CARRY8_SLICEM_CI_O[1])
                                                      0.076     6.928 r  d_1_i/qick_time_tagger_0/inst/AXI_REG/SMP[5].ftr_smp_reg[5][15]_i_1__0/O[1]
                         net (fo=1, routed)           0.025     6.953    d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[1].TAG_CALC/SMP[5].ftr_smp_reg[5][16]_0[9]
    SLICE_X113Y41        FDRE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[1].TAG_CALC/SMP[5].ftr_smp_reg[5][9]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y18        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=1, routed)           2.303     2.689    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     3.319 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.216     3.535    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.559 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=1945, routed)        2.919     6.478    d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[1].TAG_CALC/adc_clk
    SLICE_X113Y41        FDRE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[1].TAG_CALC/SMP[5].ftr_smp_reg[5][9]/C

Slack:                    inf
  Source:                 d_1_i/qick_time_tagger_0/inst/AXI_REG/slv_reg1_reg[0]_rep__2/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[1].TAG_CALC/SMP[5].ftr_smp_reg[5][10]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        4.363ns  (logic 0.361ns (8.275%)  route 4.002ns (91.725%))
  Logic Levels:           3  (CARRY8=2 LUT4=1)
  Clock Path Skew:        3.896ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    6.478ns
    Source Clock Delay      (SCD):    2.582ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.261ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.343ns
    Phase Error              (PE):    0.086ns
  Clock Net Delay (Source):      2.356ns (routing 0.763ns, distribution 1.593ns)
  Clock Net Delay (Destination): 2.919ns (routing 1.778ns, distribution 1.141ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       2.356     2.582    d_1_i/qick_time_tagger_0/inst/AXI_REG/ps_clk
    SLICE_X82Y92         FDRE                                         r  d_1_i/qick_time_tagger_0/inst/AXI_REG/slv_reg1_reg[0]_rep__2/C
  -------------------------------------------------------------------    -------------------
    SLICE_X82Y92         FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     2.658 r  d_1_i/qick_time_tagger_0/inst/AXI_REG/slv_reg1_reg[0]_rep__2/Q
                         net (fo=131, routed)         3.801     6.459    d_1_i/qick_time_tagger_0/inst/AXI_REG/slv_reg1_reg[0]_rep__2_n_0
    SLICE_X114Y40        LUT4 (Prop_C5LUT_SLICEL_I3_O)
                                                      0.158     6.617 r  d_1_i/qick_time_tagger_0/inst/AXI_REG/SMP[5].ftr_smp[5][7]_i_3__0/O
                         net (fo=1, routed)           0.149     6.766    d_1_i/qick_time_tagger_0/inst/AXI_REG/SMP[5].ftr_smp[5][7]_i_3__0_n_0
    SLICE_X113Y40        CARRY8 (Prop_CARRY8_SLICEM_DI[6]_CO[7])
                                                      0.060     6.826 r  d_1_i/qick_time_tagger_0/inst/AXI_REG/SMP[5].ftr_smp_reg[5][7]_i_1__0/CO[7]
                         net (fo=1, routed)           0.026     6.852    d_1_i/qick_time_tagger_0/inst/AXI_REG/SMP[5].ftr_smp_reg[5][7]_i_1__0_n_0
    SLICE_X113Y41        CARRY8 (Prop_CARRY8_SLICEM_CI_O[2])
                                                      0.067     6.919 r  d_1_i/qick_time_tagger_0/inst/AXI_REG/SMP[5].ftr_smp_reg[5][15]_i_1__0/O[2]
                         net (fo=1, routed)           0.026     6.945    d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[1].TAG_CALC/SMP[5].ftr_smp_reg[5][16]_0[10]
    SLICE_X113Y41        FDRE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[1].TAG_CALC/SMP[5].ftr_smp_reg[5][10]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y18        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=1, routed)           2.303     2.689    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     3.319 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.216     3.535    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.559 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=1945, routed)        2.919     6.478    d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[1].TAG_CALC/adc_clk
    SLICE_X113Y41        FDRE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_GEN/ADC[1].TAG_CALC/SMP[5].ftr_smp_reg[5][10]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/adc0_done_i_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_adc0_done_i/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.257ns  (logic 0.039ns (15.175%)  route 0.218ns (84.825%))
  Logic Levels:           0  
  Clock Path Skew:        2.316ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.818ns
    Source Clock Delay      (SCD):    1.502ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.261ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.343ns
    Phase Error              (PE):    0.086ns
  Clock Net Delay (Source):      1.382ns (routing 0.414ns, distribution 0.968ns)
  Clock Net Delay (Destination): 2.001ns (routing 1.208ns, distribution 0.793ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       1.382     1.502    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/s_axi_aclk
    SLICE_X109Y95        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/adc0_done_i_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X109Y95        FDRE (Prop_DFF_SLICEM_C_Q)
                                                      0.039     1.541 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/adc0_done_i_reg/Q
                         net (fo=1, routed)           0.218     1.759    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_adc0_done_i/src_in
    SLICE_X109Y64        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_adc0_done_i/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y18        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=1, routed)           1.575     1.927    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.632 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.798    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.817 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=1945, routed)        2.001     3.818    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_adc0_done_i/dest_clk
    SLICE_X109Y64        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_adc0_done_i/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/gcc_rd_ptr/count_gray_2r_reg[3]/C
                            (rising edge-triggered cell FDCE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/rd_gptr_rcd_reg[3]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.099ns  (logic 0.039ns (39.357%)  route 0.060ns (60.643%))
  Logic Levels:           0  
  Clock Path Skew:        2.464ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.738ns
    Source Clock Delay      (SCD):    1.274ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.261ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.343ns
    Phase Error              (PE):    0.086ns
  Clock Net Delay (Source):      1.154ns (routing 0.414ns, distribution 0.740ns)
  Clock Net Delay (Destination): 1.921ns (routing 1.208ns, distribution 0.713ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       1.154     1.274    d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/gcc_rd_ptr/ps_clk
    SLICE_X55Y219        FDCE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/gcc_rd_ptr/count_gray_2r_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X55Y219        FDCE (Prop_CFF_SLICEL_C_Q)
                                                      0.039     1.313 r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/gcc_rd_ptr/count_gray_2r_reg[3]/Q
                         net (fo=2, routed)           0.060     1.373    d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/gcc_rd_ptr_n_7
    SLICE_X55Y219        FDRE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/rd_gptr_rcd_reg[3]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y18        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=1, routed)           1.575     1.927    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.632 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.798    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.817 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=1945, routed)        1.921     3.738    d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/adc_clk
    SLICE_X55Y219        FDRE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/rd_gptr_rcd_reg[3]/C

Slack:                    inf
  Source:                 d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/gcc_rd_ptr/count_gray_2r_reg[1]/C
                            (rising edge-triggered cell FDCE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/rd_gptr_rcd_reg[1]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.133ns  (logic 0.039ns (29.303%)  route 0.094ns (70.697%))
  Logic Levels:           0  
  Clock Path Skew:        2.471ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.745ns
    Source Clock Delay      (SCD):    1.274ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.261ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.343ns
    Phase Error              (PE):    0.086ns
  Clock Net Delay (Source):      1.154ns (routing 0.414ns, distribution 0.740ns)
  Clock Net Delay (Destination): 1.928ns (routing 1.208ns, distribution 0.720ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       1.154     1.274    d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/gcc_rd_ptr/ps_clk
    SLICE_X55Y219        FDCE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/gcc_rd_ptr/count_gray_2r_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X55Y219        FDCE (Prop_DFF_SLICEL_C_Q)
                                                      0.039     1.313 r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/gcc_rd_ptr/count_gray_2r_reg[1]/Q
                         net (fo=2, routed)           0.094     1.407    d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/gcc_rd_ptr_n_9
    SLICE_X55Y216        FDRE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/rd_gptr_rcd_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y18        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=1, routed)           1.575     1.927    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.632 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.798    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.817 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=1945, routed)        1.928     3.745    d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/adc_clk
    SLICE_X55Y216        FDRE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/rd_gptr_rcd_reg[1]/C

Slack:                    inf
  Source:                 d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/gcc_rd_ptr/count_gray_2r_reg[7]/C
                            (rising edge-triggered cell FDCE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/rd_gptr_rcd_reg[7]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.146ns  (logic 0.041ns (28.143%)  route 0.105ns (71.857%))
  Logic Levels:           0  
  Clock Path Skew:        2.475ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.749ns
    Source Clock Delay      (SCD):    1.274ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.261ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.343ns
    Phase Error              (PE):    0.086ns
  Clock Net Delay (Source):      1.154ns (routing 0.414ns, distribution 0.740ns)
  Clock Net Delay (Destination): 1.932ns (routing 1.208ns, distribution 0.724ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       1.154     1.274    d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/gcc_rd_ptr/ps_clk
    SLICE_X56Y220        FDCE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/gcc_rd_ptr/count_gray_2r_reg[7]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X56Y220        FDCE (Prop_DFF2_SLICEM_C_Q)
                                                      0.041     1.315 r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/gcc_rd_ptr/count_gray_2r_reg[7]/Q
                         net (fo=2, routed)           0.105     1.420    d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/gcc_rd_ptr_n_3
    SLICE_X55Y216        FDRE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/rd_gptr_rcd_reg[7]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y18        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=1, routed)           1.575     1.927    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.632 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.798    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.817 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=1945, routed)        1.932     3.749    d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/adc_clk
    SLICE_X55Y216        FDRE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/rd_gptr_rcd_reg[7]/C

Slack:                    inf
  Source:                 d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/gcc_rd_ptr/count_gray_2r_reg[5]/C
                            (rising edge-triggered cell FDCE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/rd_gptr_rcd_reg[5]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.145ns  (logic 0.039ns (26.956%)  route 0.106ns (73.044%))
  Logic Levels:           0  
  Clock Path Skew:        2.463ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.738ns
    Source Clock Delay      (SCD):    1.275ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.261ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.343ns
    Phase Error              (PE):    0.086ns
  Clock Net Delay (Source):      1.155ns (routing 0.414ns, distribution 0.741ns)
  Clock Net Delay (Destination): 1.921ns (routing 1.208ns, distribution 0.713ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       1.155     1.275    d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/gcc_rd_ptr/ps_clk
    SLICE_X55Y220        FDCE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/gcc_rd_ptr/count_gray_2r_reg[5]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X55Y220        FDCE (Prop_DFF_SLICEL_C_Q)
                                                      0.039     1.314 r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/gcc_rd_ptr/count_gray_2r_reg[5]/Q
                         net (fo=2, routed)           0.106     1.420    d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/gcc_rd_ptr_n_5
    SLICE_X55Y219        FDRE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/rd_gptr_rcd_reg[5]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y18        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=1, routed)           1.575     1.927    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.632 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.798    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.817 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=1945, routed)        1.921     3.738    d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/adc_clk
    SLICE_X55Y219        FDRE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/rd_gptr_rcd_reg[5]/C

Slack:                    inf
  Source:                 d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/gcc_rd_ptr/count_gray_2r_reg[4]/C
                            (rising edge-triggered cell FDCE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/rd_gptr_rcd_reg[4]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.159ns  (logic 0.040ns (25.208%)  route 0.119ns (74.792%))
  Logic Levels:           0  
  Clock Path Skew:        2.464ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.738ns
    Source Clock Delay      (SCD):    1.274ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.261ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.343ns
    Phase Error              (PE):    0.086ns
  Clock Net Delay (Source):      1.154ns (routing 0.414ns, distribution 0.740ns)
  Clock Net Delay (Destination): 1.921ns (routing 1.208ns, distribution 0.713ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       1.154     1.274    d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/gcc_rd_ptr/ps_clk
    SLICE_X55Y219        FDCE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/gcc_rd_ptr/count_gray_2r_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X55Y219        FDCE (Prop_CFF2_SLICEL_C_Q)
                                                      0.040     1.314 r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/gcc_rd_ptr/count_gray_2r_reg[4]/Q
                         net (fo=2, routed)           0.119     1.433    d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/gcc_rd_ptr_n_6
    SLICE_X55Y219        FDRE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/rd_gptr_rcd_reg[4]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y18        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=1, routed)           1.575     1.927    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.632 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.798    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.817 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=1945, routed)        1.921     3.738    d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/adc_clk
    SLICE_X55Y219        FDRE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/rd_gptr_rcd_reg[4]/C

Slack:                    inf
  Source:                 d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/gcc_rd_ptr/count_gray_2r_reg[2]/C
                            (rising edge-triggered cell FDCE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/rd_gptr_rcd_reg[2]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.160ns  (logic 0.041ns (25.676%)  route 0.119ns (74.324%))
  Logic Levels:           0  
  Clock Path Skew:        2.475ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.749ns
    Source Clock Delay      (SCD):    1.274ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.261ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.343ns
    Phase Error              (PE):    0.086ns
  Clock Net Delay (Source):      1.154ns (routing 0.414ns, distribution 0.740ns)
  Clock Net Delay (Destination): 1.932ns (routing 1.208ns, distribution 0.724ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       1.154     1.274    d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/gcc_rd_ptr/ps_clk
    SLICE_X55Y219        FDCE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/gcc_rd_ptr/count_gray_2r_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X55Y219        FDCE (Prop_DFF2_SLICEL_C_Q)
                                                      0.041     1.315 r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/gcc_rd_ptr/count_gray_2r_reg[2]/Q
                         net (fo=2, routed)           0.119     1.434    d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/gcc_rd_ptr_n_8
    SLICE_X55Y216        FDRE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/rd_gptr_rcd_reg[2]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y18        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=1, routed)           1.575     1.927    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.632 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.798    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.817 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=1945, routed)        1.932     3.749    d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/adc_clk
    SLICE_X55Y216        FDRE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/rd_gptr_rcd_reg[2]/C

Slack:                    inf
  Source:                 d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/TAG[1].MEM/FIFO_PUSH/gcc_rd_ptr/count_gray_2r_reg[2]/C
                            (rising edge-triggered cell FDCE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/TAG[1].MEM/FIFO_PUSH/rd_gptr_rcd_reg[2]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.101ns  (logic 0.039ns (38.735%)  route 0.062ns (61.265%))
  Logic Levels:           0  
  Clock Path Skew:        2.333ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.672ns
    Source Clock Delay      (SCD):    1.340ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.261ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.343ns
    Phase Error              (PE):    0.086ns
  Clock Net Delay (Source):      1.220ns (routing 0.414ns, distribution 0.806ns)
  Clock Net Delay (Destination): 1.855ns (routing 1.208ns, distribution 0.647ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       1.220     1.340    d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/TAG[1].MEM/FIFO_PUSH/gcc_rd_ptr/ps_clk
    SLICE_X71Y156        FDCE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/TAG[1].MEM/FIFO_PUSH/gcc_rd_ptr/count_gray_2r_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X71Y156        FDCE (Prop_CFF_SLICEL_C_Q)
                                                      0.039     1.379 r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/TAG[1].MEM/FIFO_PUSH/gcc_rd_ptr/count_gray_2r_reg[2]/Q
                         net (fo=2, routed)           0.062     1.440    d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/TAG[1].MEM/FIFO_PUSH/gcc_rd_ptr_n_7
    SLICE_X71Y156        FDRE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/TAG[1].MEM/FIFO_PUSH/rd_gptr_rcd_reg[2]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y18        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=1, routed)           1.575     1.927    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.632 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.798    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.817 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=1945, routed)        1.855     3.672    d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/TAG[1].MEM/FIFO_PUSH/adc_clk
    SLICE_X71Y156        FDRE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/TAG[1].MEM/FIFO_PUSH/rd_gptr_rcd_reg[2]/C

Slack:                    inf
  Source:                 d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/TAG[1].MEM/FIFO_PUSH/gcc_rd_ptr/count_gray_2r_reg[4]/C
                            (rising edge-triggered cell FDCE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/TAG[1].MEM/FIFO_PUSH/rd_gptr_rcd_reg[4]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.106ns  (logic 0.039ns (36.903%)  route 0.067ns (63.097%))
  Logic Levels:           0  
  Clock Path Skew:        2.336ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.675ns
    Source Clock Delay      (SCD):    1.340ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.261ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.343ns
    Phase Error              (PE):    0.086ns
  Clock Net Delay (Source):      1.220ns (routing 0.414ns, distribution 0.806ns)
  Clock Net Delay (Destination): 1.858ns (routing 1.208ns, distribution 0.650ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       1.220     1.340    d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/TAG[1].MEM/FIFO_PUSH/gcc_rd_ptr/ps_clk
    SLICE_X71Y156        FDCE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/TAG[1].MEM/FIFO_PUSH/gcc_rd_ptr/count_gray_2r_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X71Y156        FDCE (Prop_BFF_SLICEL_C_Q)
                                                      0.039     1.379 r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/TAG[1].MEM/FIFO_PUSH/gcc_rd_ptr/count_gray_2r_reg[4]/Q
                         net (fo=2, routed)           0.067     1.445    d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/TAG[1].MEM/FIFO_PUSH/gcc_rd_ptr_n_5
    SLICE_X71Y155        FDRE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/TAG[1].MEM/FIFO_PUSH/rd_gptr_rcd_reg[4]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y18        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=1, routed)           1.575     1.927    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.632 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.798    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.817 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=1945, routed)        1.858     3.675    d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/TAG[1].MEM/FIFO_PUSH/adc_clk
    SLICE_X71Y155        FDRE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/TAG[1].MEM/FIFO_PUSH/rd_gptr_rcd_reg[4]/C

Slack:                    inf
  Source:                 d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/TAG[1].MEM/FIFO_PUSH/gcc_rd_ptr/clear_r_reg/C
                            (rising edge-triggered cell FDCE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/TAG[1].MEM/FIFO_PUSH/clr_rd_rdc_reg/D
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.105ns  (logic 0.038ns (36.300%)  route 0.067ns (63.700%))
  Logic Levels:           0  
  Clock Path Skew:        2.333ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.677ns
    Source Clock Delay      (SCD):    1.344ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.261ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.343ns
    Phase Error              (PE):    0.086ns
  Clock Net Delay (Source):      1.224ns (routing 0.414ns, distribution 0.810ns)
  Clock Net Delay (Destination): 1.860ns (routing 1.208ns, distribution 0.652ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       1.224     1.344    d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/TAG[1].MEM/FIFO_PUSH/gcc_rd_ptr/ps_clk
    SLICE_X70Y159        FDCE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/TAG[1].MEM/FIFO_PUSH/gcc_rd_ptr/clear_r_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X70Y159        FDCE (Prop_AFF_SLICEM_C_Q)
                                                      0.038     1.382 r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/TAG[1].MEM/FIFO_PUSH/gcc_rd_ptr/clear_r_reg/Q
                         net (fo=32, routed)          0.067     1.449    d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/TAG[1].MEM/FIFO_PUSH/clr_rd
    SLICE_X70Y159        FDCE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/TAG[1].MEM/FIFO_PUSH/clr_rd_rdc_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y18        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=1, routed)           1.575     1.927    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.632 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.798    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.817 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=1945, routed)        1.860     3.677    d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/TAG[1].MEM/FIFO_PUSH/adc_clk
    SLICE_X70Y159        FDCE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/TAG[1].MEM/FIFO_PUSH/clr_rd_rdc_reg/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  
  To Clock:  clk_pl_0

Max Delay            97 Endpoints
Min Delay            97 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_DAC3[15]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac13_fifo_irq/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.563ns  (logic 0.000ns (0.000%)  route 2.563ns (100.000%))
  Logic Levels:           0  
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.261ns (routing 0.690ns, distribution 1.571ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_DAC3[15]
                         net (fo=1, routed)           2.563     2.563    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac13_fifo_irq/src_in
    SLICE_X116Y108       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac13_fifo_irq/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       2.261     2.443    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac13_fifo_irq/dest_clk
    SLICE_X116Y108       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac13_fifo_irq/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/EMIOGPIOO[95]
                            (internal pin)
  Destination:            d_1_i/rst_100/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.560ns  (logic 0.150ns (5.859%)  route 2.410ns (94.141%))
  Logic Levels:           1  (LUT1=1)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.026ns (routing 0.690ns, distribution 1.336ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    PS8_X0Y0             PS8                          0.000     0.000 f  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/EMIOGPIOO[95]
                         net (fo=4, routed)           2.050     2.050    d_1_i/rst_100/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/ext_reset_in
    SLICE_X80Y112        LUT1 (Prop_H6LUT_SLICEL_I0_O)
                                                      0.150     2.200 r  d_1_i/rst_100/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1/O
                         net (fo=1, routed)           0.360     2.560    d_1_i/rst_100/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/exr_d1
    SLICE_X80Y95         FDRE                                         r  d_1_i/rst_100/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       2.026     2.208    d_1_i/rst_100/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/slowest_sync_clk
    SLICE_X80Y95         FDRE                                         r  d_1_i/rst_100/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_DAC3[14]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac13_data_irq/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.386ns  (logic 0.000ns (0.000%)  route 2.386ns (100.000%))
  Logic Levels:           0  
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.263ns (routing 0.690ns, distribution 1.573ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_DAC3[14]
                         net (fo=1, routed)           2.386     2.386    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac13_data_irq/src_in
    SLICE_X118Y105       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac13_data_irq/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       2.263     2.445    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac13_data_irq/dest_clk
    SLICE_X118Y105       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac13_data_irq/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_DAC2[14]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac12_data_irq/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.304ns  (logic 0.000ns (0.000%)  route 2.304ns (100.000%))
  Logic Levels:           0  
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.264ns (routing 0.690ns, distribution 1.574ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_DAC2[14]
                         net (fo=1, routed)           2.304     2.304    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac12_data_irq/src_in
    SLICE_X118Y107       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac12_data_irq/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       2.264     2.446    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac12_data_irq/dest_clk
    SLICE_X118Y107       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac12_data_irq/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/STATUS_DAC3[15]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac03_fifo_irq/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.220ns  (logic 0.000ns (0.000%)  route 2.220ns (100.000%))
  Logic Levels:           0  
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.271ns (routing 0.690ns, distribution 1.581ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/STATUS_DAC3[15]
                         net (fo=1, routed)           2.220     2.220    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac03_fifo_irq/src_in
    SLICE_X117Y106       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac03_fifo_irq/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       2.271     2.453    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac03_fifo_irq/dest_clk
    SLICE_X117Y106       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac03_fifo_irq/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_DAC2[15]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac12_fifo_irq/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.090ns  (logic 0.000ns (0.000%)  route 2.090ns (100.000%))
  Logic Levels:           0  
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.265ns (routing 0.690ns, distribution 1.575ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_DAC2[15]
                         net (fo=1, routed)           2.090     2.090    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac12_fifo_irq/src_in
    SLICE_X118Y108       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac12_fifo_irq/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       2.265     2.447    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac12_fifo_irq/dest_clk
    SLICE_X118Y108       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac12_fifo_irq/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_DAC0[15]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac10_fifo_irq/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.089ns  (logic 0.000ns (0.000%)  route 2.089ns (100.000%))
  Logic Levels:           0  
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.267ns (routing 0.690ns, distribution 1.577ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_DAC0[15]
                         net (fo=1, routed)           2.089     2.089    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac10_fifo_irq/src_in
    SLICE_X114Y116       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac10_fifo_irq/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       2.267     2.449    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac10_fifo_irq/dest_clk
    SLICE_X114Y116       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac10_fifo_irq/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_DAC1[14]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac11_data_irq/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.065ns  (logic 0.000ns (0.000%)  route 2.065ns (100.000%))
  Logic Levels:           0  
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.270ns (routing 0.690ns, distribution 1.580ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_DAC1[14]
                         net (fo=1, routed)           2.065     2.065    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac11_data_irq/src_in
    SLICE_X115Y106       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac11_data_irq/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       2.270     2.452    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac11_data_irq/dest_clk
    SLICE_X115Y106       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac11_data_irq/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_DAC1[15]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac11_fifo_irq/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.057ns  (logic 0.000ns (0.000%)  route 2.057ns (100.000%))
  Logic Levels:           0  
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.260ns (routing 0.690ns, distribution 1.570ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_DAC1[15]
                         net (fo=1, routed)           2.057     2.057    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac11_fifo_irq/src_in
    SLICE_X117Y104       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac11_fifo_irq/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       2.260     2.442    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac11_fifo_irq/dest_clk
    SLICE_X117Y104       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac11_fifo_irq/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[1]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac1_supplies_up_i/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.000ns  (logic 0.000ns (0.000%)  route 2.000ns (100.000%))
  Logic Levels:           0  
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.261ns (routing 0.690ns, distribution 1.571ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[1]
                         net (fo=2, routed)           2.000     2.000    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac1_supplies_up_i/src_in
    SLICE_X110Y121       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac1_supplies_up_i/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       2.261     2.443    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac1_supplies_up_i/dest_clk
    SLICE_X110Y121       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac1_supplies_up_i/syncstages_ff_reg[0]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_ADC1[3]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc11_over_range/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.130ns  (logic 0.000ns (0.000%)  route 0.130ns (100.000%))
  Logic Levels:           0  
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.567ns (routing 0.463ns, distribution 1.104ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_ADC1[3]
                         net (fo=1, routed)           0.130     0.130    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc11_over_range/src_in
    SLICE_X117Y73        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc11_over_range/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       1.567     1.714    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc11_over_range/dest_clk
    SLICE_X117Y73        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc11_over_range/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_ADC1[15]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc11_fifo_irq/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.138ns  (logic 0.000ns (0.000%)  route 0.138ns (100.000%))
  Logic Levels:           0  
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.566ns (routing 0.463ns, distribution 1.103ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_ADC1[15]
                         net (fo=1, routed)           0.138     0.138    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc11_fifo_irq/src_in
    SLICE_X118Y82        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc11_fifo_irq/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       1.566     1.713    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc11_fifo_irq/dest_clk
    SLICE_X118Y82        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc11_fifo_irq/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_ADC1[14]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc11_data_irq/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.160ns  (logic 0.000ns (0.000%)  route 0.160ns (100.000%))
  Logic Levels:           0  
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.563ns (routing 0.463ns, distribution 1.100ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_ADC1[14]
                         net (fo=1, routed)           0.160     0.160    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc11_data_irq/src_in
    SLICE_X117Y82        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc11_data_irq/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       1.563     1.710    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc11_data_irq/dest_clk
    SLICE_X117Y82        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc11_data_irq/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_ADC1[2]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc11_over_vol/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.178ns  (logic 0.000ns (0.000%)  route 0.178ns (100.000%))
  Logic Levels:           0  
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.570ns (routing 0.463ns, distribution 1.107ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_ADC1[2]
                         net (fo=1, routed)           0.178     0.178    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc11_over_vol/src_in
    SLICE_X118Y75        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc11_over_vol/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       1.570     1.717    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc11_over_vol/dest_clk
    SLICE_X118Y75        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc11_over_vol/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_ADC2[15]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc12_fifo_irq/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.194ns  (logic 0.000ns (0.000%)  route 0.194ns (100.000%))
  Logic Levels:           0  
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.554ns (routing 0.463ns, distribution 1.091ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_ADC2[15]
                         net (fo=1, routed)           0.194     0.194    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc12_fifo_irq/src_in
    SLICE_X118Y90        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc12_fifo_irq/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       1.554     1.701    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc12_fifo_irq/dest_clk
    SLICE_X118Y90        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc12_fifo_irq/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_ADC0[15]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc10_fifo_irq/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.204ns  (logic 0.000ns (0.000%)  route 0.204ns (100.000%))
  Logic Levels:           0  
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.568ns (routing 0.463ns, distribution 1.105ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_ADC0[15]
                         net (fo=1, routed)           0.204     0.204    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc10_fifo_irq/src_in
    SLICE_X118Y79        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc10_fifo_irq/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       1.568     1.715    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc10_fifo_irq/dest_clk
    SLICE_X118Y79        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc10_fifo_irq/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_ADC3[3]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc13_over_range/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.221ns  (logic 0.000ns (0.000%)  route 0.221ns (100.000%))
  Logic Levels:           0  
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.558ns (routing 0.463ns, distribution 1.095ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_ADC3[3]
                         net (fo=1, routed)           0.221     0.221    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc13_over_range/src_in
    SLICE_X117Y94        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc13_over_range/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       1.558     1.705    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc13_over_range/dest_clk
    SLICE_X117Y94        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc13_over_range/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_ADC2[2]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc12_over_vol/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.223ns  (logic 0.000ns (0.000%)  route 0.223ns (100.000%))
  Logic Levels:           0  
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.563ns (routing 0.463ns, distribution 1.100ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_ADC2[2]
                         net (fo=1, routed)           0.223     0.223    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc12_over_vol/src_in
    SLICE_X118Y86        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc12_over_vol/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       1.563     1.710    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc12_over_vol/dest_clk
    SLICE_X118Y86        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc12_over_vol/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_ADC2[3]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc12_over_range/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.230ns  (logic 0.000ns (0.000%)  route 0.230ns (100.000%))
  Logic Levels:           0  
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.555ns (routing 0.463ns, distribution 1.092ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_ADC2[3]
                         net (fo=1, routed)           0.230     0.230    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc12_over_range/src_in
    SLICE_X117Y90        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc12_over_range/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       1.555     1.702    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc12_over_range/dest_clk
    SLICE_X117Y90        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc12_over_range/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_ADC0[14]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc10_data_irq/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.233ns  (logic 0.000ns (0.000%)  route 0.233ns (100.000%))
  Logic Levels:           0  
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.564ns (routing 0.463ns, distribution 1.101ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_ADC0[14]
                         net (fo=1, routed)           0.233     0.233    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc10_data_irq/src_in
    SLICE_X117Y80        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc10_data_irq/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       1.564     1.711    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc10_data_irq/dest_clk
    SLICE_X117Y80        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc10_data_irq/syncstages_ff_reg[0]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  RFADC0_CLK
  To Clock:  clk_pl_0

Max Delay             8 Endpoints
Min Delay             8 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC0_CLK  {rise@0.000ns fall@3.906ns period=7.812ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.934ns  (logic 1.218ns (41.513%)  route 1.716ns (58.487%))
  Logic Levels:           4  (LUT4=1 LUT6=3)
  Clock Path Skew:        2.443ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.443ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.261ns (routing 0.690ns, distribution 1.571ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[8])
                                                      0.788     0.788 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/STATUS_COMMON[8]
                         net (fo=1, routed)           0.983     1.771    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_19_0[8]
    SLICE_X112Y89        LUT4 (Prop_E6LUT_SLICEM_I3_O)
                                                      0.148     1.919 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_18/O
                         net (fo=1, routed)           0.219     2.138    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_18_n_0
    SLICE_X111Y95        LUT6 (Prop_C6LUT_SLICEL_I2_O)
                                                      0.096     2.234 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_11/O
                         net (fo=1, routed)           0.219     2.453    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_11_n_0
    SLICE_X115Y97        LUT6 (Prop_C6LUT_SLICEM_I0_O)
                                                      0.098     2.551 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_5/O
                         net (fo=1, routed)           0.229     2.780    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_5_n_0
    SLICE_X110Y99        LUT6 (Prop_C6LUT_SLICEM_I4_O)
                                                      0.088     2.868 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_1/O
                         net (fo=1, routed)           0.066     2.934    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_76
    SLICE_X110Y99        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       2.261     2.443    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X110Y99        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC0_CLK  {rise@0.000ns fall@3.906ns period=7.812ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.806ns  (logic 1.217ns (43.371%)  route 1.589ns (56.629%))
  Logic Levels:           4  (LUT4=1 LUT6=3)
  Clock Path Skew:        2.424ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.424ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.242ns (routing 0.690ns, distribution 1.552ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[13])
                                                      0.771     0.771 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/STATUS_COMMON[13]
                         net (fo=1, routed)           0.840     1.611    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_19_0[11]
    SLICE_X111Y87        LUT4 (Prop_G6LUT_SLICEL_I3_O)
                                                      0.123     1.734 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_31/O
                         net (fo=1, routed)           0.095     1.829    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_31_n_0
    SLICE_X111Y89        LUT6 (Prop_G6LUT_SLICEL_I0_O)
                                                      0.089     1.918 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_14/O
                         net (fo=1, routed)           0.313     2.231    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_14_n_0
    SLICE_X114Y96        LUT6 (Prop_D6LUT_SLICEL_I0_O)
                                                      0.146     2.377 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_5/O
                         net (fo=1, routed)           0.269     2.646    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_5_n_0
    SLICE_X109Y97        LUT6 (Prop_D6LUT_SLICEM_I4_O)
                                                      0.088     2.734 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_1/O
                         net (fo=1, routed)           0.072     2.806    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_71
    SLICE_X109Y97        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       2.242     2.424    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X109Y97        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC0_CLK  {rise@0.000ns fall@3.906ns period=7.812ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.806ns  (logic 0.922ns (32.858%)  route 1.884ns (67.142%))
  Logic Levels:           5  (LUT3=1 LUT6=4)
  Clock Path Skew:        2.435ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.435ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.253ns (routing 0.690ns, distribution 1.563ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[11])
                                                      0.588     0.588 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/STATUS_COMMON[11]
                         net (fo=1, routed)           0.773     1.361    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/adc0_common_stat[11]
    SLICE_X110Y85        LUT3 (Prop_H5LUT_SLICEM_I0_O)
                                                      0.096     1.457 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/IP2Bus_Data[11]_i_33/O
                         net (fo=1, routed)           0.172     1.629    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_13_0
    SLICE_X110Y86        LUT6 (Prop_G6LUT_SLICEM_I1_O)
                                                      0.037     1.666 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_22/O
                         net (fo=1, routed)           0.369     2.035    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_22_n_0
    SLICE_X111Y96        LUT6 (Prop_H6LUT_SLICEL_I3_O)
                                                      0.051     2.086 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_13/O
                         net (fo=1, routed)           0.197     2.283    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_13_n_0
    SLICE_X113Y97        LUT6 (Prop_E6LUT_SLICEM_I0_O)
                                                      0.100     2.383 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_5/O
                         net (fo=1, routed)           0.324     2.707    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_5_n_0
    SLICE_X111Y100       LUT6 (Prop_D6LUT_SLICEL_I4_O)
                                                      0.050     2.757 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_1/O
                         net (fo=1, routed)           0.049     2.806    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_73
    SLICE_X111Y100       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       2.253     2.435    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X111Y100       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC0_CLK  {rise@0.000ns fall@3.906ns period=7.812ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.601ns  (logic 1.130ns (43.445%)  route 1.471ns (56.555%))
  Logic Levels:           5  (LUT3=1 LUT6=4)
  Clock Path Skew:        2.439ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.439ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.257ns (routing 0.690ns, distribution 1.567ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[10])
                                                      0.536     0.536 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/STATUS_COMMON[10]
                         net (fo=1, routed)           0.846     1.382    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/adc0_common_stat[10]
    SLICE_X110Y85        LUT3 (Prop_H6LUT_SLICEM_I0_O)
                                                      0.152     1.534 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/IP2Bus_Data[10]_i_29/O
                         net (fo=1, routed)           0.119     1.653    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_12_0
    SLICE_X110Y86        LUT6 (Prop_H6LUT_SLICEM_I0_O)
                                                      0.152     1.805 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_19/O
                         net (fo=1, routed)           0.262     2.067    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_19_n_0
    SLICE_X110Y96        LUT6 (Prop_H6LUT_SLICEM_I3_O)
                                                      0.053     2.120 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_12/O
                         net (fo=1, routed)           0.103     2.223    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_12_n_0
    SLICE_X111Y97        LUT6 (Prop_G6LUT_SLICEL_I0_O)
                                                      0.149     2.372 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_5/O
                         net (fo=1, routed)           0.091     2.463    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_5_n_0
    SLICE_X111Y99        LUT6 (Prop_C6LUT_SLICEL_I4_O)
                                                      0.088     2.551 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_1/O
                         net (fo=1, routed)           0.050     2.601    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_74
    SLICE_X111Y99        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       2.257     2.439    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X111Y99        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC0_CLK  {rise@0.000ns fall@3.906ns period=7.812ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.354ns  (logic 1.022ns (43.415%)  route 1.332ns (56.585%))
  Logic Levels:           4  (LUT6=4)
  Clock Path Skew:        2.436ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.436ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.254ns (routing 0.690ns, distribution 1.564ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[14])
                                                      0.698     0.698 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/STATUS_COMMON[14]
                         net (fo=1, routed)           0.769     1.467    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_19_0[12]
    SLICE_X111Y88        LUT6 (Prop_B6LUT_SLICEL_I2_O)
                                                      0.090     1.557 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_38/O
                         net (fo=1, routed)           0.088     1.645    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_38_n_0
    SLICE_X111Y88        LUT6 (Prop_C6LUT_SLICEL_I3_O)
                                                      0.096     1.741 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_17/O
                         net (fo=1, routed)           0.151     1.892    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_17_n_0
    SLICE_X112Y88        LUT6 (Prop_H6LUT_SLICEM_I1_O)
                                                      0.039     1.931 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_5/O
                         net (fo=1, routed)           0.252     2.183    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_5_n_0
    SLICE_X113Y95        LUT6 (Prop_D6LUT_SLICEM_I3_O)
                                                      0.099     2.282 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_1/O
                         net (fo=1, routed)           0.072     2.354    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_70
    SLICE_X113Y95        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       2.254     2.436    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X113Y95        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC0_CLK  {rise@0.000ns fall@3.906ns period=7.812ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.294ns  (logic 0.864ns (37.663%)  route 1.430ns (62.337%))
  Logic Levels:           4  (LUT6=4)
  Clock Path Skew:        2.436ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.436ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.254ns (routing 0.690ns, distribution 1.564ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[15])
                                                      0.525     0.525 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/STATUS_COMMON[15]
                         net (fo=1, routed)           0.861     1.386    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_19_0[13]
    SLICE_X110Y87        LUT6 (Prop_D6LUT_SLICEM_I2_O)
                                                      0.037     1.423 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_43/O
                         net (fo=1, routed)           0.045     1.468    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_43_n_0
    SLICE_X110Y87        LUT6 (Prop_H6LUT_SLICEM_I5_O)
                                                      0.101     1.569 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_19/O
                         net (fo=1, routed)           0.105     1.674    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_19_n_0
    SLICE_X111Y88        LUT6 (Prop_H6LUT_SLICEL_I4_O)
                                                      0.150     1.824 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_4/O
                         net (fo=1, routed)           0.353     2.177    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_4_n_0
    SLICE_X113Y95        LUT6 (Prop_C6LUT_SLICEM_I2_O)
                                                      0.051     2.228 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_1/O
                         net (fo=1, routed)           0.066     2.294    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_69
    SLICE_X113Y95        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       2.254     2.436    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X113Y95        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC0_CLK  {rise@0.000ns fall@3.906ns period=7.812ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.249ns  (logic 0.777ns (34.549%)  route 1.472ns (65.451%))
  Logic Levels:           3  (LUT6=3)
  Clock Path Skew:        2.437ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.437ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.255ns (routing 0.690ns, distribution 1.565ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[9])
                                                      0.532     0.532 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/STATUS_COMMON[9]
                         net (fo=1, routed)           0.902     1.434    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_19_0[9]
    SLICE_X110Y86        LUT6 (Prop_D6LUT_SLICEM_I0_O)
                                                      0.122     1.556 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_13/O
                         net (fo=1, routed)           0.352     1.908    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_13_n_0
    SLICE_X111Y97        LUT6 (Prop_F6LUT_SLICEL_I3_O)
                                                      0.035     1.943 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_3/O
                         net (fo=1, routed)           0.151     2.094    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_3_n_0
    SLICE_X113Y97        LUT6 (Prop_F6LUT_SLICEM_I1_O)
                                                      0.088     2.182 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_1/O
                         net (fo=1, routed)           0.067     2.249    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_75
    SLICE_X113Y97        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       2.255     2.437    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X113Y97        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC0_CLK  {rise@0.000ns fall@3.906ns period=7.812ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.091ns  (logic 0.797ns (38.116%)  route 1.294ns (61.884%))
  Logic Levels:           3  (LUT4=1 LUT6=2)
  Clock Path Skew:        2.431ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.431ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.249ns (routing 0.690ns, distribution 1.559ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[12])
                                                      0.611     0.611 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/STATUS_COMMON[12]
                         net (fo=1, routed)           0.821     1.432    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_19_0[10]
    SLICE_X111Y89        LUT6 (Prop_H6LUT_SLICEL_I0_O)
                                                      0.036     1.468 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_12/O
                         net (fo=1, routed)           0.181     1.649    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_12_n_0
    SLICE_X111Y94        LUT4 (Prop_E6LUT_SLICEL_I2_O)
                                                      0.099     1.748 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_4/O
                         net (fo=1, routed)           0.241     1.989    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_4_n_0
    SLICE_X111Y98        LUT6 (Prop_H6LUT_SLICEL_I3_O)
                                                      0.051     2.040 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_1/O
                         net (fo=1, routed)           0.051     2.091    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_72
    SLICE_X111Y98        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       2.249     2.431    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X111Y98        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC0_CLK  {rise@0.000ns fall@3.906ns period=7.812ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.988ns  (logic 0.353ns (35.729%)  route 0.635ns (64.271%))
  Logic Levels:           3  (LUT4=1 LUT6=2)
  Clock Path Skew:        1.704ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.704ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.557ns (routing 0.463ns, distribution 1.094ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[12])
                                                      0.274     0.274 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/STATUS_COMMON[12]
                         net (fo=1, routed)           0.405     0.679    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_19_0[10]
    SLICE_X111Y89        LUT6 (Prop_H6LUT_SLICEL_I0_O)
                                                      0.015     0.694 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_12/O
                         net (fo=1, routed)           0.091     0.785    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_12_n_0
    SLICE_X111Y94        LUT4 (Prop_E6LUT_SLICEL_I2_O)
                                                      0.041     0.826 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_4/O
                         net (fo=1, routed)           0.122     0.948    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_4_n_0
    SLICE_X111Y98        LUT6 (Prop_H6LUT_SLICEL_I3_O)
                                                      0.023     0.971 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_1/O
                         net (fo=1, routed)           0.017     0.988    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_72
    SLICE_X111Y98        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       1.557     1.704    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X111Y98        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC0_CLK  {rise@0.000ns fall@3.906ns period=7.812ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.051ns  (logic 0.327ns (31.113%)  route 0.724ns (68.887%))
  Logic Levels:           3  (LUT6=3)
  Clock Path Skew:        1.709ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.709ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.562ns (routing 0.463ns, distribution 1.099ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[9])
                                                      0.228     0.228 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/STATUS_COMMON[9]
                         net (fo=1, routed)           0.445     0.673    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_19_0[9]
    SLICE_X110Y86        LUT6 (Prop_D6LUT_SLICEM_I0_O)
                                                      0.050     0.723 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_13/O
                         net (fo=1, routed)           0.176     0.899    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_13_n_0
    SLICE_X111Y97        LUT6 (Prop_F6LUT_SLICEL_I3_O)
                                                      0.014     0.913 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_3/O
                         net (fo=1, routed)           0.079     0.992    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_3_n_0
    SLICE_X113Y97        LUT6 (Prop_F6LUT_SLICEM_I1_O)
                                                      0.035     1.027 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_1/O
                         net (fo=1, routed)           0.024     1.051    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_75
    SLICE_X113Y97        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       1.562     1.709    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X113Y97        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC0_CLK  {rise@0.000ns fall@3.906ns period=7.812ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.071ns  (logic 0.417ns (38.936%)  route 0.654ns (61.064%))
  Logic Levels:           4  (LUT6=4)
  Clock Path Skew:        1.709ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.709ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.562ns (routing 0.463ns, distribution 1.099ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[14])
                                                      0.285     0.285 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/STATUS_COMMON[14]
                         net (fo=1, routed)           0.380     0.665    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_19_0[12]
    SLICE_X111Y88        LUT6 (Prop_B6LUT_SLICEL_I2_O)
                                                      0.036     0.701 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_38/O
                         net (fo=1, routed)           0.044     0.745    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_38_n_0
    SLICE_X111Y88        LUT6 (Prop_C6LUT_SLICEL_I3_O)
                                                      0.040     0.785 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_17/O
                         net (fo=1, routed)           0.077     0.862    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_17_n_0
    SLICE_X112Y88        LUT6 (Prop_H6LUT_SLICEM_I1_O)
                                                      0.015     0.877 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_5/O
                         net (fo=1, routed)           0.127     1.004    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_5_n_0
    SLICE_X113Y95        LUT6 (Prop_D6LUT_SLICEM_I3_O)
                                                      0.041     1.045 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_1/O
                         net (fo=1, routed)           0.026     1.071    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_70
    SLICE_X113Y95        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       1.562     1.709    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X113Y95        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC0_CLK  {rise@0.000ns fall@3.906ns period=7.812ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.076ns  (logic 0.387ns (35.967%)  route 0.689ns (64.033%))
  Logic Levels:           4  (LUT6=4)
  Clock Path Skew:        1.709ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.709ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.562ns (routing 0.463ns, distribution 1.099ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[15])
                                                      0.250     0.250 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/STATUS_COMMON[15]
                         net (fo=1, routed)           0.428     0.678    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_19_0[13]
    SLICE_X110Y87        LUT6 (Prop_D6LUT_SLICEM_I2_O)
                                                      0.014     0.692 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_43/O
                         net (fo=1, routed)           0.025     0.717    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_43_n_0
    SLICE_X110Y87        LUT6 (Prop_H6LUT_SLICEM_I5_O)
                                                      0.041     0.758 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_19/O
                         net (fo=1, routed)           0.054     0.812    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_19_n_0
    SLICE_X111Y88        LUT6 (Prop_H6LUT_SLICEL_I4_O)
                                                      0.060     0.872 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_4/O
                         net (fo=1, routed)           0.158     1.030    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_4_n_0
    SLICE_X113Y95        LUT6 (Prop_C6LUT_SLICEM_I2_O)
                                                      0.022     1.052 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_1/O
                         net (fo=1, routed)           0.024     1.076    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_69
    SLICE_X113Y95        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       1.562     1.709    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X113Y95        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC0_CLK  {rise@0.000ns fall@3.906ns period=7.812ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.189ns  (logic 0.467ns (39.277%)  route 0.722ns (60.723%))
  Logic Levels:           5  (LUT3=1 LUT6=4)
  Clock Path Skew:        1.710ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.710ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.563ns (routing 0.463ns, distribution 1.100ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[10])
                                                      0.227     0.227 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/STATUS_COMMON[10]
                         net (fo=1, routed)           0.413     0.640    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/adc0_common_stat[10]
    SLICE_X110Y85        LUT3 (Prop_H6LUT_SLICEM_I0_O)
                                                      0.061     0.701 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/IP2Bus_Data[10]_i_29/O
                         net (fo=1, routed)           0.060     0.761    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_12_0
    SLICE_X110Y86        LUT6 (Prop_H6LUT_SLICEM_I0_O)
                                                      0.061     0.822 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_19/O
                         net (fo=1, routed)           0.131     0.953    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_19_n_0
    SLICE_X110Y96        LUT6 (Prop_H6LUT_SLICEM_I3_O)
                                                      0.023     0.976 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_12/O
                         net (fo=1, routed)           0.053     1.029    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_12_n_0
    SLICE_X111Y97        LUT6 (Prop_G6LUT_SLICEL_I0_O)
                                                      0.060     1.089 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_5/O
                         net (fo=1, routed)           0.048     1.137    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_5_n_0
    SLICE_X111Y99        LUT6 (Prop_C6LUT_SLICEL_I4_O)
                                                      0.035     1.172 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_1/O
                         net (fo=1, routed)           0.017     1.189    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_74
    SLICE_X111Y99        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       1.563     1.710    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X111Y99        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC0_CLK  {rise@0.000ns fall@3.906ns period=7.812ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.210ns  (logic 0.420ns (34.711%)  route 0.790ns (65.289%))
  Logic Levels:           4  (LUT4=1 LUT6=3)
  Clock Path Skew:        1.700ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.700ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.553ns (routing 0.463ns, distribution 1.090ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[13])
                                                      0.241     0.241 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/STATUS_COMMON[13]
                         net (fo=1, routed)           0.417     0.658    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_19_0[11]
    SLICE_X111Y87        LUT4 (Prop_G6LUT_SLICEL_I3_O)
                                                      0.050     0.708 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_31/O
                         net (fo=1, routed)           0.050     0.758    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_31_n_0
    SLICE_X111Y89        LUT6 (Prop_G6LUT_SLICEL_I0_O)
                                                      0.035     0.793 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_14/O
                         net (fo=1, routed)           0.159     0.952    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_14_n_0
    SLICE_X114Y96        LUT6 (Prop_D6LUT_SLICEL_I0_O)
                                                      0.059     1.011 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_5/O
                         net (fo=1, routed)           0.138     1.149    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_5_n_0
    SLICE_X109Y97        LUT6 (Prop_D6LUT_SLICEM_I4_O)
                                                      0.035     1.184 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_1/O
                         net (fo=1, routed)           0.026     1.210    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_71
    SLICE_X109Y97        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       1.553     1.700    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X109Y97        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC0_CLK  {rise@0.000ns fall@3.906ns period=7.812ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.272ns  (logic 0.411ns (32.311%)  route 0.861ns (67.689%))
  Logic Levels:           4  (LUT4=1 LUT6=3)
  Clock Path Skew:        1.715ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.715ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.568ns (routing 0.463ns, distribution 1.105ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[8])
                                                      0.237     0.237 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/STATUS_COMMON[8]
                         net (fo=1, routed)           0.490     0.727    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_19_0[8]
    SLICE_X112Y89        LUT4 (Prop_E6LUT_SLICEM_I3_O)
                                                      0.059     0.786 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_18/O
                         net (fo=1, routed)           0.116     0.902    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_18_n_0
    SLICE_X111Y95        LUT6 (Prop_C6LUT_SLICEL_I2_O)
                                                      0.040     0.942 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_11/O
                         net (fo=1, routed)           0.115     1.057    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_11_n_0
    SLICE_X115Y97        LUT6 (Prop_C6LUT_SLICEM_I0_O)
                                                      0.040     1.097 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_5/O
                         net (fo=1, routed)           0.116     1.213    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_5_n_0
    SLICE_X110Y99        LUT6 (Prop_C6LUT_SLICEM_I4_O)
                                                      0.035     1.248 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_1/O
                         net (fo=1, routed)           0.024     1.272    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_76
    SLICE_X110Y99        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       1.568     1.715    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X110Y99        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC0_CLK  {rise@0.000ns fall@3.906ns period=7.812ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.315ns  (logic 0.397ns (30.190%)  route 0.918ns (69.810%))
  Logic Levels:           5  (LUT3=1 LUT6=4)
  Clock Path Skew:        1.706ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.706ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.559ns (routing 0.463ns, distribution 1.096ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[11])
                                                      0.265     0.265 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/STATUS_COMMON[11]
                         net (fo=1, routed)           0.381     0.646    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/adc0_common_stat[11]
    SLICE_X110Y85        LUT3 (Prop_H5LUT_SLICEM_I0_O)
                                                      0.033     0.679 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/IP2Bus_Data[11]_i_33/O
                         net (fo=1, routed)           0.089     0.768    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_13_0
    SLICE_X110Y86        LUT6 (Prop_G6LUT_SLICEM_I1_O)
                                                      0.014     0.782 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_22/O
                         net (fo=1, routed)           0.184     0.966    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_22_n_0
    SLICE_X111Y96        LUT6 (Prop_H6LUT_SLICEL_I3_O)
                                                      0.023     0.989 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_13/O
                         net (fo=1, routed)           0.105     1.094    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_13_n_0
    SLICE_X113Y97        LUT6 (Prop_E6LUT_SLICEM_I0_O)
                                                      0.040     1.134 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_5/O
                         net (fo=1, routed)           0.143     1.277    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_5_n_0
    SLICE_X111Y100       LUT6 (Prop_D6LUT_SLICEL_I4_O)
                                                      0.022     1.299 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_1/O
                         net (fo=1, routed)           0.016     1.315    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_73
    SLICE_X111Y100       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       1.559     1.706    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X111Y100       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  RFADC1_CLK
  To Clock:  clk_pl_0

Max Delay             8 Endpoints
Min Delay             8 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC1_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.416ns  (logic 1.183ns (48.965%)  route 1.233ns (51.035%))
  Logic Levels:           5  (LUT4=1 LUT5=2 LUT6=2)
  Clock Path Skew:        2.443ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.443ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.261ns (routing 0.690ns, distribution 1.571ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[8])
                                                      0.788     0.788 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_COMMON[8]
                         net (fo=1, routed)           0.462     1.250    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/adc1_common_stat[8]
    SLICE_X114Y91        LUT4 (Prop_B6LUT_SLICEL_I0_O)
                                                      0.098     1.348 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_34/O
                         net (fo=1, routed)           0.089     1.437    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_34_n_0
    SLICE_X114Y91        LUT5 (Prop_C6LUT_SLICEL_I3_O)
                                                      0.035     1.472 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_26/O
                         net (fo=1, routed)           0.249     1.721    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_26_n_0
    SLICE_X115Y94        LUT5 (Prop_G6LUT_SLICEM_I1_O)
                                                      0.123     1.844 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_15/O
                         net (fo=1, routed)           0.138     1.982    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_15_n_0
    SLICE_X115Y97        LUT6 (Prop_C6LUT_SLICEM_I5_O)
                                                      0.051     2.033 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_5/O
                         net (fo=1, routed)           0.229     2.262    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_5_n_0
    SLICE_X110Y99        LUT6 (Prop_C6LUT_SLICEM_I4_O)
                                                      0.088     2.350 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_1/O
                         net (fo=1, routed)           0.066     2.416    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_76
    SLICE_X110Y99        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       2.261     2.443    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X110Y99        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC1_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.250ns  (logic 1.091ns (48.489%)  route 1.159ns (51.511%))
  Logic Levels:           5  (LUT4=1 LUT5=1 LUT6=3)
  Clock Path Skew:        2.436ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.436ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.254ns (routing 0.690ns, distribution 1.564ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[14])
                                                      0.698     0.698 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_COMMON[14]
                         net (fo=1, routed)           0.459     1.157    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/adc1_common_stat[14]
    SLICE_X116Y94        LUT4 (Prop_H6LUT_SLICEL_I0_O)
                                                      0.090     1.247 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_66/O
                         net (fo=1, routed)           0.206     1.453    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_66_n_0
    SLICE_X116Y91        LUT5 (Prop_G6LUT_SLICEL_I0_O)
                                                      0.123     1.576 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_49/O
                         net (fo=1, routed)           0.147     1.723    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_49_n_0
    SLICE_X113Y91        LUT6 (Prop_H6LUT_SLICEM_I2_O)
                                                      0.039     1.762 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_22/O
                         net (fo=1, routed)           0.185     1.947    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_22_n_0
    SLICE_X113Y95        LUT6 (Prop_G6LUT_SLICEM_I5_O)
                                                      0.090     2.037 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_6/O
                         net (fo=1, routed)           0.090     2.127    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_6_n_0
    SLICE_X113Y95        LUT6 (Prop_D6LUT_SLICEM_I5_O)
                                                      0.051     2.178 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_1/O
                         net (fo=1, routed)           0.072     2.250    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_70
    SLICE_X113Y95        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       2.254     2.436    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X113Y95        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC1_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.142ns  (logic 0.998ns (46.592%)  route 1.144ns (53.408%))
  Logic Levels:           5  (LUT4=1 LUT5=2 LUT6=2)
  Clock Path Skew:        2.439ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.439ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.257ns (routing 0.690ns, distribution 1.567ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[10])
                                                      0.536     0.536 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_COMMON[10]
                         net (fo=1, routed)           0.548     1.084    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/adc1_common_stat[10]
    SLICE_X115Y91        LUT4 (Prop_A6LUT_SLICEM_I0_O)
                                                      0.150     1.234 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_36/O
                         net (fo=1, routed)           0.094     1.328    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_36_n_0
    SLICE_X114Y91        LUT5 (Prop_D6LUT_SLICEL_I3_O)
                                                      0.036     1.364 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_27/O
                         net (fo=1, routed)           0.145     1.509    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_27_n_0
    SLICE_X114Y94        LUT5 (Prop_D6LUT_SLICEL_I1_O)
                                                      0.099     1.608 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_16/O
                         net (fo=1, routed)           0.216     1.824    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_16_n_0
    SLICE_X111Y97        LUT6 (Prop_G6LUT_SLICEL_I5_O)
                                                      0.089     1.913 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_5/O
                         net (fo=1, routed)           0.091     2.004    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_5_n_0
    SLICE_X111Y99        LUT6 (Prop_C6LUT_SLICEL_I4_O)
                                                      0.088     2.092 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_1/O
                         net (fo=1, routed)           0.050     2.142    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_74
    SLICE_X111Y99        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       2.257     2.439    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X111Y99        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC1_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.077ns  (logic 1.134ns (54.598%)  route 0.943ns (45.402%))
  Logic Levels:           4  (LUT5=2 LUT6=2)
  Clock Path Skew:        2.424ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.424ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.242ns (routing 0.690ns, distribution 1.552ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[13])
                                                      0.771     0.771 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_COMMON[13]
                         net (fo=1, routed)           0.467     1.238    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/adc1_common_stat[13]
    SLICE_X114Y94        LUT5 (Prop_A6LUT_SLICEL_I4_O)
                                                      0.149     1.387 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_36/O
                         net (fo=1, routed)           0.041     1.428    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_36_n_0
    SLICE_X114Y94        LUT5 (Prop_B6LUT_SLICEL_I4_O)
                                                      0.090     1.518 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_15/O
                         net (fo=1, routed)           0.094     1.612    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_15_n_0
    SLICE_X114Y96        LUT6 (Prop_D6LUT_SLICEL_I1_O)
                                                      0.036     1.648 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_5/O
                         net (fo=1, routed)           0.269     1.917    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_5_n_0
    SLICE_X109Y97        LUT6 (Prop_D6LUT_SLICEM_I4_O)
                                                      0.088     2.005 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_1/O
                         net (fo=1, routed)           0.072     2.077    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_71
    SLICE_X109Y97        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       2.242     2.424    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X109Y97        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC1_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.031ns  (logic 0.874ns (43.033%)  route 1.157ns (56.967%))
  Logic Levels:           5  (LUT4=1 LUT5=2 LUT6=2)
  Clock Path Skew:        2.435ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.435ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.253ns (routing 0.690ns, distribution 1.563ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[11])
                                                      0.588     0.588 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_COMMON[11]
                         net (fo=1, routed)           0.552     1.140    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/adc1_common_stat[11]
    SLICE_X113Y92        LUT4 (Prop_A6LUT_SLICEM_I0_O)
                                                      0.125     1.265 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_42/O
                         net (fo=1, routed)           0.043     1.308    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_42_n_0
    SLICE_X113Y92        LUT5 (Prop_C6LUT_SLICEM_I3_O)
                                                      0.037     1.345 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_31/O
                         net (fo=1, routed)           0.040     1.385    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_31_n_0
    SLICE_X113Y92        LUT5 (Prop_D6LUT_SLICEM_I1_O)
                                                      0.037     1.422 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_17/O
                         net (fo=1, routed)           0.149     1.571    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_17_n_0
    SLICE_X113Y97        LUT6 (Prop_E6LUT_SLICEM_I5_O)
                                                      0.037     1.608 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_5/O
                         net (fo=1, routed)           0.324     1.932    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_5_n_0
    SLICE_X111Y100       LUT6 (Prop_D6LUT_SLICEL_I4_O)
                                                      0.050     1.982 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_1/O
                         net (fo=1, routed)           0.049     2.031    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_73
    SLICE_X111Y100       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       2.253     2.435    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X111Y100       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC1_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.857ns  (logic 0.887ns (47.765%)  route 0.970ns (52.235%))
  Logic Levels:           4  (LUT3=1 LUT5=1 LUT6=2)
  Clock Path Skew:        2.431ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.431ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.249ns (routing 0.690ns, distribution 1.559ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[12])
                                                      0.611     0.611 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_COMMON[12]
                         net (fo=1, routed)           0.417     1.028    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/adc1_common_stat[12]
    SLICE_X114Y94        LUT5 (Prop_C6LUT_SLICEL_I4_O)
                                                      0.035     1.063 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_27/O
                         net (fo=1, routed)           0.134     1.197    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_27_n_0
    SLICE_X113Y92        LUT6 (Prop_H6LUT_SLICEM_I5_O)
                                                      0.039     1.236 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_14/O
                         net (fo=1, routed)           0.147     1.383    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_14_n_0
    SLICE_X113Y96        LUT3 (Prop_E6LUT_SLICEM_I1_O)
                                                      0.052     1.435 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_5/O
                         net (fo=1, routed)           0.221     1.656    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_5_n_0
    SLICE_X111Y98        LUT6 (Prop_H6LUT_SLICEL_I4_O)
                                                      0.150     1.806 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_1/O
                         net (fo=1, routed)           0.051     1.857    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_72
    SLICE_X111Y98        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       2.249     2.431    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X111Y98        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC1_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.667ns  (logic 0.743ns (44.571%)  route 0.924ns (55.429%))
  Logic Levels:           4  (LUT5=2 LUT6=2)
  Clock Path Skew:        2.436ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.436ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.254ns (routing 0.690ns, distribution 1.564ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[15])
                                                      0.525     0.525 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_COMMON[15]
                         net (fo=1, routed)           0.444     0.969    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/adc1_common_stat[15]
    SLICE_X116Y92        LUT5 (Prop_F6LUT_SLICEL_I4_O)
                                                      0.049     1.018 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_52/O
                         net (fo=1, routed)           0.081     1.099    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_52_n_0
    SLICE_X116Y91        LUT5 (Prop_F6LUT_SLICEL_I1_O)
                                                      0.035     1.134 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_23/O
                         net (fo=1, routed)           0.135     1.269    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_23_n_0
    SLICE_X116Y95        LUT6 (Prop_H6LUT_SLICEL_I5_O)
                                                      0.036     1.305 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_5/O
                         net (fo=1, routed)           0.198     1.503    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_5_n_0
    SLICE_X113Y95        LUT6 (Prop_C6LUT_SLICEM_I3_O)
                                                      0.098     1.601 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_1/O
                         net (fo=1, routed)           0.066     1.667    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_69
    SLICE_X113Y95        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       2.254     2.436    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X113Y95        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC1_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.579ns  (logic 0.853ns (54.022%)  route 0.726ns (45.978%))
  Logic Levels:           4  (LUT5=1 LUT6=3)
  Clock Path Skew:        2.437ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.437ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.255ns (routing 0.690ns, distribution 1.565ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[9])
                                                      0.532     0.532 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_COMMON[9]
                         net (fo=1, routed)           0.370     0.902    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/adc1_common_stat[9]
    SLICE_X114Y94        LUT5 (Prop_F6LUT_SLICEL_I4_O)
                                                      0.049     0.951 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_42/O
                         net (fo=1, routed)           0.039     0.990    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_42_n_0
    SLICE_X114Y94        LUT6 (Prop_H6LUT_SLICEL_I2_O)
                                                      0.036     1.026 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_21/O
                         net (fo=1, routed)           0.144     1.170    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_21_n_0
    SLICE_X114Y97        LUT6 (Prop_C6LUT_SLICEL_I5_O)
                                                      0.088     1.258 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_6/O
                         net (fo=1, routed)           0.106     1.364    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_6_n_0
    SLICE_X113Y97        LUT6 (Prop_F6LUT_SLICEM_I4_O)
                                                      0.148     1.512 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_1/O
                         net (fo=1, routed)           0.067     1.579    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_75
    SLICE_X113Y97        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       2.255     2.437    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X113Y97        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC1_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.697ns  (logic 0.359ns (51.506%)  route 0.338ns (48.494%))
  Logic Levels:           4  (LUT5=1 LUT6=3)
  Clock Path Skew:        1.709ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.709ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.562ns (routing 0.463ns, distribution 1.099ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[9])
                                                      0.228     0.228 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_COMMON[9]
                         net (fo=1, routed)           0.168     0.396    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/adc1_common_stat[9]
    SLICE_X114Y94        LUT5 (Prop_F6LUT_SLICEL_I4_O)
                                                      0.022     0.418 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_42/O
                         net (fo=1, routed)           0.021     0.439    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_42_n_0
    SLICE_X114Y94        LUT6 (Prop_H6LUT_SLICEL_I2_O)
                                                      0.015     0.454 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_21/O
                         net (fo=1, routed)           0.072     0.526    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_21_n_0
    SLICE_X114Y97        LUT6 (Prop_C6LUT_SLICEL_I5_O)
                                                      0.035     0.561 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_6/O
                         net (fo=1, routed)           0.053     0.614    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_6_n_0
    SLICE_X113Y97        LUT6 (Prop_F6LUT_SLICEM_I4_O)
                                                      0.059     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_1/O
                         net (fo=1, routed)           0.024     0.697    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_75
    SLICE_X113Y97        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       1.562     1.709    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X113Y97        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC1_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.789ns  (logic 0.341ns (43.219%)  route 0.448ns (56.781%))
  Logic Levels:           4  (LUT5=2 LUT6=2)
  Clock Path Skew:        1.709ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.709ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.562ns (routing 0.463ns, distribution 1.099ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[15])
                                                      0.250     0.250 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_COMMON[15]
                         net (fo=1, routed)           0.207     0.457    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/adc1_common_stat[15]
    SLICE_X116Y92        LUT5 (Prop_F6LUT_SLICEL_I4_O)
                                                      0.022     0.479 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_52/O
                         net (fo=1, routed)           0.045     0.524    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_52_n_0
    SLICE_X116Y91        LUT5 (Prop_F6LUT_SLICEL_I1_O)
                                                      0.014     0.538 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_23/O
                         net (fo=1, routed)           0.073     0.611    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_23_n_0
    SLICE_X116Y95        LUT6 (Prop_H6LUT_SLICEL_I5_O)
                                                      0.015     0.626 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_5/O
                         net (fo=1, routed)           0.099     0.725    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_5_n_0
    SLICE_X113Y95        LUT6 (Prop_C6LUT_SLICEM_I3_O)
                                                      0.040     0.765 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_1/O
                         net (fo=1, routed)           0.024     0.789    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_69
    SLICE_X113Y95        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       1.562     1.709    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X113Y95        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC1_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.840ns  (logic 0.386ns (45.952%)  route 0.454ns (54.048%))
  Logic Levels:           4  (LUT5=2 LUT6=2)
  Clock Path Skew:        1.700ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.700ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.553ns (routing 0.463ns, distribution 1.090ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[13])
                                                      0.241     0.241 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_COMMON[13]
                         net (fo=1, routed)           0.217     0.458    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/adc1_common_stat[13]
    SLICE_X114Y94        LUT5 (Prop_A6LUT_SLICEL_I4_O)
                                                      0.060     0.518 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_36/O
                         net (fo=1, routed)           0.024     0.542    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_36_n_0
    SLICE_X114Y94        LUT5 (Prop_B6LUT_SLICEL_I4_O)
                                                      0.036     0.578 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_15/O
                         net (fo=1, routed)           0.049     0.627    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_15_n_0
    SLICE_X114Y96        LUT6 (Prop_D6LUT_SLICEL_I1_O)
                                                      0.014     0.641 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_5/O
                         net (fo=1, routed)           0.138     0.779    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_5_n_0
    SLICE_X109Y97        LUT6 (Prop_D6LUT_SLICEM_I4_O)
                                                      0.035     0.814 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_1/O
                         net (fo=1, routed)           0.026     0.840    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_71
    SLICE_X109Y97        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       1.553     1.700    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X109Y97        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC1_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.857ns  (logic 0.385ns (44.924%)  route 0.472ns (55.076%))
  Logic Levels:           4  (LUT3=1 LUT5=1 LUT6=2)
  Clock Path Skew:        1.704ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.704ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.557ns (routing 0.463ns, distribution 1.094ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[12])
                                                      0.274     0.274 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_COMMON[12]
                         net (fo=1, routed)           0.194     0.468    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/adc1_common_stat[12]
    SLICE_X114Y94        LUT5 (Prop_C6LUT_SLICEL_I4_O)
                                                      0.014     0.482 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_27/O
                         net (fo=1, routed)           0.069     0.551    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_27_n_0
    SLICE_X113Y92        LUT6 (Prop_H6LUT_SLICEM_I5_O)
                                                      0.015     0.566 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_14/O
                         net (fo=1, routed)           0.078     0.644    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_14_n_0
    SLICE_X113Y96        LUT3 (Prop_E6LUT_SLICEM_I1_O)
                                                      0.022     0.666 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_5/O
                         net (fo=1, routed)           0.114     0.780    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_5_n_0
    SLICE_X111Y98        LUT6 (Prop_H6LUT_SLICEL_I4_O)
                                                      0.060     0.840 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_1/O
                         net (fo=1, routed)           0.017     0.857    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_72
    SLICE_X111Y98        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       1.557     1.704    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X111Y98        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC1_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.931ns  (logic 0.380ns (40.816%)  route 0.551ns (59.184%))
  Logic Levels:           5  (LUT4=1 LUT5=2 LUT6=2)
  Clock Path Skew:        1.706ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.706ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.559ns (routing 0.463ns, distribution 1.096ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[11])
                                                      0.265     0.265 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_COMMON[11]
                         net (fo=1, routed)           0.265     0.530    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/adc1_common_stat[11]
    SLICE_X113Y92        LUT4 (Prop_A6LUT_SLICEM_I0_O)
                                                      0.051     0.581 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_42/O
                         net (fo=1, routed)           0.024     0.605    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_42_n_0
    SLICE_X113Y92        LUT5 (Prop_C6LUT_SLICEM_I3_O)
                                                      0.014     0.619 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_31/O
                         net (fo=1, routed)           0.022     0.641    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_31_n_0
    SLICE_X113Y92        LUT5 (Prop_D6LUT_SLICEM_I1_O)
                                                      0.014     0.655 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_17/O
                         net (fo=1, routed)           0.081     0.736    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_17_n_0
    SLICE_X113Y97        LUT6 (Prop_E6LUT_SLICEM_I5_O)
                                                      0.014     0.750 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_5/O
                         net (fo=1, routed)           0.143     0.893    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_5_n_0
    SLICE_X111Y100       LUT6 (Prop_D6LUT_SLICEL_I4_O)
                                                      0.022     0.915 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_1/O
                         net (fo=1, routed)           0.016     0.931    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_73
    SLICE_X111Y100       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       1.559     1.706    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X111Y100       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC1_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.942ns  (logic 0.412ns (43.737%)  route 0.530ns (56.263%))
  Logic Levels:           5  (LUT4=1 LUT5=2 LUT6=2)
  Clock Path Skew:        1.710ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.710ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.563ns (routing 0.463ns, distribution 1.100ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[10])
                                                      0.227     0.227 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_COMMON[10]
                         net (fo=1, routed)           0.227     0.454    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/adc1_common_stat[10]
    SLICE_X115Y91        LUT4 (Prop_A6LUT_SLICEM_I0_O)
                                                      0.060     0.514 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_36/O
                         net (fo=1, routed)           0.052     0.566    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_36_n_0
    SLICE_X114Y91        LUT5 (Prop_D6LUT_SLICEL_I3_O)
                                                      0.014     0.580 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_27/O
                         net (fo=1, routed)           0.073     0.653    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_27_n_0
    SLICE_X114Y94        LUT5 (Prop_D6LUT_SLICEL_I1_O)
                                                      0.041     0.694 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_16/O
                         net (fo=1, routed)           0.113     0.807    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_16_n_0
    SLICE_X111Y97        LUT6 (Prop_G6LUT_SLICEL_I5_O)
                                                      0.035     0.842 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_5/O
                         net (fo=1, routed)           0.048     0.890    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_5_n_0
    SLICE_X111Y99        LUT6 (Prop_C6LUT_SLICEL_I4_O)
                                                      0.035     0.925 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_1/O
                         net (fo=1, routed)           0.017     0.942    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_74
    SLICE_X111Y99        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       1.563     1.710    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X111Y99        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC1_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.996ns  (logic 0.442ns (44.378%)  route 0.554ns (55.622%))
  Logic Levels:           5  (LUT4=1 LUT5=1 LUT6=3)
  Clock Path Skew:        1.709ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.709ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.562ns (routing 0.463ns, distribution 1.099ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[14])
                                                      0.285     0.285 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_COMMON[14]
                         net (fo=1, routed)           0.210     0.495    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/adc1_common_stat[14]
    SLICE_X116Y94        LUT4 (Prop_H6LUT_SLICEL_I0_O)
                                                      0.035     0.530 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_66/O
                         net (fo=1, routed)           0.102     0.632    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_66_n_0
    SLICE_X116Y91        LUT5 (Prop_G6LUT_SLICEL_I0_O)
                                                      0.050     0.682 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_49/O
                         net (fo=1, routed)           0.075     0.757    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_49_n_0
    SLICE_X113Y91        LUT6 (Prop_H6LUT_SLICEM_I2_O)
                                                      0.015     0.772 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_22/O
                         net (fo=1, routed)           0.097     0.869    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_22_n_0
    SLICE_X113Y95        LUT6 (Prop_G6LUT_SLICEM_I5_O)
                                                      0.035     0.904 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_6/O
                         net (fo=1, routed)           0.044     0.948    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_6_n_0
    SLICE_X113Y95        LUT6 (Prop_D6LUT_SLICEM_I5_O)
                                                      0.022     0.970 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_1/O
                         net (fo=1, routed)           0.026     0.996    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_70
    SLICE_X113Y95        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       1.562     1.709    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X113Y95        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC1_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.000ns  (logic 0.399ns (39.900%)  route 0.601ns (60.100%))
  Logic Levels:           5  (LUT4=1 LUT5=2 LUT6=2)
  Clock Path Skew:        1.715ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.715ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.568ns (routing 0.463ns, distribution 1.105ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[8])
                                                      0.237     0.237 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_COMMON[8]
                         net (fo=1, routed)           0.217     0.454    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/adc1_common_stat[8]
    SLICE_X114Y91        LUT4 (Prop_B6LUT_SLICEL_I0_O)
                                                      0.041     0.495 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_34/O
                         net (fo=1, routed)           0.044     0.539    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_34_n_0
    SLICE_X114Y91        LUT5 (Prop_C6LUT_SLICEL_I3_O)
                                                      0.014     0.553 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_26/O
                         net (fo=1, routed)           0.126     0.679    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_26_n_0
    SLICE_X115Y94        LUT5 (Prop_G6LUT_SLICEM_I1_O)
                                                      0.050     0.729 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_15/O
                         net (fo=1, routed)           0.074     0.803    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_15_n_0
    SLICE_X115Y97        LUT6 (Prop_C6LUT_SLICEM_I5_O)
                                                      0.022     0.825 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_5/O
                         net (fo=1, routed)           0.116     0.941    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_5_n_0
    SLICE_X110Y99        LUT6 (Prop_C6LUT_SLICEM_I4_O)
                                                      0.035     0.976 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_1/O
                         net (fo=1, routed)           0.024     1.000    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_76
    SLICE_X110Y99        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       1.568     1.715    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X110Y99        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  RFADC2_CLK
  To Clock:  clk_pl_0

Max Delay             8 Endpoints
Min Delay             8 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC2_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.999ns  (logic 1.304ns (43.481%)  route 1.695ns (56.519%))
  Logic Levels:           5  (LUT4=1 LUT5=1 LUT6=3)
  Clock Path Skew:        2.424ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.424ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.242ns (routing 0.690ns, distribution 1.552ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y2           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y2           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[13])
                                                      0.771     0.771 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_COMMON[13]
                         net (fo=1, routed)           0.907     1.678    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/adc2_common_stat[13]
    SLICE_X110Y96        LUT4 (Prop_B6LUT_SLICEM_I0_O)
                                                      0.149     1.827 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_56/O
                         net (fo=1, routed)           0.106     1.933    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_56_n_0
    SLICE_X110Y96        LUT5 (Prop_C6LUT_SLICEM_I0_O)
                                                      0.123     2.056 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_39/O
                         net (fo=1, routed)           0.252     2.308    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_39_n_0
    SLICE_X114Y96        LUT6 (Prop_G6LUT_SLICEL_I5_O)
                                                      0.123     2.431 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_16/O
                         net (fo=1, routed)           0.089     2.520    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_16_n_0
    SLICE_X114Y96        LUT6 (Prop_D6LUT_SLICEL_I3_O)
                                                      0.050     2.570 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_5/O
                         net (fo=1, routed)           0.269     2.839    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_5_n_0
    SLICE_X109Y97        LUT6 (Prop_D6LUT_SLICEM_I4_O)
                                                      0.088     2.927 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_1/O
                         net (fo=1, routed)           0.072     2.999    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_71
    SLICE_X109Y97        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       2.242     2.424    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X109Y97        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC2_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.908ns  (logic 1.393ns (47.902%)  route 1.515ns (52.098%))
  Logic Levels:           5  (LUT4=2 LUT6=3)
  Clock Path Skew:        2.443ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.443ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.261ns (routing 0.690ns, distribution 1.571ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y2           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y2           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[8])
                                                      0.788     0.788 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_COMMON[8]
                         net (fo=1, routed)           0.862     1.650    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/adc2_common_stat[8]
    SLICE_X112Y98        LUT4 (Prop_E6LUT_SLICEM_I0_O)
                                                      0.148     1.798 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_31/O
                         net (fo=1, routed)           0.095     1.893    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_31_n_0
    SLICE_X112Y98        LUT4 (Prop_F6LUT_SLICEM_I0_O)
                                                      0.123     2.016 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_24/O
                         net (fo=1, routed)           0.090     2.106    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_24_n_0
    SLICE_X112Y97        LUT6 (Prop_G6LUT_SLICEM_I2_O)
                                                      0.123     2.229 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_14/O
                         net (fo=1, routed)           0.173     2.402    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_14_n_0
    SLICE_X115Y97        LUT6 (Prop_C6LUT_SLICEM_I4_O)
                                                      0.123     2.525 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_5/O
                         net (fo=1, routed)           0.229     2.754    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_5_n_0
    SLICE_X110Y99        LUT6 (Prop_C6LUT_SLICEM_I4_O)
                                                      0.088     2.842 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_1/O
                         net (fo=1, routed)           0.066     2.908    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_76
    SLICE_X110Y99        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       2.261     2.443    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X110Y99        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC2_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.580ns  (logic 1.019ns (39.496%)  route 1.561ns (60.504%))
  Logic Levels:           5  (LUT4=2 LUT6=3)
  Clock Path Skew:        2.435ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.435ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.253ns (routing 0.690ns, distribution 1.563ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y2           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y2           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[11])
                                                      0.588     0.588 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_COMMON[11]
                         net (fo=1, routed)           0.869     1.457    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/adc2_common_stat[11]
    SLICE_X110Y97        LUT4 (Prop_A6LUT_SLICEM_I0_O)
                                                      0.150     1.607 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_37/O
                         net (fo=1, routed)           0.044     1.651    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_37_n_0
    SLICE_X110Y97        LUT4 (Prop_B6LUT_SLICEM_I0_O)
                                                      0.089     1.740 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_29/O
                         net (fo=1, routed)           0.170     1.910    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_29_n_0
    SLICE_X112Y97        LUT6 (Prop_H6LUT_SLICEM_I2_O)
                                                      0.090     2.000 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_16/O
                         net (fo=1, routed)           0.105     2.105    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_16_n_0
    SLICE_X113Y97        LUT6 (Prop_E6LUT_SLICEM_I4_O)
                                                      0.052     2.157 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_5/O
                         net (fo=1, routed)           0.324     2.481    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_5_n_0
    SLICE_X111Y100       LUT6 (Prop_D6LUT_SLICEL_I4_O)
                                                      0.050     2.531 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_1/O
                         net (fo=1, routed)           0.049     2.580    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_73
    SLICE_X111Y100       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       2.253     2.435    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X111Y100       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC2_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.545ns  (logic 1.073ns (42.161%)  route 1.472ns (57.839%))
  Logic Levels:           5  (LUT4=1 LUT5=1 LUT6=3)
  Clock Path Skew:        2.436ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.436ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.254ns (routing 0.690ns, distribution 1.564ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y2           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y2           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[14])
                                                      0.698     0.698 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_COMMON[14]
                         net (fo=1, routed)           0.816     1.514    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/adc2_common_stat[14]
    SLICE_X117Y93        LUT4 (Prop_G6LUT_SLICEL_I2_O)
                                                      0.149     1.663 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_60/O
                         net (fo=1, routed)           0.230     1.893    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_60_n_0
    SLICE_X115Y93        LUT5 (Prop_G6LUT_SLICEM_I2_O)
                                                      0.037     1.930 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_46/O
                         net (fo=1, routed)           0.171     2.101    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_46_n_0
    SLICE_X113Y93        LUT6 (Prop_H6LUT_SLICEM_I2_O)
                                                      0.101     2.202 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_21/O
                         net (fo=1, routed)           0.093     2.295    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_21_n_0
    SLICE_X113Y95        LUT6 (Prop_G6LUT_SLICEM_I4_O)
                                                      0.037     2.332 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_6/O
                         net (fo=1, routed)           0.090     2.422    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_6_n_0
    SLICE_X113Y95        LUT6 (Prop_D6LUT_SLICEM_I5_O)
                                                      0.051     2.473 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_1/O
                         net (fo=1, routed)           0.072     2.545    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_70
    SLICE_X113Y95        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       2.254     2.436    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X113Y95        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC2_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.364ns  (logic 0.993ns (42.005%)  route 1.371ns (57.995%))
  Logic Levels:           4  (LUT3=1 LUT6=3)
  Clock Path Skew:        2.431ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.431ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.249ns (routing 0.690ns, distribution 1.559ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y2           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y2           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[12])
                                                      0.611     0.611 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_COMMON[12]
                         net (fo=1, routed)           0.948     1.559    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/adc2_common_stat[12]
    SLICE_X112Y96        LUT6 (Prop_D6LUT_SLICEM_I1_O)
                                                      0.088     1.647 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_26/O
                         net (fo=1, routed)           0.107     1.754    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_26_n_0
    SLICE_X113Y96        LUT6 (Prop_H6LUT_SLICEM_I1_O)
                                                      0.053     1.807 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_13/O
                         net (fo=1, routed)           0.044     1.851    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_13_n_0
    SLICE_X113Y96        LUT3 (Prop_E6LUT_SLICEM_I0_O)
                                                      0.091     1.942 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_5/O
                         net (fo=1, routed)           0.221     2.163    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_5_n_0
    SLICE_X111Y98        LUT6 (Prop_H6LUT_SLICEL_I4_O)
                                                      0.150     2.313 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_1/O
                         net (fo=1, routed)           0.051     2.364    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_72
    SLICE_X111Y98        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       2.249     2.431    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X111Y98        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC2_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.345ns  (logic 0.927ns (39.531%)  route 1.418ns (60.469%))
  Logic Levels:           4  (LUT5=1 LUT6=3)
  Clock Path Skew:        2.437ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.437ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.255ns (routing 0.690ns, distribution 1.565ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y2           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y2           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[9])
                                                      0.532     0.532 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_COMMON[9]
                         net (fo=1, routed)           0.904     1.436    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/adc2_common_stat[9]
    SLICE_X112Y98        LUT5 (Prop_B6LUT_SLICEM_I4_O)
                                                      0.089     1.525 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_39/O
                         net (fo=1, routed)           0.096     1.621    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_39_n_0
    SLICE_X112Y97        LUT6 (Prop_F6LUT_SLICEM_I3_O)
                                                      0.123     1.744 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_20/O
                         net (fo=1, routed)           0.245     1.989    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_20_n_0
    SLICE_X114Y97        LUT6 (Prop_C6LUT_SLICEL_I3_O)
                                                      0.035     2.024 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_6/O
                         net (fo=1, routed)           0.106     2.130    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_6_n_0
    SLICE_X113Y97        LUT6 (Prop_F6LUT_SLICEM_I4_O)
                                                      0.148     2.278 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_1/O
                         net (fo=1, routed)           0.067     2.345    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_75
    SLICE_X113Y97        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       2.255     2.437    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X113Y97        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC2_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.178ns  (logic 0.837ns (38.430%)  route 1.341ns (61.570%))
  Logic Levels:           5  (LUT4=1 LUT5=1 LUT6=3)
  Clock Path Skew:        2.436ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.436ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.254ns (routing 0.690ns, distribution 1.564ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y2           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y2           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[15])
                                                      0.525     0.525 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_COMMON[15]
                         net (fo=1, routed)           0.749     1.274    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/adc2_common_stat[15]
    SLICE_X117Y93        LUT4 (Prop_F6LUT_SLICEL_I2_O)
                                                      0.089     1.363 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_83/O
                         net (fo=1, routed)           0.041     1.404    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_83_n_0
    SLICE_X117Y93        LUT5 (Prop_H6LUT_SLICEL_I2_O)
                                                      0.051     1.455 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_56/O
                         net (fo=1, routed)           0.309     1.764    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_56_n_0
    SLICE_X114Y95        LUT6 (Prop_D6LUT_SLICEL_I2_O)
                                                      0.036     1.800 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_25/O
                         net (fo=1, routed)           0.043     1.843    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_25_n_0
    SLICE_X114Y95        LUT6 (Prop_H6LUT_SLICEL_I3_O)
                                                      0.099     1.942 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_6/O
                         net (fo=1, routed)           0.133     2.075    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_6_n_0
    SLICE_X113Y95        LUT6 (Prop_C6LUT_SLICEM_I4_O)
                                                      0.037     2.112 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_1/O
                         net (fo=1, routed)           0.066     2.178    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_69
    SLICE_X113Y95        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       2.254     2.436    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X113Y95        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC2_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.043ns  (logic 0.850ns (41.605%)  route 1.193ns (58.395%))
  Logic Levels:           5  (LUT4=2 LUT6=3)
  Clock Path Skew:        2.439ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.439ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.257ns (routing 0.690ns, distribution 1.567ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y2           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y2           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[10])
                                                      0.536     0.536 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_COMMON[10]
                         net (fo=1, routed)           0.886     1.422    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/adc2_common_stat[10]
    SLICE_X110Y97        LUT4 (Prop_C6LUT_SLICEM_I0_O)
                                                      0.088     1.510 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_33/O
                         net (fo=1, routed)           0.040     1.550    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_33_n_0
    SLICE_X110Y97        LUT4 (Prop_D6LUT_SLICEM_I0_O)
                                                      0.037     1.587 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_25/O
                         net (fo=1, routed)           0.088     1.675    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_25_n_0
    SLICE_X111Y97        LUT6 (Prop_H6LUT_SLICEL_I2_O)
                                                      0.051     1.726 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_15/O
                         net (fo=1, routed)           0.038     1.764    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_15_n_0
    SLICE_X111Y97        LUT6 (Prop_G6LUT_SLICEL_I4_O)
                                                      0.050     1.814 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_5/O
                         net (fo=1, routed)           0.091     1.905    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_5_n_0
    SLICE_X111Y99        LUT6 (Prop_C6LUT_SLICEL_I4_O)
                                                      0.088     1.993 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_1/O
                         net (fo=1, routed)           0.050     2.043    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_74
    SLICE_X111Y99        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       2.257     2.439    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X111Y99        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC2_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.948ns  (logic 0.356ns (37.553%)  route 0.592ns (62.447%))
  Logic Levels:           5  (LUT4=2 LUT6=3)
  Clock Path Skew:        1.710ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.710ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.563ns (routing 0.463ns, distribution 1.100ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y2           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y2           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[10])
                                                      0.227     0.227 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_COMMON[10]
                         net (fo=1, routed)           0.440     0.667    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/adc2_common_stat[10]
    SLICE_X110Y97        LUT4 (Prop_C6LUT_SLICEM_I0_O)
                                                      0.035     0.702 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_33/O
                         net (fo=1, routed)           0.022     0.724    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_33_n_0
    SLICE_X110Y97        LUT4 (Prop_D6LUT_SLICEM_I0_O)
                                                      0.014     0.738 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_25/O
                         net (fo=1, routed)           0.044     0.782    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_25_n_0
    SLICE_X111Y97        LUT6 (Prop_H6LUT_SLICEL_I2_O)
                                                      0.023     0.805 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_15/O
                         net (fo=1, routed)           0.021     0.826    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_15_n_0
    SLICE_X111Y97        LUT6 (Prop_G6LUT_SLICEL_I4_O)
                                                      0.022     0.848 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_5/O
                         net (fo=1, routed)           0.048     0.896    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_5_n_0
    SLICE_X111Y99        LUT6 (Prop_C6LUT_SLICEL_I4_O)
                                                      0.035     0.931 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_1/O
                         net (fo=1, routed)           0.017     0.948    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_74
    SLICE_X111Y99        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       1.563     1.710    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X111Y99        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC2_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.037ns  (logic 0.377ns (36.355%)  route 0.660ns (63.645%))
  Logic Levels:           5  (LUT4=1 LUT5=1 LUT6=3)
  Clock Path Skew:        1.709ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.709ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.562ns (routing 0.463ns, distribution 1.099ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y2           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y2           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[15])
                                                      0.250     0.250 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_COMMON[15]
                         net (fo=1, routed)           0.366     0.616    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/adc2_common_stat[15]
    SLICE_X117Y93        LUT4 (Prop_F6LUT_SLICEL_I2_O)
                                                      0.035     0.651 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_83/O
                         net (fo=1, routed)           0.022     0.673    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_83_n_0
    SLICE_X117Y93        LUT5 (Prop_H6LUT_SLICEL_I2_O)
                                                      0.023     0.696 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_56/O
                         net (fo=1, routed)           0.156     0.852    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_56_n_0
    SLICE_X114Y95        LUT6 (Prop_D6LUT_SLICEL_I2_O)
                                                      0.014     0.866 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_25/O
                         net (fo=1, routed)           0.023     0.889    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_25_n_0
    SLICE_X114Y95        LUT6 (Prop_H6LUT_SLICEL_I3_O)
                                                      0.041     0.930 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_6/O
                         net (fo=1, routed)           0.069     0.999    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_6_n_0
    SLICE_X113Y95        LUT6 (Prop_C6LUT_SLICEM_I4_O)
                                                      0.014     1.013 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_1/O
                         net (fo=1, routed)           0.024     1.037    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_69
    SLICE_X113Y95        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       1.562     1.709    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X113Y95        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC2_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.083ns  (logic 0.386ns (35.642%)  route 0.697ns (64.358%))
  Logic Levels:           4  (LUT5=1 LUT6=3)
  Clock Path Skew:        1.709ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.709ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.562ns (routing 0.463ns, distribution 1.099ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y2           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y2           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[9])
                                                      0.228     0.228 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_COMMON[9]
                         net (fo=1, routed)           0.445     0.673    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/adc2_common_stat[9]
    SLICE_X112Y98        LUT5 (Prop_B6LUT_SLICEM_I4_O)
                                                      0.035     0.708 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_39/O
                         net (fo=1, routed)           0.052     0.760    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_39_n_0
    SLICE_X112Y97        LUT6 (Prop_F6LUT_SLICEM_I3_O)
                                                      0.050     0.810 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_20/O
                         net (fo=1, routed)           0.123     0.933    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_20_n_0
    SLICE_X114Y97        LUT6 (Prop_C6LUT_SLICEL_I3_O)
                                                      0.014     0.947 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_6/O
                         net (fo=1, routed)           0.053     1.000    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_6_n_0
    SLICE_X113Y97        LUT6 (Prop_F6LUT_SLICEM_I4_O)
                                                      0.059     1.059 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_1/O
                         net (fo=1, routed)           0.024     1.083    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_75
    SLICE_X113Y97        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       1.562     1.709    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X113Y97        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC2_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.105ns  (logic 0.427ns (38.643%)  route 0.678ns (61.357%))
  Logic Levels:           4  (LUT3=1 LUT6=3)
  Clock Path Skew:        1.704ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.704ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.557ns (routing 0.463ns, distribution 1.094ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y2           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y2           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[12])
                                                      0.274     0.274 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_COMMON[12]
                         net (fo=1, routed)           0.465     0.739    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/adc2_common_stat[12]
    SLICE_X112Y96        LUT6 (Prop_D6LUT_SLICEM_I1_O)
                                                      0.035     0.774 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_26/O
                         net (fo=1, routed)           0.057     0.831    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_26_n_0
    SLICE_X113Y96        LUT6 (Prop_H6LUT_SLICEM_I1_O)
                                                      0.023     0.854 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_13/O
                         net (fo=1, routed)           0.025     0.879    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_13_n_0
    SLICE_X113Y96        LUT3 (Prop_E6LUT_SLICEM_I0_O)
                                                      0.035     0.914 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_5/O
                         net (fo=1, routed)           0.114     1.028    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_5_n_0
    SLICE_X111Y98        LUT6 (Prop_H6LUT_SLICEL_I4_O)
                                                      0.060     1.088 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_1/O
                         net (fo=1, routed)           0.017     1.105    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_72
    SLICE_X111Y98        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       1.557     1.704    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X111Y98        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC2_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.153ns  (logic 0.436ns (37.814%)  route 0.717ns (62.186%))
  Logic Levels:           5  (LUT4=1 LUT5=1 LUT6=3)
  Clock Path Skew:        1.709ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.709ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.562ns (routing 0.463ns, distribution 1.099ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y2           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y2           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[14])
                                                      0.285     0.285 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_COMMON[14]
                         net (fo=1, routed)           0.398     0.683    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/adc2_common_stat[14]
    SLICE_X117Y93        LUT4 (Prop_G6LUT_SLICEL_I2_O)
                                                      0.060     0.743 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_60/O
                         net (fo=1, routed)           0.115     0.858    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_60_n_0
    SLICE_X115Y93        LUT5 (Prop_G6LUT_SLICEM_I2_O)
                                                      0.014     0.872 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_46/O
                         net (fo=1, routed)           0.085     0.957    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_46_n_0
    SLICE_X113Y93        LUT6 (Prop_H6LUT_SLICEM_I2_O)
                                                      0.041     0.998 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_21/O
                         net (fo=1, routed)           0.049     1.047    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_21_n_0
    SLICE_X113Y95        LUT6 (Prop_G6LUT_SLICEM_I4_O)
                                                      0.014     1.061 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_6/O
                         net (fo=1, routed)           0.044     1.105    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_6_n_0
    SLICE_X113Y95        LUT6 (Prop_D6LUT_SLICEM_I5_O)
                                                      0.022     1.127 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_1/O
                         net (fo=1, routed)           0.026     1.153    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_70
    SLICE_X113Y95        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       1.562     1.709    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X113Y95        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC2_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.191ns  (logic 0.439ns (36.860%)  route 0.752ns (63.140%))
  Logic Levels:           5  (LUT4=2 LUT6=3)
  Clock Path Skew:        1.706ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.706ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.559ns (routing 0.463ns, distribution 1.096ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y2           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y2           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[11])
                                                      0.265     0.265 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_COMMON[11]
                         net (fo=1, routed)           0.428     0.693    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/adc2_common_stat[11]
    SLICE_X110Y97        LUT4 (Prop_A6LUT_SLICEM_I0_O)
                                                      0.060     0.753 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_37/O
                         net (fo=1, routed)           0.024     0.777    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_37_n_0
    SLICE_X110Y97        LUT4 (Prop_B6LUT_SLICEM_I0_O)
                                                      0.035     0.812 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_29/O
                         net (fo=1, routed)           0.085     0.897    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_29_n_0
    SLICE_X112Y97        LUT6 (Prop_H6LUT_SLICEM_I2_O)
                                                      0.035     0.932 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_16/O
                         net (fo=1, routed)           0.056     0.988    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_16_n_0
    SLICE_X113Y97        LUT6 (Prop_E6LUT_SLICEM_I4_O)
                                                      0.022     1.010 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_5/O
                         net (fo=1, routed)           0.143     1.153    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_5_n_0
    SLICE_X111Y100       LUT6 (Prop_D6LUT_SLICEL_I4_O)
                                                      0.022     1.175 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_1/O
                         net (fo=1, routed)           0.016     1.191    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_73
    SLICE_X111Y100       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       1.559     1.706    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X111Y100       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC2_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.234ns  (logic 0.481ns (38.979%)  route 0.753ns (61.021%))
  Logic Levels:           5  (LUT4=2 LUT6=3)
  Clock Path Skew:        1.715ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.715ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.568ns (routing 0.463ns, distribution 1.105ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y2           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y2           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[8])
                                                      0.237     0.237 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_COMMON[8]
                         net (fo=1, routed)           0.427     0.664    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/adc2_common_stat[8]
    SLICE_X112Y98        LUT4 (Prop_E6LUT_SLICEM_I0_O)
                                                      0.059     0.723 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_31/O
                         net (fo=1, routed)           0.049     0.772    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_31_n_0
    SLICE_X112Y98        LUT4 (Prop_F6LUT_SLICEM_I0_O)
                                                      0.050     0.822 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_24/O
                         net (fo=1, routed)           0.049     0.871    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_24_n_0
    SLICE_X112Y97        LUT6 (Prop_G6LUT_SLICEM_I2_O)
                                                      0.050     0.921 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_14/O
                         net (fo=1, routed)           0.088     1.009    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_14_n_0
    SLICE_X115Y97        LUT6 (Prop_C6LUT_SLICEM_I4_O)
                                                      0.050     1.059 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_5/O
                         net (fo=1, routed)           0.116     1.175    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_5_n_0
    SLICE_X110Y99        LUT6 (Prop_C6LUT_SLICEM_I4_O)
                                                      0.035     1.210 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_1/O
                         net (fo=1, routed)           0.024     1.234    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_76
    SLICE_X110Y99        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       1.568     1.715    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X110Y99        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC2_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.286ns  (logic 0.458ns (35.614%)  route 0.828ns (64.386%))
  Logic Levels:           5  (LUT4=1 LUT5=1 LUT6=3)
  Clock Path Skew:        1.700ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.700ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.553ns (routing 0.463ns, distribution 1.090ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y2           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y2           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[13])
                                                      0.241     0.241 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_COMMON[13]
                         net (fo=1, routed)           0.445     0.686    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/adc2_common_stat[13]
    SLICE_X110Y96        LUT4 (Prop_B6LUT_SLICEM_I0_O)
                                                      0.060     0.746 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_56/O
                         net (fo=1, routed)           0.050     0.796    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_56_n_0
    SLICE_X110Y96        LUT5 (Prop_C6LUT_SLICEM_I0_O)
                                                      0.050     0.846 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_39/O
                         net (fo=1, routed)           0.125     0.971    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_39_n_0
    SLICE_X114Y96        LUT6 (Prop_G6LUT_SLICEL_I5_O)
                                                      0.050     1.021 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_16/O
                         net (fo=1, routed)           0.044     1.065    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_16_n_0
    SLICE_X114Y96        LUT6 (Prop_D6LUT_SLICEL_I3_O)
                                                      0.022     1.087 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_5/O
                         net (fo=1, routed)           0.138     1.225    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_5_n_0
    SLICE_X109Y97        LUT6 (Prop_D6LUT_SLICEM_I4_O)
                                                      0.035     1.260 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_1/O
                         net (fo=1, routed)           0.026     1.286    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_71
    SLICE_X109Y97        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       1.553     1.700    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X109Y97        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  RFADC3_CLK
  To Clock:  clk_pl_0

Max Delay             8 Endpoints
Min Delay             8 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC3_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.117ns  (logic 1.200ns (38.499%)  route 1.917ns (61.501%))
  Logic Levels:           5  (LUT4=1 LUT5=1 LUT6=3)
  Clock Path Skew:        2.443ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.443ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.261ns (routing 0.690ns, distribution 1.571ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC3_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y3           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y3           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[8])
                                                      0.788     0.788 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/STATUS_COMMON[8]
                         net (fo=1, routed)           1.164     1.952    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/adc3_common_stat[8]
    SLICE_X117Y100       LUT4 (Prop_B6LUT_SLICEL_I0_O)
                                                      0.051     2.003 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_29/O
                         net (fo=1, routed)           0.095     2.098    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_29_n_0
    SLICE_X117Y100       LUT5 (Prop_F6LUT_SLICEL_I0_O)
                                                      0.097     2.195 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_22/O
                         net (fo=1, routed)           0.087     2.282    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_22_n_0
    SLICE_X117Y100       LUT6 (Prop_C6LUT_SLICEL_I2_O)
                                                      0.088     2.370 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_12/O
                         net (fo=1, routed)           0.276     2.646    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_12_n_0
    SLICE_X115Y97        LUT6 (Prop_C6LUT_SLICEM_I2_O)
                                                      0.088     2.734 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_5/O
                         net (fo=1, routed)           0.229     2.963    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_5_n_0
    SLICE_X110Y99        LUT6 (Prop_C6LUT_SLICEM_I4_O)
                                                      0.088     3.051 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_1/O
                         net (fo=1, routed)           0.066     3.117    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_76
    SLICE_X110Y99        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       2.261     2.443    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X110Y99        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC3_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.997ns  (logic 1.010ns (33.700%)  route 1.987ns (66.300%))
  Logic Levels:           5  (LUT4=1 LUT5=1 LUT6=3)
  Clock Path Skew:        2.435ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.435ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.253ns (routing 0.690ns, distribution 1.563ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC3_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y3           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y3           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[11])
                                                      0.588     0.588 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/STATUS_COMMON[11]
                         net (fo=1, routed)           1.160     1.748    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/adc3_common_stat[11]
    SLICE_X117Y101       LUT4 (Prop_F6LUT_SLICEL_I0_O)
                                                      0.035     1.783 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_36/O
                         net (fo=1, routed)           0.088     1.871    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_36_n_0
    SLICE_X117Y100       LUT5 (Prop_G6LUT_SLICEL_I3_O)
                                                      0.123     1.994 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_27/O
                         net (fo=1, routed)           0.093     2.087    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_27_n_0
    SLICE_X117Y101       LUT6 (Prop_G6LUT_SLICEL_I2_O)
                                                      0.123     2.210 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_14/O
                         net (fo=1, routed)           0.273     2.483    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_14_n_0
    SLICE_X113Y97        LUT6 (Prop_E6LUT_SLICEM_I2_O)
                                                      0.091     2.574 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_5/O
                         net (fo=1, routed)           0.324     2.898    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_5_n_0
    SLICE_X111Y100       LUT6 (Prop_D6LUT_SLICEL_I4_O)
                                                      0.050     2.948 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_1/O
                         net (fo=1, routed)           0.049     2.997    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_73
    SLICE_X111Y100       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       2.253     2.435    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X111Y100       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC3_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.961ns  (logic 1.031ns (34.819%)  route 1.930ns (65.181%))
  Logic Levels:           5  (LUT4=1 LUT5=1 LUT6=3)
  Clock Path Skew:        2.439ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.439ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.257ns (routing 0.690ns, distribution 1.567ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC3_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y3           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y3           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[10])
                                                      0.536     0.536 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/STATUS_COMMON[10]
                         net (fo=1, routed)           1.306     1.842    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/adc3_common_stat[10]
    SLICE_X117Y99        LUT4 (Prop_G6LUT_SLICEL_I0_O)
                                                      0.089     1.931 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_32/O
                         net (fo=1, routed)           0.043     1.974    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_32_n_0
    SLICE_X117Y99        LUT5 (Prop_H6LUT_SLICEL_I3_O)
                                                      0.099     2.073 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_23/O
                         net (fo=1, routed)           0.091     2.164    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_23_n_0
    SLICE_X117Y100       LUT6 (Prop_D6LUT_SLICEL_I2_O)
                                                      0.122     2.286 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_13/O
                         net (fo=1, routed)           0.349     2.635    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_13_n_0
    SLICE_X111Y97        LUT6 (Prop_G6LUT_SLICEL_I2_O)
                                                      0.097     2.732 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_5/O
                         net (fo=1, routed)           0.091     2.823    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_5_n_0
    SLICE_X111Y99        LUT6 (Prop_C6LUT_SLICEL_I4_O)
                                                      0.088     2.911 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_1/O
                         net (fo=1, routed)           0.050     2.961    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_74
    SLICE_X111Y99        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       2.257     2.439    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X111Y99        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC3_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.950ns  (logic 1.119ns (37.932%)  route 1.831ns (62.068%))
  Logic Levels:           4  (LUT5=1 LUT6=3)
  Clock Path Skew:        2.424ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.424ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.242ns (routing 0.690ns, distribution 1.552ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC3_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y3           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y3           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[13])
                                                      0.771     0.771 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/STATUS_COMMON[13]
                         net (fo=1, routed)           1.282     2.053    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/adc3_common_stat[13]
    SLICE_X115Y100       LUT5 (Prop_D6LUT_SLICEM_I4_O)
                                                      0.037     2.090 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_40/O
                         net (fo=1, routed)           0.045     2.135    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_40_n_0
    SLICE_X115Y100       LUT6 (Prop_H6LUT_SLICEM_I0_O)
                                                      0.101     2.236 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_17/O
                         net (fo=1, routed)           0.163     2.399    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_17_n_0
    SLICE_X114Y96        LUT6 (Prop_D6LUT_SLICEL_I5_O)
                                                      0.122     2.521 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_5/O
                         net (fo=1, routed)           0.269     2.790    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_5_n_0
    SLICE_X109Y97        LUT6 (Prop_D6LUT_SLICEM_I4_O)
                                                      0.088     2.878 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_1/O
                         net (fo=1, routed)           0.072     2.950    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_71
    SLICE_X109Y97        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       2.242     2.424    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X109Y97        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC3_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.890ns  (logic 0.998ns (34.533%)  route 1.892ns (65.467%))
  Logic Levels:           4  (LUT5=1 LUT6=3)
  Clock Path Skew:        2.436ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.436ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.254ns (routing 0.690ns, distribution 1.564ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC3_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y3           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y3           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[14])
                                                      0.698     0.698 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/STATUS_COMMON[14]
                         net (fo=1, routed)           1.215     1.913    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/adc3_common_stat[14]
    SLICE_X118Y98        LUT5 (Prop_G6LUT_SLICEM_I4_O)
                                                      0.100     2.013 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_43/O
                         net (fo=1, routed)           0.235     2.248    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_43_n_0
    SLICE_X116Y98        LUT6 (Prop_G6LUT_SLICEL_I3_O)
                                                      0.097     2.345 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_19/O
                         net (fo=1, routed)           0.280     2.625    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_19_n_0
    SLICE_X113Y95        LUT6 (Prop_G6LUT_SLICEM_I0_O)
                                                      0.052     2.677 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_6/O
                         net (fo=1, routed)           0.090     2.767    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_6_n_0
    SLICE_X113Y95        LUT6 (Prop_D6LUT_SLICEM_I5_O)
                                                      0.051     2.818 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_1/O
                         net (fo=1, routed)           0.072     2.890    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_70
    SLICE_X113Y95        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       2.254     2.436    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X113Y95        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC3_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.883ns  (logic 0.992ns (34.409%)  route 1.891ns (65.591%))
  Logic Levels:           4  (LUT5=1 LUT6=3)
  Clock Path Skew:        2.436ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.436ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.254ns (routing 0.690ns, distribution 1.564ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC3_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y3           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y3           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[15])
                                                      0.525     0.525 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/STATUS_COMMON[15]
                         net (fo=1, routed)           1.334     1.859    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/adc3_common_stat[15]
    SLICE_X115Y99        LUT5 (Prop_F6LUT_SLICEM_I4_O)
                                                      0.148     2.007 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_45/O
                         net (fo=1, routed)           0.130     2.137    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_45_n_0
    SLICE_X116Y98        LUT6 (Prop_F6LUT_SLICEL_I2_O)
                                                      0.097     2.234 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_21/O
                         net (fo=1, routed)           0.163     2.397    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_21_n_0
    SLICE_X116Y95        LUT6 (Prop_H6LUT_SLICEL_I0_O)
                                                      0.124     2.521 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_5/O
                         net (fo=1, routed)           0.198     2.719    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_5_n_0
    SLICE_X113Y95        LUT6 (Prop_C6LUT_SLICEM_I3_O)
                                                      0.098     2.817 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_1/O
                         net (fo=1, routed)           0.066     2.883    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_69
    SLICE_X113Y95        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       2.254     2.436    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X113Y95        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC3_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.738ns  (logic 1.046ns (38.203%)  route 1.692ns (61.797%))
  Logic Levels:           4  (LUT5=2 LUT6=2)
  Clock Path Skew:        2.431ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.431ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.249ns (routing 0.690ns, distribution 1.559ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC3_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y3           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y3           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[12])
                                                      0.611     0.611 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/STATUS_COMMON[12]
                         net (fo=1, routed)           1.272     1.883    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/adc3_common_stat[12]
    SLICE_X115Y101       LUT5 (Prop_D6LUT_SLICEM_I3_O)
                                                      0.122     2.005 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_34/O
                         net (fo=1, routed)           0.045     2.050    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_34_n_0
    SLICE_X115Y101       LUT6 (Prop_H6LUT_SLICEM_I5_O)
                                                      0.101     2.151 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_18/O
                         net (fo=1, routed)           0.041     2.192    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_18_n_0
    SLICE_X115Y101       LUT5 (Prop_F6LUT_SLICEM_I2_O)
                                                      0.088     2.280 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_6/O
                         net (fo=1, routed)           0.283     2.563    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_6_n_0
    SLICE_X111Y98        LUT6 (Prop_H6LUT_SLICEL_I5_O)
                                                      0.124     2.687 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_1/O
                         net (fo=1, routed)           0.051     2.738    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_72
    SLICE_X111Y98        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       2.249     2.431    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X111Y98        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC3_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.538ns  (logic 0.913ns (35.973%)  route 1.625ns (64.027%))
  Logic Levels:           4  (LUT5=2 LUT6=2)
  Clock Path Skew:        2.437ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.437ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.255ns (routing 0.690ns, distribution 1.565ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC3_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y3           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y3           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[9])
                                                      0.532     0.532 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/STATUS_COMMON[9]
                         net (fo=1, routed)           1.229     1.761    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/adc3_common_stat[9]
    SLICE_X116Y101       LUT5 (Prop_B6LUT_SLICEL_I4_O)
                                                      0.148     1.909 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_36/O
                         net (fo=1, routed)           0.045     1.954    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_36_n_0
    SLICE_X116Y101       LUT6 (Prop_G6LUT_SLICEL_I4_O)
                                                      0.097     2.051 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_17/O
                         net (fo=1, routed)           0.046     2.097    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_17_n_0
    SLICE_X116Y101       LUT5 (Prop_E6LUT_SLICEL_I3_O)
                                                      0.099     2.196 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_5/O
                         net (fo=1, routed)           0.238     2.434    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_5_n_0
    SLICE_X113Y97        LUT6 (Prop_F6LUT_SLICEM_I3_O)
                                                      0.037     2.471 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_1/O
                         net (fo=1, routed)           0.067     2.538    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_75
    SLICE_X113Y97        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       2.255     2.437    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X113Y97        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC3_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.194ns  (logic 0.383ns (32.077%)  route 0.811ns (67.923%))
  Logic Levels:           4  (LUT5=2 LUT6=2)
  Clock Path Skew:        1.709ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.709ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.562ns (routing 0.463ns, distribution 1.099ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC3_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y3           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y3           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[9])
                                                      0.228     0.228 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/STATUS_COMMON[9]
                         net (fo=1, routed)           0.614     0.842    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/adc3_common_stat[9]
    SLICE_X116Y101       LUT5 (Prop_B6LUT_SLICEL_I4_O)
                                                      0.060     0.902 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_36/O
                         net (fo=1, routed)           0.025     0.927    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_36_n_0
    SLICE_X116Y101       LUT6 (Prop_G6LUT_SLICEL_I4_O)
                                                      0.040     0.967 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_17/O
                         net (fo=1, routed)           0.025     0.992    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_17_n_0
    SLICE_X116Y101       LUT5 (Prop_E6LUT_SLICEL_I3_O)
                                                      0.041     1.033 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_5/O
                         net (fo=1, routed)           0.123     1.156    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_5_n_0
    SLICE_X113Y97        LUT6 (Prop_F6LUT_SLICEM_I3_O)
                                                      0.014     1.170 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_1/O
                         net (fo=1, routed)           0.024     1.194    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_75
    SLICE_X113Y97        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       1.562     1.709    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X113Y97        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC3_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.291ns  (logic 0.450ns (34.857%)  route 0.841ns (65.143%))
  Logic Levels:           4  (LUT5=2 LUT6=2)
  Clock Path Skew:        1.704ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.704ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.557ns (routing 0.463ns, distribution 1.094ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC3_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y3           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y3           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[12])
                                                      0.274     0.274 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/STATUS_COMMON[12]
                         net (fo=1, routed)           0.633     0.907    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/adc3_common_stat[12]
    SLICE_X115Y101       LUT5 (Prop_D6LUT_SLICEM_I3_O)
                                                      0.050     0.957 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_34/O
                         net (fo=1, routed)           0.025     0.982    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_34_n_0
    SLICE_X115Y101       LUT6 (Prop_H6LUT_SLICEM_I5_O)
                                                      0.041     1.023 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_18/O
                         net (fo=1, routed)           0.024     1.047    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_18_n_0
    SLICE_X115Y101       LUT5 (Prop_F6LUT_SLICEM_I2_O)
                                                      0.035     1.082 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_6/O
                         net (fo=1, routed)           0.142     1.224    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_6_n_0
    SLICE_X111Y98        LUT6 (Prop_H6LUT_SLICEL_I5_O)
                                                      0.050     1.274 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_1/O
                         net (fo=1, routed)           0.017     1.291    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_72
    SLICE_X111Y98        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       1.557     1.704    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X111Y98        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC3_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.303ns  (logic 0.381ns (29.240%)  route 0.922ns (70.760%))
  Logic Levels:           4  (LUT5=1 LUT6=3)
  Clock Path Skew:        1.700ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.700ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.553ns (routing 0.463ns, distribution 1.090ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC3_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y3           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y3           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[13])
                                                      0.241     0.241 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/STATUS_COMMON[13]
                         net (fo=1, routed)           0.646     0.887    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/adc3_common_stat[13]
    SLICE_X115Y100       LUT5 (Prop_D6LUT_SLICEM_I4_O)
                                                      0.014     0.901 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_40/O
                         net (fo=1, routed)           0.025     0.926    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_40_n_0
    SLICE_X115Y100       LUT6 (Prop_H6LUT_SLICEM_I0_O)
                                                      0.041     0.967 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_17/O
                         net (fo=1, routed)           0.087     1.054    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_17_n_0
    SLICE_X114Y96        LUT6 (Prop_D6LUT_SLICEL_I5_O)
                                                      0.050     1.104 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_5/O
                         net (fo=1, routed)           0.138     1.242    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_5_n_0
    SLICE_X109Y97        LUT6 (Prop_D6LUT_SLICEM_I4_O)
                                                      0.035     1.277 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_1/O
                         net (fo=1, routed)           0.026     1.303    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_71
    SLICE_X109Y97        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       1.553     1.700    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X109Y97        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC3_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.347ns  (logic 0.409ns (30.364%)  route 0.938ns (69.636%))
  Logic Levels:           4  (LUT5=1 LUT6=3)
  Clock Path Skew:        1.709ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.709ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.562ns (routing 0.463ns, distribution 1.099ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC3_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y3           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y3           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[14])
                                                      0.285     0.285 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/STATUS_COMMON[14]
                         net (fo=1, routed)           0.607     0.892    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/adc3_common_stat[14]
    SLICE_X118Y98        LUT5 (Prop_G6LUT_SLICEM_I4_O)
                                                      0.040     0.932 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_43/O
                         net (fo=1, routed)           0.117     1.049    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_43_n_0
    SLICE_X116Y98        LUT6 (Prop_G6LUT_SLICEL_I3_O)
                                                      0.040     1.089 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_19/O
                         net (fo=1, routed)           0.144     1.233    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_19_n_0
    SLICE_X113Y95        LUT6 (Prop_G6LUT_SLICEM_I0_O)
                                                      0.022     1.255 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_6/O
                         net (fo=1, routed)           0.044     1.299    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_6_n_0
    SLICE_X113Y95        LUT6 (Prop_D6LUT_SLICEM_I5_O)
                                                      0.022     1.321 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_1/O
                         net (fo=1, routed)           0.026     1.347    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_70
    SLICE_X113Y95        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       1.562     1.709    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X113Y95        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC3_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.354ns  (logic 0.405ns (29.911%)  route 0.949ns (70.089%))
  Logic Levels:           5  (LUT4=1 LUT5=1 LUT6=3)
  Clock Path Skew:        1.715ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.715ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.568ns (routing 0.463ns, distribution 1.105ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC3_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y3           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y3           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[8])
                                                      0.237     0.237 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/STATUS_COMMON[8]
                         net (fo=1, routed)           0.580     0.817    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/adc3_common_stat[8]
    SLICE_X117Y100       LUT4 (Prop_B6LUT_SLICEL_I0_O)
                                                      0.023     0.840 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_29/O
                         net (fo=1, routed)           0.046     0.886    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_29_n_0
    SLICE_X117Y100       LUT5 (Prop_F6LUT_SLICEL_I0_O)
                                                      0.040     0.926 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_22/O
                         net (fo=1, routed)           0.041     0.967    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_22_n_0
    SLICE_X117Y100       LUT6 (Prop_C6LUT_SLICEL_I2_O)
                                                      0.035     1.002 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_12/O
                         net (fo=1, routed)           0.142     1.144    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_12_n_0
    SLICE_X115Y97        LUT6 (Prop_C6LUT_SLICEM_I2_O)
                                                      0.035     1.179 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_5/O
                         net (fo=1, routed)           0.116     1.295    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_5_n_0
    SLICE_X110Y99        LUT6 (Prop_C6LUT_SLICEM_I4_O)
                                                      0.035     1.330 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_1/O
                         net (fo=1, routed)           0.024     1.354    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_76
    SLICE_X110Y99        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       1.568     1.715    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X110Y99        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC3_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.387ns  (logic 0.439ns (31.651%)  route 0.948ns (68.349%))
  Logic Levels:           4  (LUT5=1 LUT6=3)
  Clock Path Skew:        1.709ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.709ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.562ns (routing 0.463ns, distribution 1.099ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC3_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y3           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y3           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[15])
                                                      0.250     0.250 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/STATUS_COMMON[15]
                         net (fo=1, routed)           0.675     0.925    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/adc3_common_stat[15]
    SLICE_X115Y99        LUT5 (Prop_F6LUT_SLICEM_I4_O)
                                                      0.059     0.984 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_45/O
                         net (fo=1, routed)           0.068     1.052    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_45_n_0
    SLICE_X116Y98        LUT6 (Prop_F6LUT_SLICEL_I2_O)
                                                      0.040     1.092 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_21/O
                         net (fo=1, routed)           0.082     1.174    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_21_n_0
    SLICE_X116Y95        LUT6 (Prop_H6LUT_SLICEL_I0_O)
                                                      0.050     1.224 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_5/O
                         net (fo=1, routed)           0.099     1.323    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_5_n_0
    SLICE_X113Y95        LUT6 (Prop_C6LUT_SLICEM_I3_O)
                                                      0.040     1.363 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_1/O
                         net (fo=1, routed)           0.024     1.387    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_69
    SLICE_X113Y95        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       1.562     1.709    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X113Y95        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC3_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.388ns  (logic 0.428ns (30.836%)  route 0.960ns (69.164%))
  Logic Levels:           5  (LUT4=1 LUT5=1 LUT6=3)
  Clock Path Skew:        1.710ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.710ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.563ns (routing 0.463ns, distribution 1.100ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC3_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y3           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y3           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[10])
                                                      0.227     0.227 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/STATUS_COMMON[10]
                         net (fo=1, routed)           0.641     0.868    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/adc3_common_stat[10]
    SLICE_X117Y99        LUT4 (Prop_G6LUT_SLICEL_I0_O)
                                                      0.035     0.903 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_32/O
                         net (fo=1, routed)           0.024     0.927    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_32_n_0
    SLICE_X117Y99        LUT5 (Prop_H6LUT_SLICEL_I3_O)
                                                      0.041     0.968 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_23/O
                         net (fo=1, routed)           0.049     1.017    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_23_n_0
    SLICE_X117Y100       LUT6 (Prop_D6LUT_SLICEL_I2_O)
                                                      0.050     1.067 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_13/O
                         net (fo=1, routed)           0.181     1.248    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_13_n_0
    SLICE_X111Y97        LUT6 (Prop_G6LUT_SLICEL_I2_O)
                                                      0.040     1.288 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_5/O
                         net (fo=1, routed)           0.048     1.336    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_5_n_0
    SLICE_X111Y99        LUT6 (Prop_C6LUT_SLICEL_I4_O)
                                                      0.035     1.371 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_1/O
                         net (fo=1, routed)           0.017     1.388    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_74
    SLICE_X111Y99        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       1.563     1.710    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X111Y99        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC3_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.414ns  (logic 0.436ns (30.835%)  route 0.978ns (69.165%))
  Logic Levels:           5  (LUT4=1 LUT5=1 LUT6=3)
  Clock Path Skew:        1.706ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.706ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.559ns (routing 0.463ns, distribution 1.096ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC3_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y3           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y3           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[11])
                                                      0.265     0.265 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/STATUS_COMMON[11]
                         net (fo=1, routed)           0.578     0.843    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/adc3_common_stat[11]
    SLICE_X117Y101       LUT4 (Prop_F6LUT_SLICEL_I0_O)
                                                      0.014     0.857 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_36/O
                         net (fo=1, routed)           0.049     0.906    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_36_n_0
    SLICE_X117Y100       LUT5 (Prop_G6LUT_SLICEL_I3_O)
                                                      0.050     0.956 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_27/O
                         net (fo=1, routed)           0.051     1.007    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_27_n_0
    SLICE_X117Y101       LUT6 (Prop_G6LUT_SLICEL_I2_O)
                                                      0.050     1.057 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_14/O
                         net (fo=1, routed)           0.141     1.198    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_14_n_0
    SLICE_X113Y97        LUT6 (Prop_E6LUT_SLICEM_I2_O)
                                                      0.035     1.233 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_5/O
                         net (fo=1, routed)           0.143     1.376    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_5_n_0
    SLICE_X111Y100       LUT6 (Prop_D6LUT_SLICEL_I4_O)
                                                      0.022     1.398 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_1/O
                         net (fo=1, routed)           0.016     1.414    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_73
    SLICE_X111Y100       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       1.559     1.706    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X111Y100       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  RFDAC0_CLK
  To Clock:  clk_pl_0

Max Delay           132 Endpoints
Min Delay           132 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/cdc_dac0_clk_valid_i/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.872ns  (logic 0.079ns (9.055%)  route 0.793ns (90.945%))
  Logic Levels:           0  
  Clock Path Skew:        -0.925ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.385ns
    Source Clock Delay      (SCD):    3.310ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.637ns (routing 1.490ns, distribution 1.147ns)
  Clock Net Delay (Destination): 2.203ns (routing 0.690ns, distribution 1.513ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=5276, routed)        2.637     3.310    d_1_i/rst_dac0/U0/slowest_sync_clk
    SLICE_X92Y170        FDRE                                         r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X92Y170        FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.079     3.389 r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=10, routed)          0.793     4.182    d_1_i/usp_rf_data_converter_0/inst/cdc_dac0_clk_valid_i/src_in
    SLICE_X106Y135       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/cdc_dac0_clk_valid_i/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       2.203     2.385    d_1_i/usp_rf_data_converter_0/inst/cdc_dac0_clk_valid_i/dest_clk
    SLICE_X106Y135       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/cdc_dac0_clk_valid_i/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell HSDAC clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.670ns  (logic 1.213ns (33.052%)  route 2.457ns (66.948%))
  Logic Levels:           5  (LUT4=1 LUT6=4)
  Clock Path Skew:        2.436ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.436ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.254ns (routing 0.690ns, distribution 1.564ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[15])
                                                      0.840     0.840 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/STATUS_COMMON[15]
                         net (fo=1, routed)           1.756     2.596    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/dac0_common_stat[15]
    SLICE_X116Y106       LUT4 (Prop_E6LUT_SLICEL_I0_O)
                                                      0.051     2.647 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_59/O
                         net (fo=1, routed)           0.137     2.784    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_59_n_0
    SLICE_X115Y106       LUT6 (Prop_H6LUT_SLICEM_I2_O)
                                                      0.101     2.885 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_27/O
                         net (fo=1, routed)           0.042     2.927    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_27_n_0
    SLICE_X115Y106       LUT6 (Prop_G6LUT_SLICEM_I2_O)
                                                      0.037     2.964 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_9/O
                         net (fo=1, routed)           0.094     3.058    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_9_n_0
    SLICE_X115Y104       LUT6 (Prop_H6LUT_SLICEM_I2_O)
                                                      0.039     3.097 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_2/O
                         net (fo=1, routed)           0.362     3.459    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_2_n_0
    SLICE_X113Y95        LUT6 (Prop_C6LUT_SLICEM_I0_O)
                                                      0.145     3.604 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_1/O
                         net (fo=1, routed)           0.066     3.670    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_69
    SLICE_X113Y95        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       2.254     2.436    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X113Y95        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell HSDAC clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.525ns  (logic 1.307ns (37.078%)  route 2.218ns (62.922%))
  Logic Levels:           3  (LUT4=1 LUT5=1 LUT6=1)
  Clock Path Skew:        2.424ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.424ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.242ns (routing 0.690ns, distribution 1.552ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[13])
                                                      1.059     1.059 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/STATUS_COMMON[13]
                         net (fo=1, routed)           1.699     2.758    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/dac0_common_stat[13]
    SLICE_X111Y108       LUT5 (Prop_C6LUT_SLICEL_I4_O)
                                                      0.123     2.881 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_9/O
                         net (fo=1, routed)           0.084     2.965    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_9_n_0
    SLICE_X110Y107       LUT4 (Prop_F6LUT_SLICEM_I3_O)
                                                      0.088     3.053 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_2/O
                         net (fo=1, routed)           0.363     3.416    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_2_n_0
    SLICE_X109Y97        LUT6 (Prop_D6LUT_SLICEM_I0_O)
                                                      0.037     3.453 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_1/O
                         net (fo=1, routed)           0.072     3.525    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_71
    SLICE_X109Y97        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       2.242     2.424    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X109Y97        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell HSDAC clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.379ns  (logic 1.140ns (33.738%)  route 2.239ns (66.262%))
  Logic Levels:           4  (LUT5=2 LUT6=2)
  Clock Path Skew:        2.436ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.436ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.254ns (routing 0.690ns, distribution 1.564ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[14])
                                                      0.779     0.779 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/STATUS_COMMON[14]
                         net (fo=1, routed)           1.697     2.476    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/dac0_common_stat[14]
    SLICE_X114Y107       LUT5 (Prop_H6LUT_SLICEL_I4_O)
                                                      0.099     2.575 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_31/O
                         net (fo=1, routed)           0.038     2.613    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_31_n_0
    SLICE_X114Y107       LUT5 (Prop_G6LUT_SLICEL_I2_O)
                                                      0.050     2.663 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_9/O
                         net (fo=1, routed)           0.145     2.808    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_9_n_0
    SLICE_X115Y105       LUT6 (Prop_H6LUT_SLICEM_I2_O)
                                                      0.090     2.898 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_2/O
                         net (fo=1, routed)           0.287     3.185    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_2_n_0
    SLICE_X113Y95        LUT6 (Prop_D6LUT_SLICEM_I0_O)
                                                      0.122     3.307 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_1/O
                         net (fo=1, routed)           0.072     3.379    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_70
    SLICE_X113Y95        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       2.254     2.436    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X113Y95        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell HSDAC clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.265ns  (logic 1.085ns (33.231%)  route 2.180ns (66.769%))
  Logic Levels:           4  (LUT5=1 LUT6=3)
  Clock Path Skew:        2.431ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.431ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.249ns (routing 0.690ns, distribution 1.559ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[12])
                                                      0.759     0.759 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/STATUS_COMMON[12]
                         net (fo=1, routed)           1.723     2.482    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/dac0_common_stat[12]
    SLICE_X110Y106       LUT5 (Prop_C6LUT_SLICEM_I4_O)
                                                      0.098     2.580 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_21/O
                         net (fo=1, routed)           0.040     2.620    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_21_n_0
    SLICE_X110Y106       LUT6 (Prop_D6LUT_SLICEM_I5_O)
                                                      0.037     2.657 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_9/O
                         net (fo=1, routed)           0.045     2.702    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_9_n_0
    SLICE_X110Y106       LUT6 (Prop_H6LUT_SLICEM_I4_O)
                                                      0.101     2.803 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_2/O
                         net (fo=1, routed)           0.321     3.124    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_2_n_0
    SLICE_X111Y98        LUT6 (Prop_H6LUT_SLICEL_I0_O)
                                                      0.090     3.214 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_1/O
                         net (fo=1, routed)           0.051     3.265    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_72
    SLICE_X111Y98        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       2.249     2.431    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X111Y98        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell HSDAC clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.226ns  (logic 1.000ns (30.998%)  route 2.226ns (69.002%))
  Logic Levels:           4  (LUT5=2 LUT6=2)
  Clock Path Skew:        2.437ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.437ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.255ns (routing 0.690ns, distribution 1.565ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[9])
                                                      0.674     0.674 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/STATUS_COMMON[9]
                         net (fo=1, routed)           1.715     2.389    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/dac0_common_stat[9]
    SLICE_X113Y108       LUT5 (Prop_C6LUT_SLICEM_I4_O)
                                                      0.051     2.440 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_26/O
                         net (fo=1, routed)           0.092     2.532    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_26_n_0
    SLICE_X113Y107       LUT5 (Prop_E6LUT_SLICEM_I2_O)
                                                      0.124     2.656 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_9/O
                         net (fo=1, routed)           0.192     2.848    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_9_n_0
    SLICE_X113Y103       LUT6 (Prop_G6LUT_SLICEM_I3_O)
                                                      0.100     2.948 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_2/O
                         net (fo=1, routed)           0.160     3.108    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_2_n_0
    SLICE_X113Y97        LUT6 (Prop_F6LUT_SLICEM_I0_O)
                                                      0.051     3.159 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_1/O
                         net (fo=1, routed)           0.067     3.226    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_75
    SLICE_X113Y97        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       2.255     2.437    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X113Y97        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell HSDAC clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.036ns  (logic 0.900ns (29.644%)  route 2.136ns (70.356%))
  Logic Levels:           3  (LUT5=1 LUT6=2)
  Clock Path Skew:        2.443ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.443ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.261ns (routing 0.690ns, distribution 1.571ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[8])
                                                      0.731     0.731 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/STATUS_COMMON[8]
                         net (fo=1, routed)           1.695     2.426    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/dac0_common_stat[8]
    SLICE_X111Y107       LUT5 (Prop_C6LUT_SLICEL_I4_O)
                                                      0.096     2.522 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_7/O
                         net (fo=1, routed)           0.041     2.563    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_7_n_0
    SLICE_X111Y107       LUT6 (Prop_D6LUT_SLICEL_I4_O)
                                                      0.036     2.599 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_2/O
                         net (fo=1, routed)           0.334     2.933    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_2_n_0
    SLICE_X110Y99        LUT6 (Prop_C6LUT_SLICEM_I0_O)
                                                      0.037     2.970 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_1/O
                         net (fo=1, routed)           0.066     3.036    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_76
    SLICE_X110Y99        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       2.261     2.443    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X110Y99        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell HSDAC clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.033ns  (logic 1.007ns (33.201%)  route 2.026ns (66.799%))
  Logic Levels:           3  (LUT5=1 LUT6=2)
  Clock Path Skew:        2.435ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.435ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.253ns (routing 0.690ns, distribution 1.563ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[11])
                                                      0.753     0.753 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/STATUS_COMMON[11]
                         net (fo=1, routed)           1.667     2.420    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/dac0_common_stat[11]
    SLICE_X111Y108       LUT5 (Prop_E6LUT_SLICEL_I4_O)
                                                      0.035     2.455 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_8/O
                         net (fo=1, routed)           0.091     2.546    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_8_n_0
    SLICE_X111Y108       LUT6 (Prop_G6LUT_SLICEL_I4_O)
                                                      0.097     2.643 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_2/O
                         net (fo=1, routed)           0.219     2.862    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_2_n_0
    SLICE_X111Y100       LUT6 (Prop_D6LUT_SLICEL_I0_O)
                                                      0.122     2.984 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_1/O
                         net (fo=1, routed)           0.049     3.033    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_73
    SLICE_X111Y100       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       2.253     2.435    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X111Y100       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell HSDAC clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.009ns  (logic 0.972ns (32.303%)  route 2.037ns (67.697%))
  Logic Levels:           3  (LUT5=1 LUT6=2)
  Clock Path Skew:        2.439ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.439ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.257ns (routing 0.690ns, distribution 1.567ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[10])
                                                      0.753     0.753 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/STATUS_COMMON[10]
                         net (fo=1, routed)           1.725     2.478    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/dac0_common_stat[10]
    SLICE_X111Y108       LUT5 (Prop_F6LUT_SLICEL_I4_O)
                                                      0.148     2.626 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_6/O
                         net (fo=1, routed)           0.039     2.665    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_6_n_0
    SLICE_X111Y108       LUT6 (Prop_H6LUT_SLICEL_I2_O)
                                                      0.036     2.701 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_2/O
                         net (fo=1, routed)           0.223     2.924    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_2_n_0
    SLICE_X111Y99        LUT6 (Prop_C6LUT_SLICEL_I0_O)
                                                      0.035     2.959 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_1/O
                         net (fo=1, routed)           0.050     3.009    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_74
    SLICE_X111Y99        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       2.257     2.439    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X111Y99        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[0]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/AXI_DB.xreg_TPROC_DEBUG_reg[27]/D
                            (rising edge-triggered cell FDCE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.186ns  (logic 0.116ns (9.777%)  route 1.070ns (90.223%))
  Logic Levels:           1  (LUT5=1)
  Clock Path Skew:        -1.087ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.183ns
    Source Clock Delay      (SCD):    3.270ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.597ns (routing 1.490ns, distribution 1.107ns)
  Clock Net Delay (Destination): 2.001ns (routing 0.690ns, distribution 1.311ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=5276, routed)        2.597     3.270    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
    SLICE_X81Y157        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y157        FDCE (Prop_HFF2_SLICEL_C_Q)
                                                      0.080     3.350 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[0]/Q
                         net (fo=3, routed)           1.019     4.369    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/fifo_mem/trig_0_o
    SLICE_X68Y129        LUT5 (Prop_H6LUT_SLICEL_I2_O)
                                                      0.036     4.405 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/fifo_mem/AXI_DB.xreg_TPROC_DEBUG[27]_i_1/O
                         net (fo=1, routed)           0.051     4.456    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER_n_163
    SLICE_X68Y129        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/AXI_DB.xreg_TPROC_DEBUG_reg[27]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       2.001     2.183    d_1_i/qick_processor_0/inst/QPROC/ps_clk_i
    SLICE_X68Y129        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/AXI_DB.xreg_TPROC_DEBUG_reg[27]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell HSDAC clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.484ns  (logic 0.471ns (31.739%)  route 1.013ns (68.261%))
  Logic Levels:           3  (LUT5=1 LUT6=2)
  Clock Path Skew:        1.706ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.706ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.559ns (routing 0.463ns, distribution 1.096ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[11])
                                                      0.367     0.367 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/STATUS_COMMON[11]
                         net (fo=1, routed)           0.840     1.207    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/dac0_common_stat[11]
    SLICE_X111Y108       LUT5 (Prop_E6LUT_SLICEL_I4_O)
                                                      0.014     1.221 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_8/O
                         net (fo=1, routed)           0.044     1.265    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_8_n_0
    SLICE_X111Y108       LUT6 (Prop_G6LUT_SLICEL_I4_O)
                                                      0.040     1.305 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_2/O
                         net (fo=1, routed)           0.113     1.418    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_2_n_0
    SLICE_X111Y100       LUT6 (Prop_D6LUT_SLICEL_I0_O)
                                                      0.050     1.468 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_1/O
                         net (fo=1, routed)           0.016     1.484    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_73
    SLICE_X111Y100       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       1.559     1.706    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X111Y100       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell HSDAC clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.485ns  (logic 0.463ns (31.178%)  route 1.022ns (68.822%))
  Logic Levels:           3  (LUT5=1 LUT6=2)
  Clock Path Skew:        1.710ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.710ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.563ns (routing 0.463ns, distribution 1.100ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[10])
                                                      0.375     0.375 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/STATUS_COMMON[10]
                         net (fo=1, routed)           0.867     1.242    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/dac0_common_stat[10]
    SLICE_X111Y108       LUT5 (Prop_F6LUT_SLICEL_I4_O)
                                                      0.059     1.301 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_6/O
                         net (fo=1, routed)           0.021     1.322    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_6_n_0
    SLICE_X111Y108       LUT6 (Prop_H6LUT_SLICEL_I2_O)
                                                      0.015     1.337 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_2/O
                         net (fo=1, routed)           0.117     1.454    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_2_n_0
    SLICE_X111Y99        LUT6 (Prop_C6LUT_SLICEL_I0_O)
                                                      0.014     1.468 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_1/O
                         net (fo=1, routed)           0.017     1.485    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_74
    SLICE_X111Y99        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       1.563     1.710    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X111Y99        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell HSDAC clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.518ns  (logic 0.450ns (29.644%)  route 1.068ns (70.356%))
  Logic Levels:           3  (LUT5=1 LUT6=2)
  Clock Path Skew:        1.715ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.715ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.568ns (routing 0.463ns, distribution 1.105ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[8])
                                                      0.382     0.382 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/STATUS_COMMON[8]
                         net (fo=1, routed)           0.854     1.236    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/dac0_common_stat[8]
    SLICE_X111Y107       LUT5 (Prop_C6LUT_SLICEL_I4_O)
                                                      0.040     1.276 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_7/O
                         net (fo=1, routed)           0.022     1.298    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_7_n_0
    SLICE_X111Y107       LUT6 (Prop_D6LUT_SLICEL_I4_O)
                                                      0.014     1.312 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_2/O
                         net (fo=1, routed)           0.168     1.480    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_2_n_0
    SLICE_X110Y99        LUT6 (Prop_C6LUT_SLICEM_I0_O)
                                                      0.014     1.494 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_1/O
                         net (fo=1, routed)           0.024     1.518    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_76
    SLICE_X110Y99        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       1.568     1.715    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X110Y99        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell HSDAC clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.592ns  (logic 0.471ns (29.585%)  route 1.121ns (70.415%))
  Logic Levels:           4  (LUT5=2 LUT6=2)
  Clock Path Skew:        1.709ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.709ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.562ns (routing 0.463ns, distribution 1.099ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[9])
                                                      0.338     0.338 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/STATUS_COMMON[9]
                         net (fo=1, routed)           0.862     1.200    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/dac0_common_stat[9]
    SLICE_X113Y108       LUT5 (Prop_C6LUT_SLICEM_I4_O)
                                                      0.022     1.222 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_26/O
                         net (fo=1, routed)           0.050     1.272    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_26_n_0
    SLICE_X113Y107       LUT5 (Prop_E6LUT_SLICEM_I2_O)
                                                      0.049     1.321 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_9/O
                         net (fo=1, routed)           0.100     1.421    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_9_n_0
    SLICE_X113Y103       LUT6 (Prop_G6LUT_SLICEM_I3_O)
                                                      0.040     1.461 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_2/O
                         net (fo=1, routed)           0.085     1.546    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_2_n_0
    SLICE_X113Y97        LUT6 (Prop_F6LUT_SLICEM_I0_O)
                                                      0.022     1.568 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_1/O
                         net (fo=1, routed)           0.024     1.592    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_75
    SLICE_X113Y97        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       1.562     1.709    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X113Y97        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell HSDAC clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.618ns  (logic 0.516ns (31.891%)  route 1.102ns (68.109%))
  Logic Levels:           4  (LUT5=1 LUT6=3)
  Clock Path Skew:        1.704ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.704ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.557ns (routing 0.463ns, distribution 1.094ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[12])
                                                      0.386     0.386 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/STATUS_COMMON[12]
                         net (fo=1, routed)           0.869     1.255    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/dac0_common_stat[12]
    SLICE_X110Y106       LUT5 (Prop_C6LUT_SLICEM_I4_O)
                                                      0.040     1.295 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_21/O
                         net (fo=1, routed)           0.022     1.317    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_21_n_0
    SLICE_X110Y106       LUT6 (Prop_D6LUT_SLICEM_I5_O)
                                                      0.014     1.331 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_9/O
                         net (fo=1, routed)           0.025     1.356    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_9_n_0
    SLICE_X110Y106       LUT6 (Prop_H6LUT_SLICEM_I4_O)
                                                      0.041     1.397 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_2/O
                         net (fo=1, routed)           0.169     1.566    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_2_n_0
    SLICE_X111Y98        LUT6 (Prop_H6LUT_SLICEL_I0_O)
                                                      0.035     1.601 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_1/O
                         net (fo=1, routed)           0.017     1.618    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_72
    SLICE_X111Y98        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       1.557     1.704    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X111Y98        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell HSDAC clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.663ns  (logic 0.546ns (32.832%)  route 1.117ns (67.168%))
  Logic Levels:           4  (LUT5=2 LUT6=2)
  Clock Path Skew:        1.709ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.709ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.562ns (routing 0.463ns, distribution 1.099ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[14])
                                                      0.398     0.398 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/STATUS_COMMON[14]
                         net (fo=1, routed)           0.846     1.244    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/dac0_common_stat[14]
    SLICE_X114Y107       LUT5 (Prop_H6LUT_SLICEL_I4_O)
                                                      0.041     1.285 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_31/O
                         net (fo=1, routed)           0.021     1.306    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_31_n_0
    SLICE_X114Y107       LUT5 (Prop_G6LUT_SLICEL_I2_O)
                                                      0.022     1.328 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_9/O
                         net (fo=1, routed)           0.077     1.405    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_9_n_0
    SLICE_X115Y105       LUT6 (Prop_H6LUT_SLICEM_I2_O)
                                                      0.035     1.440 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_2/O
                         net (fo=1, routed)           0.147     1.587    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_2_n_0
    SLICE_X113Y95        LUT6 (Prop_D6LUT_SLICEM_I0_O)
                                                      0.050     1.637 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_1/O
                         net (fo=1, routed)           0.026     1.663    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_70
    SLICE_X113Y95        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       1.562     1.709    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X113Y95        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell HSDAC clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.732ns  (logic 0.623ns (35.970%)  route 1.109ns (64.030%))
  Logic Levels:           3  (LUT4=1 LUT5=1 LUT6=1)
  Clock Path Skew:        1.700ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.700ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.553ns (routing 0.463ns, distribution 1.090ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[13])
                                                      0.524     0.524 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/STATUS_COMMON[13]
                         net (fo=1, routed)           0.853     1.377    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/dac0_common_stat[13]
    SLICE_X111Y108       LUT5 (Prop_C6LUT_SLICEL_I4_O)
                                                      0.050     1.427 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_9/O
                         net (fo=1, routed)           0.044     1.471    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_9_n_0
    SLICE_X110Y107       LUT4 (Prop_F6LUT_SLICEM_I3_O)
                                                      0.035     1.506 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_2/O
                         net (fo=1, routed)           0.186     1.692    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_2_n_0
    SLICE_X109Y97        LUT6 (Prop_D6LUT_SLICEM_I0_O)
                                                      0.014     1.706 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_1/O
                         net (fo=1, routed)           0.026     1.732    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_71
    SLICE_X109Y97        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       1.553     1.700    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X109Y97        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell HSDAC clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.767ns  (logic 0.564ns (31.919%)  route 1.203ns (68.081%))
  Logic Levels:           5  (LUT4=1 LUT6=4)
  Clock Path Skew:        1.709ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.709ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.562ns (routing 0.463ns, distribution 1.099ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[15])
                                                      0.413     0.413 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/STATUS_COMMON[15]
                         net (fo=1, routed)           0.855     1.268    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/dac0_common_stat[15]
    SLICE_X116Y106       LUT4 (Prop_E6LUT_SLICEL_I0_O)
                                                      0.022     1.290 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_59/O
                         net (fo=1, routed)           0.069     1.359    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_59_n_0
    SLICE_X115Y106       LUT6 (Prop_H6LUT_SLICEM_I2_O)
                                                      0.041     1.400 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_27/O
                         net (fo=1, routed)           0.024     1.424    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_27_n_0
    SLICE_X115Y106       LUT6 (Prop_G6LUT_SLICEM_I2_O)
                                                      0.014     1.438 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_9/O
                         net (fo=1, routed)           0.051     1.489    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_9_n_0
    SLICE_X115Y104       LUT6 (Prop_H6LUT_SLICEM_I2_O)
                                                      0.015     1.504 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_2/O
                         net (fo=1, routed)           0.180     1.684    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_2_n_0
    SLICE_X113Y95        LUT6 (Prop_C6LUT_SLICEM_I0_O)
                                                      0.059     1.743 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_1/O
                         net (fo=1, routed)           0.024     1.767    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_69
    SLICE_X113Y95        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       1.562     1.709    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X113Y95        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/C

Slack:                    inf
  Source:                 d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/cdc_dac0_clk_valid_i/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.426ns  (logic 0.039ns (9.160%)  route 0.387ns (90.841%))
  Logic Levels:           0  
  Clock Path Skew:        -0.125ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.663ns
    Source Clock Delay      (SCD):    1.788ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.439ns (routing 0.805ns, distribution 0.634ns)
  Clock Net Delay (Destination): 1.516ns (routing 0.463ns, distribution 1.053ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=5276, routed)        1.439     1.788    d_1_i/rst_dac0/U0/slowest_sync_clk
    SLICE_X92Y170        FDRE                                         r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X92Y170        FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.039     1.827 r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=10, routed)          0.387     2.213    d_1_i/usp_rf_data_converter_0/inst/cdc_dac0_clk_valid_i/src_in
    SLICE_X106Y135       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/cdc_dac0_clk_valid_i/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       1.516     1.663    d_1_i/usp_rf_data_converter_0/inst/cdc_dac0_clk_valid_i/dest_clk
    SLICE_X106Y135       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/cdc_dac0_clk_valid_i/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/QPER_TIME_READ.t_time_abs_cdc_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/QPER_TIME_READ.c_time_abs_r_reg[3]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.099ns  (logic 0.039ns (39.394%)  route 0.060ns (60.606%))
  Logic Levels:           0  
  Clock Path Skew:        -0.173ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.535ns
    Source Clock Delay      (SCD):    1.709ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.360ns (routing 0.805ns, distribution 0.555ns)
  Clock Net Delay (Destination): 1.388ns (routing 0.463ns, distribution 0.925ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=5276, routed)        1.360     1.709    d_1_i/qick_processor_0/inst/QPROC/t_clk_i
    SLICE_X73Y132        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPER_TIME_READ.t_time_abs_cdc_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X73Y132        FDRE (Prop_CFF_SLICEL_C_Q)
                                                      0.039     1.748 r  d_1_i/qick_processor_0/inst/QPROC/QPER_TIME_READ.t_time_abs_cdc_reg[3]/Q
                         net (fo=1, routed)           0.060     1.808    d_1_i/qick_processor_0/inst/QPROC/t_time_abs_cdc[3]
    SLICE_X73Y132        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPER_TIME_READ.c_time_abs_r_reg[3]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       1.388     1.535    d_1_i/qick_processor_0/inst/QPROC/c_clk_i
    SLICE_X73Y132        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPER_TIME_READ.c_time_abs_r_reg[3]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  RFDAC1_CLK
  To Clock:  clk_pl_0

Max Delay             8 Endpoints
Min Delay             8 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell HSDAC clocked by RFDAC1_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        4.253ns  (logic 1.530ns (35.975%)  route 2.723ns (64.025%))
  Logic Levels:           4  (LUT5=1 LUT6=3)
  Clock Path Skew:        2.424ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.424ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.242ns (routing 0.690ns, distribution 1.552ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[13])
                                                      1.059     1.059 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[13]
                         net (fo=1, routed)           2.174     3.233    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/dac1_common_stat[13]
    SLICE_X111Y103       LUT5 (Prop_D6LUT_SLICEL_I4_O)
                                                      0.146     3.379 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_30/O
                         net (fo=1, routed)           0.088     3.467    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_30_n_0
    SLICE_X111Y103       LUT6 (Prop_H6LUT_SLICEL_I5_O)
                                                      0.051     3.518 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_11/O
                         net (fo=1, routed)           0.176     3.694    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_11_n_0
    SLICE_X109Y104       LUT6 (Prop_H6LUT_SLICEM_I1_O)
                                                      0.152     3.846 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_3/O
                         net (fo=1, routed)           0.213     4.059    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_3_n_0
    SLICE_X109Y97        LUT6 (Prop_D6LUT_SLICEM_I1_O)
                                                      0.122     4.181 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_1/O
                         net (fo=1, routed)           0.072     4.253    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_71
    SLICE_X109Y97        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       2.242     2.424    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X109Y97        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell HSDAC clocked by RFDAC1_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        4.099ns  (logic 1.214ns (29.617%)  route 2.885ns (70.383%))
  Logic Levels:           4  (LUT6=4)
  Clock Path Skew:        2.436ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.436ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.254ns (routing 0.690ns, distribution 1.564ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[14])
                                                      0.779     0.779 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[14]
                         net (fo=1, routed)           2.180     2.959    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/dac1_common_stat[14]
    SLICE_X114Y104       LUT6 (Prop_H6LUT_SLICEL_I0_O)
                                                      0.124     3.083 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_35/O
                         net (fo=1, routed)           0.145     3.228    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_35_n_0
    SLICE_X113Y104       LUT6 (Prop_D6LUT_SLICEM_I1_O)
                                                      0.088     3.316 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_12/O
                         net (fo=1, routed)           0.201     3.517    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_12_n_0
    SLICE_X115Y105       LUT6 (Prop_H6LUT_SLICEM_I5_O)
                                                      0.101     3.618 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_2/O
                         net (fo=1, routed)           0.287     3.905    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_2_n_0
    SLICE_X113Y95        LUT6 (Prop_D6LUT_SLICEM_I0_O)
                                                      0.122     4.027 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_1/O
                         net (fo=1, routed)           0.072     4.099    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_70
    SLICE_X113Y95        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       2.254     2.436    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X113Y95        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell HSDAC clocked by RFDAC1_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        4.090ns  (logic 1.121ns (27.408%)  route 2.969ns (72.592%))
  Logic Levels:           4  (LUT5=1 LUT6=3)
  Clock Path Skew:        2.443ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.443ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.261ns (routing 0.690ns, distribution 1.571ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[8])
                                                      0.731     0.731 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[8]
                         net (fo=1, routed)           2.238     2.969    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/dac1_common_stat[8]
    SLICE_X115Y107       LUT5 (Prop_G6LUT_SLICEM_I4_O)
                                                      0.150     3.119 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_16/O
                         net (fo=1, routed)           0.355     3.474    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_16_n_0
    SLICE_X109Y106       LUT6 (Prop_A6LUT_SLICEM_I5_O)
                                                      0.100     3.574 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_9/O
                         net (fo=1, routed)           0.044     3.618    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_9_n_0
    SLICE_X109Y106       LUT6 (Prop_B6LUT_SLICEM_I4_O)
                                                      0.089     3.707 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_3/O
                         net (fo=1, routed)           0.266     3.973    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_3_n_0
    SLICE_X110Y99        LUT6 (Prop_C6LUT_SLICEM_I1_O)
                                                      0.051     4.024 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_1/O
                         net (fo=1, routed)           0.066     4.090    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_76
    SLICE_X110Y99        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       2.261     2.443    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X110Y99        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell HSDAC clocked by RFDAC1_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        4.054ns  (logic 1.138ns (28.071%)  route 2.916ns (71.929%))
  Logic Levels:           4  (LUT5=1 LUT6=3)
  Clock Path Skew:        2.439ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.439ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.257ns (routing 0.690ns, distribution 1.567ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[10])
                                                      0.753     0.753 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[10]
                         net (fo=1, routed)           2.095     2.848    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/dac1_common_stat[10]
    SLICE_X115Y107       LUT5 (Prop_B6LUT_SLICEM_I4_O)
                                                      0.089     2.937 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_17/O
                         net (fo=1, routed)           0.368     3.305    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_17_n_0
    SLICE_X109Y107       LUT6 (Prop_B6LUT_SLICEM_I5_O)
                                                      0.149     3.454 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_9/O
                         net (fo=1, routed)           0.093     3.547    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_9_n_0
    SLICE_X109Y107       LUT6 (Prop_C6LUT_SLICEM_I4_O)
                                                      0.051     3.598 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_3/O
                         net (fo=1, routed)           0.310     3.908    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_3_n_0
    SLICE_X111Y99        LUT6 (Prop_C6LUT_SLICEL_I1_O)
                                                      0.096     4.004 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_1/O
                         net (fo=1, routed)           0.050     4.054    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_74
    SLICE_X111Y99        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       2.257     2.439    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X111Y99        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell HSDAC clocked by RFDAC1_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.943ns  (logic 1.078ns (27.340%)  route 2.865ns (72.660%))
  Logic Levels:           4  (LUT5=1 LUT6=3)
  Clock Path Skew:        2.431ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.431ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.249ns (routing 0.690ns, distribution 1.559ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[12])
                                                      0.759     0.759 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[12]
                         net (fo=1, routed)           2.216     2.975    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/dac1_common_stat[12]
    SLICE_X109Y106       LUT5 (Prop_H6LUT_SLICEM_I4_O)
                                                      0.053     3.028 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_20/O
                         net (fo=1, routed)           0.085     3.113    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_20_n_0
    SLICE_X109Y106       LUT6 (Prop_C6LUT_SLICEM_I5_O)
                                                      0.051     3.164 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_8/O
                         net (fo=1, routed)           0.192     3.356    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_8_n_0
    SLICE_X110Y106       LUT6 (Prop_H6LUT_SLICEM_I2_O)
                                                      0.125     3.481 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_2/O
                         net (fo=1, routed)           0.321     3.802    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_2_n_0
    SLICE_X111Y98        LUT6 (Prop_H6LUT_SLICEL_I0_O)
                                                      0.090     3.892 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_1/O
                         net (fo=1, routed)           0.051     3.943    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_72
    SLICE_X111Y98        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       2.249     2.431    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X111Y98        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell HSDAC clocked by RFDAC1_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.875ns  (logic 1.226ns (31.639%)  route 2.649ns (68.361%))
  Logic Levels:           4  (LUT3=1 LUT6=3)
  Clock Path Skew:        2.436ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.436ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.254ns (routing 0.690ns, distribution 1.564ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[15])
                                                      0.840     0.840 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[15]
                         net (fo=1, routed)           2.134     2.974    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/dac1_common_stat[15]
    SLICE_X115Y104       LUT6 (Prop_C6LUT_SLICEM_I1_O)
                                                      0.051     3.025 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_30/O
                         net (fo=1, routed)           0.039     3.064    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_30_n_0
    SLICE_X115Y104       LUT3 (Prop_B6LUT_SLICEM_I0_O)
                                                      0.089     3.153 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_11/O
                         net (fo=1, routed)           0.048     3.201    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_11_n_0
    SLICE_X115Y104       LUT6 (Prop_H6LUT_SLICEM_I4_O)
                                                      0.101     3.302 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_2/O
                         net (fo=1, routed)           0.362     3.664    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_2_n_0
    SLICE_X113Y95        LUT6 (Prop_C6LUT_SLICEM_I0_O)
                                                      0.145     3.809 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_1/O
                         net (fo=1, routed)           0.066     3.875    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_69
    SLICE_X113Y95        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       2.254     2.436    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X113Y95        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell HSDAC clocked by RFDAC1_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.801ns  (logic 1.098ns (28.887%)  route 2.703ns (71.113%))
  Logic Levels:           5  (LUT4=2 LUT6=3)
  Clock Path Skew:        2.437ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.437ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.255ns (routing 0.690ns, distribution 1.565ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[9])
                                                      0.674     0.674 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[9]
                         net (fo=1, routed)           2.142     2.816    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/dac1_common_stat[9]
    SLICE_X111Y104       LUT4 (Prop_E6LUT_SLICEL_I0_O)
                                                      0.123     2.939 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_46/O
                         net (fo=1, routed)           0.097     3.036    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_46_n_0
    SLICE_X111Y104       LUT4 (Prop_F6LUT_SLICEL_I2_O)
                                                      0.123     3.159 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_29/O
                         net (fo=1, routed)           0.040     3.199    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_29_n_0
    SLICE_X111Y104       LUT6 (Prop_H6LUT_SLICEL_I5_O)
                                                      0.090     3.289 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_11/O
                         net (fo=1, routed)           0.197     3.486    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_11_n_0
    SLICE_X113Y103       LUT6 (Prop_G6LUT_SLICEM_I5_O)
                                                      0.037     3.523 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_2/O
                         net (fo=1, routed)           0.160     3.683    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_2_n_0
    SLICE_X113Y97        LUT6 (Prop_F6LUT_SLICEM_I0_O)
                                                      0.051     3.734 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_1/O
                         net (fo=1, routed)           0.067     3.801    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_75
    SLICE_X113Y97        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       2.255     2.437    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X113Y97        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell HSDAC clocked by RFDAC1_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.529ns  (logic 0.931ns (26.381%)  route 2.598ns (73.619%))
  Logic Levels:           3  (LUT6=3)
  Clock Path Skew:        2.435ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.435ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.253ns (routing 0.690ns, distribution 1.563ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[11])
                                                      0.753     0.753 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[11]
                         net (fo=1, routed)           2.206     2.959    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/dac1_common_stat[11]
    SLICE_X110Y107       LUT6 (Prop_H6LUT_SLICEM_I0_O)
                                                      0.090     3.049 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_11/O
                         net (fo=1, routed)           0.097     3.146    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_11_n_0
    SLICE_X112Y107       LUT6 (Prop_G6LUT_SLICEM_I4_O)
                                                      0.052     3.198 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_3/O
                         net (fo=1, routed)           0.246     3.444    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_3_n_0
    SLICE_X111Y100       LUT6 (Prop_D6LUT_SLICEL_I1_O)
                                                      0.036     3.480 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_1/O
                         net (fo=1, routed)           0.049     3.529    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_73
    SLICE_X111Y100       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       2.253     2.435    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X111Y100       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell HSDAC clocked by RFDAC1_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.752ns  (logic 0.438ns (25.000%)  route 1.314ns (75.000%))
  Logic Levels:           3  (LUT6=3)
  Clock Path Skew:        1.706ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.706ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.559ns (routing 0.463ns, distribution 1.096ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[11])
                                                      0.367     0.367 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[11]
                         net (fo=1, routed)           1.118     1.485    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/dac1_common_stat[11]
    SLICE_X110Y107       LUT6 (Prop_H6LUT_SLICEM_I0_O)
                                                      0.035     1.520 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_11/O
                         net (fo=1, routed)           0.051     1.571    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_11_n_0
    SLICE_X112Y107       LUT6 (Prop_G6LUT_SLICEM_I4_O)
                                                      0.022     1.593 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_3/O
                         net (fo=1, routed)           0.129     1.722    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_3_n_0
    SLICE_X111Y100       LUT6 (Prop_D6LUT_SLICEL_I1_O)
                                                      0.014     1.736 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_1/O
                         net (fo=1, routed)           0.016     1.752    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_73
    SLICE_X111Y100       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       1.559     1.706    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X111Y100       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell HSDAC clocked by RFDAC1_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.871ns  (logic 0.509ns (27.205%)  route 1.362ns (72.795%))
  Logic Levels:           5  (LUT4=2 LUT6=3)
  Clock Path Skew:        1.709ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.709ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.562ns (routing 0.463ns, distribution 1.099ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[9])
                                                      0.338     0.338 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[9]
                         net (fo=1, routed)           1.083     1.421    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/dac1_common_stat[9]
    SLICE_X111Y104       LUT4 (Prop_E6LUT_SLICEL_I0_O)
                                                      0.050     1.471 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_46/O
                         net (fo=1, routed)           0.048     1.519    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_46_n_0
    SLICE_X111Y104       LUT4 (Prop_F6LUT_SLICEL_I2_O)
                                                      0.050     1.569 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_29/O
                         net (fo=1, routed)           0.022     1.591    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_29_n_0
    SLICE_X111Y104       LUT6 (Prop_H6LUT_SLICEL_I5_O)
                                                      0.035     1.626 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_11/O
                         net (fo=1, routed)           0.100     1.726    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_11_n_0
    SLICE_X113Y103       LUT6 (Prop_G6LUT_SLICEM_I5_O)
                                                      0.014     1.740 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_2/O
                         net (fo=1, routed)           0.085     1.825    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_2_n_0
    SLICE_X113Y97        LUT6 (Prop_F6LUT_SLICEM_I0_O)
                                                      0.022     1.847 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_1/O
                         net (fo=1, routed)           0.024     1.871    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_75
    SLICE_X113Y97        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       1.562     1.709    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X113Y97        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell HSDAC clocked by RFDAC1_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.899ns  (logic 0.570ns (30.016%)  route 1.329ns (69.984%))
  Logic Levels:           4  (LUT3=1 LUT6=3)
  Clock Path Skew:        1.709ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.709ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.562ns (routing 0.463ns, distribution 1.099ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[15])
                                                      0.413     0.413 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[15]
                         net (fo=1, routed)           1.076     1.489    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/dac1_common_stat[15]
    SLICE_X115Y104       LUT6 (Prop_C6LUT_SLICEM_I1_O)
                                                      0.022     1.511 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_30/O
                         net (fo=1, routed)           0.022     1.533    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_30_n_0
    SLICE_X115Y104       LUT3 (Prop_B6LUT_SLICEM_I0_O)
                                                      0.035     1.568 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_11/O
                         net (fo=1, routed)           0.027     1.595    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_11_n_0
    SLICE_X115Y104       LUT6 (Prop_H6LUT_SLICEM_I4_O)
                                                      0.041     1.636 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_2/O
                         net (fo=1, routed)           0.180     1.816    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_2_n_0
    SLICE_X113Y95        LUT6 (Prop_C6LUT_SLICEM_I0_O)
                                                      0.059     1.875 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_1/O
                         net (fo=1, routed)           0.024     1.899    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_69
    SLICE_X113Y95        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       1.562     1.709    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X113Y95        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell HSDAC clocked by RFDAC1_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.960ns  (logic 0.517ns (26.378%)  route 1.443ns (73.622%))
  Logic Levels:           4  (LUT5=1 LUT6=3)
  Clock Path Skew:        1.704ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.704ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.557ns (routing 0.463ns, distribution 1.094ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[12])
                                                      0.386     0.386 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[12]
                         net (fo=1, routed)           1.119     1.505    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/dac1_common_stat[12]
    SLICE_X109Y106       LUT5 (Prop_H6LUT_SLICEM_I4_O)
                                                      0.023     1.528 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_20/O
                         net (fo=1, routed)           0.042     1.570    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_20_n_0
    SLICE_X109Y106       LUT6 (Prop_C6LUT_SLICEM_I5_O)
                                                      0.022     1.592 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_8/O
                         net (fo=1, routed)           0.096     1.688    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_8_n_0
    SLICE_X110Y106       LUT6 (Prop_H6LUT_SLICEM_I2_O)
                                                      0.051     1.739 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_2/O
                         net (fo=1, routed)           0.169     1.908    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_2_n_0
    SLICE_X111Y98        LUT6 (Prop_H6LUT_SLICEL_I0_O)
                                                      0.035     1.943 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_1/O
                         net (fo=1, routed)           0.017     1.960    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_72
    SLICE_X111Y98        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       1.557     1.704    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X111Y98        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell HSDAC clocked by RFDAC1_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        2.000ns  (logic 0.532ns (26.600%)  route 1.468ns (73.400%))
  Logic Levels:           4  (LUT5=1 LUT6=3)
  Clock Path Skew:        1.710ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.710ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.563ns (routing 0.463ns, distribution 1.100ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[10])
                                                      0.375     0.375 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[10]
                         net (fo=1, routed)           1.062     1.437    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/dac1_common_stat[10]
    SLICE_X115Y107       LUT5 (Prop_B6LUT_SLICEM_I4_O)
                                                      0.035     1.472 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_17/O
                         net (fo=1, routed)           0.184     1.656    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_17_n_0
    SLICE_X109Y107       LUT6 (Prop_B6LUT_SLICEM_I5_O)
                                                      0.060     1.716 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_9/O
                         net (fo=1, routed)           0.044     1.760    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_9_n_0
    SLICE_X109Y107       LUT6 (Prop_C6LUT_SLICEM_I4_O)
                                                      0.022     1.782 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_3/O
                         net (fo=1, routed)           0.161     1.943    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_3_n_0
    SLICE_X111Y99        LUT6 (Prop_C6LUT_SLICEL_I1_O)
                                                      0.040     1.983 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_1/O
                         net (fo=1, routed)           0.017     2.000    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_74
    SLICE_X111Y99        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       1.563     1.710    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X111Y99        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell HSDAC clocked by RFDAC1_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        2.019ns  (logic 0.540ns (26.746%)  route 1.479ns (73.254%))
  Logic Levels:           4  (LUT5=1 LUT6=3)
  Clock Path Skew:        1.715ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.715ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.568ns (routing 0.463ns, distribution 1.105ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[8])
                                                      0.382     0.382 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[8]
                         net (fo=1, routed)           1.131     1.513    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/dac1_common_stat[8]
    SLICE_X115Y107       LUT5 (Prop_G6LUT_SLICEM_I4_O)
                                                      0.060     1.573 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_16/O
                         net (fo=1, routed)           0.161     1.734    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_16_n_0
    SLICE_X109Y106       LUT6 (Prop_A6LUT_SLICEM_I5_O)
                                                      0.041     1.775 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_9/O
                         net (fo=1, routed)           0.024     1.799    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_9_n_0
    SLICE_X109Y106       LUT6 (Prop_B6LUT_SLICEM_I4_O)
                                                      0.035     1.834 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_3/O
                         net (fo=1, routed)           0.139     1.973    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_3_n_0
    SLICE_X110Y99        LUT6 (Prop_C6LUT_SLICEM_I1_O)
                                                      0.022     1.995 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_1/O
                         net (fo=1, routed)           0.024     2.019    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_76
    SLICE_X110Y99        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       1.568     1.715    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X110Y99        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell HSDAC clocked by RFDAC1_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        2.021ns  (logic 0.574ns (28.402%)  route 1.447ns (71.598%))
  Logic Levels:           4  (LUT6=4)
  Clock Path Skew:        1.709ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.709ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.562ns (routing 0.463ns, distribution 1.099ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[14])
                                                      0.398     0.398 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[14]
                         net (fo=1, routed)           1.100     1.498    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/dac1_common_stat[14]
    SLICE_X114Y104       LUT6 (Prop_H6LUT_SLICEL_I0_O)
                                                      0.050     1.548 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_35/O
                         net (fo=1, routed)           0.071     1.619    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_35_n_0
    SLICE_X113Y104       LUT6 (Prop_D6LUT_SLICEM_I1_O)
                                                      0.035     1.654 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_12/O
                         net (fo=1, routed)           0.103     1.757    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_12_n_0
    SLICE_X115Y105       LUT6 (Prop_H6LUT_SLICEM_I5_O)
                                                      0.041     1.798 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_2/O
                         net (fo=1, routed)           0.147     1.945    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_2_n_0
    SLICE_X113Y95        LUT6 (Prop_D6LUT_SLICEM_I0_O)
                                                      0.050     1.995 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_1/O
                         net (fo=1, routed)           0.026     2.021    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_70
    SLICE_X113Y95        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       1.562     1.709    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X113Y95        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell HSDAC clocked by RFDAC1_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        2.085ns  (logic 0.717ns (34.388%)  route 1.368ns (65.612%))
  Logic Levels:           4  (LUT5=1 LUT6=3)
  Clock Path Skew:        1.700ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.700ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.553ns (routing 0.463ns, distribution 1.090ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[13])
                                                      0.524     0.524 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[13]
                         net (fo=1, routed)           1.097     1.621    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/dac1_common_stat[13]
    SLICE_X111Y103       LUT5 (Prop_D6LUT_SLICEL_I4_O)
                                                      0.059     1.680 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_30/O
                         net (fo=1, routed)           0.042     1.722    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_30_n_0
    SLICE_X111Y103       LUT6 (Prop_H6LUT_SLICEL_I5_O)
                                                      0.023     1.745 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_11/O
                         net (fo=1, routed)           0.091     1.836    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_11_n_0
    SLICE_X109Y104       LUT6 (Prop_H6LUT_SLICEM_I1_O)
                                                      0.061     1.897 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_3/O
                         net (fo=1, routed)           0.112     2.009    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_3_n_0
    SLICE_X109Y97        LUT6 (Prop_D6LUT_SLICEM_I1_O)
                                                      0.050     2.059 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_1/O
                         net (fo=1, routed)           0.026     2.085    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_71
    SLICE_X109Y97        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       1.553     1.700    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X109Y97        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  clk_out1_d_1_clk_adc0_x2_0
  To Clock:  clk_pl_0

Max Delay            76 Endpoints
Min Delay            76 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/FABRIC_CLK
                            (rising edge-triggered cell HSADC clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[5]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.539ns  (logic 0.934ns (36.786%)  route 1.605ns (63.214%))
  Logic Levels:           4  (LUT4=1 LUT6=3)
  Clock Path Skew:        -4.104ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.437ns
    Source Clock Delay      (SCD):    6.541ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.261ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.343ns
    Phase Error              (PE):    0.086ns
  Clock Net Delay (Source):      3.303ns (routing 1.963ns, distribution 1.340ns)
  Clock Net Delay (Destination): 2.255ns (routing 0.690ns, distribution 1.565ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y18        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=1, routed)           2.565     3.092    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.965 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     3.210    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.238 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=1945, routed)        3.303     6.541    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/m0_axis_aclk
    HSADC_X0Y0           HSADC                                        r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/FABRIC_CLK
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y0           HSADC (Prop_HSADC_FABRIC_CLK_STATUS_COMMON[5])
                                                      0.450     6.991 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/STATUS_COMMON[5]
                         net (fo=1, routed)           1.012     8.003    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_19_0[5]
    SLICE_X110Y86        LUT4 (Prop_C6LUT_SLICEM_I2_O)
                                                      0.123     8.126 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_21/O
                         net (fo=1, routed)           0.059     8.185    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_21_n_0
    SLICE_X110Y86        LUT6 (Prop_F6LUT_SLICEM_I5_O)
                                                      0.148     8.333 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_12/O
                         net (fo=1, routed)           0.245     8.578    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_12_n_0
    SLICE_X110Y95        LUT6 (Prop_G6LUT_SLICEM_I2_O)
                                                      0.090     8.668 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_4/O
                         net (fo=1, routed)           0.230     8.898    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_4_n_0
    SLICE_X113Y97        LUT6 (Prop_G6LUT_SLICEM_I3_O)
                                                      0.123     9.021 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_1/O
                         net (fo=1, routed)           0.059     9.080    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_79
    SLICE_X113Y97        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[5]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       2.255     2.437    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X113Y97        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[5]/C

Slack:                    inf
  Source:                 d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/cdc_adc0_clk_valid_i/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.219ns  (logic 0.079ns (6.482%)  route 1.140ns (93.518%))
  Logic Levels:           0  
  Clock Path Skew:        -3.829ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.394ns
    Source Clock Delay      (SCD):    6.223ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.261ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.343ns
    Phase Error              (PE):    0.086ns
  Clock Net Delay (Source):      2.985ns (routing 1.963ns, distribution 1.022ns)
  Clock Net Delay (Destination): 2.212ns (routing 0.690ns, distribution 1.522ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y18        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=1, routed)           2.565     3.092    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.965 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     3.210    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.238 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=1945, routed)        2.985     6.223    d_1_i/rst_adc0_x2/U0/slowest_sync_clk
    SLICE_X80Y109        FDRE                                         r  d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X80Y109        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     6.302 r  d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=932, routed)         1.140     7.442    d_1_i/usp_rf_data_converter_0/inst/cdc_adc0_clk_valid_i/src_in
    SLICE_X106Y97        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/cdc_adc0_clk_valid_i/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       2.212     2.394    d_1_i/usp_rf_data_converter_0/inst/cdc_adc0_clk_valid_i/dest_clk
    SLICE_X106Y97        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/cdc_adc0_clk_valid_i/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/clr_fifo_req_reg/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/do_push_reg_rep/D
                            (rising edge-triggered cell FDCE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.255ns  (logic 0.204ns (16.257%)  route 1.051ns (83.743%))
  Logic Levels:           1  (LUT5=1)
  Clock Path Skew:        -4.233ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.098ns
    Source Clock Delay      (SCD):    6.331ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.261ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.343ns
    Phase Error              (PE):    0.086ns
  Clock Net Delay (Source):      3.093ns (routing 1.963ns, distribution 1.130ns)
  Clock Net Delay (Destination): 1.916ns (routing 0.690ns, distribution 1.226ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y18        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=1, routed)           2.565     3.092    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.965 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     3.210    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.238 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=1945, routed)        3.093     6.331    d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/adc_clk
    SLICE_X52Y220        FDCE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/clr_fifo_req_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X52Y220        FDCE (Prop_DFF2_SLICEL_C_Q)
                                                      0.081     6.412 f  d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/clr_fifo_req_reg/Q
                         net (fo=7, routed)           1.001     7.413    d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/gcc_rd_ptr/clr_fifo_req
    SLICE_X52Y332        LUT5 (Prop_C6LUT_SLICEL_I1_O)
                                                      0.123     7.536 r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/gcc_rd_ptr/do_push_rep_i_1/O
                         net (fo=1, routed)           0.050     7.586    d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH_n_33
    SLICE_X52Y332        FDCE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/do_push_reg_rep/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       1.916     2.098    d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/ps_clk
    SLICE_X52Y332        FDCE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/do_push_reg_rep/C

Slack:                    inf
  Source:                 d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/clr_fifo_req_reg/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/do_push_reg_rep__0/D
                            (rising edge-triggered cell FDCE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.253ns  (logic 0.203ns (16.204%)  route 1.050ns (83.796%))
  Logic Levels:           1  (LUT5=1)
  Clock Path Skew:        -4.233ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.098ns
    Source Clock Delay      (SCD):    6.331ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.261ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.343ns
    Phase Error              (PE):    0.086ns
  Clock Net Delay (Source):      3.093ns (routing 1.963ns, distribution 1.130ns)
  Clock Net Delay (Destination): 1.916ns (routing 0.690ns, distribution 1.226ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y18        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=1, routed)           2.565     3.092    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.965 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     3.210    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.238 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=1945, routed)        3.093     6.331    d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/adc_clk
    SLICE_X52Y220        FDCE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/clr_fifo_req_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X52Y220        FDCE (Prop_DFF2_SLICEL_C_Q)
                                                      0.081     6.412 f  d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/clr_fifo_req_reg/Q
                         net (fo=7, routed)           1.001     7.413    d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/gcc_rd_ptr/clr_fifo_req
    SLICE_X52Y332        LUT5 (Prop_D6LUT_SLICEL_I1_O)
                                                      0.122     7.535 r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/gcc_rd_ptr/do_push_rep__0_i_1/O
                         net (fo=1, routed)           0.049     7.584    d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH_n_34
    SLICE_X52Y332        FDCE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/do_push_reg_rep__0/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       1.916     2.098    d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/ps_clk
    SLICE_X52Y332        FDCE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/do_push_reg_rep__0/C

Slack:                    inf
  Source:                 d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/clr_fifo_req_reg/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/do_push_reg/D
                            (rising edge-triggered cell FDCE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.974ns  (logic 0.227ns (23.308%)  route 0.747ns (76.692%))
  Logic Levels:           1  (LUT5=1)
  Clock Path Skew:        -4.238ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.093ns
    Source Clock Delay      (SCD):    6.331ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.261ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.343ns
    Phase Error              (PE):    0.086ns
  Clock Net Delay (Source):      3.093ns (routing 1.963ns, distribution 1.130ns)
  Clock Net Delay (Destination): 1.911ns (routing 0.690ns, distribution 1.221ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y18        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=1, routed)           2.565     3.092    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.965 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     3.210    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.238 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=1945, routed)        3.093     6.331    d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/adc_clk
    SLICE_X52Y220        FDCE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/clr_fifo_req_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X52Y220        FDCE (Prop_DFF2_SLICEL_C_Q)
                                                      0.081     6.412 f  d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/clr_fifo_req_reg/Q
                         net (fo=7, routed)           0.698     7.110    d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/gcc_rd_ptr/clr_fifo_req
    SLICE_X52Y283        LUT5 (Prop_D6LUT_SLICEL_I1_O)
                                                      0.146     7.256 r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH/gcc_rd_ptr/do_push_i_1__1/O
                         net (fo=1, routed)           0.049     7.305    d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/FIFO_PUSH_n_32
    SLICE_X52Y283        FDCE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/do_push_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       1.911     2.093    d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/ps_clk
    SLICE_X52Y283        FDCE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/MEM0/do_push_reg/C

Slack:                    inf
  Source:                 d_1_i/qick_time_tagger_0/inst/QTT/FSM_onehot_time_trig_st_reg[1]/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/qick_time_tagger_0/inst/CMD/qtt_cmp_th_reg[14]/CE
                            (rising edge-triggered cell FDCE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.034ns  (logic 0.202ns (19.530%)  route 0.832ns (80.470%))
  Logic Levels:           1  (LUT6=1)
  Clock Path Skew:        -3.984ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.188ns
    Source Clock Delay      (SCD):    6.172ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.261ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.343ns
    Phase Error              (PE):    0.086ns
  Clock Net Delay (Source):      2.934ns (routing 1.963ns, distribution 0.971ns)
  Clock Net Delay (Destination): 2.006ns (routing 0.690ns, distribution 1.316ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y18        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=1, routed)           2.565     3.092    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.965 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     3.210    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.238 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=1945, routed)        2.934     6.172    d_1_i/qick_time_tagger_0/inst/QTT/adc_clk
    SLICE_X71Y99         FDCE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/FSM_onehot_time_trig_st_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X71Y99         FDCE (Prop_DFF_SLICEL_C_Q)
                                                      0.079     6.251 f  d_1_i/qick_time_tagger_0/inst/QTT/FSM_onehot_time_trig_st_reg[1]/Q
                         net (fo=6, routed)           0.258     6.509    d_1_i/qick_time_tagger_0/inst/CMD/Q[0]
    SLICE_X70Y95         LUT6 (Prop_G6LUT_SLICEM_I5_O)
                                                      0.123     6.632 r  d_1_i/qick_time_tagger_0/inst/CMD/qtt_cmp_th[15]_i_1/O
                         net (fo=16, routed)          0.574     7.206    d_1_i/qick_time_tagger_0/inst/CMD/qtt_cmp_th
    SLICE_X67Y100        FDCE                                         r  d_1_i/qick_time_tagger_0/inst/CMD/qtt_cmp_th_reg[14]/CE
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       2.006     2.188    d_1_i/qick_time_tagger_0/inst/CMD/c_clk
    SLICE_X67Y100        FDCE                                         r  d_1_i/qick_time_tagger_0/inst/CMD/qtt_cmp_th_reg[14]/C

Slack:                    inf
  Source:                 d_1_i/qick_time_tagger_0/inst/QTT/FSM_onehot_time_trig_st_reg[1]/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/qick_time_tagger_0/inst/CMD/qtt_cmp_th_reg[15]/CE
                            (rising edge-triggered cell FDCE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.034ns  (logic 0.202ns (19.530%)  route 0.832ns (80.470%))
  Logic Levels:           1  (LUT6=1)
  Clock Path Skew:        -3.984ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.188ns
    Source Clock Delay      (SCD):    6.172ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.261ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.343ns
    Phase Error              (PE):    0.086ns
  Clock Net Delay (Source):      2.934ns (routing 1.963ns, distribution 0.971ns)
  Clock Net Delay (Destination): 2.006ns (routing 0.690ns, distribution 1.316ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y18        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=1, routed)           2.565     3.092    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.965 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     3.210    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.238 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=1945, routed)        2.934     6.172    d_1_i/qick_time_tagger_0/inst/QTT/adc_clk
    SLICE_X71Y99         FDCE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/FSM_onehot_time_trig_st_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X71Y99         FDCE (Prop_DFF_SLICEL_C_Q)
                                                      0.079     6.251 f  d_1_i/qick_time_tagger_0/inst/QTT/FSM_onehot_time_trig_st_reg[1]/Q
                         net (fo=6, routed)           0.258     6.509    d_1_i/qick_time_tagger_0/inst/CMD/Q[0]
    SLICE_X70Y95         LUT6 (Prop_G6LUT_SLICEM_I5_O)
                                                      0.123     6.632 r  d_1_i/qick_time_tagger_0/inst/CMD/qtt_cmp_th[15]_i_1/O
                         net (fo=16, routed)          0.574     7.206    d_1_i/qick_time_tagger_0/inst/CMD/qtt_cmp_th
    SLICE_X67Y100        FDCE                                         r  d_1_i/qick_time_tagger_0/inst/CMD/qtt_cmp_th_reg[15]/CE
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       2.006     2.188    d_1_i/qick_time_tagger_0/inst/CMD/c_clk
    SLICE_X67Y100        FDCE                                         r  d_1_i/qick_time_tagger_0/inst/CMD/qtt_cmp_th_reg[15]/C

Slack:                    inf
  Source:                 d_1_i/qick_time_tagger_0/inst/QTT/FSM_onehot_time_trig_st_reg[1]/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/qick_time_tagger_0/inst/CMD/qtt_cmp_th_reg[8]/CE
                            (rising edge-triggered cell FDCE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.034ns  (logic 0.202ns (19.530%)  route 0.832ns (80.470%))
  Logic Levels:           1  (LUT6=1)
  Clock Path Skew:        -3.984ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.188ns
    Source Clock Delay      (SCD):    6.172ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.261ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.343ns
    Phase Error              (PE):    0.086ns
  Clock Net Delay (Source):      2.934ns (routing 1.963ns, distribution 0.971ns)
  Clock Net Delay (Destination): 2.006ns (routing 0.690ns, distribution 1.316ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y18        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=1, routed)           2.565     3.092    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.965 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     3.210    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.238 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=1945, routed)        2.934     6.172    d_1_i/qick_time_tagger_0/inst/QTT/adc_clk
    SLICE_X71Y99         FDCE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/FSM_onehot_time_trig_st_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X71Y99         FDCE (Prop_DFF_SLICEL_C_Q)
                                                      0.079     6.251 f  d_1_i/qick_time_tagger_0/inst/QTT/FSM_onehot_time_trig_st_reg[1]/Q
                         net (fo=6, routed)           0.258     6.509    d_1_i/qick_time_tagger_0/inst/CMD/Q[0]
    SLICE_X70Y95         LUT6 (Prop_G6LUT_SLICEM_I5_O)
                                                      0.123     6.632 r  d_1_i/qick_time_tagger_0/inst/CMD/qtt_cmp_th[15]_i_1/O
                         net (fo=16, routed)          0.574     7.206    d_1_i/qick_time_tagger_0/inst/CMD/qtt_cmp_th
    SLICE_X67Y100        FDCE                                         r  d_1_i/qick_time_tagger_0/inst/CMD/qtt_cmp_th_reg[8]/CE
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       2.006     2.188    d_1_i/qick_time_tagger_0/inst/CMD/c_clk
    SLICE_X67Y100        FDCE                                         r  d_1_i/qick_time_tagger_0/inst/CMD/qtt_cmp_th_reg[8]/C

Slack:                    inf
  Source:                 d_1_i/qick_time_tagger_0/inst/QTT/FSM_onehot_time_trig_st_reg[1]/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/qick_time_tagger_0/inst/CMD/qtt_cmp_th_reg[9]/CE
                            (rising edge-triggered cell FDCE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.034ns  (logic 0.202ns (19.530%)  route 0.832ns (80.470%))
  Logic Levels:           1  (LUT6=1)
  Clock Path Skew:        -3.984ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.188ns
    Source Clock Delay      (SCD):    6.172ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.261ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.343ns
    Phase Error              (PE):    0.086ns
  Clock Net Delay (Source):      2.934ns (routing 1.963ns, distribution 0.971ns)
  Clock Net Delay (Destination): 2.006ns (routing 0.690ns, distribution 1.316ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y18        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=1, routed)           2.565     3.092    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.965 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     3.210    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.238 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=1945, routed)        2.934     6.172    d_1_i/qick_time_tagger_0/inst/QTT/adc_clk
    SLICE_X71Y99         FDCE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/FSM_onehot_time_trig_st_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X71Y99         FDCE (Prop_DFF_SLICEL_C_Q)
                                                      0.079     6.251 f  d_1_i/qick_time_tagger_0/inst/QTT/FSM_onehot_time_trig_st_reg[1]/Q
                         net (fo=6, routed)           0.258     6.509    d_1_i/qick_time_tagger_0/inst/CMD/Q[0]
    SLICE_X70Y95         LUT6 (Prop_G6LUT_SLICEM_I5_O)
                                                      0.123     6.632 r  d_1_i/qick_time_tagger_0/inst/CMD/qtt_cmp_th[15]_i_1/O
                         net (fo=16, routed)          0.574     7.206    d_1_i/qick_time_tagger_0/inst/CMD/qtt_cmp_th
    SLICE_X67Y100        FDCE                                         r  d_1_i/qick_time_tagger_0/inst/CMD/qtt_cmp_th_reg[9]/CE
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       2.006     2.188    d_1_i/qick_time_tagger_0/inst/CMD/c_clk
    SLICE_X67Y100        FDCE                                         r  d_1_i/qick_time_tagger_0/inst/CMD/qtt_cmp_th_reg[9]/C

Slack:                    inf
  Source:                 d_1_i/qick_time_tagger_0/inst/QTT/FSM_onehot_time_trig_st_reg[1]/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/qick_time_tagger_0/inst/CMD/qtt_cmp_th_reg[11]/CE
                            (rising edge-triggered cell FDCE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.942ns  (logic 0.202ns (21.440%)  route 0.740ns (78.560%))
  Logic Levels:           1  (LUT6=1)
  Clock Path Skew:        -3.993ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.179ns
    Source Clock Delay      (SCD):    6.172ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.261ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.343ns
    Phase Error              (PE):    0.086ns
  Clock Net Delay (Source):      2.934ns (routing 1.963ns, distribution 0.971ns)
  Clock Net Delay (Destination): 1.997ns (routing 0.690ns, distribution 1.307ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y18        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=1, routed)           2.565     3.092    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.965 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     3.210    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.238 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=1945, routed)        2.934     6.172    d_1_i/qick_time_tagger_0/inst/QTT/adc_clk
    SLICE_X71Y99         FDCE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/FSM_onehot_time_trig_st_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X71Y99         FDCE (Prop_DFF_SLICEL_C_Q)
                                                      0.079     6.251 f  d_1_i/qick_time_tagger_0/inst/QTT/FSM_onehot_time_trig_st_reg[1]/Q
                         net (fo=6, routed)           0.258     6.509    d_1_i/qick_time_tagger_0/inst/CMD/Q[0]
    SLICE_X70Y95         LUT6 (Prop_G6LUT_SLICEM_I5_O)
                                                      0.123     6.632 r  d_1_i/qick_time_tagger_0/inst/CMD/qtt_cmp_th[15]_i_1/O
                         net (fo=16, routed)          0.482     7.114    d_1_i/qick_time_tagger_0/inst/CMD/qtt_cmp_th
    SLICE_X68Y96         FDCE                                         r  d_1_i/qick_time_tagger_0/inst/CMD/qtt_cmp_th_reg[11]/CE
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       1.997     2.179    d_1_i/qick_time_tagger_0/inst/CMD/c_clk
    SLICE_X68Y96         FDCE                                         r  d_1_i/qick_time_tagger_0/inst/CMD/qtt_cmp_th_reg[11]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/cdc_adc0_clk_valid_i/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.617ns  (logic 0.039ns (6.324%)  route 0.578ns (93.676%))
  Logic Levels:           0  
  Clock Path Skew:        -2.020ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.679ns
    Source Clock Delay      (SCD):    3.700ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.261ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.343ns
    Phase Error              (PE):    0.086ns
  Clock Net Delay (Source):      1.639ns (routing 1.074ns, distribution 0.565ns)
  Clock Net Delay (Destination): 1.532ns (routing 0.463ns, distribution 1.069ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y18        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=1, routed)           1.405     1.668    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.898 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     2.044    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.061 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=1945, routed)        1.639     3.700    d_1_i/rst_adc0_x2/U0/slowest_sync_clk
    SLICE_X80Y109        FDRE                                         r  d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X80Y109        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.039     3.739 r  d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=932, routed)         0.578     4.316    d_1_i/usp_rf_data_converter_0/inst/cdc_adc0_clk_valid_i/src_in
    SLICE_X106Y97        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/cdc_adc0_clk_valid_i/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       1.532     1.679    d_1_i/usp_rf_data_converter_0/inst/cdc_adc0_clk_valid_i/dest_clk
    SLICE_X106Y97        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/cdc_adc0_clk_valid_i/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/FABRIC_CLK
                            (rising edge-triggered cell HSADC clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[5]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.217ns  (logic 0.422ns (34.675%)  route 0.795ns (65.325%))
  Logic Levels:           4  (LUT4=1 LUT6=3)
  Clock Path Skew:        -2.152ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.709ns
    Source Clock Delay      (SCD):    3.861ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.261ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.343ns
    Phase Error              (PE):    0.086ns
  Clock Net Delay (Source):      1.800ns (routing 1.074ns, distribution 0.726ns)
  Clock Net Delay (Destination): 1.562ns (routing 0.463ns, distribution 1.099ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y18        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=1, routed)           1.405     1.668    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.898 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     2.044    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.061 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=1945, routed)        1.800     3.861    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/m0_axis_aclk
    HSADC_X0Y0           HSADC                                        r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/FABRIC_CLK
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y0           HSADC (Prop_HSADC_FABRIC_CLK_STATUS_COMMON[5])
                                                      0.228     4.089 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/STATUS_COMMON[5]
                         net (fo=1, routed)           0.502     4.591    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_19_0[5]
    SLICE_X110Y86        LUT4 (Prop_C6LUT_SLICEM_I2_O)
                                                      0.050     4.641 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_21/O
                         net (fo=1, routed)           0.031     4.672    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_21_n_0
    SLICE_X110Y86        LUT6 (Prop_F6LUT_SLICEM_I5_O)
                                                      0.059     4.731 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_12/O
                         net (fo=1, routed)           0.123     4.854    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_12_n_0
    SLICE_X110Y95        LUT6 (Prop_G6LUT_SLICEM_I2_O)
                                                      0.035     4.889 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_4/O
                         net (fo=1, routed)           0.118     5.007    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_4_n_0
    SLICE_X113Y97        LUT6 (Prop_G6LUT_SLICEM_I3_O)
                                                      0.050     5.057 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_1/O
                         net (fo=1, routed)           0.021     5.078    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_79
    SLICE_X113Y97        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[5]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       1.562     1.709    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X113Y97        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[5]/C

Slack:                    inf
  Source:                 d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/TAG[1].MEM/FIFO_PUSH/gcc_wr_ptr/count_gray_2r_reg[2]/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/TAG[1].MEM/FIFO_PUSH/wr_gptr_rcd_reg[2]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.107ns  (logic 0.039ns (36.449%)  route 0.068ns (63.552%))
  Logic Levels:           0  
  Clock Path Skew:        -2.173ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.530ns
    Source Clock Delay      (SCD):    3.704ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.261ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.343ns
    Phase Error              (PE):    0.086ns
  Clock Net Delay (Source):      1.643ns (routing 1.074ns, distribution 0.569ns)
  Clock Net Delay (Destination): 1.383ns (routing 0.463ns, distribution 0.920ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y18        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=1, routed)           1.405     1.668    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.898 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     2.044    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.061 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=1945, routed)        1.643     3.704    d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/TAG[1].MEM/FIFO_PUSH/gcc_wr_ptr/adc_clk
    SLICE_X70Y156        FDCE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/TAG[1].MEM/FIFO_PUSH/gcc_wr_ptr/count_gray_2r_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X70Y156        FDCE (Prop_DFF_SLICEM_C_Q)
                                                      0.039     3.743 r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/TAG[1].MEM/FIFO_PUSH/gcc_wr_ptr/count_gray_2r_reg[2]/Q
                         net (fo=1, routed)           0.068     3.811    d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/TAG[1].MEM/FIFO_PUSH/count_gray_2r[2]
    SLICE_X72Y156        FDRE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/TAG[1].MEM/FIFO_PUSH/wr_gptr_rcd_reg[2]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       1.383     1.530    d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/TAG[1].MEM/FIFO_PUSH/ps_clk
    SLICE_X72Y156        FDRE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/TAG[1].MEM/FIFO_PUSH/wr_gptr_rcd_reg[2]/C

Slack:                    inf
  Source:                 d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/TAG[1].MEM/FIFO_PUSH/gcc_wr_ptr/count_gray_2r_reg[4]/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/TAG[1].MEM/FIFO_PUSH/wr_gptr_rcd_reg[4]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.110ns  (logic 0.038ns (34.545%)  route 0.072ns (65.455%))
  Logic Levels:           0  
  Clock Path Skew:        -2.177ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.526ns
    Source Clock Delay      (SCD):    3.704ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.261ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.343ns
    Phase Error              (PE):    0.086ns
  Clock Net Delay (Source):      1.643ns (routing 1.074ns, distribution 0.569ns)
  Clock Net Delay (Destination): 1.379ns (routing 0.463ns, distribution 0.916ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y18        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=1, routed)           1.405     1.668    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.898 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     2.044    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.061 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=1945, routed)        1.643     3.704    d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/TAG[1].MEM/FIFO_PUSH/gcc_wr_ptr/adc_clk
    SLICE_X70Y156        FDCE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/TAG[1].MEM/FIFO_PUSH/gcc_wr_ptr/count_gray_2r_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X70Y156        FDCE (Prop_CFF_SLICEM_C_Q)
                                                      0.038     3.742 r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/TAG[1].MEM/FIFO_PUSH/gcc_wr_ptr/count_gray_2r_reg[4]/Q
                         net (fo=1, routed)           0.072     3.814    d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/TAG[1].MEM/FIFO_PUSH/count_gray_2r[4]
    SLICE_X70Y156        FDRE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/TAG[1].MEM/FIFO_PUSH/wr_gptr_rcd_reg[4]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       1.379     1.526    d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/TAG[1].MEM/FIFO_PUSH/ps_clk
    SLICE_X70Y156        FDRE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/TAG[1].MEM/FIFO_PUSH/wr_gptr_rcd_reg[4]/C

Slack:                    inf
  Source:                 d_1_i/qick_time_tagger_0/inst/QTT/ARM.ARM_MEM/FIFO_PUSH/gcc_wr_ptr/count_gray_2r_reg[2]/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/qick_time_tagger_0/inst/QTT/ARM.ARM_MEM/FIFO_PUSH/wr_gptr_rcd_reg[2]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.098ns  (logic 0.039ns (39.796%)  route 0.059ns (60.204%))
  Logic Levels:           0  
  Clock Path Skew:        -2.209ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.514ns
    Source Clock Delay      (SCD):    3.723ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.261ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.343ns
    Phase Error              (PE):    0.086ns
  Clock Net Delay (Source):      1.662ns (routing 1.074ns, distribution 0.588ns)
  Clock Net Delay (Destination): 1.367ns (routing 0.463ns, distribution 0.904ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y18        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=1, routed)           1.405     1.668    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.898 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     2.044    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.061 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=1945, routed)        1.662     3.723    d_1_i/qick_time_tagger_0/inst/QTT/ARM.ARM_MEM/FIFO_PUSH/gcc_wr_ptr/adc_clk
    SLICE_X74Y200        FDCE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/ARM.ARM_MEM/FIFO_PUSH/gcc_wr_ptr/count_gray_2r_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X74Y200        FDCE (Prop_DFF_SLICEL_C_Q)
                                                      0.039     3.762 r  d_1_i/qick_time_tagger_0/inst/QTT/ARM.ARM_MEM/FIFO_PUSH/gcc_wr_ptr/count_gray_2r_reg[2]/Q
                         net (fo=1, routed)           0.059     3.821    d_1_i/qick_time_tagger_0/inst/QTT/ARM.ARM_MEM/FIFO_PUSH/count_gray_2r[2]
    SLICE_X74Y200        FDRE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/ARM.ARM_MEM/FIFO_PUSH/wr_gptr_rcd_reg[2]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       1.367     1.514    d_1_i/qick_time_tagger_0/inst/QTT/ARM.ARM_MEM/FIFO_PUSH/ps_clk
    SLICE_X74Y200        FDRE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/ARM.ARM_MEM/FIFO_PUSH/wr_gptr_rcd_reg[2]/C

Slack:                    inf
  Source:                 d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/TAG[1].MEM/FIFO_PUSH/gcc_wr_ptr/count_gray_2r_reg[0]/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/TAG[1].MEM/FIFO_PUSH/wr_gptr_rcd_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.118ns  (logic 0.040ns (33.898%)  route 0.078ns (66.102%))
  Logic Levels:           0  
  Clock Path Skew:        -2.178ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.530ns
    Source Clock Delay      (SCD):    3.709ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.261ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.343ns
    Phase Error              (PE):    0.086ns
  Clock Net Delay (Source):      1.648ns (routing 1.074ns, distribution 0.574ns)
  Clock Net Delay (Destination): 1.383ns (routing 0.463ns, distribution 0.920ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y18        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=1, routed)           1.405     1.668    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.898 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     2.044    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.061 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=1945, routed)        1.648     3.709    d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/TAG[1].MEM/FIFO_PUSH/gcc_wr_ptr/adc_clk
    SLICE_X73Y155        FDCE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/TAG[1].MEM/FIFO_PUSH/gcc_wr_ptr/count_gray_2r_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X73Y155        FDCE (Prop_CFF2_SLICEL_C_Q)
                                                      0.040     3.749 r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/TAG[1].MEM/FIFO_PUSH/gcc_wr_ptr/count_gray_2r_reg[0]/Q
                         net (fo=1, routed)           0.078     3.827    d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/TAG[1].MEM/FIFO_PUSH/count_gray_2r[0]
    SLICE_X72Y156        FDRE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/TAG[1].MEM/FIFO_PUSH/wr_gptr_rcd_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       1.383     1.530    d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/TAG[1].MEM/FIFO_PUSH/ps_clk
    SLICE_X72Y156        FDRE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/TAG[1].MEM/FIFO_PUSH/wr_gptr_rcd_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/TAG[1].MEM/FIFO_PUSH/gcc_wr_ptr/count_gray_2r_reg[1]/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/TAG[1].MEM/FIFO_PUSH/wr_gptr_rcd_reg[1]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.124ns  (logic 0.039ns (31.452%)  route 0.085ns (68.548%))
  Logic Levels:           0  
  Clock Path Skew:        -2.181ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.529ns
    Source Clock Delay      (SCD):    3.711ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.261ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.343ns
    Phase Error              (PE):    0.086ns
  Clock Net Delay (Source):      1.650ns (routing 1.074ns, distribution 0.576ns)
  Clock Net Delay (Destination): 1.382ns (routing 0.463ns, distribution 0.919ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y18        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=1, routed)           1.405     1.668    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.898 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     2.044    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.061 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=1945, routed)        1.650     3.711    d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/TAG[1].MEM/FIFO_PUSH/gcc_wr_ptr/adc_clk
    SLICE_X72Y155        FDCE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/TAG[1].MEM/FIFO_PUSH/gcc_wr_ptr/count_gray_2r_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X72Y155        FDCE (Prop_HFF2_SLICEM_C_Q)
                                                      0.039     3.750 r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/TAG[1].MEM/FIFO_PUSH/gcc_wr_ptr/count_gray_2r_reg[1]/Q
                         net (fo=1, routed)           0.085     3.835    d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/TAG[1].MEM/FIFO_PUSH/count_gray_2r[1]
    SLICE_X72Y156        FDRE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/TAG[1].MEM/FIFO_PUSH/wr_gptr_rcd_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       1.382     1.529    d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/TAG[1].MEM/FIFO_PUSH/ps_clk
    SLICE_X72Y156        FDRE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/TAG[1].MEM/FIFO_PUSH/wr_gptr_rcd_reg[1]/C

Slack:                    inf
  Source:                 d_1_i/qick_time_tagger_0/inst/QTT/ARM.ARM_MEM/FIFO_PUSH/gcc_wr_ptr/count_gray_2r_reg[1]/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/qick_time_tagger_0/inst/QTT/ARM.ARM_MEM/FIFO_PUSH/wr_gptr_rcd_reg[1]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.109ns  (logic 0.039ns (35.780%)  route 0.070ns (64.220%))
  Logic Levels:           0  
  Clock Path Skew:        -2.215ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.511ns
    Source Clock Delay      (SCD):    3.726ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.261ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.343ns
    Phase Error              (PE):    0.086ns
  Clock Net Delay (Source):      1.665ns (routing 1.074ns, distribution 0.591ns)
  Clock Net Delay (Destination): 1.364ns (routing 0.463ns, distribution 0.901ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y18        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=1, routed)           1.405     1.668    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.898 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     2.044    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.061 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=1945, routed)        1.665     3.726    d_1_i/qick_time_tagger_0/inst/QTT/ARM.ARM_MEM/FIFO_PUSH/gcc_wr_ptr/adc_clk
    SLICE_X74Y199        FDCE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/ARM.ARM_MEM/FIFO_PUSH/gcc_wr_ptr/count_gray_2r_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X74Y199        FDCE (Prop_EFF_SLICEL_C_Q)
                                                      0.039     3.765 r  d_1_i/qick_time_tagger_0/inst/QTT/ARM.ARM_MEM/FIFO_PUSH/gcc_wr_ptr/count_gray_2r_reg[1]/Q
                         net (fo=1, routed)           0.070     3.835    d_1_i/qick_time_tagger_0/inst/QTT/ARM.ARM_MEM/FIFO_PUSH/count_gray_2r[1]
    SLICE_X74Y199        FDRE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/ARM.ARM_MEM/FIFO_PUSH/wr_gptr_rcd_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       1.364     1.511    d_1_i/qick_time_tagger_0/inst/QTT/ARM.ARM_MEM/FIFO_PUSH/ps_clk
    SLICE_X74Y199        FDRE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/ARM.ARM_MEM/FIFO_PUSH/wr_gptr_rcd_reg[1]/C

Slack:                    inf
  Source:                 d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/TAG[1].MEM/FIFO_PUSH/gcc_wr_ptr/count_gray_2r_reg[5]/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/TAG[1].MEM/FIFO_PUSH/wr_gptr_rcd_reg[5]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.140ns  (logic 0.039ns (27.857%)  route 0.101ns (72.143%))
  Logic Levels:           0  
  Clock Path Skew:        -2.177ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.526ns
    Source Clock Delay      (SCD):    3.704ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.261ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.343ns
    Phase Error              (PE):    0.086ns
  Clock Net Delay (Source):      1.643ns (routing 1.074ns, distribution 0.569ns)
  Clock Net Delay (Destination): 1.379ns (routing 0.463ns, distribution 0.916ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y18        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=1, routed)           1.405     1.668    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.898 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     2.044    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.061 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=1945, routed)        1.643     3.704    d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/TAG[1].MEM/FIFO_PUSH/gcc_wr_ptr/adc_clk
    SLICE_X70Y156        FDCE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/TAG[1].MEM/FIFO_PUSH/gcc_wr_ptr/count_gray_2r_reg[5]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X70Y156        FDCE (Prop_CFF2_SLICEM_C_Q)
                                                      0.039     3.743 r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/TAG[1].MEM/FIFO_PUSH/gcc_wr_ptr/count_gray_2r_reg[5]/Q
                         net (fo=1, routed)           0.101     3.844    d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/TAG[1].MEM/FIFO_PUSH/count_gray_2r[5]
    SLICE_X70Y156        FDRE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/TAG[1].MEM/FIFO_PUSH/wr_gptr_rcd_reg[5]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       1.379     1.526    d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/TAG[1].MEM/FIFO_PUSH/ps_clk
    SLICE_X70Y156        FDRE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/TAG_MEM/TAG[1].MEM/FIFO_PUSH/wr_gptr_rcd_reg[5]/C

Slack:                    inf
  Source:                 d_1_i/qick_time_tagger_0/inst/QTT/ARM.ARM_MEM/FIFO_PUSH/gcc_wr_ptr/count_gray_2r_reg[3]/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/qick_time_tagger_0/inst/QTT/ARM.ARM_MEM/FIFO_PUSH/wr_gptr_rcd_reg[3]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.121ns  (logic 0.041ns (33.884%)  route 0.080ns (66.116%))
  Logic Levels:           0  
  Clock Path Skew:        -2.209ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.514ns
    Source Clock Delay      (SCD):    3.723ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.261ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.343ns
    Phase Error              (PE):    0.086ns
  Clock Net Delay (Source):      1.662ns (routing 1.074ns, distribution 0.588ns)
  Clock Net Delay (Destination): 1.367ns (routing 0.463ns, distribution 0.904ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y18        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=1, routed)           1.405     1.668    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.898 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     2.044    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.061 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=1945, routed)        1.662     3.723    d_1_i/qick_time_tagger_0/inst/QTT/ARM.ARM_MEM/FIFO_PUSH/gcc_wr_ptr/adc_clk
    SLICE_X74Y200        FDCE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/ARM.ARM_MEM/FIFO_PUSH/gcc_wr_ptr/count_gray_2r_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X74Y200        FDCE (Prop_DFF2_SLICEL_C_Q)
                                                      0.041     3.764 r  d_1_i/qick_time_tagger_0/inst/QTT/ARM.ARM_MEM/FIFO_PUSH/gcc_wr_ptr/count_gray_2r_reg[3]/Q
                         net (fo=1, routed)           0.080     3.844    d_1_i/qick_time_tagger_0/inst/QTT/ARM.ARM_MEM/FIFO_PUSH/count_gray_2r[3]
    SLICE_X74Y200        FDRE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/ARM.ARM_MEM/FIFO_PUSH/wr_gptr_rcd_reg[3]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       1.367     1.514    d_1_i/qick_time_tagger_0/inst/QTT/ARM.ARM_MEM/FIFO_PUSH/ps_clk
    SLICE_X74Y200        FDRE                                         r  d_1_i/qick_time_tagger_0/inst/QTT/ARM.ARM_MEM/FIFO_PUSH/wr_gptr_rcd_reg[3]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  clk_pl_0
  To Clock:  clk_pl_0

Max Delay            88 Endpoints
Min Delay            88 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/EXT_LPF/ACTIVE_LOW_AUX.ACT_LO_AUX/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.706ns  (logic 0.167ns (6.171%)  route 2.539ns (93.829%))
  Logic Levels:           1  (LUT1=1)
  Clock Path Skew:        -0.434ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.191ns
    Source Clock Delay      (SCD):    2.625ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.399ns (routing 0.763ns, distribution 1.636ns)
  Clock Net Delay (Destination): 2.009ns (routing 0.690ns, distribution 1.319ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       2.399     2.625    d_1_i/rst_100/U0/slowest_sync_clk
    SLICE_X83Y81         FDRE                                         r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/C
  -------------------------------------------------------------------    -------------------
    SLICE_X83Y81         FDRE (Prop_AFF_SLICEM_C_Q)
                                                      0.077     2.702 f  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/Q
                         net (fo=125, routed)         2.345     5.047    d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/EXT_LPF/ACTIVE_LOW_AUX.ACT_LO_AUX/peripheral_aresetn[0]_bufg_place_replica
    SLICE_X33Y38         LUT1 (Prop_E6LUT_SLICEL_I0_O)
                                                      0.090     5.137 r  d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/EXT_LPF/ACTIVE_LOW_AUX.ACT_LO_AUX/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1/O
                         net (fo=1, routed)           0.194     5.331    d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/EXT_LPF/ACTIVE_LOW_AUX.ACT_LO_AUX/asr_d1
    SLICE_X33Y38         FDRE                                         r  d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/EXT_LPF/ACTIVE_LOW_AUX.ACT_LO_AUX/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       2.009     2.191    d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/EXT_LPF/ACTIVE_LOW_AUX.ACT_LO_AUX/aclk
    SLICE_X33Y38         FDRE                                         r  d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/EXT_LPF/ACTIVE_LOW_AUX.ACT_LO_AUX/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/C

Slack:                    inf
  Source:                 d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axi_dma_gen/U0/I_RST_MODULE/REG_HRD_RST/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.323ns  (logic 0.077ns (3.315%)  route 2.246ns (96.685%))
  Logic Levels:           0  
  Clock Path Skew:        -0.499ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.125ns
    Source Clock Delay      (SCD):    2.625ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.399ns (routing 0.763ns, distribution 1.636ns)
  Clock Net Delay (Destination): 1.943ns (routing 0.690ns, distribution 1.253ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       2.399     2.625    d_1_i/rst_100/U0/slowest_sync_clk
    SLICE_X83Y81         FDRE                                         r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/C
  -------------------------------------------------------------------    -------------------
    SLICE_X83Y81         FDRE (Prop_AFF_SLICEM_C_Q)
                                                      0.077     2.702 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/Q
                         net (fo=125, routed)         2.246     4.947    d_1_i/axi_dma_gen/U0/I_RST_MODULE/REG_HRD_RST/peripheral_aresetn[0]_bufg_place_replica
    SLICE_X51Y51         FDRE                                         r  d_1_i/axi_dma_gen/U0/I_RST_MODULE/REG_HRD_RST/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       1.943     2.125    d_1_i/axi_dma_gen/U0/I_RST_MODULE/REG_HRD_RST/s_axi_lite_aclk
    SLICE_X51Y51         FDRE                                         r  d_1_i/axi_dma_gen/U0/I_RST_MODULE/REG_HRD_RST/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/C

Slack:                    inf
  Source:                 d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[0]/PRE
                            (recovery check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Recovery (Max at Slow Process Corner)
  Data Path Delay:        2.317ns  (logic 0.106ns (4.575%)  route 2.211ns (95.425%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        -0.389ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.211ns
    Source Clock Delay      (SCD):    2.600ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.374ns (routing 0.763ns, distribution 1.611ns)
  Clock Net Delay (Destination): 2.029ns (routing 0.690ns, distribution 1.339ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       2.374     2.600    d_1_i/rst_100/U0/slowest_sync_clk
    SLICE_X83Y83         FDRE                                         r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X83Y83         FDRE (Prop_BFF_SLICEM_C_Q)
                                                      0.078     2.678 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           0.699     3.377    d_1_i/rst_100/U0/peripheral_aresetn[0]_bufg_place
    BUFGCE_X0Y44         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.405 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_bufg_place/O
                         net (fo=7045, routed)        1.512     4.917    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/src_arst
    SLICE_X24Y33         FDPE                                         f  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[0]/PRE  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       2.029     2.211    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/dest_clk
    SLICE_X24Y33         FDPE                                         r  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[1]/PRE
                            (recovery check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Recovery (Max at Slow Process Corner)
  Data Path Delay:        2.317ns  (logic 0.106ns (4.575%)  route 2.211ns (95.425%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        -0.389ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.211ns
    Source Clock Delay      (SCD):    2.600ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.374ns (routing 0.763ns, distribution 1.611ns)
  Clock Net Delay (Destination): 2.029ns (routing 0.690ns, distribution 1.339ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       2.374     2.600    d_1_i/rst_100/U0/slowest_sync_clk
    SLICE_X83Y83         FDRE                                         r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X83Y83         FDRE (Prop_BFF_SLICEM_C_Q)
                                                      0.078     2.678 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           0.699     3.377    d_1_i/rst_100/U0/peripheral_aresetn[0]_bufg_place
    BUFGCE_X0Y44         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.405 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_bufg_place/O
                         net (fo=7045, routed)        1.512     4.917    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/src_arst
    SLICE_X24Y33         FDPE                                         f  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[1]/PRE  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       2.029     2.211    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/dest_clk
    SLICE_X24Y33         FDPE                                         r  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[1]/C

Slack:                    inf
  Source:                 d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[0]/PRE
                            (recovery check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Recovery (Max at Slow Process Corner)
  Data Path Delay:        2.314ns  (logic 0.106ns (4.581%)  route 2.208ns (95.419%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        -0.385ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.215ns
    Source Clock Delay      (SCD):    2.600ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.374ns (routing 0.763ns, distribution 1.611ns)
  Clock Net Delay (Destination): 2.033ns (routing 0.690ns, distribution 1.343ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       2.374     2.600    d_1_i/rst_100/U0/slowest_sync_clk
    SLICE_X83Y83         FDRE                                         r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X83Y83         FDRE (Prop_BFF_SLICEM_C_Q)
                                                      0.078     2.678 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           0.699     3.377    d_1_i/rst_100/U0/peripheral_aresetn[0]_bufg_place
    BUFGCE_X0Y44         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.405 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_bufg_place/O
                         net (fo=7045, routed)        1.509     4.914    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/src_arst
    SLICE_X29Y52         FDPE                                         f  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[0]/PRE  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       2.033     2.215    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/dest_clk
    SLICE_X29Y52         FDPE                                         r  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[1]/PRE
                            (recovery check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Recovery (Max at Slow Process Corner)
  Data Path Delay:        2.314ns  (logic 0.106ns (4.581%)  route 2.208ns (95.419%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        -0.385ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.215ns
    Source Clock Delay      (SCD):    2.600ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.374ns (routing 0.763ns, distribution 1.611ns)
  Clock Net Delay (Destination): 2.033ns (routing 0.690ns, distribution 1.343ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       2.374     2.600    d_1_i/rst_100/U0/slowest_sync_clk
    SLICE_X83Y83         FDRE                                         r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X83Y83         FDRE (Prop_BFF_SLICEM_C_Q)
                                                      0.078     2.678 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           0.699     3.377    d_1_i/rst_100/U0/peripheral_aresetn[0]_bufg_place
    BUFGCE_X0Y44         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.405 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_bufg_place/O
                         net (fo=7045, routed)        1.509     4.914    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/src_arst
    SLICE_X29Y52         FDPE                                         f  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[1]/PRE  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       2.033     2.215    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/dest_clk
    SLICE_X29Y52         FDPE                                         r  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[1]/C

Slack:                    inf
  Source:                 d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[0]/PRE
                            (recovery check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Recovery (Max at Slow Process Corner)
  Data Path Delay:        2.297ns  (logic 0.106ns (4.615%)  route 2.191ns (95.385%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        -0.395ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.205ns
    Source Clock Delay      (SCD):    2.600ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.374ns (routing 0.763ns, distribution 1.611ns)
  Clock Net Delay (Destination): 2.023ns (routing 0.690ns, distribution 1.333ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       2.374     2.600    d_1_i/rst_100/U0/slowest_sync_clk
    SLICE_X83Y83         FDRE                                         r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X83Y83         FDRE (Prop_BFF_SLICEM_C_Q)
                                                      0.078     2.678 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           0.699     3.377    d_1_i/rst_100/U0/peripheral_aresetn[0]_bufg_place
    BUFGCE_X0Y44         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.405 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_bufg_place/O
                         net (fo=7045, routed)        1.492     4.897    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/src_arst
    SLICE_X31Y36         FDPE                                         f  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[0]/PRE  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       2.023     2.205    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/dest_clk
    SLICE_X31Y36         FDPE                                         r  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[1]/PRE
                            (recovery check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Recovery (Max at Slow Process Corner)
  Data Path Delay:        2.297ns  (logic 0.106ns (4.615%)  route 2.191ns (95.385%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        -0.395ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.205ns
    Source Clock Delay      (SCD):    2.600ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.374ns (routing 0.763ns, distribution 1.611ns)
  Clock Net Delay (Destination): 2.023ns (routing 0.690ns, distribution 1.333ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       2.374     2.600    d_1_i/rst_100/U0/slowest_sync_clk
    SLICE_X83Y83         FDRE                                         r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X83Y83         FDRE (Prop_BFF_SLICEM_C_Q)
                                                      0.078     2.678 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           0.699     3.377    d_1_i/rst_100/U0/peripheral_aresetn[0]_bufg_place
    BUFGCE_X0Y44         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.405 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_bufg_place/O
                         net (fo=7045, routed)        1.492     4.897    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/src_arst
    SLICE_X31Y36         FDPE                                         f  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[1]/PRE  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       2.023     2.205    d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/dest_clk
    SLICE_X31Y36         FDPE                                         r  d_1_i/ps8_0_axi_periph/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[1]/C

Slack:                    inf
  Source:                 d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axi_dma_tproc/U0/I_RST_MODULE/REG_HRD_RST/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.246ns  (logic 0.077ns (3.429%)  route 2.169ns (96.571%))
  Logic Levels:           0  
  Clock Path Skew:        -0.505ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.120ns
    Source Clock Delay      (SCD):    2.625ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.399ns (routing 0.763ns, distribution 1.636ns)
  Clock Net Delay (Destination): 1.938ns (routing 0.690ns, distribution 1.248ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       2.399     2.625    d_1_i/rst_100/U0/slowest_sync_clk
    SLICE_X83Y81         FDRE                                         r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/C
  -------------------------------------------------------------------    -------------------
    SLICE_X83Y81         FDRE (Prop_AFF_SLICEM_C_Q)
                                                      0.077     2.702 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/Q
                         net (fo=125, routed)         2.169     4.870    d_1_i/axi_dma_tproc/U0/I_RST_MODULE/REG_HRD_RST/peripheral_aresetn[0]_bufg_place_replica
    SLICE_X56Y40         FDRE                                         r  d_1_i/axi_dma_tproc/U0/I_RST_MODULE/REG_HRD_RST/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       1.938     2.120    d_1_i/axi_dma_tproc/U0/I_RST_MODULE/REG_HRD_RST/s_axi_lite_aclk
    SLICE_X56Y40         FDRE                                         r  d_1_i/axi_dma_tproc/U0/I_RST_MODULE/REG_HRD_RST/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/C

Slack:                    inf
  Source:                 d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axi_smc/inst/m00_nodes/m00_aw_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[0]/CLR
                            (recovery check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Recovery (Max at Slow Process Corner)
  Data Path Delay:        2.267ns  (logic 0.079ns (3.485%)  route 2.188ns (96.515%))
  Logic Levels:           0  
  Clock Path Skew:        -0.277ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.204ns
    Source Clock Delay      (SCD):    2.481ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.255ns (routing 0.763ns, distribution 1.492ns)
  Clock Net Delay (Destination): 2.022ns (routing 0.690ns, distribution 1.332ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       2.255     2.481    d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/aclk
    SLICE_X36Y38         FDRE                                         r  d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X36Y38         FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.079     2.560 r  d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/Q
                         net (fo=72, routed)          2.188     4.748    d_1_i/axi_smc/inst/m00_nodes/m00_aw_node/inst/s_sc_xpm_cdc_async_rst_inst/src_arst
    SLICE_X32Y22         FDCE                                         f  d_1_i/axi_smc/inst/m00_nodes/m00_aw_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[0]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       2.022     2.204    d_1_i/axi_smc/inst/m00_nodes/m00_aw_node/inst/s_sc_xpm_cdc_async_rst_inst/dest_clk
    SLICE_X32Y22         FDCE                                         r  d_1_i/axi_smc/inst/m00_nodes/m00_aw_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[0]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/axis_switch_0/inst/gen_static_router.inst_static_router/inst_start_router_config/ctrl_soft_reset_r_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_switch_0/inst/gen_static_router.gen_synch.inst_rst_synch/inst_xpm_cdc_single/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.093ns  (logic 0.039ns (41.935%)  route 0.054ns (58.064%))
  Logic Levels:           0  
  Clock Path Skew:        0.186ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.512ns
    Source Clock Delay      (SCD):    1.326ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.206ns (routing 0.414ns, distribution 0.792ns)
  Clock Net Delay (Destination): 1.365ns (routing 0.463ns, distribution 0.902ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       1.206     1.326    d_1_i/axis_switch_0/inst/gen_static_router.inst_static_router/inst_start_router_config/s_axi_ctrl_aclk
    SLICE_X58Y55         FDRE                                         r  d_1_i/axis_switch_0/inst/gen_static_router.inst_static_router/inst_start_router_config/ctrl_soft_reset_r_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X58Y55         FDRE (Prop_GFF_SLICEL_C_Q)
                                                      0.039     1.365 r  d_1_i/axis_switch_0/inst/gen_static_router.inst_static_router/inst_start_router_config/ctrl_soft_reset_r_reg/Q
                         net (fo=1, routed)           0.054     1.419    d_1_i/axis_switch_0/inst/gen_static_router.gen_synch.inst_rst_synch/inst_xpm_cdc_single/src_in
    SLICE_X58Y55         FDRE                                         r  d_1_i/axis_switch_0/inst/gen_static_router.gen_synch.inst_rst_synch/inst_xpm_cdc_single/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       1.365     1.512    d_1_i/axis_switch_0/inst/gen_static_router.gen_synch.inst_rst_synch/inst_xpm_cdc_single/dest_clk
    SLICE_X58Y55         FDRE                                         r  d_1_i/axis_switch_0/inst/gen_static_router.gen_synch.inst_rst_synch/inst_xpm_cdc_single/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axis_switch_0/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_req_ff_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_switch_0/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.124ns  (logic 0.039ns (31.448%)  route 0.085ns (68.552%))
  Logic Levels:           0  
  Clock Path Skew:        0.186ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.513ns
    Source Clock Delay      (SCD):    1.327ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.207ns (routing 0.414ns, distribution 0.793ns)
  Clock Net Delay (Destination): 1.366ns (routing 0.463ns, distribution 0.903ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       1.207     1.327    d_1_i/axis_switch_0/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_clk
    SLICE_X59Y54         FDRE                                         r  d_1_i/axis_switch_0/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_req_ff_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X59Y54         FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.039     1.366 r  d_1_i/axis_switch_0/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_req_ff_reg/Q
                         net (fo=2, routed)           0.085     1.451    d_1_i/axis_switch_0/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/src_in
    SLICE_X59Y54         FDRE                                         r  d_1_i/axis_switch_0/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       1.366     1.513    d_1_i/axis_switch_0/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/dest_clk
    SLICE_X59Y54         FDRE                                         r  d_1_i/axis_switch_0/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axi_smc/inst/m00_nodes/m00_ar_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[0]/CLR
                            (removal check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Removal (Min at Fast Process Corner)
  Data Path Delay:        0.144ns  (logic 0.039ns (27.051%)  route 0.105ns (72.949%))
  Logic Levels:           0  
  Clock Path Skew:        0.182ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.545ns
    Source Clock Delay      (SCD):    1.363ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.243ns (routing 0.414ns, distribution 0.829ns)
  Clock Net Delay (Destination): 1.398ns (routing 0.463ns, distribution 0.935ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       1.243     1.363    d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/aclk
    SLICE_X36Y38         FDRE                                         r  d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X36Y38         FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.039     1.402 r  d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/Q
                         net (fo=72, routed)          0.105     1.507    d_1_i/axi_smc/inst/m00_nodes/m00_ar_node/inst/s_sc_xpm_cdc_async_rst_inst/src_arst
    SLICE_X37Y38         FDCE                                         f  d_1_i/axi_smc/inst/m00_nodes/m00_ar_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[0]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       1.398     1.545    d_1_i/axi_smc/inst/m00_nodes/m00_ar_node/inst/s_sc_xpm_cdc_async_rst_inst/dest_clk
    SLICE_X37Y38         FDCE                                         r  d_1_i/axi_smc/inst/m00_nodes/m00_ar_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axi_smc/inst/m00_nodes/m00_ar_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[1]/CLR
                            (removal check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Removal (Min at Fast Process Corner)
  Data Path Delay:        0.144ns  (logic 0.039ns (27.051%)  route 0.105ns (72.949%))
  Logic Levels:           0  
  Clock Path Skew:        0.182ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.545ns
    Source Clock Delay      (SCD):    1.363ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.243ns (routing 0.414ns, distribution 0.829ns)
  Clock Net Delay (Destination): 1.398ns (routing 0.463ns, distribution 0.935ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       1.243     1.363    d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/aclk
    SLICE_X36Y38         FDRE                                         r  d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X36Y38         FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.039     1.402 r  d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/Q
                         net (fo=72, routed)          0.105     1.507    d_1_i/axi_smc/inst/m00_nodes/m00_ar_node/inst/s_sc_xpm_cdc_async_rst_inst/src_arst
    SLICE_X37Y38         FDCE                                         f  d_1_i/axi_smc/inst/m00_nodes/m00_ar_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[1]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       1.398     1.545    d_1_i/axi_smc/inst/m00_nodes/m00_ar_node/inst/s_sc_xpm_cdc_async_rst_inst/dest_clk
    SLICE_X37Y38         FDCE                                         r  d_1_i/axi_smc/inst/m00_nodes/m00_ar_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[1]/C

Slack:                    inf
  Source:                 d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axi_smc/inst/m00_nodes/m00_ar_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[2]/CLR
                            (removal check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Removal (Min at Fast Process Corner)
  Data Path Delay:        0.144ns  (logic 0.039ns (27.051%)  route 0.105ns (72.949%))
  Logic Levels:           0  
  Clock Path Skew:        0.182ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.545ns
    Source Clock Delay      (SCD):    1.363ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.243ns (routing 0.414ns, distribution 0.829ns)
  Clock Net Delay (Destination): 1.398ns (routing 0.463ns, distribution 0.935ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       1.243     1.363    d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/aclk
    SLICE_X36Y38         FDRE                                         r  d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X36Y38         FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.039     1.402 r  d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/Q
                         net (fo=72, routed)          0.105     1.507    d_1_i/axi_smc/inst/m00_nodes/m00_ar_node/inst/s_sc_xpm_cdc_async_rst_inst/src_arst
    SLICE_X37Y38         FDCE                                         f  d_1_i/axi_smc/inst/m00_nodes/m00_ar_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[2]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       1.398     1.545    d_1_i/axi_smc/inst/m00_nodes/m00_ar_node/inst/s_sc_xpm_cdc_async_rst_inst/dest_clk
    SLICE_X37Y38         FDCE                                         r  d_1_i/axi_smc/inst/m00_nodes/m00_ar_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[2]/C

Slack:                    inf
  Source:                 d_1_i/axis_switch_0/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_sendd_ff_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_switch_0/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.193ns  (logic 0.039ns (20.244%)  route 0.154ns (79.756%))
  Logic Levels:           0  
  Clock Path Skew:        0.187ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.517ns
    Source Clock Delay      (SCD):    1.330ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.210ns (routing 0.414ns, distribution 0.796ns)
  Clock Net Delay (Destination): 1.370ns (routing 0.463ns, distribution 0.907ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       1.210     1.330    d_1_i/axis_switch_0/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_clk
    SLICE_X58Y57         FDRE                                         r  d_1_i/axis_switch_0/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_sendd_ff_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X58Y57         FDRE (Prop_HFF2_SLICEL_C_Q)
                                                      0.039     1.369 r  d_1_i/axis_switch_0/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_sendd_ff_reg/Q
                         net (fo=2, routed)           0.154     1.522    d_1_i/axis_switch_0/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/src_in
    SLICE_X59Y54         FDRE                                         r  d_1_i/axis_switch_0/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       1.370     1.517    d_1_i/axis_switch_0/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/dest_clk
    SLICE_X59Y54         FDRE                                         r  d_1_i/axis_switch_0/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axi_smc/inst/s01_nodes/s01_b_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[0]/CLR
                            (removal check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Removal (Min at Fast Process Corner)
  Data Path Delay:        0.218ns  (logic 0.039ns (17.856%)  route 0.179ns (82.144%))
  Logic Levels:           0  
  Clock Path Skew:        0.186ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.549ns
    Source Clock Delay      (SCD):    1.363ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.243ns (routing 0.414ns, distribution 0.829ns)
  Clock Net Delay (Destination): 1.402ns (routing 0.463ns, distribution 0.939ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       1.243     1.363    d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/aclk
    SLICE_X36Y38         FDRE                                         r  d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X36Y38         FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.039     1.402 r  d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/Q
                         net (fo=72, routed)          0.179     1.581    d_1_i/axi_smc/inst/s01_nodes/s01_b_node/inst/s_sc_xpm_cdc_async_rst_inst/src_arst
    SLICE_X33Y40         FDCE                                         f  d_1_i/axi_smc/inst/s01_nodes/s01_b_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[0]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       1.402     1.549    d_1_i/axi_smc/inst/s01_nodes/s01_b_node/inst/s_sc_xpm_cdc_async_rst_inst/dest_clk
    SLICE_X33Y40         FDCE                                         r  d_1_i/axi_smc/inst/s01_nodes/s01_b_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axi_smc/inst/s01_nodes/s01_b_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[1]/CLR
                            (removal check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Removal (Min at Fast Process Corner)
  Data Path Delay:        0.218ns  (logic 0.039ns (17.856%)  route 0.179ns (82.144%))
  Logic Levels:           0  
  Clock Path Skew:        0.186ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.549ns
    Source Clock Delay      (SCD):    1.363ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.243ns (routing 0.414ns, distribution 0.829ns)
  Clock Net Delay (Destination): 1.402ns (routing 0.463ns, distribution 0.939ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       1.243     1.363    d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/aclk
    SLICE_X36Y38         FDRE                                         r  d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X36Y38         FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.039     1.402 r  d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/Q
                         net (fo=72, routed)          0.179     1.581    d_1_i/axi_smc/inst/s01_nodes/s01_b_node/inst/s_sc_xpm_cdc_async_rst_inst/src_arst
    SLICE_X33Y40         FDCE                                         f  d_1_i/axi_smc/inst/s01_nodes/s01_b_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[1]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       1.402     1.549    d_1_i/axi_smc/inst/s01_nodes/s01_b_node/inst/s_sc_xpm_cdc_async_rst_inst/dest_clk
    SLICE_X33Y40         FDCE                                         r  d_1_i/axi_smc/inst/s01_nodes/s01_b_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[1]/C

Slack:                    inf
  Source:                 d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axi_smc/inst/s01_nodes/s01_b_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[2]/CLR
                            (removal check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Removal (Min at Fast Process Corner)
  Data Path Delay:        0.218ns  (logic 0.039ns (17.856%)  route 0.179ns (82.144%))
  Logic Levels:           0  
  Clock Path Skew:        0.186ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.549ns
    Source Clock Delay      (SCD):    1.363ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.243ns (routing 0.414ns, distribution 0.829ns)
  Clock Net Delay (Destination): 1.402ns (routing 0.463ns, distribution 0.939ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       1.243     1.363    d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/aclk
    SLICE_X36Y38         FDRE                                         r  d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X36Y38         FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.039     1.402 r  d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/Q
                         net (fo=72, routed)          0.179     1.581    d_1_i/axi_smc/inst/s01_nodes/s01_b_node/inst/s_sc_xpm_cdc_async_rst_inst/src_arst
    SLICE_X33Y40         FDCE                                         f  d_1_i/axi_smc/inst/s01_nodes/s01_b_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[2]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       1.402     1.549    d_1_i/axi_smc/inst/s01_nodes/s01_b_node/inst/s_sc_xpm_cdc_async_rst_inst/dest_clk
    SLICE_X33Y40         FDCE                                         r  d_1_i/axi_smc/inst/s01_nodes/s01_b_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[2]/C

Slack:                    inf
  Source:                 d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axi_smc/inst/m00_nodes/m00_b_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[0]/CLR
                            (removal check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Removal (Min at Fast Process Corner)
  Data Path Delay:        0.259ns  (logic 0.039ns (15.032%)  route 0.220ns (84.968%))
  Logic Levels:           0  
  Clock Path Skew:        0.190ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.553ns
    Source Clock Delay      (SCD):    1.363ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.243ns (routing 0.414ns, distribution 0.829ns)
  Clock Net Delay (Destination): 1.406ns (routing 0.463ns, distribution 0.943ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       1.243     1.363    d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/aclk
    SLICE_X36Y38         FDRE                                         r  d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X36Y38         FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.039     1.402 r  d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/Q
                         net (fo=72, routed)          0.220     1.623    d_1_i/axi_smc/inst/m00_nodes/m00_b_node/inst/s_sc_xpm_cdc_async_rst_inst/src_arst
    SLICE_X35Y31         FDCE                                         f  d_1_i/axi_smc/inst/m00_nodes/m00_b_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[0]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       1.406     1.553    d_1_i/axi_smc/inst/m00_nodes/m00_b_node/inst/s_sc_xpm_cdc_async_rst_inst/dest_clk
    SLICE_X35Y31         FDCE                                         r  d_1_i/axi_smc/inst/m00_nodes/m00_b_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[0]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  RFDAC0_CLK
  To Clock:  

Max Delay             8 Endpoints
Min Delay             8 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[0]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            PMOD0_0
                            (output port)
  Path Group:             (none)
  Path Type:              Max at Slow Process Corner
  Data Path Delay:        4.793ns  (logic 1.014ns (21.165%)  route 3.778ns (78.835%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.597ns (routing 1.490ns, distribution 1.107ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=5276, routed)        2.597     3.270    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
    SLICE_X81Y157        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y157        FDCE (Prop_HFF2_SLICEL_C_Q)
                                                      0.080     3.350 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[0]/Q
                         net (fo=3, routed)           3.778     7.128    PMOD0_0_OBUF
    C17                  OBUF (Prop_OUTBUF_HPIOB_M_I_O)
                                                      0.934     8.063 r  PMOD0_0_OBUF_inst/O
                         net (fo=0)                   0.000     8.063    PMOD0_0
    C17                                                               r  PMOD0_0 (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_dt_r_reg[0][1]_lopt_replica/C
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            PMOD0_5
                            (output port)
  Path Group:             (none)
  Path Type:              Max at Slow Process Corner
  Data Path Delay:        4.098ns  (logic 1.034ns (25.229%)  route 3.064ns (74.771%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.505ns (routing 1.490ns, distribution 1.015ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=5276, routed)        2.505     3.178    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
    SLICE_X75Y138        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_dt_r_reg[0][1]_lopt_replica/C
  -------------------------------------------------------------------    -------------------
    SLICE_X75Y138        FDCE (Prop_HFF2_SLICEM_C_Q)
                                                      0.078     3.256 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_dt_r_reg[0][1]_lopt_replica/Q
                         net (fo=1, routed)           3.064     6.320    lopt_1
    K16                  OBUF (Prop_OUTBUF_HPIOB_M_I_O)
                                                      0.956     7.276 r  PMOD0_5_OBUF_inst/O
                         net (fo=0)                   0.000     7.276    PMOD0_5
    K16                                                               r  PMOD0_5 (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[3]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            PMOD0_3
                            (output port)
  Path Group:             (none)
  Path Type:              Max at Slow Process Corner
  Data Path Delay:        3.826ns  (logic 1.030ns (26.918%)  route 2.796ns (73.082%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.505ns (routing 1.490ns, distribution 1.015ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=5276, routed)        2.505     3.178    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
    SLICE_X76Y151        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X76Y151        FDCE (Prop_CFF_SLICEM_C_Q)
                                                      0.078     3.256 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[3]/Q
                         net (fo=2, routed)           2.796     6.052    PMOD0_3_OBUF
    H17                  OBUF (Prop_OUTBUF_HPIOB_M_I_O)
                                                      0.952     7.004 r  PMOD0_3_OBUF_inst/O
                         net (fo=0)                   0.000     7.004    PMOD0_3
    H17                                                               r  PMOD0_3 (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[1]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            PMOD0_1
                            (output port)
  Path Group:             (none)
  Path Type:              Max at Slow Process Corner
  Data Path Delay:        3.708ns  (logic 1.026ns (27.673%)  route 2.682ns (72.327%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.499ns (routing 1.490ns, distribution 1.009ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=5276, routed)        2.499     3.172    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
    SLICE_X75Y145        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X75Y145        FDCE (Prop_DFF2_SLICEM_C_Q)
                                                      0.080     3.252 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[1]/Q
                         net (fo=2, routed)           2.682     5.934    PMOD0_1_OBUF
    M18                  OBUF (Prop_OUTBUF_HPIOB_SNGL_I_O)
                                                      0.946     6.880 r  PMOD0_1_OBUF_inst/O
                         net (fo=0)                   0.000     6.880    PMOD0_1
    M18                                                               r  PMOD0_1 (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[2]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            PMOD0_2
                            (output port)
  Path Group:             (none)
  Path Type:              Max at Slow Process Corner
  Data Path Delay:        3.668ns  (logic 1.031ns (28.103%)  route 2.637ns (71.897%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.505ns (routing 1.490ns, distribution 1.015ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=5276, routed)        2.505     3.178    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
    SLICE_X76Y151        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X76Y151        FDCE (Prop_DFF_SLICEM_C_Q)
                                                      0.078     3.256 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[2]/Q
                         net (fo=2, routed)           2.637     5.893    PMOD0_2_OBUF
    H16                  OBUF (Prop_OUTBUF_HPIOB_S_I_O)
                                                      0.953     6.846 r  PMOD0_2_OBUF_inst/O
                         net (fo=0)                   0.000     6.846    PMOD0_2
    H16                                                               r  PMOD0_2 (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_dt_r_reg[0][0]_lopt_replica/C
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            PMOD0_4
                            (output port)
  Path Group:             (none)
  Path Type:              Max at Slow Process Corner
  Data Path Delay:        3.639ns  (logic 1.036ns (28.460%)  route 2.603ns (71.540%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.513ns (routing 1.490ns, distribution 1.023ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=5276, routed)        2.513     3.186    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
    SLICE_X78Y142        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_dt_r_reg[0][0]_lopt_replica/C
  -------------------------------------------------------------------    -------------------
    SLICE_X78Y142        FDCE (Prop_HFF_SLICEM_C_Q)
                                                      0.079     3.265 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_dt_r_reg[0][0]_lopt_replica/Q
                         net (fo=1, routed)           2.603     5.868    lopt
    J16                  OBUF (Prop_OUTBUF_HPIOB_S_I_O)
                                                      0.957     6.825 r  PMOD0_4_OBUF_inst/O
                         net (fo=0)                   0.000     6.825    PMOD0_4
    J16                                                               r  PMOD0_4 (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_dt_r_reg[0][2]_lopt_replica/C
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            PMOD0_6
                            (output port)
  Path Group:             (none)
  Path Type:              Max at Slow Process Corner
  Data Path Delay:        3.597ns  (logic 1.024ns (28.473%)  route 2.573ns (71.527%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.513ns (routing 1.490ns, distribution 1.023ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=5276, routed)        2.513     3.186    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
    SLICE_X78Y142        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_dt_r_reg[0][2]_lopt_replica/C
  -------------------------------------------------------------------    -------------------
    SLICE_X78Y142        FDCE (Prop_GFF_SLICEM_C_Q)
                                                      0.078     3.264 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_dt_r_reg[0][2]_lopt_replica/Q
                         net (fo=1, routed)           2.573     5.837    lopt_2
    H15                  OBUF (Prop_OUTBUF_HPIOB_S_I_O)
                                                      0.946     6.784 r  PMOD0_6_OBUF_inst/O
                         net (fo=0)                   0.000     6.784    PMOD0_6
    H15                                                               r  PMOD0_6 (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_dt_r_reg[0][3]_lopt_replica/C
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            PMOD0_7
                            (output port)
  Path Group:             (none)
  Path Type:              Max at Slow Process Corner
  Data Path Delay:        3.517ns  (logic 1.022ns (29.061%)  route 2.495ns (70.939%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.513ns (routing 1.490ns, distribution 1.023ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=5276, routed)        2.513     3.186    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
    SLICE_X78Y142        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_dt_r_reg[0][3]_lopt_replica/C
  -------------------------------------------------------------------    -------------------
    SLICE_X78Y142        FDCE (Prop_FFF_SLICEM_C_Q)
                                                      0.076     3.262 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_dt_r_reg[0][3]_lopt_replica/Q
                         net (fo=1, routed)           2.495     5.757    lopt_3
    J15                  OBUF (Prop_OUTBUF_HPIOB_M_I_O)
                                                      0.946     6.703 r  PMOD0_7_OBUF_inst/O
                         net (fo=0)                   0.000     6.703    PMOD0_7
    J15                                                               r  PMOD0_7 (OUT)
  -------------------------------------------------------------------    -------------------





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_dt_r_reg[0][3]_lopt_replica/C
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            PMOD0_7
                            (output port)
  Path Group:             (none)
  Path Type:              Min at Fast Process Corner
  Data Path Delay:        1.698ns  (logic 0.475ns (27.958%)  route 1.223ns (72.042%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.370ns (routing 0.805ns, distribution 0.565ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=5276, routed)        1.370     1.719    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
    SLICE_X78Y142        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_dt_r_reg[0][3]_lopt_replica/C
  -------------------------------------------------------------------    -------------------
    SLICE_X78Y142        FDCE (Prop_FFF_SLICEM_C_Q)
                                                      0.037     1.756 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_dt_r_reg[0][3]_lopt_replica/Q
                         net (fo=1, routed)           1.223     2.979    lopt_3
    J15                  OBUF (Prop_OUTBUF_HPIOB_M_I_O)
                                                      0.438     3.416 r  PMOD0_7_OBUF_inst/O
                         net (fo=0)                   0.000     3.416    PMOD0_7
    J15                                                               r  PMOD0_7 (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_dt_r_reg[0][2]_lopt_replica/C
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            PMOD0_6
                            (output port)
  Path Group:             (none)
  Path Type:              Min at Fast Process Corner
  Data Path Delay:        1.723ns  (logic 0.477ns (27.674%)  route 1.246ns (72.326%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.370ns (routing 0.805ns, distribution 0.565ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=5276, routed)        1.370     1.719    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
    SLICE_X78Y142        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_dt_r_reg[0][2]_lopt_replica/C
  -------------------------------------------------------------------    -------------------
    SLICE_X78Y142        FDCE (Prop_GFF_SLICEM_C_Q)
                                                      0.039     1.758 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_dt_r_reg[0][2]_lopt_replica/Q
                         net (fo=1, routed)           1.246     3.004    lopt_2
    H15                  OBUF (Prop_OUTBUF_HPIOB_S_I_O)
                                                      0.438     3.441 r  PMOD0_6_OBUF_inst/O
                         net (fo=0)                   0.000     3.441    PMOD0_6
    H15                                                               r  PMOD0_6 (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_dt_r_reg[0][0]_lopt_replica/C
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            PMOD0_4
                            (output port)
  Path Group:             (none)
  Path Type:              Min at Fast Process Corner
  Data Path Delay:        1.746ns  (logic 0.487ns (27.889%)  route 1.259ns (72.111%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.370ns (routing 0.805ns, distribution 0.565ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=5276, routed)        1.370     1.719    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
    SLICE_X78Y142        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_dt_r_reg[0][0]_lopt_replica/C
  -------------------------------------------------------------------    -------------------
    SLICE_X78Y142        FDCE (Prop_HFF_SLICEM_C_Q)
                                                      0.039     1.758 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_dt_r_reg[0][0]_lopt_replica/Q
                         net (fo=1, routed)           1.259     3.017    lopt
    J16                  OBUF (Prop_OUTBUF_HPIOB_S_I_O)
                                                      0.448     3.464 r  PMOD0_4_OBUF_inst/O
                         net (fo=0)                   0.000     3.464    PMOD0_4
    J16                                                               r  PMOD0_4 (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[2]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            PMOD0_2
                            (output port)
  Path Group:             (none)
  Path Type:              Min at Fast Process Corner
  Data Path Delay:        1.770ns  (logic 0.483ns (27.298%)  route 1.287ns (72.702%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.363ns (routing 0.805ns, distribution 0.558ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=5276, routed)        1.363     1.712    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
    SLICE_X76Y151        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X76Y151        FDCE (Prop_DFF_SLICEM_C_Q)
                                                      0.039     1.751 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[2]/Q
                         net (fo=2, routed)           1.287     3.038    PMOD0_2_OBUF
    H16                  OBUF (Prop_OUTBUF_HPIOB_S_I_O)
                                                      0.444     3.482 r  PMOD0_2_OBUF_inst/O
                         net (fo=0)                   0.000     3.482    PMOD0_2
    H16                                                               r  PMOD0_2 (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[1]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            PMOD0_1
                            (output port)
  Path Group:             (none)
  Path Type:              Min at Fast Process Corner
  Data Path Delay:        1.784ns  (logic 0.479ns (26.827%)  route 1.306ns (73.173%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.363ns (routing 0.805ns, distribution 0.558ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=5276, routed)        1.363     1.712    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
    SLICE_X75Y145        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X75Y145        FDCE (Prop_DFF2_SLICEM_C_Q)
                                                      0.041     1.753 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[1]/Q
                         net (fo=2, routed)           1.306     3.058    PMOD0_1_OBUF
    M18                  OBUF (Prop_OUTBUF_HPIOB_SNGL_I_O)
                                                      0.438     3.496 r  PMOD0_1_OBUF_inst/O
                         net (fo=0)                   0.000     3.496    PMOD0_1
    M18                                                               r  PMOD0_1 (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[3]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            PMOD0_3
                            (output port)
  Path Group:             (none)
  Path Type:              Min at Fast Process Corner
  Data Path Delay:        1.844ns  (logic 0.481ns (26.098%)  route 1.363ns (73.902%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.363ns (routing 0.805ns, distribution 0.558ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=5276, routed)        1.363     1.712    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
    SLICE_X76Y151        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X76Y151        FDCE (Prop_CFF_SLICEM_C_Q)
                                                      0.038     1.750 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[3]/Q
                         net (fo=2, routed)           1.363     3.113    PMOD0_3_OBUF
    H17                  OBUF (Prop_OUTBUF_HPIOB_M_I_O)
                                                      0.443     3.557 r  PMOD0_3_OBUF_inst/O
                         net (fo=0)                   0.000     3.557    PMOD0_3
    H17                                                               r  PMOD0_3 (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_dt_r_reg[0][1]_lopt_replica/C
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            PMOD0_5
                            (output port)
  Path Group:             (none)
  Path Type:              Min at Fast Process Corner
  Data Path Delay:        1.991ns  (logic 0.486ns (24.420%)  route 1.505ns (75.580%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.366ns (routing 0.805ns, distribution 0.561ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=5276, routed)        1.366     1.715    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
    SLICE_X75Y138        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_dt_r_reg[0][1]_lopt_replica/C
  -------------------------------------------------------------------    -------------------
    SLICE_X75Y138        FDCE (Prop_HFF2_SLICEM_C_Q)
                                                      0.039     1.754 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_dt_r_reg[0][1]_lopt_replica/Q
                         net (fo=1, routed)           1.505     3.259    lopt_1
    K16                  OBUF (Prop_OUTBUF_HPIOB_M_I_O)
                                                      0.447     3.706 r  PMOD0_5_OBUF_inst/O
                         net (fo=0)                   0.000     3.706    PMOD0_5
    K16                                                               r  PMOD0_5 (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[0]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC0_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            PMOD0_0
                            (output port)
  Path Group:             (none)
  Path Type:              Min at Fast Process Corner
  Data Path Delay:        2.308ns  (logic 0.465ns (20.152%)  route 1.843ns (79.848%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.419ns (routing 0.805ns, distribution 0.614ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt_0
    BUFG_GT_X1Y104       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac0_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=5276, routed)        1.419     1.768    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
    SLICE_X81Y157        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y157        FDCE (Prop_HFF2_SLICEL_C_Q)
                                                      0.039     1.807 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[0]/Q
                         net (fo=3, routed)           1.843     3.649    PMOD0_0_OBUF
    C17                  OBUF (Prop_OUTBUF_HPIOB_M_I_O)
                                                      0.426     4.075 r  PMOD0_0_OBUF_inst/O
                         net (fo=0)                   0.000     4.075    PMOD0_0
    C17                                                               r  PMOD0_0 (OUT)
  -------------------------------------------------------------------    -------------------





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  clk_pl_0
  To Clock:  

Max Delay             6 Endpoints
Min Delay             6 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                            (clock source 'clk_pl_0'  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/PLL_MONCLK
  Path Group:             (none)
  Path Type:              Max at Slow Process Corner
  Data Path Delay:        2.824ns  (logic 0.028ns (0.992%)  route 2.796ns (99.009%))
  Logic Levels:           1  (BUFG_PS=1)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 fall edge)
                                                      5.000     5.000 f  
    PS8_X0Y0             PS8                          0.000     5.000 f  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     5.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     5.226 f  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=29124, routed)       2.598     7.824    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/s_axi_aclk
    HSDAC_X0Y1           HSDAC                                        f  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/PLL_MONCLK
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                            (clock source 'clk_pl_0'  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/PLL_MONCLK
  Path Group:             (none)
  Path Type:              Max at Slow Process Corner
  Data Path Delay:        2.816ns  (logic 0.028ns (0.994%)  route 2.788ns (99.006%))
  Logic Levels:           1  (BUFG_PS=1)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 fall edge)
                                                      5.000     5.000 f  
    PS8_X0Y0             PS8                          0.000     5.000 f  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     5.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     5.226 f  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=29124, routed)       2.590     7.816    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/s_axi_aclk
    HSADC_X0Y0           HSADC                                        f  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/PLL_MONCLK
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                            (clock source 'clk_pl_0'  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/PLL_MONCLK
  Path Group:             (none)
  Path Type:              Max at Slow Process Corner
  Data Path Delay:        2.814ns  (logic 0.028ns (0.995%)  route 2.786ns (99.005%))
  Logic Levels:           1  (BUFG_PS=1)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 fall edge)
                                                      5.000     5.000 f  
    PS8_X0Y0             PS8                          0.000     5.000 f  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     5.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     5.226 f  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=29124, routed)       2.588     7.814    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/s_axi_aclk
    HSADC_X0Y1           HSADC                                        f  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/PLL_MONCLK
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                            (clock source 'clk_pl_0'  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/PLL_MONCLK
  Path Group:             (none)
  Path Type:              Max at Slow Process Corner
  Data Path Delay:        2.804ns  (logic 0.028ns (0.999%)  route 2.776ns (99.001%))
  Logic Levels:           1  (BUFG_PS=1)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 fall edge)
                                                      5.000     5.000 f  
    PS8_X0Y0             PS8                          0.000     5.000 f  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     5.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     5.226 f  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=29124, routed)       2.578     7.804    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/s_axi_aclk
    HSDAC_X0Y0           HSDAC                                        f  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/PLL_MONCLK
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                            (clock source 'clk_pl_0'  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/PLL_MONCLK
  Path Group:             (none)
  Path Type:              Max at Slow Process Corner
  Data Path Delay:        2.771ns  (logic 0.028ns (1.010%)  route 2.743ns (98.990%))
  Logic Levels:           1  (BUFG_PS=1)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 fall edge)
                                                      5.000     5.000 f  
    PS8_X0Y0             PS8                          0.000     5.000 f  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     5.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     5.226 f  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=29124, routed)       2.545     7.771    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/s_axi_aclk
    HSADC_X0Y2           HSADC                                        f  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/PLL_MONCLK
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                            (clock source 'clk_pl_0'  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/PLL_MONCLK
  Path Group:             (none)
  Path Type:              Max at Slow Process Corner
  Data Path Delay:        2.754ns  (logic 0.028ns (1.017%)  route 2.726ns (98.983%))
  Logic Levels:           1  (BUFG_PS=1)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 fall edge)
                                                      5.000     5.000 f  
    PS8_X0Y0             PS8                          0.000     5.000 f  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     5.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     5.226 f  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=29124, routed)       2.528     7.754    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/s_axi_aclk
    HSADC_X0Y3           HSADC                                        f  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/PLL_MONCLK
  -------------------------------------------------------------------    -------------------





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                            (clock source 'clk_pl_0'  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/PLL_MONCLK
  Path Group:             (none)
  Path Type:              Min at Fast Process Corner
  Data Path Delay:        1.488ns  (logic 0.017ns (1.142%)  route 1.471ns (98.858%))
  Logic Levels:           1  (BUFG_PS=1)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=29124, routed)       1.368     1.488    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/s_axi_aclk
    HSADC_X0Y3           HSADC                                        r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/PLL_MONCLK
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                            (clock source 'clk_pl_0'  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/PLL_MONCLK
  Path Group:             (none)
  Path Type:              Min at Fast Process Corner
  Data Path Delay:        1.499ns  (logic 0.017ns (1.134%)  route 1.482ns (98.866%))
  Logic Levels:           1  (BUFG_PS=1)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=29124, routed)       1.379     1.499    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/s_axi_aclk
    HSADC_X0Y2           HSADC                                        r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/PLL_MONCLK
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                            (clock source 'clk_pl_0'  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/PLL_MONCLK
  Path Group:             (none)
  Path Type:              Min at Fast Process Corner
  Data Path Delay:        1.514ns  (logic 0.017ns (1.123%)  route 1.497ns (98.877%))
  Logic Levels:           1  (BUFG_PS=1)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=29124, routed)       1.394     1.514    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/s_axi_aclk
    HSDAC_X0Y0           HSDAC                                        r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/PLL_MONCLK
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                            (clock source 'clk_pl_0'  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/PLL_MONCLK
  Path Group:             (none)
  Path Type:              Min at Fast Process Corner
  Data Path Delay:        1.520ns  (logic 0.017ns (1.118%)  route 1.503ns (98.882%))
  Logic Levels:           1  (BUFG_PS=1)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=29124, routed)       1.400     1.520    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/s_axi_aclk
    HSADC_X0Y1           HSADC                                        r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/PLL_MONCLK
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                            (clock source 'clk_pl_0'  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/PLL_MONCLK
  Path Group:             (none)
  Path Type:              Min at Fast Process Corner
  Data Path Delay:        1.527ns  (logic 0.017ns (1.113%)  route 1.510ns (98.887%))
  Logic Levels:           1  (BUFG_PS=1)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=29124, routed)       1.407     1.527    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/s_axi_aclk
    HSDAC_X0Y1           HSDAC                                        r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/PLL_MONCLK
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                            (clock source 'clk_pl_0'  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/PLL_MONCLK
  Path Group:             (none)
  Path Type:              Min at Fast Process Corner
  Data Path Delay:        1.530ns  (logic 0.017ns (1.111%)  route 1.513ns (98.889%))
  Logic Levels:           1  (BUFG_PS=1)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=29124, routed)       1.410     1.530    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/s_axi_aclk
    HSADC_X0Y0           HSADC                                        r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/PLL_MONCLK
  -------------------------------------------------------------------    -------------------





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  
  To Clock:  clk_out1_d_1_clk_adc0_x2_0

Max Delay             1 Endpoint
Min Delay             1 Endpoint
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/LOCKED
                            (internal pin)
  Destination:            d_1_i/rst_adc0_x2/U0/EXT_LPF/lpf_int_reg/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.126ns  (logic 0.051ns (1.631%)  route 3.075ns (98.369%))
  Logic Levels:           1  (LUT4=1)
  Clock Uncertainty:      0.139ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.094ns
    Phase Error              (PE):    0.086ns
  Clock Net Delay (Destination): 2.664ns (routing 1.778ns, distribution 0.886ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    MMCM_X0Y7            MMCME4_ADV                   0.000     0.000 f  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/LOCKED
                         net (fo=1, routed)           3.026     3.026    d_1_i/rst_adc0_x2/U0/EXT_LPF/dcm_locked
    SLICE_X80Y110        LUT4 (Prop_B6LUT_SLICEL_I0_O)
                                                      0.051     3.077 r  d_1_i/rst_adc0_x2/U0/EXT_LPF/lpf_int0/O
                         net (fo=1, routed)           0.049     3.126    d_1_i/rst_adc0_x2/U0/EXT_LPF/lpf_int0__0
    SLICE_X80Y110        FDRE                                         r  d_1_i/rst_adc0_x2/U0/EXT_LPF/lpf_int_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y18        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=1, routed)           2.303     2.689    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     3.319 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.216     3.535    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.559 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=1945, routed)        2.664     6.223    d_1_i/rst_adc0_x2/U0/EXT_LPF/slowest_sync_clk
    SLICE_X80Y110        FDRE                                         r  d_1_i/rst_adc0_x2/U0/EXT_LPF/lpf_int_reg/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/LOCKED
                            (internal pin)
  Destination:            d_1_i/rst_adc0_x2/U0/EXT_LPF/lpf_int_reg/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.601ns  (logic 0.023ns (1.437%)  route 1.578ns (98.563%))
  Logic Levels:           1  (LUT4=1)
  Clock Uncertainty:      0.139ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.094ns
    Phase Error              (PE):    0.086ns
  Clock Net Delay (Destination): 1.846ns (routing 1.208ns, distribution 0.638ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    MMCM_X0Y7            MMCME4_ADV                   0.000     0.000 f  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/LOCKED
                         net (fo=1, routed)           1.563     1.563    d_1_i/rst_adc0_x2/U0/EXT_LPF/dcm_locked
    SLICE_X80Y110        LUT4 (Prop_B6LUT_SLICEL_I0_O)
                                                      0.023     1.586 r  d_1_i/rst_adc0_x2/U0/EXT_LPF/lpf_int0/O
                         net (fo=1, routed)           0.015     1.601    d_1_i/rst_adc0_x2/U0/EXT_LPF/lpf_int0__0
    SLICE_X80Y110        FDRE                                         r  d_1_i/rst_adc0_x2/U0/EXT_LPF/lpf_int_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y18        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=1, routed)           1.575     1.927    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.632 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.798    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y179        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.817 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y1 (CLOCK_ROOT)    net (fo=1945, routed)        1.846     3.663    d_1_i/rst_adc0_x2/U0/EXT_LPF/slowest_sync_clk
    SLICE_X80Y110        FDRE                                         r  d_1_i/rst_adc0_x2/U0/EXT_LPF/lpf_int_reg/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  
  To Clock:  clk_pl_0

Max Delay             7 Endpoints
Min Delay             7 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[2]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[2]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.554ns  (logic 0.468ns (13.168%)  route 3.086ns (86.832%))
  Logic Levels:           5  (LUT4=1 LUT6=4)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.248ns (routing 0.690ns, distribution 1.558ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[2]
                         net (fo=1, routed)           2.054     2.054    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/dac1_common_stat[2]
    SLICE_X115Y107       LUT4 (Prop_A6LUT_SLICEM_I0_O)
                                                      0.150     2.204 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[2]_i_72/O
                         net (fo=1, routed)           0.379     2.583    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[2]_i_72_n_0
    SLICE_X109Y105       LUT6 (Prop_C6LUT_SLICEM_I0_O)
                                                      0.051     2.634 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[2]_i_52/O
                         net (fo=1, routed)           0.192     2.826    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[2]_i_52_n_0
    SLICE_X110Y105       LUT6 (Prop_H6LUT_SLICEM_I1_O)
                                                      0.125     2.951 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[2]_i_22/O
                         net (fo=1, routed)           0.089     3.040    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[2]_i_22_n_0
    SLICE_X110Y104       LUT6 (Prop_G6LUT_SLICEM_I5_O)
                                                      0.052     3.092 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[2]_i_6/O
                         net (fo=1, routed)           0.314     3.406    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[2]_i_6_n_0
    SLICE_X112Y95        LUT6 (Prop_H6LUT_SLICEM_I5_O)
                                                      0.090     3.496 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[2]_i_1/O
                         net (fo=1, routed)           0.058     3.554    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_82
    SLICE_X112Y95        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[2]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       2.248     2.430    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X112Y95        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[2]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[1]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[1]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.383ns  (logic 0.359ns (10.611%)  route 3.024ns (89.389%))
  Logic Levels:           5  (LUT4=1 LUT6=4)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.254ns (routing 0.690ns, distribution 1.564ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[1]
                         net (fo=2, routed)           2.212     2.212    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/dac1_common_stat[1]
    SLICE_X109Y105       LUT4 (Prop_H6LUT_SLICEM_I0_O)
                                                      0.152     2.364 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[1]_i_69/O
                         net (fo=1, routed)           0.201     2.565    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[1]_i_69_n_0
    SLICE_X109Y105       LUT6 (Prop_D6LUT_SLICEM_I0_O)
                                                      0.099     2.664 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[1]_i_51/O
                         net (fo=1, routed)           0.229     2.893    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[1]_i_51_n_0
    SLICE_X110Y104       LUT6 (Prop_C6LUT_SLICEM_I5_O)
                                                      0.037     2.930 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[1]_i_26/O
                         net (fo=1, routed)           0.133     3.063    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[1]_i_26_n_0
    SLICE_X111Y104       LUT6 (Prop_C6LUT_SLICEL_I2_O)
                                                      0.035     3.098 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[1]_i_6/O
                         net (fo=1, routed)           0.200     3.298    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[1]_i_6_n_0
    SLICE_X111Y97        LUT6 (Prop_D6LUT_SLICEL_I5_O)
                                                      0.036     3.334 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[1]_i_1/O
                         net (fo=1, routed)           0.049     3.383    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_83
    SLICE_X111Y97        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       2.254     2.436    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X111Y97        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[1]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[3]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[3]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.379ns  (logic 0.346ns (10.240%)  route 3.033ns (89.760%))
  Logic Levels:           5  (LUT6=5)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.246ns (routing 0.690ns, distribution 1.556ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[3]
                         net (fo=1, routed)           2.181     2.181    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/dac1_common_stat[3]
    SLICE_X113Y104       LUT6 (Prop_C6LUT_SLICEM_I5_O)
                                                      0.037     2.218 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[3]_i_66/O
                         net (fo=1, routed)           0.138     2.356    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[3]_i_66_n_0
    SLICE_X113Y104       LUT6 (Prop_H6LUT_SLICEM_I5_O)
                                                      0.039     2.395 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[3]_i_32/O
                         net (fo=1, routed)           0.206     2.601    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[3]_i_32_n_0
    SLICE_X113Y105       LUT6 (Prop_C6LUT_SLICEM_I1_O)
                                                      0.088     2.689 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[3]_i_10/O
                         net (fo=1, routed)           0.098     2.787    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[3]_i_10_n_0
    SLICE_X112Y104       LUT6 (Prop_G6LUT_SLICEM_I5_O)
                                                      0.037     2.824 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[3]_i_2/O
                         net (fo=1, routed)           0.344     3.168    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[3]_i_2_n_0
    SLICE_X113Y96        LUT6 (Prop_C6LUT_SLICEM_I0_O)
                                                      0.145     3.313 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[3]_i_1/O
                         net (fo=1, routed)           0.066     3.379    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_81
    SLICE_X113Y96        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[3]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       2.246     2.428    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X113Y96        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[3]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[4]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[4]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.160ns  (logic 0.483ns (15.285%)  route 2.677ns (84.715%))
  Logic Levels:           5  (LUT6=5)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.254ns (routing 0.690ns, distribution 1.564ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[4]
                         net (fo=1, routed)           2.060     2.060    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/dac1_common_stat[4]
    SLICE_X114Y103       LUT6 (Prop_G6LUT_SLICEL_I5_O)
                                                      0.035     2.095 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[4]_i_44/O
                         net (fo=1, routed)           0.044     2.139    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[4]_i_44_n_0
    SLICE_X114Y103       LUT6 (Prop_H6LUT_SLICEL_I5_O)
                                                      0.051     2.190 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[4]_i_24/O
                         net (fo=1, routed)           0.047     2.237    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[4]_i_24_n_0
    SLICE_X114Y103       LUT6 (Prop_C6LUT_SLICEL_I0_O)
                                                      0.123     2.360 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[4]_i_9/O
                         net (fo=1, routed)           0.149     2.509    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[4]_i_9_n_0
    SLICE_X114Y106       LUT6 (Prop_G6LUT_SLICEL_I5_O)
                                                      0.149     2.658 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[4]_i_3/O
                         net (fo=1, routed)           0.318     2.976    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[4]_i_3_n_0
    SLICE_X113Y95        LUT6 (Prop_B6LUT_SLICEM_I2_O)
                                                      0.125     3.101 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[4]_i_1/O
                         net (fo=1, routed)           0.059     3.160    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_80
    SLICE_X113Y95        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[4]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       2.254     2.436    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X113Y95        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[4]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[5]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[5]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.086ns  (logic 0.292ns (9.462%)  route 2.794ns (90.538%))
  Logic Levels:           4  (LUT4=1 LUT5=2 LUT6=1)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.255ns (routing 0.690ns, distribution 1.565ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[5]
                         net (fo=1, routed)           2.276     2.276    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/dac1_common_stat[5]
    SLICE_X115Y107       LUT5 (Prop_H6LUT_SLICEM_I4_O)
                                                      0.090     2.366 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_19/O
                         net (fo=1, routed)           0.096     2.462    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_19_n_0
    SLICE_X114Y107       LUT4 (Prop_E6LUT_SLICEL_I2_O)
                                                      0.099     2.561 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_8/O
                         net (fo=1, routed)           0.041     2.602    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_8_n_0
    SLICE_X114Y107       LUT5 (Prop_B6LUT_SLICEL_I1_O)
                                                      0.051     2.653 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_3/O
                         net (fo=1, routed)           0.322     2.975    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_3_n_0
    SLICE_X113Y97        LUT6 (Prop_G6LUT_SLICEM_I2_O)
                                                      0.052     3.027 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_1/O
                         net (fo=1, routed)           0.059     3.086    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_79
    SLICE_X113Y97        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[5]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       2.255     2.437    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X113Y97        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[5]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[0]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.000ns  (logic 0.353ns (11.767%)  route 2.647ns (88.233%))
  Logic Levels:           4  (LUT6=4)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.256ns (routing 0.690ns, distribution 1.566ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[0]
                         net (fo=1, routed)           2.130     2.130    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/dac1_common_stat[0]
    SLICE_X112Y105       LUT6 (Prop_H6LUT_SLICEM_I3_O)
                                                      0.090     2.220 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[0]_i_61/O
                         net (fo=1, routed)           0.104     2.324    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[0]_i_61_n_0
    SLICE_X113Y105       LUT6 (Prop_H6LUT_SLICEM_I0_O)
                                                      0.053     2.377 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[0]_i_27/O
                         net (fo=1, routed)           0.128     2.505    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[0]_i_27_n_0
    SLICE_X113Y105       LUT6 (Prop_F6LUT_SLICEM_I1_O)
                                                      0.088     2.593 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[0]_i_6/O
                         net (fo=1, routed)           0.213     2.806    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[0]_i_6_n_0
    SLICE_X113Y97        LUT6 (Prop_D6LUT_SLICEM_I5_O)
                                                      0.122     2.928 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[0]_i_1/O
                         net (fo=1, routed)           0.072     3.000    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_84
    SLICE_X113Y97        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       2.256     2.438    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X113Y97        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[7]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[7]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.730ns  (logic 0.281ns (10.293%)  route 2.449ns (89.707%))
  Logic Levels:           4  (LUT4=1 LUT5=2 LUT6=1)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.257ns (routing 0.690ns, distribution 1.567ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[7]
                         net (fo=1, routed)           2.069     2.069    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/dac1_common_stat[7]
    SLICE_X110Y107       LUT5 (Prop_C6LUT_SLICEM_I4_O)
                                                      0.051     2.120 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[7]_i_21/O
                         net (fo=1, routed)           0.040     2.160    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[7]_i_21_n_0
    SLICE_X110Y107       LUT4 (Prop_A6LUT_SLICEM_I2_O)
                                                      0.090     2.250 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[7]_i_9/O
                         net (fo=1, routed)           0.044     2.294    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[7]_i_9_n_0
    SLICE_X110Y107       LUT5 (Prop_B6LUT_SLICEM_I1_O)
                                                      0.089     2.383 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[7]_i_3/O
                         net (fo=1, routed)           0.247     2.630    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[7]_i_3_n_0
    SLICE_X111Y99        LUT6 (Prop_B6LUT_SLICEL_I2_O)
                                                      0.051     2.681 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[7]_i_1/O
                         net (fo=1, routed)           0.049     2.730    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_77
    SLICE_X111Y99        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[7]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       2.257     2.439    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X111Y99        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[7]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_COMMON[3]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[3]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.568ns  (logic 0.085ns (14.965%)  route 0.483ns (85.035%))
  Logic Levels:           4  (LUT5=2 LUT6=2)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.555ns (routing 0.463ns, distribution 1.092ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_COMMON[3]
                         net (fo=1, routed)           0.291     0.291    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/adc1_common_stat[3]
    SLICE_X113Y91        LUT5 (Prop_B6LUT_SLICEM_I4_O)
                                                      0.014     0.305 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[3]_i_60/O
                         net (fo=1, routed)           0.044     0.349    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[3]_i_60_n_0
    SLICE_X113Y91        LUT5 (Prop_C6LUT_SLICEM_I1_O)
                                                      0.014     0.363 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[3]_i_26/O
                         net (fo=1, routed)           0.083     0.446    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[3]_i_26_n_0
    SLICE_X113Y96        LUT6 (Prop_F6LUT_SLICEM_I5_O)
                                                      0.035     0.481 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[3]_i_6/O
                         net (fo=1, routed)           0.041     0.522    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[3]_i_6_n_0
    SLICE_X113Y96        LUT6 (Prop_C6LUT_SLICEM_I5_O)
                                                      0.022     0.544 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[3]_i_1/O
                         net (fo=1, routed)           0.024     0.568    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_81
    SLICE_X113Y96        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[3]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       1.555     1.702    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X113Y96        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[3]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_COMMON[0]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.651ns  (logic 0.110ns (16.897%)  route 0.541ns (83.103%))
  Logic Levels:           4  (LUT6=4)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.564ns (routing 0.463ns, distribution 1.101ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_COMMON[0]
                         net (fo=1, routed)           0.250     0.250    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/adc1_common_stat[0]
    SLICE_X114Y89        LUT6 (Prop_B6LUT_SLICEL_I0_O)
                                                      0.023     0.273 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[0]_i_51/O
                         net (fo=1, routed)           0.047     0.320    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[0]_i_51_n_0
    SLICE_X114Y89        LUT6 (Prop_H6LUT_SLICEL_I1_O)
                                                      0.050     0.370 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[0]_i_19/O
                         net (fo=1, routed)           0.137     0.507    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[0]_i_19_n_0
    SLICE_X113Y95        LUT6 (Prop_H6LUT_SLICEM_I4_O)
                                                      0.015     0.522 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[0]_i_4/O
                         net (fo=1, routed)           0.081     0.603    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[0]_i_4_n_0
    SLICE_X113Y97        LUT6 (Prop_D6LUT_SLICEM_I2_O)
                                                      0.022     0.625 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[0]_i_1/O
                         net (fo=1, routed)           0.026     0.651    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_84
    SLICE_X113Y97        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       1.564     1.711    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X113Y97        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_COMMON[4]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[4]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.664ns  (logic 0.183ns (27.560%)  route 0.481ns (72.440%))
  Logic Levels:           4  (LUT5=1 LUT6=3)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.562ns (routing 0.463ns, distribution 1.099ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_COMMON[4]
                         net (fo=1, routed)           0.238     0.238    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/adc1_common_stat[4]
    SLICE_X113Y89        LUT5 (Prop_F6LUT_SLICEM_I4_O)
                                                      0.059     0.297 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[4]_i_34/O
                         net (fo=1, routed)           0.107     0.404    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[4]_i_34_n_0
    SLICE_X113Y90        LUT6 (Prop_C6LUT_SLICEM_I2_O)
                                                      0.014     0.418 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[4]_i_14/O
                         net (fo=1, routed)           0.083     0.501    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[4]_i_14_n_0
    SLICE_X113Y95        LUT6 (Prop_F6LUT_SLICEM_I5_O)
                                                      0.050     0.551 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[4]_i_5/O
                         net (fo=1, routed)           0.032     0.583    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[4]_i_5_n_0
    SLICE_X113Y95        LUT6 (Prop_B6LUT_SLICEM_I4_O)
                                                      0.060     0.643 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[4]_i_1/O
                         net (fo=1, routed)           0.021     0.664    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_80
    SLICE_X113Y95        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[4]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       1.562     1.709    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X113Y95        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[4]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_COMMON[7]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[7]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.708ns  (logic 0.149ns (21.045%)  route 0.559ns (78.955%))
  Logic Levels:           4  (LUT3=1 LUT5=1 LUT6=2)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.563ns (routing 0.463ns, distribution 1.100ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_COMMON[7]
                         net (fo=1, routed)           0.235     0.235    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/adc1_common_stat[7]
    SLICE_X113Y89        LUT5 (Prop_B6LUT_SLICEM_I3_O)
                                                      0.035     0.270 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[7]_i_25/O
                         net (fo=1, routed)           0.025     0.295    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[7]_i_25_n_0
    SLICE_X113Y89        LUT6 (Prop_G6LUT_SLICEM_I0_O)
                                                      0.040     0.335 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[7]_i_17/O
                         net (fo=1, routed)           0.158     0.493    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[7]_i_17_n_0
    SLICE_X114Y97        LUT3 (Prop_D5LUT_SLICEL_I1_O)
                                                      0.033     0.526 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[7]_i_5/O
                         net (fo=1, routed)           0.126     0.652    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[7]_i_5_n_0
    SLICE_X111Y99        LUT6 (Prop_B6LUT_SLICEL_I4_O)
                                                      0.041     0.693 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[7]_i_1/O
                         net (fo=1, routed)           0.015     0.708    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_77
    SLICE_X111Y99        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[7]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       1.563     1.710    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X111Y99        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[7]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_COMMON[1]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[1]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.721ns  (logic 0.122ns (16.917%)  route 0.599ns (83.083%))
  Logic Levels:           4  (LUT6=4)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.562ns (routing 0.463ns, distribution 1.099ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_COMMON[1]
                         net (fo=2, routed)           0.252     0.252    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/adc1_common_stat[1]
    SLICE_X114Y90        LUT6 (Prop_G6LUT_SLICEL_I4_O)
                                                      0.050     0.302 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[1]_i_45/O
                         net (fo=1, routed)           0.072     0.374    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[1]_i_45_n_0
    SLICE_X114Y91        LUT6 (Prop_H6LUT_SLICEL_I4_O)
                                                      0.015     0.389 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[1]_i_19/O
                         net (fo=1, routed)           0.152     0.541    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[1]_i_19_n_0
    SLICE_X112Y95        LUT6 (Prop_G6LUT_SLICEM_I5_O)
                                                      0.022     0.563 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[1]_i_4/O
                         net (fo=1, routed)           0.107     0.670    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[1]_i_4_n_0
    SLICE_X111Y97        LUT6 (Prop_D6LUT_SLICEL_I3_O)
                                                      0.035     0.705 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[1]_i_1/O
                         net (fo=1, routed)           0.016     0.721    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_83
    SLICE_X111Y97        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       1.562     1.709    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X111Y97        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[1]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_COMMON[2]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[2]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.774ns  (logic 0.173ns (22.351%)  route 0.601ns (77.649%))
  Logic Levels:           4  (LUT5=1 LUT6=3)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.555ns (routing 0.463ns, distribution 1.092ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_COMMON[2]
                         net (fo=1, routed)           0.265     0.265    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/adc1_common_stat[2]
    SLICE_X115Y90        LUT5 (Prop_B6LUT_SLICEM_I4_O)
                                                      0.050     0.315 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[2]_i_31/O
                         net (fo=1, routed)           0.047     0.362    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[2]_i_31_n_0
    SLICE_X115Y91        LUT6 (Prop_B6LUT_SLICEM_I3_O)
                                                      0.022     0.384 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[2]_i_10/O
                         net (fo=1, routed)           0.153     0.537    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[2]_i_10_n_0
    SLICE_X116Y96        LUT6 (Prop_G6LUT_SLICEL_I4_O)
                                                      0.050     0.587 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[2]_i_2/O
                         net (fo=1, routed)           0.115     0.702    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[2]_i_2_n_0
    SLICE_X112Y95        LUT6 (Prop_H6LUT_SLICEM_I0_O)
                                                      0.051     0.753 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[2]_i_1/O
                         net (fo=1, routed)           0.021     0.774    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_82
    SLICE_X112Y95        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[2]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       1.555     1.702    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X112Y95        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[2]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/STATUS_COMMON[5]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[5]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.264ns  (logic 0.094ns (7.437%)  route 1.170ns (92.563%))
  Logic Levels:           4  (LUT5=2 LUT6=2)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.562ns (routing 0.463ns, distribution 1.099ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/STATUS_COMMON[5]
                         net (fo=1, routed)           0.881     0.881    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/dac0_common_stat[5]
    SLICE_X114Y107       LUT5 (Prop_C6LUT_SLICEL_I4_O)
                                                      0.014     0.895 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_20/O
                         net (fo=1, routed)           0.043     0.938    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_20_n_0
    SLICE_X113Y106       LUT6 (Prop_F6LUT_SLICEM_I5_O)
                                                      0.022     0.960 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_9/O
                         net (fo=1, routed)           0.064     1.024    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_9_n_0
    SLICE_X114Y107       LUT5 (Prop_B6LUT_SLICEL_I3_O)
                                                      0.036     1.060 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_3/O
                         net (fo=1, routed)           0.161     1.221    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_3_n_0
    SLICE_X113Y97        LUT6 (Prop_G6LUT_SLICEM_I2_O)
                                                      0.022     1.243 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_1/O
                         net (fo=1, routed)           0.021     1.264    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_79
    SLICE_X113Y97        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[5]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y61        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=29124, routed)       1.562     1.709    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X113Y97        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[5]/C





